CN111863728B - Array substrate and manufacturing method thereof - Google Patents

Array substrate and manufacturing method thereof Download PDF

Info

Publication number
CN111863728B
CN111863728B CN202010605707.0A CN202010605707A CN111863728B CN 111863728 B CN111863728 B CN 111863728B CN 202010605707 A CN202010605707 A CN 202010605707A CN 111863728 B CN111863728 B CN 111863728B
Authority
CN
China
Prior art keywords
gate insulating
insulating layer
terminal
semiconductor
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202010605707.0A
Other languages
Chinese (zh)
Other versions
CN111863728A (en
Inventor
费米
王鸣昕
卞存健
徐尚君
舒扬
袁玲
程一鸣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nanjing Boe Display Technology Co ltd
Original Assignee
Nanjing Boe Display Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanjing Boe Display Technology Co ltd filed Critical Nanjing Boe Display Technology Co ltd
Priority to CN202010605707.0A priority Critical patent/CN111863728B/en
Publication of CN111863728A publication Critical patent/CN111863728A/en
Application granted granted Critical
Publication of CN111863728B publication Critical patent/CN111863728B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

The application provides an array substrate and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: s1: depositing a first metal layer on a glass substrate; s2: forming a semiconductor channel hole in the region where the semiconductor channel is located and on the gate insulating layer and a terminal contact hole on the first terminal; wherein the thickness of the gate insulating layer isTo the point ofThe thickness of the gate insulating layer below the semiconductor channel hole isTo the point ofS3: forming a semiconductor layer in a portion of the semiconductor channel hole; s4: source and drain electrodes respectively contacting both ends of the semiconductor layer and a second terminal contacting the first terminal through the terminal contact hole are formed. The array substrate increases the overlapping distance of the first metal layer and the second metal layerTo the point ofAnd the parasitic capacitance of the overlapping area of the first metal layer and the second metal layer is reduced, and the parasitic capacitance of the TFT switch is reduced under the condition that an additional mask is not added.

Description

Array substrate and manufacturing method thereof
Technical Field
The application relates to the technical field of developing panels, in particular to an array substrate and a manufacturing method thereof.
Background
TFT (Thin Film Transistor) is an abbreviation for thin film transistor. TFT type display screens are the mainstream display devices for various types of screens, where each pixel point on the display screen is driven by a thin film transistor integrated behind the pixel point. The TFT-LCD, AMOLED, AMQLED and Micro-LED have good display effect, and have a dense and inseparable relation with the array substrate.
Currently, the mainstream development technologies of the existing panel include a narrow frame design and a self-luminous display technology. The frame narrowing and self-luminous pixel compensation circuits place higher demands on the panel circuit design. Firstly, more wires are integrated in an AA area, overlapping of different metal wires can be increased, parasitic capacitance caused by overlapping is increased, voltage drop of the wires can be increased, and power consumption of the panel is increased. In the conventional array substrate, a certain overlapping area exists between the gate and the source and the drain, so that a capacitance Cgs between the gate and the source and a capacitance Cgd between the gate and the drain are formed, and parasitic capacitance is also formed by the intersection of the scanning line and the data line on the array substrate. The existence of the overlap capacitor can enable the pixel electrode to have a certain jump voltage, namely when a certain row is opened or closed, the grid voltage changes between the closing voltage Voff and the opening voltage Von, and the parasitic capacitor enables the pixel electrode to generate the jump voltage in the process, and the jump voltage is proportional to the capacitance value of the parasitic capacitor.
Fig. 1 is a schematic diagram showing the structure of a conventional BCE TFT (back channel etch type TFT), which includes a substrate 10, a gate electrode 20 disposed on the substrate 10, a gate insulating layer 30 covering the gate electrode 10, an active layer 40 disposed on the gate insulating layer 30, and a source electrode 51 and a drain electrode 52 disposed on the gate insulating layer 30 and the active layer 40 and respectively contacting both ends of the active layer 40.
The thickness of the conventional gate insulation layer 30 is typicallyTo reduce panel power consumption, it is desirable to reduce resistive and capacitive loads. Since the capacitance is inversely proportional to the distance between the gate and the source drain, the purpose of reducing the capacitance can be achieved by increasing the distance between the gate and the source drain. However, the distance between the gate and the source/drain increases, and the TFT characteristics are also affected, so that the conventional array substrate cannot achieve the purpose of reducing the device capacitance and thus the device power consumption.
Disclosure of Invention
The application aims to provide an array substrate which reduces parasitic capacitance of an overlapped area of a first metal layer and a second metal layer and realizes reduced power consumption and a manufacturing method thereof.
The application provides a manufacturing method of an array substrate, which comprises the following steps:
s1: depositing a first metal layer on a glass substrate, and then forming a grid electrode positioned in a pixel area and a first terminal positioned in a terminal area through exposure, development and etching;
s2: firstly, depositing a gate insulating layer covering a gate and a first terminal and a photoresist on the gate insulating layer; then exposing and developing the gate insulating layer and the photoresist to form a semiconductor channel hole positioned in the area where the semiconductor channel is positioned and positioned on the gate insulating layer and a terminal contact hole positioned on the first terminal; finally ashing to remove the photoresistance; wherein the thickness of the gate insulating layer isTo->The thickness of the gate insulating layer under the semiconductor channel hole is +.>To->
S3: depositing a semiconductor material layer on the basis of the step S2, and etching the semiconductor material layer to form a semiconductor layer positioned in part of the semiconductor channel holes;
s4: and depositing a second metal layer on the basis of the step S3, and performing metal etching on the second metal layer to form a source electrode and a drain electrode which are respectively contacted with two ends of the semiconductor layer and a second terminal contacted with the first terminal through the terminal contact hole.
The application also provides a manufacturing method of the array substrate, which comprises the following steps:
s1: depositing a first metal layer on a glass substrate, and then forming a grid electrode positioned in a pixel area and a first terminal positioned in a terminal area through exposure, development and etching;
s2: firstly, depositing a gate insulating layer covering a gate and a first terminal and a photoresist on the gate insulating layer; then exposing and developing the gate insulating layer and the photoresist to form a semiconductor channel hole which is positioned in the area where the semiconductor channel is positioned and is positioned on the gate insulating layer; finally ashing to remove the photoresistance; wherein the thickness of the gate insulating layer isTo->The thickness of the gate insulating layer under the semiconductor channel hole is +.>To->
S3: depositing a semiconductor material layer on the basis of the step S2, and etching the semiconductor material layer to form a semiconductor layer positioned in part of the semiconductor channel holes;
s4: etching the gate insulating layer and forming a terminal contact hole on the first terminal;
s5: and depositing a second metal layer on the basis of the step S4, and performing metal etching on the second metal layer to form a source electrode and a drain electrode which are respectively contacted with two ends of the semiconductor layer and a second terminal contacted with the first terminal through the terminal contact hole.
The application also provides a manufacturing method of the array substrate, which comprises the following steps:
s1: depositing a first metal layer on a glass substrate, and then forming a grid electrode positioned in a pixel area and a first terminal positioned in a terminal area through exposure, development and etching;
s2: first, depositing a first gate insulating layer covering the gate and the first terminal and a negative photoresist on the first gate insulating layer; then exposing, developing and etching the negative photoresist to form a semiconductor channel hole which is positioned in the area where the semiconductor channel is positioned and positioned on the gate electrode; finally ashing to remove the negative photoresist; wherein the material of the first gate insulating layer is low-temperature SiNx with thickness ofTo->
S3: firstly, depositing a second gate insulating layer and a positive photoresist on the second gate insulating layer on the basis of the step S2; then exposing, developing and etching the second gate insulating layer and the positive photoresist to form a semiconductor channel hole on the precursor semiconductor channel hole, wherein the semiconductor channel hole is formed by etching part of the second gate insulating layer; finally ashing to remove the positive photoresist; wherein the thickness of the second gate insulating layer isTo-> The sum of the thicknesses of the first gate insulating layer and the second gate insulating layer in the source electrode region and the drain electrode region is +.>To->The thickness of the second gate insulating layer below the semiconductor channel hole is +>To->
S4: depositing a semiconductor material layer on the basis of the step S3, and etching the semiconductor material layer to form a semiconductor layer with a part positioned in the semiconductor channel hole;
s5: etching the first gate insulating layer and the second gate insulating layer on the basis of the step S4 and forming a terminal contact hole on the first terminal;
s6: and depositing a second metal layer on the basis of the step S5, and performing metal etching on the second metal layer to form a source electrode and a drain electrode which are respectively contacted with two ends of the semiconductor layer and a second terminal contacted with the first terminal through the terminal contact hole.
The application also provides an array substrate which is manufactured by the manufacturing method of the array substrate.
The array substrate increases the overlapping distance of the first metal layer and the second metal layerTo the point ofAnd the parasitic capacitance of the overlapping area of the first metal layer and the second metal layer is reduced, and the parasitic capacitance of the TFT switch is reduced under the condition that an additional mask is not added.
Drawings
Fig. 1 is a schematic structural diagram of a conventional BCE TFT;
FIGS. 2 (a) to 5 are views illustrating a method for fabricating an array substrate according to a first embodiment of the present application;
fig. 6 to 10 are views illustrating a method for manufacturing an array substrate according to a second embodiment of the present application;
fig. 11 to 16 are views illustrating a method for manufacturing an array substrate according to a second embodiment of the present application;
FIG. 17 is a graph showing the relationship between Vgs and Ids simulated by the array substrate of the present application.
Detailed Description
The present application is further illustrated in the accompanying drawings and detailed description which are to be understood as being merely illustrative of the application and not limiting of its scope, and various modifications of the application, which are equivalent to those skilled in the art upon reading the application, will fall within the scope of the application as defined in the appended claims.
For the sake of simplicity of the drawing, the parts relevant to the present application are shown only schematically in the figures, which do not represent the actual structure thereof as a product. Additionally, in order to simplify the drawing for ease of understanding, components having the same structure or function in some of the drawings are shown schematically with only one of them, or only one of them is labeled. Herein, "a" means not only "only this one" but also "more than one" case.
Fig. 2 (a) to 5 are views illustrating a method for manufacturing an array substrate according to a first embodiment of the present application, which includes the following steps:
s1: as shown in fig. 2 (a) to 2 (d), a first metal layer 20 is deposited on a glass substrate 10, and then a gate electrode 21 located in a pixel region and a first terminal 22 located in a terminal region are formed by exposure development and etching.
The step S1 specifically comprises the following steps:
s11: as shown in fig. 2 (a), a first metal layer 20 is deposited on a glass substrate 10, and a first photoresist 101 is coated on the first metal layer 20;
s12: as shown in fig. 2 (b), the first photoresist 101 is exposed and developed, and the first photoresist 101 is developed;
s13: as shown in fig. 2 (c), the first metal layer 20 not covered by the first photoresist 101 is etched away and a gate electrode 21 located in the pixel region and a first terminal 22 located in the terminal region are formed;
s14: as shown in fig. 2 (d), the first photoresist 101 is ashed off.
S2: as shown in fig. 3 (a) to 3 (d), a gate insulating layer 30 covering the gate electrode 21 and the first terminal 22 and a second photoresist 102 on the gate insulating layer 30 are first deposited; then, the gate insulating layer 30 and the second photoresist 102 are exposed and developed by using the gate insulating layer semi-transparent mask 200, so that a semiconductor channel hole 31 which is positioned in the area where the semiconductor channel is positioned and positioned on the gate insulating layer 30 and a terminal contact hole 32 which is positioned on the first terminal 22 are formed; finally, ashing removes the second photoresist 102.
The step S2 specifically comprises the following steps:
s21: as shown in fig. 3 (a), a gate insulating layer 30 covering the gate electrode 21 and the first terminal 22 and a second photoresist 102 on the gate insulating layer 30 are deposited, the gate insulating layer 30 having a thickness ofTo-> (preferably +.>) The thickness of the gate insulating layer 30 is increased by +.>To->(preferably +.>)；
S22: as shown in fig. 3 (b), the second photoresist 102 is exposed and developed by using the semi-transparent mask 200 of the gate insulating layer, all of the second photoresist 102 in the region where the semiconductor channel is located is developed, and the second photoresist 102 in the region where the terminal contact hole is located is developed; the semi-transparent mask 200 of the gate insulating layer comprises a semi-exposure region 201 positioned in the region where the semiconductor channel is positioned, a full-exposure region 202 positioned in the region where the terminal contact hole is positioned and other non-exposure regions, wherein the transmittance of the semi-exposure region 201 is 70%, and the transmittance of the full-exposure region 202 is 100%;
s23: as shown in fig. 3 (c), the second photoresist 102 and the gate insulating layer 30 are continuously exposed, developed and etched, the gate insulating layer 30 in the region where the terminal contact hole is located is etched first, and the terminal contact hole 32 is formed, then the second photoresist 102 in the region where the semiconductor channel is located is ashed and the second photoresist is removed, and finally the gate insulating layer in the region where the semiconductor channel is located is etched and the semiconductor channel hole 31 is formed;
s24: as shown in fig. 3 (d), the second photoresist 102 is ashed away.
In step S23, when the gate insulating layer 30 in the region where the semiconductor channel is located is etched, the etching time and/or the amount of the etching liquid are controlled, and only the gate insulating layer in the semiconductor channel hole 31 is etched to an increased thickness, and the thickness of the gate insulating layer 30 under the semiconductor channel hole 31 isTo->(preferably +.>) The thickness of the gate insulating layer 30 is etched away to +>To->(preferably +.>) This ensures that the thickness between the gate electrode 21 and the semiconductor layer is constant so as not to affect the performance of the TFT switch.
S3: as shown in fig. 4, a semiconductor material layer is deposited on the basis of step S2, and a semiconductor mask (not shown) is used to etch the semiconductor material layer to form a semiconductor layer 40 located in a portion of the semiconductor channel hole 31;
s4: as shown in fig. 5, a second metal layer is deposited on the basis of step S3, and source and drain electrodes 51 and 52 respectively contacting both ends of the semiconductor layer 40 and a second terminal 53 contacting the first terminal 22 through the terminal contact hole 32 are formed by metal etching the second metal layer using a source and drain mask (not shown).
The array substrate is formed through the method.
The application is to deposit the gate insulating layer 30 for thickening treatment, and the thickness of the gate insulating layer 30 is increased to cause the condition that the etching is not sinking when the terminal contact hole 32 is etched and formed, so the thickness of the gate insulating layer 30 is increased within the range ofTo->(preferably +.>)。
After the film formation of the gate insulating layer 30, the semi-transparent mask 200 of the gate insulating layer is adopted to expose and form a semiconductor channel hole 31 positioned on the gate insulating layer 30 and a terminal contact hole 32 positioned on the first terminal 22, so that the thickness between the gate 22 and the semiconductor layer 40 is ensured to be unchanged, and the performance of the TFT switch is not affected. The thickness of the gate insulating layer 30 under the semiconductor layer 40 is the thickness of the existing gate insulating layer, i.eTo->(preferably +.>) The thickness of the insulating layer in other regions isTo->(preferably +.>) Therefore, the characteristics of the TFT switch can be ensured, the overlapping capacitance between the wires in the panel can be reduced, and the overlapping capacitance value can be reduced to 69% of the original value. The parasitic capacitances Cgs and Cgd of the TFT switches are also slightly reduced.
The method does not increase the number of masks, and reduces the power consumption of the panel while guaranteeing the cost.
Fig. 6 to 10 are views illustrating a method for manufacturing an array substrate according to a second embodiment of the present application, which includes the following steps:
s1: as shown in fig. 6, a first metal layer is deposited on the glass substrate 10 ', and then a gate electrode 21 ' located in the pixel region and a first terminal 22 ' located in the terminal region are formed by exposure, development and etching.
S2: as shown in fig. 7 (a) to 7 (d), a gate insulating layer 30 ' covering the gate electrode 21 ' and the first terminal 22 ' and a photoresist 102 ' on the gate insulating layer 30 ' are first deposited; then, a source-drain mask (not shown) is used to expose, develop and etch the gate insulating layer 30 'and the photoresist 102' to form a semiconductor channel hole 31 'located in the region where the semiconductor channel is located and on the gate insulating layer 30'; finally, ashing removes the photoresist 102'.
The specific method of step S2 is as follows:
s21: as shown in fig. 7 (a), a gate insulating layer 30 'covering the gate electrode 21' and the first terminal 22 'and a photoresist 102' on the gate insulating layer 30 'are deposited, the gate insulating layer 30' having a thickness ofTo->(preferably +.>) The thickness of the gate insulation layer 30' is increased based on the existing thickness>To->(preferably +.>)；
S22: as shown in fig. 7 b, the photoresist 102 'is exposed and developed using a source-drain mask (not shown), and a portion of the photoresist 102' in the region of the semiconductor channel is developed away; the source drain semi-transparent mask comprises a full exposure area and other non-exposure areas which are positioned in the area where the semiconductor channel is positioned, and the transmittance of the full exposure area 202 is 100%;
s23: as shown in fig. 7 (c), the etching of the gate insulating layer 30 ' is continued to form a semiconductor channel hole 31 ' located on the gate insulating layer 30 ';
s24: as shown in fig. 7 (d), the photoresist 102' is ashed away.
S3: as shown in fig. 8, a semiconductor material layer is deposited on the basis of step S2, and a semiconductor mask (not shown) is used to etch the semiconductor material layer to form a semiconductor layer 40 'located in a portion of the semiconductor channel hole 31';
s4: as shown in fig. 9, the gate insulating layer 30 ' is etched using a gate insulating layer mask (not shown) and terminal contact holes 32 ' are formed in the first terminals 22 '.
S5: as shown in fig. 10, a second metal layer is deposited on the basis of step S4, and a source electrode 51 'and a drain electrode 52' respectively contacting both ends of the semiconductor layer 40 'and a second terminal 53' contacting the first terminal 22 'through the terminal contact hole 32' are formed by metal etching the second metal layer using a source and drain mask (not shown).
The array substrate is formed through the method.
The second embodiment differs from the first embodiment in that: the first embodiment adopts a semi-transparent mask of a gate insulating layer, the second embodiment adopts a mask of a gate insulating layer, and the steps of the second embodiment are more than those of the first embodiment.
Fig. 11 to 16 are views illustrating a method for manufacturing an array substrate according to a second embodiment of the present application, which includes the following steps:
s1: as shown in fig. 11, a first metal layer is deposited on the glass substrate 10 ', and then the gate electrode 21 ' located in the pixel region and the first terminal 22 ' located in the terminal region are formed by exposure, development and etching.
S2: as shown in fig. 12 (a) to 12 (d), first, a first gate insulating layer 301 ' covering the gate electrode 21 ' and the first terminal 22 ' and a negative photoresist 102 ' on the first gate insulating layer 30 ' are deposited; then, a semiconductor mask (not shown) is used to expose, develop and etch the negative photoresist 102 ' to form a semiconductor channel hole 31 ' located in the area of the semiconductor channel and located on the gate electrode 21 '; finally, ashing removes the negative photoresist 102'.
The specific method of step S2 is as follows:
s21: as shown in fig. 12 (a), a first gate insulating layer 301 'covering the gate electrode 21' and the first terminal 22 'and a negative photoresist 102' on the first gate insulating layer 301 'are deposited, and the material of the first gate insulating layer 301' is SiNx at a low temperature and has a thickness ofTo->(preferably +.>)；
S22: as shown in fig. 12 b, a semiconductor mask (not shown) is used to expose and develop the negative photoresist 102 ', and the negative photoresist 102 ' with the semiconductor channel in the region of the first gate insulating layer 301 ' is developed away.
S23: as shown in fig. 12 (c), the first gate insulating layer 301 ' is continued to be etched to form a precursor semiconductor channel hole 31 ' located over the gate electrode 21 ';
s24: as shown in fig. 12 (d), ashing removes the negative photoresist 102'.
S3: as shown in fig. 13 (a) and 13 (b), first, a second gate insulating layer 302 ' and a positive photoresist 103 ' on the second gate insulating layer 302 ' are deposited on the basis of step S2; then, the second gate insulating layer 302 'and the positive photoresist 103' are exposed, developed and etched using a source-drain mask (not shown) so that a semiconductor channel hole 32 'is formed on the precursor semiconductor channel hole 31', the semiconductor channel hole 32 'being formed by etching a portion of the second gate insulating layer 302'; and finally ashing removes the positive photoresist 103'.
Wherein the thickness of the second gate insulating layer 302' isTo->(preferably +.>) The sum of the thicknesses of the first gate insulating layer 301 'and the second gate insulating layer 302' in the region where the second metal layer is located is +.>To the point of(preferably +.>) The method comprises the steps of carrying out a first treatment on the surface of the The second gate insulating layer 302 'underlying the semiconductor channel hole 31' has a thickness ofTo->(preferably +.>)。
S4: as shown in fig. 14, a semiconductor material layer is deposited on the basis of step S3, and a semiconductor layer 40 'partially located in semiconductor channel hole 31' is formed by a semiconductor mask (not shown).
S5: as shown in fig. 15, a first gate insulating layer 301 'and a second gate insulating layer 302' are etched using a gate insulating layer mask (not shown) on the basis of step S4 and terminal contact holes 32 'are formed in the first terminal 22'.
S6: as shown in fig. 16, a second metal layer is deposited on the basis of step S5, and a source and drain mask (not shown) is used to metal etch the second metal layer to form source and drain electrodes 51 'and 52' respectively in contact with both ends of the semiconductor layer 40 ', and a second terminal 53' in contact with the first terminal 22 'through the terminal contact hole 32'.
The array substrate is formed through the method.
According to the third embodiment, the first grid insulating layer formed by the low-temperature SiNx material is deposited, the semiconductor mask and the source drain mask are adopted for repeated exposure on the basis of the existing mask, the overlapping thickness between the grid and the source and the drain is increased to the greatest extent, and the capacitance is reduced.
The application also discloses an array substrate manufactured by the method.
The application increases the overlapping distance between the first metal layer and the second metal layerTo->The array substrate can be formed by adopting a semi-transparent mask plate and source drain mask plate combination of a gate insulating layer or a semiconductor mask plate and source drain mask plate combination and simultaneously using exposure treatment. Fig. 17 is a graph of the relationship between Vgs (voltage between gate and source) and Ids (current between source and drain) of a TFT device simulated with the fitted defect parameters, fitted on the basis of experimental data using TCAD software. Wherein, the normal TFT is the graph of the existing TFT device, and the low-power consumption device TFT is the graph of the TFT device. The results showed that there was no significant difference in TFT characteristics, and a slight difference in threshold voltage was an experimental error.
The array substrate of the application increases the overlapping distance between the first metal and the second metalTo the point ofThe parasitic capacitance of the overlapping area between the first metal and the second metal is reduced while the electrical characteristics of the TFT device are ensured, and the parasitic capacitance of the array substrate is reduced under the condition that an additional mask is not added.
The preferred embodiments of the present application have been described in detail above, but the present application is not limited to the specific details of the above embodiments, and various equivalent changes (such as number, shape, position, etc.) may be made to the technical solution of the present application within the scope of the technical concept of the present application, and these equivalent changes all fall within the scope of the present application.

Claims (8)

1. The manufacturing method of the array substrate is characterized by comprising the following steps of:
s1: depositing a first metal layer on a glass substrate, and then forming a grid electrode positioned in a pixel area and a first terminal positioned in a terminal area through exposure, development and etching;
s2: firstly, depositing a gate insulating layer covering a gate and a first terminal and a photoresist on the gate insulating layer; then exposing and developing the gate insulating layer and the photoresist to form a semiconductor channel hole positioned in the area where the semiconductor channel is positioned and positioned on the gate insulating layer and a terminal contact hole positioned on the first terminal; finally ashing to remove the photoresistance; wherein the thickness of the gate insulating layer isTo->The thickness of the gate insulating layer under the semiconductor channel hole is +.>To->
S3: depositing a semiconductor material layer on the basis of the step S2, and etching the semiconductor material layer to form a semiconductor layer positioned in part of the semiconductor channel holes;
s4: depositing a second metal layer on the basis of the step S3, and performing metal etching on the second metal layer to form a source electrode and a drain electrode which are respectively contacted with two ends of the semiconductor layer and a second terminal contacted with the first terminal through a terminal contact hole;
the step S2 specifically comprises the following steps:
s21: depositing a gate insulating layer covering the gate and the first terminal and a photoresist on the gate insulating layer;
s22: exposing and developing the photoresist by adopting a semi-transparent mask plate of the gate insulating layer, developing partial photoresist in the area where the semiconductor channel is located, and developing all the photoresist in the area where the terminal contact hole is located; the semi-transparent mask of the gate insulating layer comprises a semi-exposure area positioned in the area where the semiconductor channel is positioned, a full-exposure area positioned in the area where the terminal contact hole is positioned and other non-exposure areas;
s23: continuing exposing, developing and etching the photoresist and the gate insulating layer, firstly etching the gate insulating layer in the area where the terminal contact hole is positioned and forming the terminal contact hole, then ashing part of the photoresist in the area where the semiconductor channel is positioned and removing the part of the photoresist, and finally etching the gate insulating layer in the area where the semiconductor channel is positioned and forming the semiconductor channel hole;
s24: ashing to remove the photoresist.
2. The method for manufacturing an array substrate according to claim 1, wherein in step S3, a semiconductor mask is used to etch the semiconductor material layer to form a semiconductor layer located in a portion of the semiconductor channel hole; in step S4, the source and drain electrodes contacting with the two ends of the semiconductor layer and the second terminal contacting with the first terminal through the terminal contact hole are formed by metal etching the second metal layer by using the source and drain mask.
3. The manufacturing method of the array substrate is characterized by comprising the following steps of:
s1: depositing a first metal layer on a glass substrate, and then forming a grid electrode positioned in a pixel area and a first terminal positioned in a terminal area through exposure, development and etching;
s2: firstly, depositing a gate insulating layer covering a gate and a first terminal and a photoresist on the gate insulating layer; then exposing and developing the gate insulating layer and the photoresist to form a semiconductor channel hole which is positioned in the area where the semiconductor channel is positioned and is positioned on the gate insulating layer; finally ashing to remove the photoresistance; wherein the thickness of the gate insulating layer isTo->The thickness of the gate insulating layer under the semiconductor channel hole is +.>To->
S3: depositing a semiconductor material layer on the basis of the step S2, and etching the semiconductor material layer to form a semiconductor layer positioned in part of the semiconductor channel holes;
s4: etching the gate insulating layer and forming a terminal contact hole on the first terminal;
s5: depositing a second metal layer on the basis of the step S4, and performing metal etching on the second metal layer to form a source electrode and a drain electrode which are respectively contacted with two ends of the semiconductor layer and a second terminal contacted with the first terminal through a terminal contact hole;
the step S2 specifically comprises the following steps:
s21: depositing a gate insulating layer covering the gate and the first terminal and a photoresist on the gate insulating layer;
s22: exposing and developing the photoresist by using a source-drain transparent mask, and developing away part of the photoresist in the area where the semiconductor channel is located; the source drain semi-transparent mask comprises a full exposure area and other non-exposure areas which are positioned in the area where the semiconductor channel is positioned;
s23: continuing to expose, develop and etch the gate insulating layer to form a semiconductor channel hole on the gate insulating layer;
s24: ashing to remove the photoresist.
4. The method for manufacturing an array substrate according to claim 3, wherein in step S3, a semiconductor mask is used to etch the semiconductor material layer to form a semiconductor layer located in a portion of the semiconductor channel hole; in step S4, etching the gate insulating layer by using a gate insulating layer mask plate and forming a terminal contact hole positioned on the first terminal; in step S5, the source and drain electrodes contacting with the two ends of the semiconductor layer and the second terminal contacting with the first terminal through the terminal contact hole are formed by metal etching the second metal layer by using the source and drain mask.
5. The manufacturing method of the array substrate is characterized by comprising the following steps of:
s1: depositing a first metal layer on a glass substrate, and then forming a grid electrode positioned in a pixel area and a first terminal positioned in a terminal area through exposure, development and etching;
s2: first, depositing a first gate insulating layer covering the gate and the first terminal and a negative photoresist on the first gate insulating layer; then exposing, developing and etching the negative photoresist to form a semiconductor channel hole which is positioned in the area where the semiconductor channel is positioned and positioned on the gate electrode; finally ashing to remove the negative photoresist; wherein the material of the first gate insulating layer is low-temperature SiNx with thickness ofTo->
S3: firstly, depositing a second gate insulating layer and a positive photoresist on the second gate insulating layer on the basis of the step S2; then exposing, developing and etching the second gate insulating layer and the positive photoresist to form a semiconductor channel hole on the precursor semiconductor channel hole, wherein the semiconductor channel hole is formed by etching part of the second gate insulating layer; finally ashing to remove the positive photoresist; wherein the thickness of the second gate insulating layer isTo-> The sum of the thicknesses of the first gate insulating layer and the second gate insulating layer in the source electrode region and the drain electrode region is +.>To->The thickness of the second gate insulating layer below the semiconductor channel hole is +>To->
S4: depositing a semiconductor material layer on the basis of the step S3, and etching the semiconductor material layer to form a semiconductor layer with a part positioned in the semiconductor channel hole;
s5: etching the first gate insulating layer and the second gate insulating layer on the basis of the step S4 and forming a terminal contact hole on the first terminal;
s6: and depositing a second metal layer on the basis of the step S5, and performing metal etching on the second metal layer to form a source electrode and a drain electrode which are respectively contacted with two ends of the semiconductor layer and a second terminal contacted with the first terminal through the terminal contact hole.
6. The method of manufacturing an array substrate according to claim 5, wherein the step S2 specifically includes the steps of:
s21: depositing a first gate insulating layer covering the gate and the first terminal and a negative photoresist on the first gate insulating layer;
s22: exposing and developing the negative photoresist by using a semiconductor mask, wherein the negative photoresist which is positioned in the area of the semiconductor channel and is positioned on the first grid insulating layer is developed;
s23: continuing to expose, develop and etch the first gate insulating layer to form a precursor semiconductor channel hole on the gate;
s24: ashing removes the negative photoresist.
7. The method according to claim 5, wherein in step S3, the second gate insulating layer and the positive photoresist are exposed, developed and etched by using a source-drain mask so that a semiconductor channel hole is formed on the precursor semiconductor channel hole; in step S4, forming a semiconductor layer partially positioned in the semiconductor channel hole through the semiconductor mask plate; in step S5, etching the first gate insulating layer and the second gate insulating layer by using a gate insulating layer mask and forming a terminal contact hole on the first terminal; in step S6, the source and drain electrodes contacting with the two ends of the semiconductor layer and the second terminal contacting with the first terminal through the terminal contact hole are formed by metal etching the second metal layer by using the source and drain mask.
8. An array substrate manufactured by the manufacturing method of an array substrate according to any one of claims 1 to 7.
CN202010605707.0A 2020-06-29 2020-06-29 Array substrate and manufacturing method thereof Active CN111863728B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010605707.0A CN111863728B (en) 2020-06-29 2020-06-29 Array substrate and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010605707.0A CN111863728B (en) 2020-06-29 2020-06-29 Array substrate and manufacturing method thereof

Publications (2)

Publication Number Publication Date
CN111863728A CN111863728A (en) 2020-10-30
CN111863728B true CN111863728B (en) 2023-12-08

Family

ID=72988756

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010605707.0A Active CN111863728B (en) 2020-06-29 2020-06-29 Array substrate and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN111863728B (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101477989A (en) * 2008-01-04 2009-07-08 群康科技(深圳)有限公司 Thin-film transistor substrates and manufacturing method therefor
CN102842587A (en) * 2012-09-24 2012-12-26 京东方科技集团股份有限公司 Array substrate, manufacturing method of array substrate and display device
CN107820639A (en) * 2016-11-08 2018-03-20 深圳市柔宇科技有限公司 OLED display, array base palte and preparation method thereof
CN109768015A (en) * 2019-01-29 2019-05-17 南京中电熊猫平板显示科技有限公司 A kind of array substrate and its manufacturing method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101477989A (en) * 2008-01-04 2009-07-08 群康科技(深圳)有限公司 Thin-film transistor substrates and manufacturing method therefor
CN102842587A (en) * 2012-09-24 2012-12-26 京东方科技集团股份有限公司 Array substrate, manufacturing method of array substrate and display device
CN107820639A (en) * 2016-11-08 2018-03-20 深圳市柔宇科技有限公司 OLED display, array base palte and preparation method thereof
CN109768015A (en) * 2019-01-29 2019-05-17 南京中电熊猫平板显示科技有限公司 A kind of array substrate and its manufacturing method

Also Published As

Publication number Publication date
CN111863728A (en) 2020-10-30

Similar Documents

Publication Publication Date Title
US9613986B2 (en) Array substrate and its manufacturing method, display device
US8895334B2 (en) Thin film transistor array substrate and method for manufacturing the same and electronic device
US11087985B2 (en) Manufacturing method of TFT array substrate
JP2010041058A (en) Thin film transistor, substrate and manufacturing method thereof
CN107359126B (en) Thin film transistor, preparation method thereof, array substrate and display panel
US20140120657A1 (en) Back Channel Etching Oxide Thin Film Transistor Process Architecture
US20120276697A1 (en) Manufacturing method of array substrate
CN103715267A (en) TFT, TFT array substrate, manufacturing method of TFT array substrate and display device
CN106024813B (en) A kind of production method and related device of low temperature polycrystalline silicon tft array substrate
US20180292696A1 (en) Array substrate, manufacturing method thereof, display panel and display device
CN109494257B (en) Thin film transistor, manufacturing method thereof, array substrate and display device
CN107799466B (en) TFT substrate and manufacturing method thereof
CN107068692B (en) Display device, array substrate and manufacturing method thereof
EP2757589A2 (en) Methods for fabricating a thin film transistor and an array substrate
CN105514173A (en) Thin film transistor and preparation method, array substrate and preparation method, and display device
US9741861B2 (en) Display device and method for manufacturing the same
KR20100133170A (en) Thin film transistor manufacturing method using two photo masks
CN114089571B (en) Array substrate, manufacturing method and display panel
CN110854205A (en) Thin film transistor, manufacturing method, display panel and display device
CN113725157B (en) Array substrate and manufacturing method thereof
US10134765B2 (en) Oxide semiconductor TFT array substrate and method for manufacturing the same
CN111739841A (en) In-cell touch panel with top gate structure and manufacturing method
CN110600483A (en) Array substrate and manufacturing method thereof
CN106298523B (en) thin film transistor, method for manufacturing thin film transistor, and method for manufacturing array substrate
CN107195689B (en) Thin film transistor, manufacturing method thereof and OLED display panel

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information
CB02 Change of applicant information

Address after: No.7 Tianyou Road, Qixia District, Nanjing City, Jiangsu Province

Applicant after: Nanjing BOE Display Technology Co.,Ltd.

Address before: No.7 Tianyou Road, Qixia District, Nanjing City, Jiangsu Province

Applicant before: NANJING CEC PANDA FPD TECHNOLOGY Co.,Ltd.

GR01 Patent grant
GR01 Patent grant