CN107068692B - Display device, array substrate and manufacturing method thereof - Google Patents
Display device, array substrate and manufacturing method thereof Download PDFInfo
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- CN107068692B CN107068692B CN201710261623.8A CN201710261623A CN107068692B CN 107068692 B CN107068692 B CN 107068692B CN 201710261623 A CN201710261623 A CN 201710261623A CN 107068692 B CN107068692 B CN 107068692B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
Abstract
The present disclosure provides a display device, an array substrate and a method of manufacturing the same. The manufacturing method of the array substrate comprises the following steps: forming a grid metal layer at least comprising a thin film transistor area and a power line area on a substrate; forming a grid electrode in the thin film transistor area and a power line in the power line area through a composition process, wherein the thickness of the grid electrode is smaller than that of the power line; and forming a stacked gate insulating layer, an active layer and a source-drain metal layer in the thin film transistor area through a composition process to obtain the thin film transistor.
Description
Technical Field
The disclosure relates to the technical field of display, and particularly relates to a display device, an array substrate and a manufacturing method of the array substrate.
Background
At present, with the wide application of display panels, people have higher and higher requirements for product quality. The quality of the array substrate, which is a core component of the display panel, is directly related to the quality of the final product. The existing array substrate is generally provided with a thin film transistor, when a grid electrode of the thin film transistor is formed, a grid electrode metal layer is required to be formed on a glass substrate firstly, and then the grid electrode is formed on the grid electrode metal layer through a photoetching process; however, the gate metal layer is not only used to form the gate, but also can form the power line and the like on the same layer as the gate through a photolithography process.
For the power line, in order to reduce the line resistance and ensure the voltage drop, a larger thickness is required to be ensured; however, because the thermal stability of metal is inferior to that of glass, the metal with larger thickness needs to release internal stress in the high-temperature process, so that the metal layer contracts inwards to form a plurality of raised 'hillocks', namely a 'hillock' phenomenon appears; these hillocks may penetrate the gate insulating layer, causing short circuit of metal on both sides of the gate insulating layer, which makes the thin film transistor difficult to work normally, thereby affecting the normal operation of the array substrate and the display panel, and the thicker the metal, the higher the occurrence rate of the hillock phenomenon, thereby greatly reducing the yield of the product.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
An object of the present disclosure is to provide a display device, an array substrate, and a method of manufacturing the array substrate, which overcome one or more of the problems due to the limitations and disadvantages of the related art, at least to some extent.
According to an aspect of the present disclosure, there is provided a method of manufacturing an array substrate, including:
forming a grid metal layer at least comprising a thin film transistor area and a power line area on a substrate;
forming a grid electrode in the thin film transistor area and a power line in the power line area through a composition process, wherein the thickness of the grid electrode is smaller than that of the power line;
and forming a stacked gate insulating layer, an active layer and a source-drain metal layer in the thin film transistor area through a composition process to obtain the thin film transistor.
In an exemplary embodiment of the present disclosure, the gate metal layer further includes a storage capacitor region, and the method of manufacturing the array substrate further includes:
and forming a capacitance electrode in the storage capacitance area through a composition process, wherein the thickness of the capacitance electrode is less than that of the power line.
In an exemplary embodiment of the present disclosure, the gate metal layer further includes a gate line region, and the method of manufacturing the array substrate further includes:
and forming a grid line on the grid line region by a composition process, wherein the grid line comprises a crossing region which crosses the signal line, and the thickness of the grid line in the crossing region is smaller than that of the power line.
In an exemplary embodiment of the present disclosure, after the forming of the gate electrode and before the forming of the gate insulating layer, the method of manufacturing the array substrate further includes:
forming an oxidation preventing layer on the substrate including the gate;
an anti-oxidation layer pattern is formed through a composition process, the anti-oxidation layer pattern at least covers an area with the thickness smaller than that of the power line on the grid metal layer, and the sum of the thicknesses of the anti-oxidation layer and the area with the thickness smaller than that of the power line on the grid metal layer is smaller than that of the power line.
In an exemplary embodiment of the present disclosure, the forming of the gate electrode in the thin film transistor region and the power line in the power line region includes:
coating a photoresist layer on the grid metal layer;
exposing and developing the photoresist layer by adopting a half-tone mask plate to obtain at least a completely removed area, a reserved area corresponding to the power line area and a half-reserved area corresponding to the thin film transistor area;
removing the exposed gate metal layer in the completely removed region by adopting an etching process;
removing the photoresist in the semi-reserved area by adopting an ashing process to expose the gate metal layer in the thin film transistor area;
thinning the grid metal layer in the thin film transistor area by adopting an etching process;
and removing the photoresist layer of the reserved area by adopting a stripping process.
According to an aspect of the present disclosure, there is provided an array substrate including:
a substrate base plate;
the power line is arranged on the substrate base plate;
the thin film transistor is arranged on the substrate and comprises a grid electrode, a grid insulation layer, an active layer and a source drain metal layer, the grid electrode and the power line are arranged on the same layer, and the thickness of the grid electrode is smaller than that of the power line.
In an exemplary embodiment of the present disclosure, the array substrate further includes:
the storage capacitor comprises a capacitor electrode, the capacitor electrode is arranged on the substrate and arranged on the same layer with the grid, and the thickness of the capacitor electrode is smaller than that of the power line.
In an exemplary embodiment of the present disclosure, the array substrate further includes:
the grid line is arranged on the substrate and arranged on the same layer as the grid electrode, and comprises a cross region;
and the signal line is arranged above the grid line and is intersected with the grid line in the intersection region, and the thickness of the signal line and the grid line in the intersection region is smaller than that of the power line.
In an exemplary embodiment of the present disclosure, the array substrate further includes:
and the anti-oxidation layer pattern is arranged between the grid metal layer and the grid insulating layer, at least covers an area with the thickness smaller than that of the power line on the grid metal layer, and the sum of the thicknesses of the anti-oxidation layer and the area with the thickness smaller than that of the power line on the grid metal layer is smaller than that of the power line.
According to an aspect of the present disclosure, a display device includes:
the array substrate as set forth in any one of the above.
According to the manufacturing method of the array substrate, the array substrate and the display device, the product yield can be improved by enabling different areas on the grid metal layer to have different thicknesses, and the line resistance of a power line is prevented from being influenced; specifically, a gate electrode may be formed in the thin film transistor region and a power line may be formed in the power line region through a patterning process, and the thickness of the gate electrode is less than that of the power line. Therefore, the thickness of the power line can be prevented from being reduced, the line resistance and the voltage drop of the power line can be ensured, the thickness of the grid can be reduced, the phenomenon of 'hillock', namely 'hillock', can be prevented from occurring on the grid, and the normal work of the thin film transistor can be ensured. Therefore, the yield of products can be improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.
Fig. 1 is a flowchart of a method for manufacturing an array substrate according to the present disclosure.
Fig. 2 is a flowchart of a method for implementing step S120 in fig. 1.
Fig. 3 is a schematic structural diagram corresponding to step S110 in fig. 2.
Fig. 4 is a schematic structural diagram corresponding to step S1201 in fig. 2.
Fig. 5 is a first schematic structural diagram corresponding to step S1202 in fig. 2.
Fig. 6 is a second schematic structural diagram corresponding to step S1202 in fig. 2.
Fig. 7 is a schematic structural diagram corresponding to step S1203 in fig. 2.
Fig. 8 is a schematic structural diagram corresponding to step S1204 in fig. 2.
Fig. 9 is a schematic structural diagram corresponding to step S1205 in fig. 2.
Fig. 10 is a schematic structural diagram corresponding to step S1206 in fig. 2.
Fig. 11 is a schematic structural diagram of an oxidation preventing layer in the manufacturing method of the array substrate of the present disclosure.
Fig. 12 is a schematic structural diagram of a thin film transistor of an array substrate according to the present disclosure.
Fig. 13 is a schematic structural diagram of a thin film transistor and a capacitor electrode of an array substrate according to the present disclosure.
Fig. 14 is a schematic structural diagram of a gate line and a signal line of an array substrate according to the present disclosure.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and the like. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.
Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.
The terms "the" and "said" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.
In this exemplary embodiment, first, a method for manufacturing an array substrate is provided, which may be used to manufacture an array substrate for a display device such as an OLED (Organic Light-Emitting Diode) display device or a liquid crystal display device, and as shown in fig. 1, the method for manufacturing an array substrate according to this embodiment may include the following steps:
step 110, forming a gate metal layer at least comprising a thin film transistor region and a power line region on a substrate;
step S120, forming a grid electrode in the thin film transistor area and a power line in the power line area through a composition process, wherein the thickness of the grid electrode is smaller than that of the power line;
step S130, forming a stacked gate insulating layer, an active layer, and a source-drain metal layer in the tft region by a patterning process to obtain a tft.
In the manufacturing method of the array substrate of the present embodiment, a gate electrode may be formed in the thin film transistor region and a power line may be formed in the power line region through a patterning process, and the thickness of the gate electrode is smaller than that of the power line. Therefore, the thickness of the power line can be prevented from being reduced, the line resistance and the voltage drop of the power line can be ensured, the thickness of the grid can be reduced, the phenomenon of 'hillock', namely 'hillock', can be prevented from occurring on the grid, and the normal work of the thin film transistor can be ensured. Therefore, the yield of products can be improved.
Next, each step of the method for manufacturing the array substrate in the present exemplary embodiment will be further described.
In step S110, as shown in fig. 3, a gate metal layer 2 including at least a thin film transistor region and a power line region is formed on a substrate 1.
In this embodiment, the gate metal layer 2 may be formed on the substrate by a chemical vapor deposition method, but not limited thereto, and other methods may be used to form the gate metal layer 2; the gate metal layer 2 can be divided into a plurality of regions, and at least comprises a thin film transistor region and a power line region; the gate of the thin film transistor may be located in the thin film transistor region, and the power line of the array substrate may be located in the power line region.
In step S120, as shown in fig. 10, a gate electrode 21 is formed in the tft region and a power line 22 is formed in the power line region through a patterning process, and a thickness of the gate electrode 21 is smaller than a thickness of the power line 22.
In this embodiment, the method of forming the gate electrode 21 and the power line 22 may use a halftone mask to form the gate electrode 21 in the tft region and form the power line 22 in the power line region through a patterning process. For example, as shown in fig. 2 and fig. 4 to fig. 7, the method for forming the gate electrode 21 and the power line 22 may include the following steps S1201 to S1206, but fig. 4 to fig. 7 are only schematic diagrams reflecting the processes of the gate electrode 21 and the power line 22 and the thickness relationship therebetween, and do not constitute a limitation on the positional relationship and the connection relationship thereof, wherein:
in step S1201, as shown in fig. 4, a photoresist layer 3 is coated on the gate metal layer 2.
The photoresist layer 3 may be a positive photoresist or a negative photoresist; and before coating the photoresist layer 3, the substrate 1 with the gate metal layer 2 can be cleaned to remove surface particles and avoid impurity interference.
In step S1202, as shown in fig. 5 and 6, the photoresist layer 3 is exposed and developed by using a halftone mask 4, so as to obtain at least a completely removed area, a reserved area corresponding to the power line area, and a semi-reserved area corresponding to the tft area; wherein fig. 5 shows the exposure of the photoresist layer 3 using a halftone mask 4; fig. 6 shows the photoresist layer 3 after development.
The half-tone mask 4 at least comprises a non-light-transmitting area, a full-light-transmitting area and a semi-light-transmitting area; if the photoresist layer 3 adopts positive photoresist, during exposure, the non-light-transmitting area corresponds to the power supply area, the semi-light-transmitting area corresponds to the thin film transistor area, and the full-light-transmitting area corresponds to an area which does not need to be reserved; the halftone mask 4 can be irradiated by ultraviolet light, so that the photoresist layer 3 in the non-light-transmitting area is insoluble in a developing solution, the photoresist layer 3 in the semi-light-transmitting area is not completely soluble in the developing solution, and the photoresist layer 3 in the full-light-transmitting area is completely soluble in the developing solution; after development by the developer, the above-described completely removed region, the remaining region, and the semi-remaining region are formed, and the thickness of the photoresist layer 3 of the remaining region is greater than that of the photoresist layer 3 of the semi-remaining region. If the photoresist layer 3 is made of negative photoresist, the positions of the non-light-transmitting region and the full-light-transmitting region of the halftone mask 4 are interchanged, and the specific principle is well known and will not be described in detail herein.
In step S1203, as shown in fig. 7, an etching process is used to remove the gate metal layer 2 exposed by the completely removed region.
The etching process may adopt dry etching or wet etching to remove the gate metal layer 2 exposed in the completely removed region, and the remaining region includes a thin film transistor region and a power line region.
In step S1204, as shown in fig. 8, an ashing process is used to remove the photoresist layer 3 in the semi-reserved region, so as to expose the gate metal layer 2 in the tft region.
Because the thickness of the photoresist layer 3 in the reserved area is greater than that of the photoresist layer 3 in the semi-reserved area, after the photoresist layer 3 in the semi-reserved area is removed, the photoresist layer 3 in the reserved area can be thinned, so that the gate metal layer 2 in the power line area is still covered by the photoresist layer 3, and the gate metal layer 2 in the thin film transistor area is exposed.
In step S1205, as shown in fig. 9, an etching process is used to thin the gate metal layer 2 in the tft region.
The thickness of the gate metal layer 2 in the thin film transistor area can be reduced by adopting dry etching or wet etching, and the gate metal layer 2 in the power line area cannot be reduced due to the coverage of the photoresist layer 3.
In step S1206, as shown in fig. 10, the photoresist layer 3 in the reserved area is removed by a lift-off process.
After step S1206 is completed, the gate electrode 21 and the power line 22 can be obtained, and the thickness of the gate electrode 21 is smaller than that of the power line 22, so as to prevent the gate electrode 21 from "hillock", avoid raising the line resistance of the power line 22, and be beneficial to ensuring the voltage drop of the power line 22.
It should be noted that the method for forming the gate electrode 21 in the thin film transistor region and forming the power line 22 in the power line region through the patterning process in steps S1201 to S1206 is only an exemplary illustration and does not limit the present disclosure, and other embodiments may also be adopted, which is not described herein again.
In step S130, as shown in fig. 12, a gate insulating layer 5, an active layer 6, and a source-drain metal layer 7 are stacked on the tft region through a patterning process to obtain a tft.
In this embodiment, the methods for forming the gate insulating layer 5, the active layer 6 and the source-drain metal layer 7 may refer to conventional methods in the art, and will not be described in detail herein.
In this embodiment, as shown in fig. 13, the gate metal layer 2 may further include a storage capacitor region, and the method for manufacturing the array substrate may further include:
forming a capacitance electrode 23 in the storage capacitance region by a patterning process, wherein the thickness of the capacitance electrode 23 is smaller than that of the power line 22; the thickness of the capacitor electrode 23 may be the same as the thickness of the gate 21, and the capacitor electrode 23 and the gate 21 may be formed by a one-step patterning process, and the specific process may refer to the steps S1201 to S1206, which is not described herein again; certainly, the thickness of the capacitor electrode 23 may also be greater than the gate 21, but less than the thickness of the power line 22, so as to avoid a "hillock" phenomenon at the capacitor electrode 23, which is beneficial to ensuring the normal operation of the storage capacitor, and further improving the yield of products.
In this embodiment, as shown in fig. 14, the gate metal layer 2 may further include a gate line region, and the method for manufacturing an array substrate may further include:
a gate line 24 is formed on the gate line region by a patterning process, the gate line 24 includes a crossing region crossing the signal line 8, and the thickness of the gate line 24 at the crossing region is smaller than that of the power line 22. The thickness of the gate line 24 in the intersection region may be the same as the thickness of the gate electrode 21, or the thickness of the other region of the gate line 24 may be the same as the thickness of the gate electrode 21; the signal line 8 may be used to input a driving signal to the thin film transistor.
The gate line 24 and the gate electrode 21 may be formed by a one-step patterning process, and the specific process may refer to the steps S1201 to S1206, which is not described herein again; of course, the thickness of the gate line 24 at the intersection region may be larger than the gate electrode 21, but smaller than the power line 22. Thereby avoiding the occurrence of a "hillock" phenomenon on the gate line 24 in the crossing region and preventing the gate line 24 and the signal line 8 from being short-circuited due to the "hillock" phenomenon; meanwhile, the thickness of the grid line 24 in the intersection area is reduced, so that the climbing difficulty of the signal line 8 in the intersection area can be reduced, the signal line 8 is prevented from being broken due to overlarge climbing gradient, the normal work of the signal line 8 and the grid line 24 is guaranteed, and the product yield is further improved.
In this embodiment, as shown in fig. 11 to 14, the method for manufacturing the array substrate may further include, after forming the gate electrode 21 and before forming the gate insulating layer 5:
forming an oxidation preventing layer 9 on the base substrate 1 including the gate electrode 21;
an anti-oxidation layer pattern is formed through a composition process, the anti-oxidation layer pattern at least covers a region of the gate metal layer 2, the thickness of which is less than that of the power line 22, and the sum of the thicknesses of the anti-oxidation layer 9 and the region of the gate metal layer 2, the thickness of which is less than that of the power line 22, is less than that of the power line 22.
The material of the oxidation preventing layer 9 may be a metal, such as molybdenum, but not limited thereto, and may be other conductive and non-oxidizable materials; the oxidation preventing layer pattern may cover not only the region of the gate metal layer 2 having a thickness smaller than that of the power line 22 but also other regions of the gate metal layer 2 remaining such as the power line 22. The region of the gate metal layer 2 having a thickness smaller than that of the power line 22 may include the gate electrode 21, the capacitor electrode 23, and the gate line 24 at the intersection region, so as to ensure that the respective thicknesses of the gate electrode 21, the capacitor electrode 23, and the gate line 24 at the intersection region are smaller than that of the power line 22 even after the anti-oxidation layer pattern is formed. The anti-oxidation layer pattern can prevent oxidation and further avoid the phenomenon of 'hillock'.
In this embodiment, the method of forming the oxidation preventing layer pattern by the patterning process may include:
after the step S1204 is completed and before the step S1205 is performed, depositing the oxidation preventing layer 9 once to cover the gate insulating layer 2;
after the above step S1206, the oxidation preventing layer 9 on the gate metal layer 2 in the area with the thickness smaller than that of the power line 22 is removed, the oxidation preventing layer 9 covering the gate insulating layer 2 may be deposited again, and the oxidation preventing layer 9 corresponding to the completely removed area in the step 1202 is removed by using a photolithography process to obtain an oxidation preventing layer pattern.
Of course, the method for forming the oxidation preventing layer pattern by the patterning process may also be: after the above step S1206 is completed, the oxidation preventing layer 9 covering the gate metal layer 2 is deposited, and the oxidation preventing layer 9 corresponding to the completely removed region in the step S1202 is removed by the photolithography process to obtain an oxidation preventing layer pattern.
It should be noted that although the various steps of the methods of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that these steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc.
The present exemplary embodiment also provides an array substrate, and as shown in fig. 11 to 14, the array substrate of the present exemplary embodiment may include a substrate 1, a power line 22, and a thin film transistor.
In the present embodiment, the power supply line 22 may be provided on the base substrate 1.
In this embodiment, the thin film transistor may be disposed on the substrate 1, and the thin film transistor may include a gate electrode 21, a gate insulating layer 5, an active layer 6, and a source-drain metal layer 7, where the gate electrode 21 and the power line 22 are disposed on the same layer, and the thickness of the gate electrode 21 is smaller than that of the power line 22.
In this embodiment, the array substrate may further include a storage capacitor, the storage capacitor includes a capacitor electrode 23, the capacitor electrode 23 is disposed on the substrate 1 and on the same layer as the gate 21, and a thickness of the capacitor electrode 23 is smaller than a thickness of the power line 22.
In this embodiment, the array substrate further includes a gate line 24 and a signal line 8, the gate line 24 may be disposed on the substrate 1 and disposed on the same layer as the gate electrode 21, and the gate line 24 includes a crossing region;
the signal line 8 may be disposed above the gate line 24 and cross the gate line at the crossing region, and the thickness of the gate line 24 at the crossing region is smaller than that of the power line 22; the signal line 8 may be used to input a driving signal to the thin film transistor.
In this embodiment, the array substrate may further include an anti-oxidation layer pattern, the anti-oxidation layer pattern may be disposed between the gate metal layer 2 and the gate insulating layer 5, the anti-oxidation layer pattern at least covers a region of the gate metal layer 2 with a thickness smaller than that of the power line 22, and a sum of thicknesses of the anti-oxidation layer 9 and the region of the gate metal layer 2 with a thickness smaller than that of the power line 22 is smaller than that of the power line 22.
It should be noted that, for details of each portion of the array substrate in the present exemplary embodiment, reference may be made to the above-mentioned embodiment of the manufacturing method of the array substrate, and details are not repeated here.
The present exemplary embodiment also provides a display device, and the display device of the present exemplary embodiment may include the array substrate described in any one of the above embodiments.
In the array substrate and the display device according to the exemplary embodiment of the present disclosure, since the thickness of the gate electrode 21 of the thin film transistor is smaller than the thickness of the power line 22, it is possible to avoid reducing the thickness of the power line 22, and to ensure the line resistance and the voltage drop of the power line 22, and to prevent a "hillock", i.e., "hillock", from occurring on the gate electrode 21 due to an excessively large thickness of the gate electrode 21, so as to ensure the normal operation of the thin film transistor. Therefore, the yield of products can be improved.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
Claims (10)
1. A method for manufacturing an array substrate includes:
forming a grid metal layer at least comprising a thin film transistor area and a power line area on a substrate;
forming a grid electrode in the thin film transistor area and a power line in the power line area through a composition process, wherein the thickness of the grid electrode is smaller than that of the power line;
forming an anti-oxidation layer on the substrate including the grid, wherein the thickness of the anti-oxidation layer is smaller than that of the grid metal layer;
forming an anti-oxidation layer pattern through a composition process, wherein the anti-oxidation layer pattern at least covers an area with the thickness smaller than that of the power line on the grid metal layer;
and forming a stacked gate insulating layer, an active layer and a source-drain metal layer in the thin film transistor area through a composition process to obtain the thin film transistor.
2. The method for manufacturing the array substrate according to claim 1, wherein the gate metal layer further comprises a storage capacitor region, and the method for manufacturing the array substrate further comprises:
and forming a capacitance electrode in the storage capacitance area through a composition process, wherein the thickness of the capacitance electrode is less than that of the power line.
3. The method for manufacturing the array substrate according to claim 1 or 2, wherein the gate metal layer further comprises a gate line region, and the method for manufacturing the array substrate further comprises:
and forming a grid line on the grid line region by a composition process, wherein the grid line comprises a crossing region which crosses the signal line, and the thickness of the grid line in the crossing region is smaller than that of the power line.
4. The method of claim 1, wherein a sum of thicknesses of any one of the oxidation preventing layer and the gate metal layer in a region having a thickness smaller than the power line is smaller than a thickness of the power line.
5. The method of claim 1, wherein the forming a gate in the thin film transistor region and a power line in the power line region comprises:
coating a photoresist layer on the grid metal layer;
exposing and developing the photoresist layer by adopting a half-tone mask plate to obtain at least a completely removed area, a reserved area corresponding to the power line area and a half-reserved area corresponding to the thin film transistor area;
removing the exposed gate metal layer in the completely removed region by adopting an etching process;
removing the photoresist in the semi-reserved area by adopting an ashing process to expose the gate metal layer in the thin film transistor area;
thinning the grid metal layer in the thin film transistor area by adopting an etching process;
and removing the photoresist layer of the reserved area by adopting a stripping process.
6. An array substrate, comprising:
a substrate base plate;
the power line is arranged on the substrate base plate;
the thin film transistor is arranged on the substrate and comprises a grid electrode, a grid insulation layer, an active layer and a source drain metal layer, the grid electrode and the power line are arranged on the same layer, and the thickness of the grid electrode is smaller than that of the power line;
and the anti-oxidation layer pattern is arranged between the grid electrode and the grid insulation layer, and the thickness of the anti-oxidation layer pattern is smaller than that of the grid electrode.
7. The array substrate of claim 6, further comprising:
the storage capacitor comprises a capacitor electrode, the capacitor electrode is arranged on the substrate and arranged on the same layer with the grid, and the thickness of the capacitor electrode is smaller than that of the power line.
8. The array substrate of claim 6 or 7, further comprising:
the grid line is arranged on the substrate and arranged on the same layer as the grid electrode, and comprises a cross region;
and the signal line is arranged above the grid line and is intersected with the grid line in the intersection region, and the thickness of the signal line and the grid line in the intersection region is smaller than that of the power line.
9. The array substrate of claim 8, wherein a sum of thicknesses of the oxidation prevention layer and the gate electrode is less than a thickness of the power line.
10. A display device, comprising:
an array substrate as claimed in any one of claims 6 to 9.
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| CN107579083A (en) * | 2017-09-30 | 2018-01-12 | 京东方科技集团股份有限公司 | Array base palte and preparation method and display device |
| CN109920801B (en) | 2019-03-11 | 2022-02-01 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| US11355576B2 (en) | 2020-04-01 | 2022-06-07 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Display panel and fabrication method thereof |
| CN111430420A (en) * | 2020-04-01 | 2020-07-17 | 武汉华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
| CN112151555A (en) * | 2020-09-25 | 2020-12-29 | 合肥鑫晟光电科技有限公司 | Array substrate, display panel, display device and manufacturing method |
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| JPH10307298A (en) * | 1997-05-08 | 1998-11-17 | Casio Comput Co Ltd | Liquid crystal display device |
| CN104022077A (en) * | 2014-05-27 | 2014-09-03 | 京东方科技集团股份有限公司 | Array substrate, preparing method thereof and display device |
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| KR20120061383A (en) * | 2010-12-03 | 2012-06-13 | 삼성전자주식회사 | Display device and method of manufacturing the same |
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| JPH10307298A (en) * | 1997-05-08 | 1998-11-17 | Casio Comput Co Ltd | Liquid crystal display device |
| CN104022077A (en) * | 2014-05-27 | 2014-09-03 | 京东方科技集团股份有限公司 | Array substrate, preparing method thereof and display device |
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