WO2015096393A1

WO2015096393A1 - Array substrate, manufacturing method therefor, and display device

Info

Publication number: WO2015096393A1
Application number: PCT/CN2014/078853
Authority: WO
Inventors: 崔承镇; 金熙哲; 宋泳锡; 刘圣烈
Original assignee: 京东方科技集团股份有限公司
Priority date: 2013-12-23
Filing date: 2014-05-29
Publication date: 2015-07-02
Also published as: CN103681489A; CN103681489B

Abstract

A method for manufacturing an array substrate. The method for manufacturing the array substrate comprises three masking processes, among which, the first masking process is used for forming a source electrode (6), a drain electrode (7), an active layer (8), and a pixel electrode (5) of a thin-film transistor in the array substrate, where the active layer (8) and the pixel electrode (5) are arranged in a same layer above the substrate (1), and the source electrode (6) and the drain electrode (7) are located above the active layer (8). Also provided are an array substrate and a display device.

Description

Array substrate, manufacturing method thereof, and display device

Technical field

Embodiments of the present disclosure relate to an array substrate, a method of manufacturing the same, and a display device.

Background technique

Liquid crystal display devices are widely used in televisions due to their small size, low power consumption, and low radiation. On monitors, laptops, tablets, etc.

At present, when manufacturing a twisted nematic (TN, Twisted Nematic) type array substrate, it is usually required To perform six mask processes, which are the gate, gate insulating layer, etch stop layer, source and drain metal The layer, the passivation layer, and the pixel electrode layer are patterned. For each masking process, manufacturing costs are required High masks also require process steps such as exposure, development, etching, ashing, etc. The array substrate manufacturing process is complicated and the production cost is high. Therefore, there is a need for a masking process that can reduce the masking process. Production method.

Summary of the invention

One technical problem to be solved by the present disclosure is the problem that the array substrate manufacturing process is complicated.

At least one embodiment of the present disclosure provides a method of fabricating an array substrate, including: a masking process, a second masking process, and a third masking process, wherein the first masking process is used for Forming a source, a drain, an active layer, and a pixel electrode of the thin film transistor in the array substrate, wherein The source layer and the pixel electrode are disposed on the substrate in the same layer, and the source and the drain are located on the active layer Above, the second mask process is used to form a source, a drain, and an active source covering the thin film transistor a layer and an insulating layer of the pixel electrode, and forming an opening in the insulating layer, the opening being located at Above the junction of the drain and the pixel electrode, the third masking process is used to form the source a gate above the insulating layer between the drain and the drain, and forming a contact electrode in the opening, The contact electrode electrically connects the drain and the pixel electrode.

In an embodiment of the present disclosure, the first mask process uses gray scales having three hues a mask, the gray mask having a first gray level in a region where the pixel electrode is to be formed, to be formed The region of the thin film transistor channel has a second gray scale, and has a third region in a region where the source and drain are to be formed Gray scale, wherein the first gray level is smaller than the second gray level, and the second gray level is smaller than the third gray level.

In an embodiment of the present disclosure, the active layer and the pixel electrode are oxidized by the same metal The layer is formed.

In one embodiment of the present disclosure, the metal oxide is IGZO or ITZO or IGZO A mixture with ITZO.

In an embodiment of the present disclosure, the first mask process includes: sequentially on a substrate Forming a metal oxide layer and a source/drain metal layer; then, forming a first photoresist on the base substrate a first lithography after exposing and developing the first photoresist layer by using the gradation mask The glue layer has a first thickness in a region where the pixel electrode is to be formed, in a region where a thin film transistor channel is to be formed The domain has a second thickness, and has a third thickness in a region where the source and the drain are to be formed, wherein the first thickness Less than the second thickness, the second thickness is less than the third thickness; etching away the gold not covered with the first photoresist layer Is an oxide layer and a source/drain metal layer; removing the first thickness of the first photoresist layer after exposure and development as a whole Thickness, exposing the area where the pixel electrode is to be formed; etching away the area where the pixel electrode is to be formed The source and drain metal layers expose the underlying metal oxide layer; the exposed metal oxide layer Performing plasma treatment to form a pixel electrode; and then removing the second thickness of the first photoresist layer as a whole Subtracting the thickness of the first thickness to expose the area of the thin film transistor channel to be formed; etching away the exposure The source and drain metal layers are formed to form the source and drain of the thin film transistor; the remaining first photolithography is removed Adhesive layer.

In an embodiment of the present disclosure, the plasma processing process and the first photoresist The process of removing the thickness of the second thickness as a whole from the thickness of the first thickness is simultaneously performed.

In an embodiment of the present disclosure, the second mask process includes: forming a cover film a source, a drain, an active layer of the transistor, and an insulating layer of the pixel electrode; forming a shape on the insulating layer Forming a second photoresist layer; exposing the second photoresist layer with a monotone mask to remove a second photoresist layer above the junction of the drain and the pixel electrode; the exposed insulation The layer is etched to form a boundary between the drain and the pixel electrode on the insulating layer An opening above to expose a portion of the drain and pixel electrodes below it; remove the remaining second Photoresist layer.

In an embodiment of the present disclosure, the third mask process includes: forming on the entire substrate a gate metal layer covering the insulating layer and filling the opening; forming on the gate metal layer a third photoresist layer; exposing the third photoresist layer using a monotone mask to retain only a region of the gate to be formed and a third photoresist layer over the opening; the exposed gate gold The genus layer is etched and the remaining third photoresist layer is removed to form a gate and electrically connect the drain And a contact electrode of the pixel electrode.

At least one embodiment of the present disclosure also provides an array substrate, including: a substrate; formed in An active layer and a pixel electrode above the substrate, wherein the active layer and the pixel electrode are disposed in the same layer; Forming a source and a drain over the active layer; covering the substrate, the source, the drain, and the active layer And an insulating layer of the pixel electrode, the insulating layer having a boundary above the drain and the pixel electrode An opening; a gate formed over the insulating layer and between the source and the drain; formed in The opening is electrically connected to the drain and the contact electrode of the pixel electrode.

According to an embodiment of the present disclosure, the active layer and the pixel electrode are oxidized by the same metal The layer is formed.

According to an embodiment of the present disclosure, the metal oxide is IGZO or ITZO or IGZO A mixture with ITZO.

At least one embodiment of the present disclosure also provides a display device including the above array substrate.

By adopting the array substrate manufacturing method disclosed in the present disclosure, the system of the array substrate is greatly reduced The manufacturing process steps reduce the manufacturing cost of the array substrate.

DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will be made for the drawings of the embodiments. Briefly, it will be apparent that the drawings in the following description relate only to some embodiments of the invention. Rather than limiting the invention.

1 shows a flow chart of a method of fabricating an array substrate in accordance with an embodiment of the present invention;

2 shows a flow chart of a method of fabricating an array substrate in accordance with an embodiment of the present invention;

3-18 illustrate steps formed in various steps of an array substrate manufacturing method according to an embodiment of the present invention. A schematic diagram of a structure in which FIG. 18 shows a schematic view of an array substrate in accordance with an embodiment of the present invention.

detailed description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the following will be The technical solutions of the embodiments of the present disclosure are clearly and completely described in the drawings of the embodiments. Obviously, The described embodiments are a part of the embodiments of the present disclosure, and not all of the embodiments. Based on the description The embodiments of the present disclosure are obtained by those skilled in the art without creative labor. All other embodiments are within the scope of the disclosure.

FIG. 1 illustrates a flow chart of a method of fabricating an array substrate in accordance with an embodiment of the present disclosure. As shown in Figure 1 It is shown that the array substrate manufacturing method according to the embodiment of the present invention adopts three mask processes in total, compared to the invention. The six mask processes required to make twisted nematic array substrates are reduced by three, reducing The manufacturing process steps of the array substrate reduce the manufacturing cost of the array substrate.

A method of manufacturing an array substrate according to an embodiment of the present disclosure includes:

a first masking process P1 for forming a thin film in the array substrate a source, a drain, an active layer, and a pixel electrode of the transistor, wherein the active layer and the pixel electrode The same layer is disposed above the substrate, and the source and the drain are located above the active layer;

a second mask process P2 for forming a source covering the thin film transistor a drain electrode, an active layer, and an insulating layer of the pixel electrode, and for forming an opening on the insulating layer a port, the opening being located above a boundary between the drain and the pixel electrode;

a third mask process P3 for forming between the source and the drain a gate above the insulating layer and used to form a contact electrode in the opening such that The drain is electrically connected to the pixel electrode.

An array base according to an embodiment of the present invention shown in FIG. 2 will be described below with reference to FIGS. 3 through 18. Flow chart of the board manufacturing method.

In step S1, a metal oxide layer 2 and a source/drain metal layer 3 are sequentially formed on the substrate 1, such as Figure 3 shows. Metal oxide layer is oxidized by IGZO, ITZO or other metals with semiconducting properties Composition, or composition of IGZO, ITZO or other metal oxides having semiconducting properties The source/drain metal layer is made of a metal such as copper, aluminum or molybdenum. Forming gold by means such as deposition It belongs to oxide layer 2 and source/drain metal layer 3.

Next, in step S2, a first photoresist layer is first coated on the source/drain metal layer 3, The photoresist layer is then exposed using a grayscale mask consisting of three shades. Grayscale mask The film plate has a first gray level in a region where the pixel electrode is to be formed, in a region where a thin film transistor channel is to be formed The domain has a second gray level, and has a third gray level in a region where the source and the drain are to be formed, wherein the first gray level Less than the second gradation, the second gradation is smaller than the third gradation. For example, the third gradation is a full tone. Figure 4 The structure of the first photoresist layer 4 after exposure and development through the gray mask is shown, the first photoresist layer 4 having a first thickness d1 in a region where the pixel electrode is to be formed, in a region where a thin film transistor channel is to be formed The domain has a second thickness d2, and has a third thickness d3 in a region where the source and the drain are to be formed, wherein the first The thickness d1 is smaller than the second thickness d2, and the second thickness d2 is smaller than the third thickness d3.

Next, in step S3, a first etching process is performed to etch away the outside of the pixel area. The metal oxide layer 2 and the source/drain metal layer 3 covered with the first photoresist layer are covered. Figure 5 shows at this time Schematic diagram of the structure formed after the etching process is completed.

Next, in step S4, a portion of the photoresist layer is removed, for example, by a process such as ashing. FIG. 6 is a schematic view showing a structure formed after completion of the ashing process, wherein the first photoresist layer The thickness of the first thickness is removed as a whole, thereby exposing the area where the pixel electrode is to be formed.

Next, in step S5, a second etching process is performed to etch away the exposed source and drain gold. The layer 3, that is, the portion of the region where the source/drain metal layer is to be formed with the pixel electrode is etched away, thereby exposing Metal oxide layer 2. Figure 7 shows a schematic view of the structure formed after the completion of the etching process.

Next, in step S6, the exposed metal oxide layer is subjected to plasma treatment so that The portion of the metal oxide layer is electrically conductive such that the portion of the metal oxide layer is used as a pixel Extreme 5. The plasma treatment process is carried out in a drying apparatus. For metal oxidation of IGZO, ITZO, etc. The object itself is transparent, and the pixel electrode thus fabricated is also transparent. Figure 8 shows the shape Schematic diagram of the structure formed after forming a pixel electrode.

Next, in step S7, for example, the first light is removed again by a process such as ashing. Part of the engraved layer. Figure 9 is a schematic view showing the structure formed after the completion of the ashing process, The first photoresist layer is entirely removed from the second thickness minus the thickness of the first thickness, ie, after passing through After the secondary ashing process, the portion of the first photoresist layer having the second thickness is completely removed, and exposed The area where the thin film transistor channel is to be formed. For example, the ashing process in step S7 and the step S6 The plasma treatment process is carried out simultaneously in the drying apparatus.

Next, in step S8, a third etching process is performed to etch away the exposed source and drain gold. Layer 3, thereby forming source 6 and drain 7, and the metal oxide layer under source 6 and drain 7 is The active layer 8 of the thin film transistor. For example, the source/drain metal layer is copper and the metal oxide layer is IGZO, Etching the source/drain metal layer does not affect the underlying metal oxide layer. When the source leaks gold When the genus layer is aluminum or molybdenum, a metal oxide layer which is not affected by the etching of aluminum or molybdenum should be selected to avoid Damage to the performance of the active layer. Figure 10 shows an outline of the structure formed after the completion of the etching process. Figure.

Then, in step S9, the remaining first photoresist layer is removed, and FIG. 11 shows the step. Schematic diagram of the structure formed after S9. This completes the first mask process.

Next, the second mask process will be explained. In step S10, such as deposition is employed on the substrate 1. The insulating layer 9 is formed by a process to cover the substrate 1, the source 6, the drain 7, the active layer 8, and the pixel electrode 5. The structure obtained is shown in FIG.

Next, in step S11, the second photoresist layer 10 is coated on the insulating layer 9, and the single layer is used. The color mask mask exposes the second photoresist layer 10 to remove the boundary between the drain electrode 7 and the pixel electrode 5 a second photoresist layer above. Figure 13 shows the second photoresist layer 10 after exposure and development is completed. pattern.

Next, in step S12, the exposed insulating layer 9 is etched to expose the underside a portion of the drain 7 and the pixel electrode 5 so as to be above the junction of the drain 7 and the pixel electrode 5 An opening is formed, and the resulting structure is as shown in FIG.

Next, in step S13, the remaining second photoresist layer is removed, and the formed structure is as Figure 15 shows. This completes the second mask process.

Next, in step S14, for example, a gate is formed on the substrate 1 by a deposition method. a metal layer 11 covering the insulating layer 9 and filling the opening formed in the step S13, the formed junction The structure is shown in Figure 16.

Next, in step S15, a third photoresist layer 12 is coated on the gate metal layer 11, and Exposing the third photoresist layer 12 with a monotone mask to retain only the region where the gate is to be formed The domain, and the third photoresist layer 12 over the opening formed in step S13. Figure 17 shows the exposure The pattern of the photoresist layer 12 after the light development is completed.

Finally, in step S16, the gate metal layer 11 is etched, and the remaining third is removed. a photoresist layer 12 to form a gate electrode 13 and a contact electrode 14 for using the drain electrode 7 and the image The element electrodes 5 are electrically connected. This completes the fabrication of the entire array substrate. Figure 18 shows the final formation The structure of the array substrate.

As shown in FIG. 18, the array substrate according to the present invention includes: a substrate 1; formed above the substrate 1. The active layer 8 and the pixel electrode 5, the active layer 8 and the pixel electrode 5 are disposed in the same layer and are made of the same metal Oxide formation, metal oxide in active layer 8 has semiconductor properties, gold in pixel electrode 5 The oxide is subjected to plasma treatment and has a conductor property, and the metal oxide layer may be IGZO or ITZO or a mixture of IGZO and ITZO. A source 6 and a drain 7 are formed over the active layer 8, the source The pole 6, the drain 7 and the active layer 8 are electrically insulated from the gate 13 by the insulating layer 9 thereon, thereby forming a thin Membrane transistor. The insulating layer 9 covers the substrate 1, the source 6, the drain 7, the active layer 8, and the pixel electrode 5, And having an opening above the boundary between the drain electrode 7 and the pixel electrode 5, and the contact electrode 14 is formed at the opening Inside, the drain 7 and the pixel electrode 5 are electrically connected.

By adopting the array substrate manufacturing method disclosed by the invention, the system of the array substrate is greatly reduced The manufacturing process steps reduce the manufacturing cost of the array substrate.

The above description is only an exemplary embodiment of the present invention, and is not intended to limit the protection of the present invention. The scope of the invention is defined by the appended claims.

This application claims the Chinese Patent Application No. 201310718064.0 submitted on December 23, 2013. The priority of the above-mentioned Chinese Patent Application is hereby incorporated by reference in its entirety in its entirety in its entirety. section.

Claims

A method of manufacturing an array substrate, comprising: a first mask process, a second mask process, and a              Three mask processes, wherein:

The first mask process is used to form a source and a drain of a thin film transistor in the array substrate,              An active layer and a pixel electrode, wherein the active layer and the pixel electrode are disposed on the substrate in the same layer,              The source and drain are located above the active layer;

The second mask process is used to form a source, a drain, and an active layer covering the thin film transistor              And an insulating layer of the pixel electrode, and for forming an opening in the insulating layer, the opening is located              The drain is above the junction with the pixel electrode;

The third masking process is for forming the insulating layer between the source and the drain              a top gate and for forming a contact electrode in the opening for the drain and the image              The element electrodes are electrically connected.
The method of claim 1 wherein said first masking process employs three a tone grayscale mask having a first gray level in a region where a pixel electrode is to be formed (g1), having a second gradation (g2) in a region where a thin film transistor channel is to be formed, in a source to be formed The regions of the pole and the drain have a third gray level (g3), wherein the first gray level (g1) is smaller than the second gray level (g2), The second gray level (g2) is smaller than the third gray level (g3).
The method according to claim 1 or 2, wherein said active layer and said pixel electrode Formed from the same metal oxide layer.
The method according to claim 3, wherein said metal oxide is IGZO or ITZO Or a mixture of IGZO and ITZO.
The method of claim 3 wherein said first masking process comprises:

Forming a metal oxide layer and a source/drain metal layer sequentially on the substrate;

Forming a first photoresist layer on the source/drain metal layer;

First photolithography after exposing and developing the first photoresist layer by using the grayscale mask              The adhesive layer has a first thickness (d1) in a region where the pixel electrode is to be formed, in which a thin film transistor trench is to be formed              The region of the track has a second thickness (d2) having a third thickness (d3) in the region where the source and drain are to be formed,              Wherein the first thickness (d1) is smaller than the second thickness (d2), and the second thickness (d2) is smaller than the third thickness (d3);

Etching away the metal oxide layer and the source/drain metal layer not covered with the first photoresist layer;

Removing the thickness of the first thickness (d1) from the first photoresist layer after exposure and development, and exposing              An area where the pixel electrode is to be formed;

Etching away the source/drain metal layer in the region where the pixel electrode is to be formed to expose the metal underneath              Oxide layer

Plasma treatment of the exposed metal oxide layer to form a pixel electrode;

Removing the first thickness of the first photoresist layer from the thickness of the first thickness (d2-d1) as a whole              Exposing a region of a thin film transistor channel to be formed;

Etching off the exposed source and drain metal layers to form the source and drain of the thin film transistor;

The remaining first photoresist layer is removed.
The method of claim 5 wherein said plasma processing process is said to be first The process of removing the second thickness from the entire thickness of the photoresist layer minus the thickness of the first thickness (d2-d1) is simultaneously performed.
The method according to any one of claims 1 to 6, wherein said second masking process              include:

Forming an insulation covering a source, a drain, an active layer, and the pixel electrode of the thin film transistor              Floor;

Forming a second photoresist layer on the insulating layer;

Exposing the second photoresist layer with a monotone mask to remove the drain and              a second photoresist layer above the intersection of the pixel electrodes;

Etching the exposed insulating layer, forming a drain at the drain in the insulating layer              An opening above the junction of the pixel electrode to expose a drain and a portion of the pixel electrode therebelow              Minute;

The remaining second photoresist layer is removed.
The method according to any one of claims 1 to 7, wherein said third masking process              include:

Forming a gate metal layer on the entire substrate to cover the insulating layer and filling the opening;

Forming a third photoresist layer on the gate metal layer;

Exposing the third photoresist layer with a monotone mask to retain only the gate to be formed              And a third photoresist layer over the opening;

Etching the exposed gate metal layer and removing the remaining third photoresist layer to              A gate electrode and a contact electrode are formed, the contact electrode electrically connecting the drain electrode and the pixel electrode.
An array substrate comprising:

Substrate

An active layer and a pixel electrode formed over the substrate, the active layer and the pixel electrode              Same layer setting;

Forming a source and a drain above the active layer;

An insulating layer covering the substrate, the source, the drain, the active layer, and the pixel electrode, the insulating layer              Having an opening above a boundary between the drain and the pixel electrode;

Forming a gate over the insulating layer between the source and the drain;

A contact electrode formed in the opening to electrically connect the drain and the pixel electrode.
The array substrate according to claim 9, wherein said active layer and said pixel electrode Formed from the same metal oxide layer.
The array substrate according to claim 10, wherein said metal oxide is IGZO or ITZO or a mixture of IGZO and ITZO.
A display device comprising the array substrate of any one of claims 9 to 11.