WO2015096393A1 - Substrat de réseau, son procédé de fabrication et dispositif d'affichage - Google Patents

Substrat de réseau, son procédé de fabrication et dispositif d'affichage Download PDF

Info

Publication number
WO2015096393A1
WO2015096393A1 PCT/CN2014/078853 CN2014078853W WO2015096393A1 WO 2015096393 A1 WO2015096393 A1 WO 2015096393A1 CN 2014078853 W CN2014078853 W CN 2014078853W WO 2015096393 A1 WO2015096393 A1 WO 2015096393A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
drain
pixel electrode
source
thickness
Prior art date
Application number
PCT/CN2014/078853
Other languages
English (en)
Chinese (zh)
Inventor
崔承镇
金熙哲
宋泳锡
刘圣烈
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2015096393A1 publication Critical patent/WO2015096393A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Definitions

  • Embodiments of the present disclosure relate to an array substrate, a method of manufacturing the same, and a display device.
  • Liquid crystal display devices are widely used in televisions due to their small size, low power consumption, and low radiation. On monitors, laptops, tablets, etc.
  • One technical problem to be solved by the present disclosure is the problem that the array substrate manufacturing process is complicated.
  • At least one embodiment of the present disclosure provides a method of fabricating an array substrate, including: a masking process, a second masking process, and a third masking process, wherein the first masking process is used for Forming a source, a drain, an active layer, and a pixel electrode of the thin film transistor in the array substrate, wherein The source layer and the pixel electrode are disposed on the substrate in the same layer, and the source and the drain are located on the active layer
  • the second mask process is used to form a source, a drain, and an active source covering the thin film transistor a layer and an insulating layer of the pixel electrode, and forming an opening in the insulating layer, the opening being located at Above the junction of the drain and the pixel electrode
  • the third masking process is used to form the source a gate above the insulating layer between the drain and the drain, and forming a contact electrode in the opening, The contact electrode electrically connects the drain and the pixel electrode.
  • the first mask process uses gray scales having three hues a mask, the gray mask having a first gray level in a region where the pixel electrode is to be formed, to be formed
  • the region of the thin film transistor channel has a second gray scale, and has a third region in a region where the source and drain are to be formed Gray scale, wherein the first gray level is smaller than the second gray level, and the second gray level is smaller than the third gray level.
  • the active layer and the pixel electrode are oxidized by the same metal
  • the layer is formed.
  • the metal oxide is IGZO or ITZO or IGZO A mixture with ITZO.
  • the first mask process includes: sequentially on a substrate Forming a metal oxide layer and a source/drain metal layer; then, forming a first photoresist on the base substrate a first lithography after exposing and developing the first photoresist layer by using the gradation mask
  • the glue layer has a first thickness in a region where the pixel electrode is to be formed, in a region where a thin film transistor channel is to be formed
  • the domain has a second thickness, and has a third thickness in a region where the source and the drain are to be formed, wherein the first thickness Less than the second thickness, the second thickness is less than the third thickness; etching away the gold not covered with the first photoresist layer Is an oxide layer and a source/drain metal layer; removing the first thickness of the first photoresist layer after exposure and development as a whole Thickness, exposing the area where the pixel electrode is to be formed; etching away the area where the pixel electrode is to be formed
  • the plasma processing process and the first photoresist The process of removing the thickness of the second thickness as a whole from the thickness of the first thickness is simultaneously performed.
  • the second mask process includes: forming a cover film a source, a drain, an active layer of the transistor, and an insulating layer of the pixel electrode; forming a shape on the insulating layer Forming a second photoresist layer; exposing the second photoresist layer with a monotone mask to remove a second photoresist layer above the junction of the drain and the pixel electrode; the exposed insulation The layer is etched to form a boundary between the drain and the pixel electrode on the insulating layer An opening above to expose a portion of the drain and pixel electrodes below it; remove the remaining second Photoresist layer.
  • the third mask process includes: forming on the entire substrate a gate metal layer covering the insulating layer and filling the opening; forming on the gate metal layer a third photoresist layer; exposing the third photoresist layer using a monotone mask to retain only a region of the gate to be formed and a third photoresist layer over the opening; the exposed gate gold The genus layer is etched and the remaining third photoresist layer is removed to form a gate and electrically connect the drain And a contact electrode of the pixel electrode.
  • At least one embodiment of the present disclosure also provides an array substrate, including: a substrate; formed in An active layer and a pixel electrode above the substrate, wherein the active layer and the pixel electrode are disposed in the same layer; Forming a source and a drain over the active layer; covering the substrate, the source, the drain, and the active layer And an insulating layer of the pixel electrode, the insulating layer having a boundary above the drain and the pixel electrode An opening; a gate formed over the insulating layer and between the source and the drain; formed in The opening is electrically connected to the drain and the contact electrode of the pixel electrode.
  • the active layer and the pixel electrode are oxidized by the same metal
  • the layer is formed.
  • the metal oxide is IGZO or ITZO or IGZO A mixture with ITZO.
  • At least one embodiment of the present disclosure also provides a display device including the above array substrate.
  • the system of the array substrate is greatly reduced
  • the manufacturing process steps reduce the manufacturing cost of the array substrate.
  • FIG. 1 shows a flow chart of a method of fabricating an array substrate in accordance with an embodiment of the present invention
  • FIG. 2 shows a flow chart of a method of fabricating an array substrate in accordance with an embodiment of the present invention
  • FIG. 18 illustrate steps formed in various steps of an array substrate manufacturing method according to an embodiment of the present invention.
  • FIG. 18 shows a schematic view of an array substrate in accordance with an embodiment of the present invention.
  • FIG. 1 illustrates a flow chart of a method of fabricating an array substrate in accordance with an embodiment of the present disclosure.
  • the array substrate manufacturing method according to the embodiment of the present invention adopts three mask processes in total, compared to the invention.
  • the six mask processes required to make twisted nematic array substrates are reduced by three, reducing
  • the manufacturing process steps of the array substrate reduce the manufacturing cost of the array substrate.
  • a first masking process P1 for forming a thin film in the array substrate a source, a drain, an active layer, and a pixel electrode of the transistor, wherein the active layer and the pixel electrode The same layer is disposed above the substrate, and the source and the drain are located above the active layer;
  • a second mask process P2 for forming a source covering the thin film transistor a drain electrode, an active layer, and an insulating layer of the pixel electrode, and for forming an opening on the insulating layer a port, the opening being located above a boundary between the drain and the pixel electrode;
  • FIG. 2 An array base according to an embodiment of the present invention shown in FIG. 2 will be described below with reference to FIGS. 3 through 18. Flow chart of the board manufacturing method.
  • a metal oxide layer 2 and a source/drain metal layer 3 are sequentially formed on the substrate 1, such as Figure 3 shows.
  • Metal oxide layer is oxidized by IGZO, ITZO or other metals with semiconducting properties Composition, or composition of IGZO, ITZO or other metal oxides having semiconducting properties
  • the source/drain metal layer is made of a metal such as copper, aluminum or molybdenum. Forming gold by means such as deposition It belongs to oxide layer 2 and source/drain metal layer 3.
  • a first photoresist layer is first coated on the source/drain metal layer 3, The photoresist layer is then exposed using a grayscale mask consisting of three shades.
  • Grayscale mask The film plate has a first gray level in a region where the pixel electrode is to be formed, in a region where a thin film transistor channel is to be formed.
  • the domain has a second gray level, and has a third gray level in a region where the source and the drain are to be formed, wherein the first gray level Less than the second gradation, the second gradation is smaller than the third gradation.
  • the third gradation is a full tone.
  • Figure 4 The structure of the first photoresist layer 4 after exposure and development through the gray mask is shown, the first photoresist layer 4 having a first thickness d1 in a region where the pixel electrode is to be formed, in a region where a thin film transistor channel is to be formed
  • the domain has a second thickness d2, and has a third thickness d3 in a region where the source and the drain are to be formed, wherein the first The thickness d1 is smaller than the second thickness d2, and the second thickness d2 is smaller than the third thickness d3.
  • step S3 a first etching process is performed to etch away the outside of the pixel area.
  • the metal oxide layer 2 and the source/drain metal layer 3 covered with the first photoresist layer are covered.
  • Figure 5 shows at this time Schematic diagram of the structure formed after the etching process is completed.
  • step S4 a portion of the photoresist layer is removed, for example, by a process such as ashing.
  • FIG. 6 is a schematic view showing a structure formed after completion of the ashing process, wherein the first photoresist layer The thickness of the first thickness is removed as a whole, thereby exposing the area where the pixel electrode is to be formed.
  • step S5 a second etching process is performed to etch away the exposed source and drain gold.
  • the layer 3, that is, the portion of the region where the source/drain metal layer is to be formed with the pixel electrode is etched away, thereby exposing Metal oxide layer 2.
  • Figure 7 shows a schematic view of the structure formed after the completion of the etching process.
  • step S6 the exposed metal oxide layer is subjected to plasma treatment so that The portion of the metal oxide layer is electrically conductive such that the portion of the metal oxide layer is used as a pixel Extreme 5.
  • the plasma treatment process is carried out in a drying apparatus.
  • the object itself is transparent, and the pixel electrode thus fabricated is also transparent.
  • Figure 8 shows the shape Schematic diagram of the structure formed after forming a pixel electrode.
  • step S7 for example, the first light is removed again by a process such as ashing. Part of the engraved layer.
  • Figure 9 is a schematic view showing the structure formed after the completion of the ashing process, The first photoresist layer is entirely removed from the second thickness minus the thickness of the first thickness, ie, after passing through After the secondary ashing process, the portion of the first photoresist layer having the second thickness is completely removed, and exposed The area where the thin film transistor channel is to be formed.
  • the ashing process in step S7 and the step S6 The plasma treatment process is carried out simultaneously in the drying apparatus.
  • step S8 a third etching process is performed to etch away the exposed source and drain gold.
  • Layer 3, thereby forming source 6 and drain 7, and the metal oxide layer under source 6 and drain 7 is The active layer 8 of the thin film transistor.
  • the source/drain metal layer is copper and the metal oxide layer is IGZO, Etching the source/drain metal layer does not affect the underlying metal oxide layer.
  • the source leaks gold
  • the genus layer is aluminum or molybdenum
  • a metal oxide layer which is not affected by the etching of aluminum or molybdenum should be selected to avoid Damage to the performance of the active layer.
  • Figure 10 shows an outline of the structure formed after the completion of the etching process. Figure.
  • step S9 the remaining first photoresist layer is removed, and FIG. 11 shows the step. Schematic diagram of the structure formed after S9. This completes the first mask process.
  • step S10 such as deposition is employed on the substrate 1.
  • the insulating layer 9 is formed by a process to cover the substrate 1, the source 6, the drain 7, the active layer 8, and the pixel electrode 5. The structure obtained is shown in FIG.
  • step S11 the second photoresist layer 10 is coated on the insulating layer 9, and the single layer is used.
  • the color mask mask exposes the second photoresist layer 10 to remove the boundary between the drain electrode 7 and the pixel electrode 5 a second photoresist layer above.
  • Figure 13 shows the second photoresist layer 10 after exposure and development is completed. pattern.
  • step S12 the exposed insulating layer 9 is etched to expose the underside a portion of the drain 7 and the pixel electrode 5 so as to be above the junction of the drain 7 and the pixel electrode 5 An opening is formed, and the resulting structure is as shown in FIG.
  • step S13 the remaining second photoresist layer is removed, and the formed structure is as Figure 15 shows. This completes the second mask process.
  • step S14 for example, a gate is formed on the substrate 1 by a deposition method.
  • a metal layer 11 covering the insulating layer 9 and filling the opening formed in the step S13, the formed junction
  • the structure is shown in Figure 16.
  • step S15 a third photoresist layer 12 is coated on the gate metal layer 11, and Exposing the third photoresist layer 12 with a monotone mask to retain only the region where the gate is to be formed The domain, and the third photoresist layer 12 over the opening formed in step S13.
  • Figure 17 shows the exposure The pattern of the photoresist layer 12 after the light development is completed.
  • step S16 the gate metal layer 11 is etched, and the remaining third is removed. a photoresist layer 12 to form a gate electrode 13 and a contact electrode 14 for using the drain electrode 7 and the image The element electrodes 5 are electrically connected. This completes the fabrication of the entire array substrate.
  • Figure 18 shows the final formation The structure of the array substrate.
  • the array substrate according to the present invention includes: a substrate 1; formed above the substrate 1.
  • the active layer 8 and the pixel electrode 5, the active layer 8 and the pixel electrode 5 are disposed in the same layer and are made of the same metal Oxide formation, metal oxide in active layer 8 has semiconductor properties, gold in pixel electrode 5
  • the oxide is subjected to plasma treatment and has a conductor property, and the metal oxide layer may be IGZO or ITZO or a mixture of IGZO and ITZO.
  • a source 6 and a drain 7 are formed over the active layer 8, the source The pole 6, the drain 7 and the active layer 8 are electrically insulated from the gate 13 by the insulating layer 9 thereon, thereby forming a thin Membrane transistor.
  • the insulating layer 9 covers the substrate 1, the source 6, the drain 7, the active layer 8, and the pixel electrode 5, And having an opening above the boundary between the drain electrode 7 and the pixel electrode 5, and the contact electrode 14 is formed at the opening Inside, the drain 7 and the pixel electrode 5 are electrically connected.
  • the system of the array substrate is greatly reduced
  • the manufacturing process steps reduce the manufacturing cost of the array substrate.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Thin Film Transistor (AREA)

Abstract

La présente invention concerne un procédé de fabrication d'un substrat de réseau. Ledit procédé de fabrication du substrat de réseau comprend trois opérations de masquage, la première opération de masquage étant destinée à former une électrode source (6), une électrode drain (7), une couche active (8) et une électrode de pixel (5) d'un transistor à couches minces dans le substrat de réseau, ladite couche active (8) et ladite électrode de pixel (5) étant agencées dans une même couche au-dessus du substrat (1), l'électrode source (6) et l'électrode drain (7) étant quant à elles disposées au-dessus de la couche active (8). L'invention concerne en outre un substrat de réseau et un dispositif d'affichage.
PCT/CN2014/078853 2013-12-23 2014-05-29 Substrat de réseau, son procédé de fabrication et dispositif d'affichage WO2015096393A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310718064.0A CN103681489B (zh) 2013-12-23 2013-12-23 阵列基板及其制造方法、显示装置
CN201310718064.0 2013-12-23

Publications (1)

Publication Number Publication Date
WO2015096393A1 true WO2015096393A1 (fr) 2015-07-02

Family

ID=50318627

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/078853 WO2015096393A1 (fr) 2013-12-23 2014-05-29 Substrat de réseau, son procédé de fabrication et dispositif d'affichage

Country Status (2)

Country Link
CN (1) CN103681489B (fr)
WO (1) WO2015096393A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681489B (zh) * 2013-12-23 2016-01-06 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置
CN107887398B (zh) * 2017-11-14 2022-01-21 京东方科技集团股份有限公司 阵列基板及其制备方法、显示面板以及显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1992236A (zh) * 2005-12-29 2007-07-04 Lg.菲利浦Lcd株式会社 薄膜晶体管阵列基板及其制造方法
CN102681277A (zh) * 2012-04-16 2012-09-19 京东方科技集团股份有限公司 阵列基板及其制造方法和液晶显示面板
CN103456742A (zh) * 2013-08-27 2013-12-18 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN103681489A (zh) * 2013-12-23 2014-03-26 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007333808A (ja) * 2006-06-12 2007-12-27 Mitsubishi Electric Corp アクティブマトリクス表示装置
JP5235363B2 (ja) * 2007-09-04 2013-07-10 株式会社ジャパンディスプレイイースト 液晶表示装置
JP2010204338A (ja) * 2009-03-03 2010-09-16 Seiko Epson Corp 電気光学装置および電子機器
CN102651403A (zh) * 2012-04-16 2012-08-29 京东方科技集团股份有限公司 薄膜晶体管、阵列基板及其制造方法和显示面板
CN103018974B (zh) * 2012-11-30 2016-05-25 京东方科技集团股份有限公司 液晶显示装置、多晶硅阵列基板及制作方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1992236A (zh) * 2005-12-29 2007-07-04 Lg.菲利浦Lcd株式会社 薄膜晶体管阵列基板及其制造方法
CN102681277A (zh) * 2012-04-16 2012-09-19 京东方科技集团股份有限公司 阵列基板及其制造方法和液晶显示面板
CN103456742A (zh) * 2013-08-27 2013-12-18 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN103681489A (zh) * 2013-12-23 2014-03-26 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置

Also Published As

Publication number Publication date
CN103681489B (zh) 2016-01-06
CN103681489A (zh) 2014-03-26

Similar Documents

Publication Publication Date Title
WO2017054384A1 (fr) Substrat matriciel, son procédé de fabrication et écran d'affichage
US9716110B2 (en) Array substrate, method for manufacturing the same, and display device
WO2014127587A1 (fr) Substrat de matrice et procédé de fabrication associé, et dispositif d'affichage
CN103715137B (zh) 阵列基板及其制造方法、显示装置
WO2017008497A1 (fr) Procédé de fabrication d'un transistor à couches minces d'oxyde
WO2014124568A1 (fr) Transistor à couche mince, substrat de matrice, procédé de fabrication et dispositif d'affichage
JP2008040502A (ja) 薄膜トランジスタｌｃｄ画素ユニットおよびその製造方法
WO2017118073A1 (fr) Substrat matriciel et son procédé de préparation et appareil d'affichage
WO2017024640A1 (fr) Substrat de matrice et procédé de fabrication associé
WO2015149469A1 (fr) Procédé de préparation d'un substrat de réseau, substrat de réseau et dispositif d'affichage
WO2013181909A1 (fr) Transistor en couche mince et substrat à réseau et procédés de fabrication de ceux-ci
WO2014005404A1 (fr) Procédé de fabrication de transistor en couches minces et procédé de fabrication de substrat de réseau
TW201418855A (zh) 顯示面板之陣列基板及其製作方法
JP6188793B2 (ja) Ｔｆｔアレイ基板及びその製造方法、表示装置
WO2018205886A1 (fr) Transistor à couches minces et son procédé de fabrication, substrat de réseau et appareil d'affichage
WO2014015628A1 (fr) Substrat de réseau, son procédé de fabrication et dispositif d'affichage
EP2757589A2 (fr) Procédés de fabrication d'un transistor à film mince et d'un substrat en réseau
WO2013189144A1 (fr) Substrat de réseau, son procédé de fabrication et dispositif d'affichage
CN102629588B (zh) 阵列基板的制造方法
JP6134766B2 (ja) 垂直型薄膜トランジスタ及びその製造方法
CN102116977B (zh) 阵列基板及其制造方法
US9494837B2 (en) Manufacturing method of TFT array substrate, TFT array substrate and display device
WO2014005348A1 (fr) Procédé de fabrication d'un substrat de matrice, substrat de matrice et dispositif d'affichage à cristaux liquides
WO2015096393A1 (fr) Substrat de réseau, son procédé de fabrication et dispositif d'affichage
CN109037241B (zh) Ltps阵列基板及其制造方法、显示面板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14873499

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 05/12/2016)

122 Ep: pct application non-entry in european phase

Ref document number: 14873499

Country of ref document: EP

Kind code of ref document: A1