EP2757589A2 - Procédés de fabrication d'un transistor à film mince et d'un substrat en réseau - Google Patents

Procédés de fabrication d'un transistor à film mince et d'un substrat en réseau Download PDF

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Publication number
EP2757589A2
EP2757589A2 EP14151795.3A EP14151795A EP2757589A2 EP 2757589 A2 EP2757589 A2 EP 2757589A2 EP 14151795 A EP14151795 A EP 14151795A EP 2757589 A2 EP2757589 A2 EP 2757589A2
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EP
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Prior art keywords
layer
photoresist
region
forming
substrate
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EP14151795.3A
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German (de)
English (en)
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EP2757589A3 (fr
Inventor
Shuibin Ni
Zhen Wang
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Publication of EP2757589A2 publication Critical patent/EP2757589A2/fr
Publication of EP2757589A3 publication Critical patent/EP2757589A3/fr
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device

Definitions

  • the present invention relates to the field of display technology, and particularly, to a method for fabricating a thin film transistor and a method for fabricating an array substrate.
  • Oxide semiconductors which are represented by IGZO (Indium Gallium Zinc Oxide) are widely used in the field of liquid-crystal display because of their properties of high electron mobility and good uniformity, and are materials used for fabricating the channel of a TFT (Thin Film Transistor).
  • IGZO Indium Gallium Zinc Oxide
  • a fabricating procedure of an existing oxide-semiconductor thin-film-transistor array substrate is as follows: sequentially forming a gate metal layer, a gate insulation layer, an IGZO semiconductor layer, a barrier layer, a source-drain metal layer, a passivation layer and a pixel electrode layer on a substrate.
  • a whole patterning process including steps of deposition, photoresist applying, exposure, developing, etching and peeling is needed, so as to form respective film pattern layer, that is , the exposure step needs to be performed six times, in order to form an IGZO-TFT array substrate.
  • the number of times of performing the patterning process is large, and the period of the patterning process is long.
  • An objective of the present invention is to provide methods for fabricating a thin film transistor and an array substrate, and these methods can reduce the number of times of performing the patterning process during the fabricating procedure of the thin film transistor and the array substrate.
  • forming the oxide semiconductor layer and the barrier layer by performing the patterning process once comprises:
  • the multi-tone mask comprises: a fully transparent region, a semi-transparent region and an opaque region;
  • the multi-tone mask comprises: a mask baseplate and a semi-transparent film;
  • the step of forming the gate insulation layer on the substrate comprises: forming a gate insulation film on the substrate where the gate layer has been formed so as to cover the gate layer.
  • the step of forming the source-drain layer on the substrate comprises: forming a source-drain metal film on the substrate where the oxide semiconductor layer and the barrier layer have been formed; and forming the source-drain layer from the source-drain metal film by performing a patterning process once, so as to cover the oxide semiconductor layer.
  • a material used for forming the oxide semiconductor layer is indium gallium zinc oxide.
  • a material used for forming the gate layer and/or the source-drain layer is molybdenum.
  • Embodiments of the present invention provide a method for fabricating an array substrate, which comprises steps of: disposing a thin film transistor on a substrate; and disposing a pixel electrode layer on the substrate where the thin film transistor has been formed, wherein, the step of disposing the thin film transistor on the substrate uses any of the methods for fabricating a thin film transistor provided by the embodiments of the present invention.
  • the methods for fabricating a thin film transistor and an array substrate provided by the embodiments of the invention could form the oxide semiconductor layer and the barrier layer by performing a patterning process once. Therefore, compared with the situation in the prior art that the patterning processes need to be respectively performed for the formation of the oxide semiconductor layer and the formation of the barrier layer, technical effect of reducing the number of times of performing a patterning process is realized.
  • Figure 1 shows a top view of an existing array substrate.
  • Figure 2 shows a sectional diagram taken along a line a-a' in Figure 1 , schematically showing a thin film transistor 100 on an array substrate.
  • the thin film transistor 100 comprises: a gate layer 2 provided on a substrate 1; a gate insulation layer 3 covering the gate layer 2; an oxide semiconductor layer 4 located on the gate insulation layer 3; a barrier layer 5 located on and partially covering the oxide semiconductor layer 4; and a source-drain layer 6 which is located above the oxide semiconductor layer 4 and the barrier layer 5 and covers a part of the oxide semiconductor layer 4 which is not covered by the barrier layer 5 as well as both ends of the barrier layer 5; the source-drain layer 6 comprises a drain 61, located at one end of the oxide semiconductor layer 4 and barrier layer 5, and a source 62 at another end.
  • a method for fabricating a thin film transistor provided by the embodiments of the present invention is described in the following; however, the present invention is not limited to the thin film transistors shown in the figures
  • the embodiment of the present invention provides a method for fabricating a thin film transistor, comprising steps of: forming the gate layer on the substrate; forming the gate insulation layer so as to cover the gate layer; forming the oxide semiconductor layer and the barrier layer; and forming the source-drain layer on the oxide semiconductor layer and the barrier layer.
  • the step of forming the oxide semiconductor layer and the barrier layer comprises:
  • the substrate is a transparent substrate.
  • the material used for forming the oxide semiconductor layer may be IGZO, MIZO (Mg-In-Zn-O, magnesium-indium-zinc-oxygen), or the like.
  • the embodiments of the present invention are described in details by taking IGZO as an example of the material of the oxide semiconductor.
  • the material used for forming the barrier layer may be SiO 2 (silicon dioxide).
  • the material used for forming the gate layer and the source-drain layer may be a conductive material such as a metal.
  • the embodiments of the present invention is described in details by taking molybdenum as an example of the material of the gate layer and the source-drain layer.
  • film refers to a layer of film fabricated by disposing a certain material on a substrate through a deposition process or other process. If no patterning process needs to be performed on such "film” during the whole fabrication procedure, then such “film” may also be called as “layer”. If a patterning process needs to be performed on such "film” during the whole fabrication procedure, then it is called as “film” before the patterning process, and is called as “layer” after the patterning process. At least one film “pattern” is included in the "layer” subjected to a patterning process.
  • a material of the gate insulation layer may be SiN x (silicon nitride).
  • SiN x silicon nitride
  • the oxide semiconductor layer is formed by performing a patterning process on the oxide semiconductor film
  • the barrier layer is formed by performing a patterning process on the barrier film. Both the gate layer and the source-drain layer are patterns.
  • patterning process is a process for forming a layer including at least one pattern from a film; and the patterning process usually includes: coating a photoresist on the film, exposing the photoresist by using a mask, removing part of the photoresist that needs to be removed by using a developer, then etching a part of the film that is not covered by the photoresist, and finally peeling off the remaining photoresist.
  • the "one patterning process” means that exposure is performed only once during the patterning process.
  • a method for fabricating the thin film transistor 100 comprises steps of:
  • a material of the gate film preferably is molybdenum; a film is formed preferably through a deposition process, with which the gate metal film is formed on the substrate; and the gate layer is formed through one time exposure process or the like.
  • a layer of insulating material is formed on the substrate with the gate layer formed thereon, preferably by means of deposition process, so as to form the gate insulation layer; and the gate insulation layer has a function of electrical insulation.
  • a layer of oxide semiconductor film is formed on the substrate with the gate layer and the gate insulation layer formed thereon, preferably by means of deposition process; subsequently, a layer of barrier film is formed on the oxide semiconductor film, preferably by means of deposition process; and then the oxide semiconductor layer and the barrier layer are formed through one patterning process.
  • the oxide semiconductor layer is used as an active layer; the barrier layer is used as an etch stop layer, for avoiding influence on the oxide semiconductor layer when metal layers above the oxide semiconductor layer are etched in subsequent processes, and also for avoiding changes of property of the thin film transistor caused by reactions between the oxide semiconductor layer and oxygen or water in the air when the oxide semiconductor layer is exposed to the air.
  • description is made by taking an IGZO film as an example of the oxide semiconductor film.
  • a material used for forming the source-drain metal film preferably is molybdenum.
  • the layer of the source-drain metal film is formed by means of deposition process on the substrate where the oxide semiconductor layer and the barrier layer have been formed; and the source-drain layer is formed through one time exposure process and the like.
  • the source 62 and the drain 61 included in the formed source-drain layer 6 each cover a part of the oxide semiconductor layer 4 that is not covered by the barrier layer 5 and one end of the barrier layer 5.
  • PVX layer i.e. the passivation layer
  • the passivation layer may also be formed on the substrate so as to cover the source-drain layer and the exposed portion of the barrier layer.
  • the method for fabricating a thin film transistor provided by the above embodiment simply uses one patterning process to form the oxide semiconductor layer and the barrier layer, thus, compared with the situation in the prior art that patterning processes need to be respectively performed for the formation of the oxide semiconductor layer and the formation of the barrier layer, technical effect of reducing the number of times of performing the patterning process is realized.
  • Figure 4 shows a preferable implementation of "forming the gate layer from the gate metal film by performing the patterning process once" in the above step S101, which includes the following steps S1011 to S1014:
  • photoresists are divided into positive photoresists and negative photoresists. Those generate insoluble substance after being irradiated by light is negative photoresists; on the contrary, those become into soluble substance after being irradiated by light are positive photoresists.
  • soluble and insoluble are defined in relative to specific developers. The embodiments of the present invention are described in details by taking positive photoresist as an example.
  • the mask may be a normal mask comprising transparent regions and opaque regions.
  • a positive photoresist photoresist in regions where light irradiation has occurred through the transparent regions forms soluble substance; photoresist in regions where light irradiation has not occurred forms insoluble substance.
  • developer can be used to develop the photoresist, and part of photoresist that needs to be removed is then removed.
  • the photoresist that needs to be removed is the photoresist that does not correspond to the gate layer.
  • developer is used to remove the photoresist located in the region that has been irradiated by light, while the photoresist located in the region that has not been irradiated by light remains.
  • an etchant may be used to etch the part of the gate metal film that is not covered by the photoresist.
  • the photoresist is peeled off, and the gate layer is formed on the substrate.
  • Figure 5 shows a preferable implementation of "forming the oxide semiconductor layer and the barrier layer by performing the patterning process once" in the above step S103, which includes the following steps S1031 to S1036:
  • a layer of oxide semiconductor film is formed on the gate insulation layer by means of deposition process, then a layer of barrier film is deposited on the oxide semiconductor film, and a layer of photoresist is coated on the barrier film. As shown in Figure 6 , the oxide semiconductor film 40 and the barrier film 50 are coated with a layer of photoresist 9.
  • the multi-tone mask may preferably be a half-grey or half-tone mask. Developer may be used to develop the photoresist exposed by using the half-grey or half-tone mask, and a photoresist completely preserved region, a photoresist partially preserved region and a photoresist completely removed region are formed after developing.
  • region A is the photoresist completely preserved region, which corresponds to the channel region of the thin film transistor; and thickness of the photoresist in this region should be as uniform as possible, which equals to the original thickness of the photoresist when the coating is completed.
  • Region B is the photoresist partially preserved region, which corresponds to a region where the oxide semiconductor layer is to be formed except for the channel region; and thickness of the photoresist in this region should also be as uniform as possible, which is smaller than the original thickness of the photoresist when the coating is completed; preferably, the thickness of the photoresist in this region may be but not limited to half of the original thickness.
  • Regions other than regions A and B are the photoresist completely removed region, wherein the photoresist is completely removed.
  • the half-grey or half-tone mask includes: a fully transparent region, a semi-transparent region and an opaque region.
  • the half-grey or half-tone mask includes a mask baseplate and a semi-transparent film.
  • the mask baseplate includes a fully transparent portion and an opaque portion.
  • the fully transparent portion corresponds to the fully transparent region and the semi-transparent region of the half-grey or half-tone mask; the opaque portion corresponds to the opaque region of the half-grey or half-tone mask.
  • the semi-transparent film is attached onto the mask baseplate, and corresponds to the semi-transparent region of half-grey or half-tone mask.
  • the opaque region of the half-grey or half-tone mask corresponds to the photoresist completely preserved region; the semi-transparent region corresponds to the photoresist partially preserved region; the fully transparent region corresponds to the photoresist completely removed region.
  • the photoresist is a negative photoresist, the fully transparent region of the half-grey or half-tone mask corresponds to the photoresist completely preserved region; the semi-transparent region corresponds to the photoresist partially preserved region; the opaque region corresponds to the photoresist completely removed region.
  • the embodiments of the invention are described by taking a positive photoresist as an example.
  • an etchant may be used to etch a part of the oxide semiconductor film 40 and a part of the barrier film 50 which are not covered by the photoresist, so as to form the oxide semiconductor layer 4 from the oxide semiconductor film, and form the first barrier pattern 51 from the barrier film.
  • the "ashing process” means thinning the entire photoresist, so that the photoresist in the photoresist partially preserved region is completed removed, while the photoresist in the photoresist completely preserved region still remains with a certain thickness.
  • an etchant may be used to etch a part of the barrier film of the first barrier pattern 51, which corresponds the photoresist partial preserved region, i.e., to etch the part which is not covered by the photoresist, so as to form the barrier layer 5.
  • the remaining photoresist is peeled off, so as to expose the barrier layer 5.
  • the barrier layer and the oxide semiconductor with different shapes are respectively formed.
  • objective of forming the oxide semiconductor layer and the barrier layer only through one patterning process is realized; thus, the number of times of performing exposure by using a mask is reduced, and the fabricating cost is significantly saved.
  • Current display devices at least comprises: organic light emitting displays (OLEDs) and liquid-crystal display devices.
  • OLEDs organic light emitting displays
  • liquid-crystal display devices uses electric field to control light transmission through liquid crystals, so as to display images. Based on directions in which electric fields drive liquid crystals, the liquid-crystal display devices can be roughly divided into vertical electric field driving type and horizontal electric field driving type.
  • a vertical electric field driving type liquid-crystal display device disposes common electrodes and pixel electrodes opposite to each other on upper and lower substrates, and vertical electric fields are formed between the common electrodes and the pixel electrodes so as to drive liquid crystals, such as a TN (Twist Nematic) type liquid-crystal display device or a VA (Vertical Alignment) type liquid-crystal display device.
  • TN Transist Nematic
  • VA Vertical Alignment
  • a horizontal electric field driving type liquid-crystal display device disposes the common electrodes and the pixel electrodes on the lower substrate, and horizontal electric fields are formed between the common electrodes and the pixel electrodes so as to drive liquid crystals, such as a ADS (Advanced-Super Dimensional Switching) type liquid-crystal display device or a IPS (In Plane Switch) type liquid-crystal display device.
  • ADS Advanced-Super Dimensional Switching
  • IPS In Plane Switch
  • any of the above display devices it comprises an array substrate; and the array substrate includes a structure of a thin film transistor and a pixel electrode layer. Therefore, the present invention applies to a fabricating procedure of any display device.
  • Methods provided by the present invention and devices fabricated by the methods may apply to any of the above display devices, and any other device that includes a thin film transistor array substrate.
  • Embodiments of the present invention provides a method for fabricating an array substrate, comprising: a step of disposing a thin film transistor on a substrate, and a step of disposing a pixel electrode layer on the substrate with the thin film transistor formed thereon; wherein, the step of disposing the thin film transistor on the substrate uses any of the methods for fabricating a thin film transistor provided by the embodiments of the present invention.
  • the embodiments of the present invention are described in details by taking an array substrate in a TN type or VA type liquid-crystal display device as an example.
  • the array substrate includes the thin film transistor 100, and also includes gate lines 10, data lines 11, and a pixel electrode layer 8.
  • the gate lines and the gate are disposed in the same layer-level, and are patterns of the gate metal layer;
  • the data lines, the source and the drain are disposed in the same layer-level, and are patterns of the source-drain metal layer.
  • the method for fabricating an array substrate specifically comprises:
  • molybdenum is deposited on the substrate preferably by means of deposition process, so as to form the gate metal film; and the gate metal layer which includes the gate and the gate lines are formed through one time exposure process and the like.
  • the gate is connected to a gate line.
  • a layer of insulating material is formed on the substrate where the gate metal layer has been formed, preferably by means of deposition process, so as to form the gate insulation layer.
  • the gate insulation layer has a function of electrical insulation.
  • the oxide semiconductor film and the barrier film are sequentially formed on the gate insulation layer preferably by means of deposition process.
  • the method of forming the oxide semiconductor layer from the oxide semiconductor film and the barrier layer from the barrier film through one patterning process may refer to the above steps S1031 to S1036.
  • a material used for forming the source-drain metal film preferably is molybdenum.
  • the layer of source-drain metal film is formed on the substrate where the oxide semiconductor layer and the barrier layer have been formed, preferably by means of deposition process; and the source-drain metal layer is formed through one time exposure process and the like.
  • the source-drain metal layer includes data lines, a source and a drain; wherein, the source is connected to a data line, and the drain is connected to the pixel electrode layer which will be described later.
  • the source 62 and the drain 61 each cover a part of the oxide semiconductor layer 4 which is not covered by the barrier layer 5 and a part of the barrier layer 5 at one end.
  • a material used for forming the passivation film may be SiN x (silicon nitride).
  • SiN x silicon nitride
  • a layer of SiN x film is formed preferably by a deposition process, and the passivation layer is formed through one time exposure other process and the like.
  • a material used for forming the pixel electrode film may be ITO (indium tin oxide).
  • ITO indium tin oxide
  • a layer of indium tin oxide film is formed preferably by a deposition process, and the pixel electrode layer (for example, the pixel electrode layer 8 shown in Figures 1 and 12 ) is formed through one time exposure process and the like.
  • the inventive aspect of the present invention is forming the oxide semiconductor layer and the barrier layer through one patterning process; fabricating methods of other layers, such as methods of forming the gate metal layer, the gate insulation layer, the source-drain metal layer, the passivation layer and the pixel electrode layer on the substrate, are the same as those in the prior art, thus simply refer to the prior art, and will not be described in the embodiments of the present invention.
  • the above method also comprises a step of forming the common electrodes on the substrate.
  • the common electrodes may be disposed on the pixel electrodes; and in this case, after the pixel electrodes have been formed, a common electrode film is formed on the substrate with the pixel electrodes formed thereon, then the common electrode film is formed into the common electrodes through one patterning process.
  • the common electrodes may be located in the same layer-level as the pixel electrodes; in this case, while forming the pixel electrodes on the substrate, the pixel electrodes and the common electrodes may be formed through one time exposure process and the like synchronously.
  • the oxide semiconductor layer and the barrier layer are formed by performing the patterning process once; thus, compared with the prior art, the number of times of performing patterning is reduced, fabricating period is shortened, and fabricating cost is saved.

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EP14151795.3A 2013-01-21 2014-01-20 Procédés de fabrication d'un transistor à film mince et d'un substrat en réseau Withdrawn EP2757589A3 (fr)

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CN201310020495XA CN103117224A (zh) 2013-01-21 2013-01-21 一种薄膜晶体管和阵列基板的制作方法

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EP2757589A2 true EP2757589A2 (fr) 2014-07-23
EP2757589A3 EP2757589A3 (fr) 2017-09-13

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JP (1) JP2014140033A (fr)
KR (1) KR20140094447A (fr)
CN (1) CN103117224A (fr)

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KR20140094447A (ko) 2014-07-30
CN103117224A (zh) 2013-05-22

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