CN104167365A - 金属氧化物薄膜晶体管、阵列基板及制作方法、显示装置 - Google Patents

金属氧化物薄膜晶体管、阵列基板及制作方法、显示装置 Download PDF

Info

Publication number
CN104167365A
CN104167365A CN201410384418.7A CN201410384418A CN104167365A CN 104167365 A CN104167365 A CN 104167365A CN 201410384418 A CN201410384418 A CN 201410384418A CN 104167365 A CN104167365 A CN 104167365A
Authority
CN
China
Prior art keywords
metal oxide
film transistor
oxide thin
barrier layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201410384418.7A
Other languages
English (en)
Inventor
赵磊
郭炜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN201410384418.7A priority Critical patent/CN104167365A/zh
Publication of CN104167365A publication Critical patent/CN104167365A/zh
Priority to PCT/CN2014/093649 priority patent/WO2016019672A1/zh
Priority to US14/771,267 priority patent/US9627414B2/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/465Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/467Chemical or electrical treatment, e.g. electrolytic etching using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02565Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/469Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers
    • H01L21/4757After-treatment
    • H01L21/47573Etching the layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/1288Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356Disposition, e.g. buried gate electrode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66969Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02186Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing titanium, e.g. TiO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02266Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • H01L21/31122Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明提供了一种金属氧化物薄膜晶体管、阵列基板及制作方法、显示装置,属于薄膜晶体管制造工艺领域。其中,该金属氧化物薄膜晶体管的制作方法,采用一次构图工艺形成薄膜晶体管的氧化物有源层和刻蚀阻挡层的图形。本发明的技术方案能够简化金属氧化物薄膜晶体管的制作工艺,降低金属氧化物薄膜晶体管的制造成本,同时提高金属氧化物薄膜晶体管的稳定性及良品率。

Description

金属氧化物薄膜晶体管、阵列基板及制作方法、显示装置
技术领域
本发明涉及薄膜晶体管制造工艺领域,特别是指一种金属氧化物薄膜晶体管、阵列基板及制作方法、显示装置。
背景技术
薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display,简称TFT-LCD)具有体积小、功耗低、无辐射等特点,在当前的平板显示器市场中占据了主导地位。
近年来TFT-LCD获得了飞速的发展,尤其是液晶电视发展的更为迅速,其尺寸和分辨率不断地提高,大尺寸、高分辨率的液晶电视成为TFT-LCD发展的一个主流。随着TFT-LCD尺寸的不断增大、分辨率的不断提高,为了提高显示质量,势必要采用更高频率的驱动电路,同时图像信号的延迟变的更为严重,信号延迟成为制约大尺寸、高分辨率TFT-LCD显示效果的关键因素之一。
随着液晶显示器尺寸的不断增大,驱动电路频率的不断提高,现有的非晶硅薄膜晶体管迁移率很难满足要求,非晶硅薄膜晶体管的迁移率一般在0.5左右,而在液晶显示器尺寸超过80英寸,驱动频率为120Hz时需要1cm2/Vs以上的迁移率,显然现有非晶硅薄膜晶体管的迁移率很难满足要求。而多晶硅薄膜晶体管尽管迁移率比较高,但是均一性较差,制作工艺复杂;金属氧化物薄膜晶体管迁移率高,均一性好,制作工艺简单,可以很好地满足大尺寸、高刷新频率液晶显示器和有源有机电致发光器件高迁移率的需求。
金属氧化物薄膜晶体管以IGZO(Indium Gallium Zinc Oxide铟镓锌氧化物)为代表,IGZO是一种含有铟、镓和锌的非晶氧化物,载流子迁移率是非晶硅的20~30倍,可以提高TFT对像素电极的充放电速率,提高像素的响应速度,实现更快的刷新率,同时更快的响应也大大提高了像素的行扫描速率,使得超高分辨率在TFT-LCD中成为可能。另外,由于IGZO还可提高每个像素的透光率,能够使得显示装置具有更高的能效水平。
现在一般采用四次到五次构图工艺制作金属氧化物薄膜晶体管,主要是IGZO在传统的刻蚀源漏金属层的刻蚀液中的腐蚀速率极快,同时由于IGZO材料对于水和氧的敏感性导致工艺过程中需要形成一层保护层来保护IGZO同时阻止源漏金属层的刻蚀液的刻蚀,因此需要在金属氧化物半导体层上增加一刻蚀阻挡层(ESL,Etch Isolation Layer)的制作步骤,以保护金属氧化物半导体层不被源漏金属层的刻蚀液腐蚀,但是这样就增加了金属氧化物薄膜晶体管的结构以及制作工艺的复杂性,从而降低了金属氧化物薄膜晶体管的产能。同时,IGZO存在对紫外光的敏感性,在紫外光照下其电学性能会发生比较严重的漂移,严重影响IGZO-TFT的稳定性及良品率。
发明内容
本发明要解决的技术问题是提供一种金属氧化物薄膜晶体管、阵列基板及制作方法、显示装置,能够简化金属氧化物薄膜晶体管的制作工艺,降低金属氧化物薄膜晶体管的制造成本,同时提高金属氧化物薄膜晶体管的稳定性及良品率。
为解决上述技术问题,本发明的实施例提供技术方案如下:
一方面,提供一种金属氧化物薄膜晶体管的制作方法,采用一次构图工艺形成薄膜晶体管的氧化物有源层和刻蚀阻挡层的图形。
进一步地,所述刻蚀阻挡层采用TiO2或TiO2与CeO2的混合物制成。
进一步地,在同一次构图工艺中,通过干刻工艺形成所述刻蚀阻挡层的图形,通过湿刻工艺形成所述氧化物有源层的图形。
进一步地,所述采用一次构图工艺形成薄膜晶体管的氧化物有源层和刻蚀阻挡层的图形包括:
在基板上依次沉积金属氧化物半导体层和刻蚀阻挡层;
在所述刻蚀阻挡层上涂覆光刻胶,利用半色调掩膜板或灰色调掩膜板进行曝光显影得到光刻胶未保留区域、光刻胶部分保留区域和光刻胶完全保留区域;
通过干刻工艺刻蚀掉光刻胶未保留区域的刻蚀阻挡层,并采用湿刻工艺刻蚀掉光刻胶未保留区域的金属氧化物半导体层,形成金属氧化物半导体层的图形;
灰化掉光刻胶部分保留区域的光刻胶,通过干刻工艺刻蚀掉光刻胶部分保留区域的刻蚀阻挡层,形成刻蚀阻挡层的图形;
对未被刻蚀阻挡层覆盖的金属氧化物半导体层进行等离子处理,形成所述氧化物有源层;
剥离光刻胶完全保留区域的光刻胶。
进一步地,在基板上沉积刻蚀阻挡层包括:
以Ti(OC4H9)4为源物质,将预设流量的N2通入Ti(OC4H9)4中进行鼓泡并作为载气,将Ti(OC4H9)4带入反应器,同时将预设流量的O2通入所述反应器,通过金属气相沉积方式在基板上沉积一层TiO2薄膜;或
以金属Ti为靶材,在O2气氛下通过直流磁控溅射方式在基板上沉积一层TiO2薄膜;或
以CeO2和TiO2按照预设比例混合后的混合物为靶材,通过磁控溅射方式在基板上沉积一层CeO2和TiO2的混合物薄膜。
进一步地,所述干刻工艺采用的刻蚀气体为CF4、或CF4和O2的混合气体、或CCl4、或BCl3、或BCl3和Cl2的混合气体。
进一步地,所述制作方法具体包括:
提供一衬底基板;
通过一次构图工艺在所述衬底基板上形成栅电极和栅线;
在形成有所述栅电极和栅线的基板上形成栅绝缘层;
通过一次构图工艺在所述栅绝缘层上形成所述氧化物有源层和刻蚀阻挡层的图形;
通过一次构图工艺在形成有所述氧化物有源层和刻蚀阻挡层的图形的基板上形成源电极、漏电极和数据线。
本发明实施例还提供了一种金属氧化物薄膜晶体管阵列基板的制作方法,在以上述方法制作金属氧化物薄膜晶体管之后,通过一次构图工艺在形成有源电极、漏电极和数据线的基板上形成包括有过孔的钝化层;通过一次构图工艺在所述钝化层上形成像素电极,所述像素电极通过所述过孔与所述漏电极连接。
本发明实施例还提供了一种以上述方法制作的金属氧化物薄膜晶体管,所述薄膜晶体管的源电极和漏电极与未被刻蚀阻挡层覆盖的氧化物有源层相连接。
进一步地,所述刻蚀阻挡层的材料为TiO2或TiO2与CeO2的混合物。
进一步地,所述刻蚀阻挡层的厚度为
进一步地,TiO2与CeO2的混合物中,TiO2所占的比例为0.4-0.5。
进一步地,所述氧化物有源层的材料为IGZO、ITZO、或ZnON,氧化物有源层的厚度为
进一步地,所述薄膜晶体管具体包括:
衬底基板;
位于所述衬底基板上的栅电极和栅线;
位于形成有所述栅电极和栅线的基板上的栅绝缘层;
位于所述栅绝缘层上的所述氧化物有源层和刻蚀阻挡层的图形;
位于形成有所述氧化物有源层和刻蚀阻挡层的图形的基板上的源电极、漏电极和数据线。
本发明实施例还提供了一种阵列基板,包括如上所述的金属氧化物薄膜晶体管,还包括位于形成有所述源电极、漏电极和数据线的基板上的包括有过孔的钝化层;位于所述钝化层上的像素电极,所述像素电极通过所述过孔与所述漏电极连接。
本发明实施例还提供了一种显示装置,包括如上所述的阵列基板。
本发明的实施例具有以下有益效果:
上述方案中,采用一次构图工艺形成金属氧化物薄膜晶体管的氧化物有源层和刻蚀阻挡层的图形,简化了金属氧化物薄膜晶体管的制作工艺,从而能够降低金属氧化物薄膜晶体管的制造成本,同时提高金属氧化物薄膜晶体管的产能。
附图说明
图1为现有技术通过六次构图工艺制作的金属氧化物薄膜晶体管阵列基板的结构示意图;
图2为TiO2及CeO2:TiO2的紫外吸收光谱示意图;
图3A-3E为本发明实施例制作氧化物有源层和刻蚀阻挡层的示意图;
图4为本发明实施例制作的金属氧化物薄膜晶体管的结构示意图;
图5为本发明实施例制作的金属氧化物薄膜晶体管阵列基板的结构示意图。
附图标记
1衬底基板  2栅电极  3栅绝缘层  4氧化物有源层  5源漏金属层
6刻蚀阻挡层  7钝化层  8像素电极
具体实施方式
为使本发明的实施例要解决的技术问题、技术方案和优点更加清楚,下面将结合附图及具体实施例进行详细描述。
本发明的实施例针对现有技术中金属氧化物薄膜晶体管的制作工艺复杂的问题,提供一种金属氧化物薄膜晶体管、阵列基板及制作方法、显示装置,能够简化金属氧化物薄膜晶体管的制作工艺,降低金属氧化物薄膜晶体管的制造成本,同时提高金属氧化物薄膜晶体管的稳定性及良品率。
本发明的金属氧化物薄膜晶体管的制作方法,采用一次构图工艺形成薄膜晶体管的氧化物有源层和刻蚀阻挡层的图形,简化了金属氧化物薄膜晶体管的制作工艺,从而能够降低金属氧化物薄膜晶体管的制造成本,同时提高金属氧化物薄膜晶体管的产能。
进一步地,所述刻蚀阻挡层采用TiO2或TiO2与CeO2的混合物制成,即采用TiO2薄膜或者CeO2:TiO2薄膜作为刻蚀阻挡层,TiO2同时具有较好的紫外光吸收特性,因此,刻蚀阻挡层也可以作为紫外吸收层,有效避免了金属氧化物半导体材料在紫外光照下发生的电学性能漂移的现象,提高了金属氧化物薄膜晶体管的稳定性及良品率。
进一步地,在同一次构图工艺中,通过干刻工艺形成刻蚀阻挡层的图形,通过湿刻工艺形成氧化物有源层的图形。
进一步地,所述采用一次构图工艺形成薄膜晶体管的氧化物有源层和刻蚀阻挡层的图形包括:
在基板上依次沉积金属氧化物半导体层和刻蚀阻挡层,其中,所述基板包括衬底基板以及在衬底基板上形成的部分膜层;
在所述刻蚀阻挡层上涂覆光刻胶,利用半色调掩膜板或灰色调掩膜板进行曝光显影得到光刻胶未保留区域、光刻胶部分保留区域和光刻胶完全保留区域;
通过干刻工艺刻蚀掉光刻胶未保留区域的刻蚀阻挡层,并采用湿刻工艺刻蚀掉光刻胶未保留区域的金属氧化物半导体层,形成金属氧化物半导体层的图形;
灰化掉光刻胶部分保留区域的光刻胶,通过干刻工艺刻蚀掉光刻胶部分保留区域的刻蚀阻挡层,形成刻蚀阻挡层的图形;
对未被刻蚀阻挡层覆盖的金属氧化物半导体层进行等离子处理,形成所述氧化物有源层;
剥离光刻胶完全保留区域的光刻胶。
其中,在基板上沉积刻蚀阻挡层包括:
以Ti(OC4H9)4为源物质,将预设流量的N2通入Ti(OC4H9)4中进行鼓泡并作为载气,将Ti(OC4H9)4带入反应器,同时将预设流量的O2通入所述反应器,通过金属气相沉积方式在基板上沉积一层TiO2薄膜;或
以金属Ti为靶材,在O2气氛下通过直流磁控溅射方式在基板上沉积一层TiO2薄膜;或
以CeO2和TiO2按照预设比例混合后的混合物为靶材,通过磁控溅射方式在基板上沉积一层CeO2和TiO2的混合物薄膜。
进一步地,所述干刻工艺采用的刻蚀气体为CF4、或CF4和O2的混合气体、或CCl4、或BCl3、或BCl3和Cl2的混合气体。
进一步地,所述金属氧化物薄膜晶体管的制作方法具体包括:
提供一衬底基板;
通过一次构图工艺在所述衬底基板上形成栅电极和栅线;
在形成有所述栅电极和栅线的基板上形成栅绝缘层;
通过一次构图工艺在所述栅绝缘层上形成所述氧化物有源层和刻蚀阻挡层的图形;
通过一次构图工艺在形成有所述氧化物有源层和刻蚀阻挡层的图形的基板上形成源电极、漏电极和数据线。
本发明实施例还提供了一种金属氧化物薄膜晶体管阵列基板的制作方法,包括上述的金属氧化物薄膜晶体管的制作方法,还包括:通过一次构图工艺在形成有所述源电极、漏电极和数据线的基板上形成包括有过孔的钝化层;通过一次构图工艺在所述钝化层上形成像素电极,所述像素电极通过所述过孔与所述漏电极连接。
本发明实施例还提供了一种以上述方法制作的金属氧化物薄膜晶体管,所述薄膜晶体管的源电极和漏电极与未被刻蚀阻挡层覆盖的氧化物有源层相连接。
进一步地,所述刻蚀阻挡层的材料为TiO2或TiO2与CeO2的混合物,即采用TiO2薄膜或者CeO2:TiO2薄膜作为刻蚀阻挡层,由于TiO2同时具有较好的紫外光吸收特性,因此,刻蚀阻挡层也可以作为紫外吸收层,有效避免了金属氧化物半导体材料在紫外光照下发生的电学性能漂移的现象,提高了金属氧化物薄膜晶体管的稳定性及良品率。
进一步地,所述刻蚀阻挡层的厚度为这样可以使刻蚀阻挡层对氧化物有源层形成较好的保护,并在紫外光照时尽量避免氧化物有源层受到紫外光照的影响。
进一步地,TiO2与CeO2的混合物中,TiO2所占的比例优选为0.4-0.5。进一步地,氧化物有源层的材料为IGZO、ITZO、或ZnON,氧化物有源层的厚度优选为
进一步地,所述薄膜晶体管具体包括:
衬底基板;
位于所述衬底基板上的栅电极和栅线;
位于形成有所述栅电极和栅线的基板上的栅绝缘层;
位于所述栅绝缘层上的所述氧化物有源层和刻蚀阻挡层的图形;
位于形成有所述氧化物有源层和刻蚀阻挡层的图形的基板上的源电极、漏电极和数据线。
本发明实施例还提供了一种金属氧化物薄膜晶体管阵列基板,包括上述的金属氧化物薄膜晶体管,还包括位于形成有所述源电极、漏电极和数据线的基板上的包括有过孔的钝化层;位于所述钝化层上的像素电极,所述像素电极通过所述过孔与所述漏电极连接。
本发明实施例还提供了一种显示装置,包括上述的金属氧化物薄膜晶体管阵列基板。其中,金属氧化物薄膜晶体管阵列基板的结构同上述实施例,在此不再赘述。另外,显示装置其他部分的结构可以参考现有技术,对此本文不再详细描述。该显示装置可以为:显示面板、电子纸、电视、显示器、数码相框、手机、平板电脑等具有任何显示功能的产品或部件。
下面结合具体的实施例对本发明的金属氧化物薄膜晶体管及其制作方法进行详细介绍:
金属氧化物半导体材料如IGZO在传统的刻蚀源漏金属层的刻蚀液中的腐蚀速率极快,同时由于金属氧化物半导体材料对水和氧的敏感性,因此在金属氧化物薄膜晶体管的制作工艺过程中需要形成一层刻蚀阻挡层来保护由金属氧化物半导体材料制成的氧化物有源层,阻止源漏金属层的刻蚀液对氧化物有源层的刻蚀,但是这样就增加了薄膜晶体管的结构以及制作工艺的复杂性,从而降低了金属氧化物薄膜晶体管的产能,现有技术一般采用四次到五次构图工艺制作金属氧化物薄膜晶体管,相应地,需要采用六次到七次构图工艺制作金属氧化物薄膜晶体管阵列基板,图1所示为现有技术通过六次构图工艺制作的金属氧化物薄膜晶体管阵列基板的结构示意图。另外,金属氧化物半导体材料如IGZO存在对紫外光的敏感性,在紫外光照下其电学性能会发生比较严重的漂移,严重影响IGZO-TFT的稳定性及良品率。
TiO2薄膜是一种多功能材料,具有高折射率和高介电常数,同时具有较好的紫外光吸收特性,其还具有制备工艺简单,性质稳定,易于实现图形化的优点。图2为TiO2及CeO2:TiO2的紫外吸收光谱示意图,其中a曲线为TiO2的紫外吸收光谱曲线;b曲线为CeO2:TiO2=0.9:0.1时,CeO2:TiO2混合物薄膜的紫外吸收光谱曲线;c曲线为CeO2:TiO2=0.8:0.2时,CeO2:TiO2混合物薄膜的紫外吸收光谱曲线;d曲线为CeO2:TiO2=0.7:0.3时,CeO2:TiO2混合物薄膜的紫外吸收光谱曲线;e曲线为CeO2:TiO2=0.6:0.4时,CeO2:TiO2混合物薄膜的紫外吸收光谱曲线;f曲线为CeO2:TiO2=0.5:0.5时,CeO2:TiO2混合物薄膜的紫外吸收光谱曲线;g曲线为CeO2:TiO2=0.4:0.6时,CeO2:TiO2混合物薄膜的紫外吸收光谱曲线。
如图2中a曲线所示,TiO2薄膜对于波长在300nm以下的紫外光具有较高的吸收性;TiO2与CeO2进行掺杂后,形成的CeO2:TiO2薄膜的紫外吸收光谱的起始线会变为400nm,如图2中的g曲线所示。另外,TiO2薄膜及CeO2:TiO2薄膜还具有较好的致密性,能有效的对金属氧化物半导体材料实现保护,因此,本发明实施例采用TiO2或CeO2:TiO2薄膜来制作刻蚀阻挡层,既能实现对金属氧化物半导体材料的保护,又能对紫外光进行吸收,避免紫外光对金属氧化物半导体材料性能产生的不良影响,有效提高了金属氧化物薄膜晶体管的稳定性及良品率。
具体地,本实施例的金属氧化物薄膜晶体管的制作方法包括以下步骤:
步骤1、提供一衬底基板1,在衬底基板1上形成栅电极2和栅线(图中未标出)的图形;
其中,衬底基板1可为玻璃基板或石英基板。具体地,可以采用溅射或热蒸发的方法在衬底基板1上沉积厚度约为的栅金属层,栅金属层可以是Cu,Al,Ag,Mo,Cr,Nd,Ni,Mn,Ti,Ta,W等金属以及这些金属的合金,栅金属层可以为单层结构或者多层结构,多层结构比如Cu\Mo,Ti\Cu\Ti,Mo\Al\Mo等。在栅金属层上涂覆一层光刻胶,采用掩膜板对光刻胶进行曝光,使光刻胶形成光刻胶未保留区域和光刻胶保留区域,其中,光刻胶保留区域对应于栅线和栅电极2的图形所在区域,光刻胶未保留区域对应于上述图形以外的区域;进行显影处理,光刻胶未保留区域的光刻胶被完全去除,光刻胶保留区域的光刻胶厚度保持不变;通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的栅金属薄膜,剥离剩余的光刻胶,形成栅线和栅电极2的图形。
步骤2、在完成步骤1的基板上形成栅绝缘层3;
具体地,可以采用等离子体增强化学气相沉积(PECVD)方法在完成步骤1的基板上沉积厚度为的栅绝缘层3,栅绝缘层3可以选用氧化物、氮化物或者氧氮化合物,对应的反应气体是SiH4、NH3、N2或SiH2Cl2、NH3、N2
步骤3、在完成步骤2的基板上形成氧化物有源层4和刻蚀阻挡层6的图形;
具体地,如图3A所示,在基板上依次沉积金属氧化物半导体层和TiO2薄膜或CeO2:TiO2薄膜,金属氧化物半导体层可以采用IGZO、ITZO、或ZnON,金属氧化物半导体层的厚度为TiO2薄膜或CeO2:TiO2薄膜的厚度为在采用CeO2:TiO2薄膜制作刻蚀阻挡层时,TiO2所占的比例优选为0.4-0.5。。
TiO2薄膜的制备方法主要包括溶胶凝胶法、有机电合成法、化学气相沉积(CVD)及物理气相沉积(PVD)等。具体地,可以以Ti(OC4H9)4为源物质,将预设流量的N2通入Ti(OC4H9)4中进行鼓泡并作为载气,将Ti(OC4H9)4带入反应器,同时将预设流量的O2通入所述反应器,通过金属气相沉积方式在基板上沉积一层TiO2薄膜;或以金属Ti为靶材,在O2气氛下通过直流磁控溅射方式在基板上沉积一层TiO2薄膜;或以CeO2和TiO2按照预设比例混合后的混合物为靶材,通过磁控溅射方式在基板上沉积一层CeO2和TiO2的混合物薄膜。在TiO2薄膜或CeO2:TiO2薄膜上涂覆光刻胶,利用半色调掩膜板或灰色调掩膜板进行曝光显影得到光刻胶未保留区域、光刻胶部分保留区域和光刻胶完全保留区域。
如图3B所示,通过干刻工艺刻蚀掉光刻胶未保留区域的TiO2薄膜或CeO2:TiO2薄膜,其中,干刻工艺采用的刻蚀气体可以为CF4、或CF4和O2的混合气体、或CCl4、或BCl3、或BCl3和Cl2的混合气体。
如图3C所示,采用湿刻工艺刻蚀掉光刻胶未保留区域的金属氧化物半导体层,形成金属氧化物半导体层的图形。
如图3D所示,灰化掉光刻胶部分保留区域的光刻胶。
如图3E所示,通过干刻工艺刻蚀掉光刻胶部分保留区域的TiO2薄膜或CeO2:TiO2薄膜,形成刻蚀阻挡层6的图形;采用CF4+O2的混合气体或CF4对未被刻蚀阻挡层6覆盖的金属氧化物半导体层进行等离子处理,形成氧化物有源层4,之后剥离光刻胶完全保留区域的光刻胶。
本实施例通过一次构图工艺形成氧化物有源层和刻蚀阻挡层的图形,避免了由于刻蚀阻挡层的增加导致的构图工艺次数以及生产成本的增加,又避免了传统工艺中对源漏金属层进行刻蚀导致氧化物有源层出现损伤的现象。
步骤4、在完成步骤3的基板上形成数据线、源电极和漏电极的图形。
具体地,可以在完成步骤3的基板上采用磁控溅射、热蒸发或其它成膜方法沉积一层厚度约为的源漏金属层5,源漏金属层5可以是Cu,Al,Ag,Mo,Cr,Nd,Ni,Mn,Ti,Ta,W等金属以及这些金属的合金。源漏金属层5可以是单层结构或者多层结构,多层结构比如Cu\Mo,Ti\Cu\Ti,Mo\Al\Mo等。在源漏金属层5上涂覆一层光刻胶,采用掩膜板对光刻胶进行曝光,使光刻胶形成光刻胶未保留区域和光刻胶保留区域,其中,光刻胶保留区域对应于源电极、漏电极和数据线的图形所在区域,光刻胶未保留区域对应于上述图形以外的区域;进行显影处理,光刻胶未保留区域的光刻胶被完全去除,光刻胶保留区域的光刻胶厚度保持不变;通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的源漏金属层5,剥离剩余的光刻胶,形成漏电极、源电极以及数据线。
通过上述步骤1-4即可制作出本实施例的金属氧化物薄膜晶体管,其截面示意图如图4所示,可以看出,在氧化物有源层4上形成有刻蚀阻挡层6,源电极和漏电极与未被刻蚀阻挡层6覆盖的氧化物有源层4连接。
在完成上述步骤1-4的基础上,还可以制作包括上述金属氧化物薄膜晶体管的阵列基板,具体地,该阵列基板的制作方法除包括上述步骤1-4之外,还包括:
步骤5,在完成步骤4的基板上形成包括有过孔的钝化层7;
具体地,可以在完成步骤4的基板1上采用磁控溅射、热蒸发、PECVD或其它成膜方法沉积厚度为的钝化层7,钝化层7可以选用氧化物、氮化物或者氧氮化合物,具体地,钝化层材料可以是SiNx,SiOx或Si(ON)x,钝化层7还可以使用Al2O3。钝化层可以是单层结构,也可以是采用氮化硅和氧化硅构成的两层结构。其中,硅的氧化物对应的反应气体可以为SiH4,N2O;氮化物或者氧氮化合物对应气体可以是SiH4,NH3,N2或SiH2Cl2,NH3,N2。通过一次构图工艺形成包括有过孔的钝化层7的图形,具体地,可以在钝化层7上涂覆一层厚度约为的有机树脂,有机树脂可以是苯并环丁烯(BCB),也可以是其他的有机感光材料,曝光显影后,通过一次刻蚀工艺形成有过孔的钝化层7的图形。
步骤6、在完成步骤5的基板上形成像素电极8的图形。
具体地,在完成步骤5的基板上通过溅射或热蒸发的方法沉积厚度约为的透明导电层,透明导电层可以是ITO、IZO或者其他的透明金属氧化物,在透明导电层上涂覆一层光刻胶,采用掩膜板对光刻胶进行曝光,使光刻胶形成光刻胶未保留区域和光刻胶保留区域,其中,光刻胶保留区域对应于像素电极的图形所在区域,光刻胶未保留区域对应于上述图形以外的区域;进行显影处理,光刻胶未保留区域的光刻胶被完全去除,光刻胶保留区域的光刻胶厚度保持不变;通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的透明导电层薄膜,剥离剩余的光刻胶,形成像素电极8的图形,像素电极8通过过孔与漏电极连接。
通过上述步骤1-6即可制作出本实施例的金属氧化物薄膜晶体管阵列基板,其截面示意图如图5所示。
本发明实施例采用半色调掩膜板或灰色调掩膜板,通过湿法刻蚀和干法刻蚀相结合的手段利用一次构图工艺形成氧化物有源层和刻蚀阻挡层的图形,在不引入新设备、新膜层的情况下将金属氧化物薄膜晶体管的制作流程由4次构图工艺简化为3次构图工艺,减少了对氧化物有源层的损伤,简化了金属氧化物薄膜晶体管的制作工艺,从而能够降低金属氧化物薄膜晶体管的制造成本,同时提高金属氧化物薄膜晶体管的产能。另外本实施例采用TiO2薄膜或者CeO2:TiO2薄膜作为刻蚀阻挡层,由于TiO2同时具有较好的紫外光吸收特性,因此刻蚀阻挡层可以对紫外光进行吸收,有效避免了金属氧化物材料在紫外光照下发生的电学性能漂移的现象,有效提高了金属氧化物薄膜晶体管的稳定性及良品率。
以上所述是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明所述原理的前提下,还可以作出若干改进和润饰,这些改进和润饰也应视为本发明的保护范围。

Claims (16)

1.一种金属氧化物薄膜晶体管的制作方法,其特征在于,采用一次构图工艺形成薄膜晶体管的氧化物有源层和刻蚀阻挡层的图形。
2.根据权利要求1所述的金属氧化物薄膜晶体管的制作方法,其特征在于,所述刻蚀阻挡层采用TiO2或TiO2与CeO2的混合物制成。
3.根据权利要求2所述的金属氧化物薄膜晶体管的制作方法,其特征在于,在同一次构图工艺中,通过干刻工艺形成所述刻蚀阻挡层的图形,通过湿刻工艺形成所述氧化物有源层的图形。
4.根据权利要求1-3任一所述的金属氧化物薄膜晶体管的制作方法,其特征在于,所述采用一次构图工艺形成薄膜晶体管的氧化物有源层和刻蚀阻挡层的图形包括:
在基板上依次沉积金属氧化物半导体层和刻蚀阻挡层;
在所述刻蚀阻挡层上涂覆光刻胶,利用半色调掩膜板或灰色调掩膜板进行曝光显影得到光刻胶未保留区域、光刻胶部分保留区域和光刻胶完全保留区域;
通过干刻工艺刻蚀掉光刻胶未保留区域的刻蚀阻挡层,并采用湿刻工艺刻蚀掉光刻胶未保留区域的金属氧化物半导体层,形成金属氧化物半导体层的图形;
灰化掉光刻胶部分保留区域的光刻胶,通过干刻工艺刻蚀掉光刻胶部分保留区域的刻蚀阻挡层,形成刻蚀阻挡层的图形;
对未被刻蚀阻挡层覆盖的金属氧化物半导体层进行等离子处理,形成所述氧化物有源层;
剥离光刻胶完全保留区域的光刻胶。
5.根据权利要求4所述的金属氧化物薄膜晶体管的制作方法,其特征在于,在基板上沉积刻蚀阻挡层包括:
以Ti(OC4H9)4为源物质,将预设流量的N2通入Ti(OC4H9)4中进行鼓泡并作为载气,将Ti(OC4H9)4带入反应器,同时将预设流量的O2通入所述反应器,通过金属气相沉积方式在基板上沉积一层TiO2薄膜;或
以金属Ti为靶材,在O2气氛下通过直流磁控溅射方式在基板上沉积一层TiO2薄膜;或
以CeO2和TiO2按照预设比例混合后的混合物为靶材,通过磁控溅射方式在基板上沉积一层CeO2和TiO2的混合物薄膜。
6.根据权利要求4所述的金属氧化物薄膜晶体管的制作方法,其特征在于,所述干刻工艺采用的刻蚀气体为CF4、或CF4和O2的混合气体、或CCl4、或BCl3、或BCl3和Cl2的混合气体。
7.根据权利要求4所述的金属氧化物薄膜晶体管的制作方法,其特征在于,所述制作方法具体包括:
提供一衬底基板;
通过一次构图工艺在所述衬底基板上形成栅电极和栅线;
在形成有所述栅电极和栅线的基板上形成栅绝缘层;
通过一次构图工艺在所述栅绝缘层上形成所述氧化物有源层和刻蚀阻挡层的图形;
通过一次构图工艺在形成有所述氧化物有源层和刻蚀阻挡层的图形的基板上形成源电极、漏电极和数据线。
8.一种金属氧化物薄膜晶体管阵列基板的制作方法,其特征在于,在以权利要求1-7中任一项所述方法制作金属氧化物薄膜晶体管之后,通过一次构图工艺在形成有源电极、漏电极和数据线的基板上形成包括有过孔的钝化层;通过一次构图工艺在所述钝化层上形成像素电极,所述像素电极通过所述过孔与所述漏电极连接。
9.一种以权利要求1-7中任一项所述方法制作的金属氧化物薄膜晶体管,其特征在于,所述薄膜晶体管的源电极和漏电极与未被刻蚀阻挡层覆盖的氧化物有源层相连接。
10.根据权利要求9所述的金属氧化物薄膜晶体管,其特征在于,所述刻蚀阻挡层的材料为TiO2或TiO2与CeO2的混合物。
11.根据权利要求10所述的金属氧化物薄膜晶体管,其特征在于,所述刻蚀阻挡层的厚度为
12.根据权利要求10所述的金属氧化物薄膜晶体管,其特征在于,TiO2与CeO2的混合物中,TiO2所占的比例为0.4-0.5。
13.根据权利要求9所述的金属氧化物薄膜晶体管,其特征在于,所述氧化物有源层的材料为IGZO、ITZO、或ZnON,氧化物有源层的厚度为
14.根据权利要求10所述的金属氧化物薄膜晶体管,其特征在于,所述薄膜晶体管具体包括:
衬底基板;
位于所述衬底基板上的栅电极和栅线;
位于形成有所述栅电极和栅线的基板上的栅绝缘层;
位于所述栅绝缘层上的所述氧化物有源层和刻蚀阻挡层的图形;
位于形成有所述氧化物有源层和刻蚀阻挡层的图形的基板上的源电极、漏电极和数据线。
15.一种阵列基板,其特征在于,包括如权利要求9-14中任一项所述的金属氧化物薄膜晶体管,还包括位于形成有所述源电极、漏电极和数据线的基板上的包括有过孔的钝化层;位于所述钝化层上的像素电极,所述像素电极通过所述过孔与所述漏电极连接。
16.一种显示装置,其特征在于,包括如权利要求15所述的阵列基板。
CN201410384418.7A 2014-08-06 2014-08-06 金属氧化物薄膜晶体管、阵列基板及制作方法、显示装置 Pending CN104167365A (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201410384418.7A CN104167365A (zh) 2014-08-06 2014-08-06 金属氧化物薄膜晶体管、阵列基板及制作方法、显示装置
PCT/CN2014/093649 WO2016019672A1 (zh) 2014-08-06 2014-12-12 金属氧化物薄膜晶体管、阵列基板及制作方法、显示装置
US14/771,267 US9627414B2 (en) 2014-08-06 2014-12-24 Metallic oxide thin film transistor, array substrate and their manufacturing methods, display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410384418.7A CN104167365A (zh) 2014-08-06 2014-08-06 金属氧化物薄膜晶体管、阵列基板及制作方法、显示装置

Publications (1)

Publication Number Publication Date
CN104167365A true CN104167365A (zh) 2014-11-26

Family

ID=51911135

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410384418.7A Pending CN104167365A (zh) 2014-08-06 2014-08-06 金属氧化物薄膜晶体管、阵列基板及制作方法、显示装置

Country Status (3)

Country Link
US (1) US9627414B2 (zh)
CN (1) CN104167365A (zh)
WO (1) WO2016019672A1 (zh)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105118864A (zh) * 2015-08-14 2015-12-02 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、显示器件
WO2016019672A1 (zh) * 2014-08-06 2016-02-11 京东方科技集团股份有限公司 金属氧化物薄膜晶体管、阵列基板及制作方法、显示装置
CN105957872A (zh) * 2016-07-18 2016-09-21 京东方科技集团股份有限公司 阵列基板的制作方法、阵列基板及显示装置
WO2016180016A1 (en) * 2015-05-12 2016-11-17 Boe Technology Group Co., Ltd. Thin film transistor, array substrate and display device having the same, and method of manufacturing thereof
CN106206744A (zh) * 2016-08-30 2016-12-07 武汉华星光电技术有限公司 一种金属氧化物薄膜晶体管及其制备方法
CN107248373A (zh) * 2017-06-08 2017-10-13 京东方科技集团股份有限公司 一种显示面板及制作方法、显示装置
CN109166868A (zh) * 2018-09-03 2019-01-08 深圳市华星光电半导体显示技术有限公司 一种阵列基板及其制备方法、显示面板
CN109346526A (zh) * 2018-10-19 2019-02-15 京东方科技集团股份有限公司 氧化物薄膜晶体管及其制备方法、阵列基板及显示装置
CN110120426A (zh) * 2018-02-07 2019-08-13 南京中电熊猫平板显示科技有限公司 一种薄膜晶体管的制造方法及薄膜晶体管

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100576408C (zh) 2006-12-28 2009-12-30 甘国工 等离子体显示器滤光板及使用该滤光板的显示器
KR101334181B1 (ko) * 2007-04-20 2013-11-28 삼성전자주식회사 선택적으로 결정화된 채널층을 갖는 박막 트랜지스터 및 그제조 방법
CN101036879A (zh) 2007-04-24 2007-09-19 浙江大学 稀土掺杂的二氧化钛薄膜及其制备方法
KR101533391B1 (ko) * 2008-08-06 2015-07-02 삼성디스플레이 주식회사 박막 트랜지스터 기판과 그 제조 방법
TWI489628B (zh) 2009-04-02 2015-06-21 Semiconductor Energy Lab 半導體裝置和其製造方法
KR101578694B1 (ko) * 2009-06-02 2015-12-21 엘지디스플레이 주식회사 산화물 박막 트랜지스터의 제조방법
CN101615613B (zh) 2009-08-12 2010-10-06 友达光电股份有限公司 像素结构、有机电激发光显示单元及其制造方法
CN103299430A (zh) 2010-12-30 2013-09-11 周星工程股份有限公司 薄膜晶体管及其制造方法
CN102629574A (zh) * 2011-08-22 2012-08-08 京东方科技集团股份有限公司 一种氧化物tft阵列基板及其制造方法和电子器件
CN102629628B (zh) * 2011-09-29 2016-06-01 京东方科技集团股份有限公司 一种tft阵列基板及其制造方法和液晶显示器
CN102651341B (zh) * 2012-01-13 2014-06-11 京东方科技集团股份有限公司 一种tft阵列基板的制造方法
KR101438039B1 (ko) * 2012-05-24 2014-11-03 엘지디스플레이 주식회사 산화물 박막 트랜지스터, 그 제조방법, 이를 구비한 표시장치 및 그 제조방법
CN104335353B (zh) * 2012-06-06 2017-04-05 株式会社神户制钢所 薄膜晶体管
CN102723367B (zh) 2012-06-29 2015-02-11 昆山工研院新型平板显示技术中心有限公司 一种氧化物半导体薄膜晶体管
CN102983135B (zh) * 2012-12-13 2016-03-16 京东方科技集团股份有限公司 一种阵列基板、显示装置及阵列基板的制备方法
CN103117224A (zh) * 2013-01-21 2013-05-22 京东方科技集团股份有限公司 一种薄膜晶体管和阵列基板的制作方法
CN103178021B (zh) 2013-02-28 2015-02-11 京东方科技集团股份有限公司 一种氧化物薄膜晶体管阵列基板及制作方法、显示面板
US9590113B2 (en) * 2013-03-19 2017-03-07 Applied Materials, Inc. Multilayer passivation or etch stop TFT
CN103693860A (zh) 2013-05-22 2014-04-02 林嘉佑 自洁净玻璃的制备方法
WO2015059850A1 (ja) * 2013-10-24 2015-04-30 株式会社Joled 薄膜トランジスタの製造方法
CN104167365A (zh) * 2014-08-06 2014-11-26 京东方科技集团股份有限公司 金属氧化物薄膜晶体管、阵列基板及制作方法、显示装置

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9627414B2 (en) 2014-08-06 2017-04-18 Boe Technology Group Co., Ltd. Metallic oxide thin film transistor, array substrate and their manufacturing methods, display device
WO2016019672A1 (zh) * 2014-08-06 2016-02-11 京东方科技集团股份有限公司 金属氧化物薄膜晶体管、阵列基板及制作方法、显示装置
EP3295475A4 (en) * 2015-05-12 2018-12-19 BOE Technology Group Co., Ltd. Thin film transistor, array substrate and display device having the same, and method of manufacturing thereof
WO2016180016A1 (en) * 2015-05-12 2016-11-17 Boe Technology Group Co., Ltd. Thin film transistor, array substrate and display device having the same, and method of manufacturing thereof
US10008612B2 (en) 2015-05-12 2018-06-26 Boe Technology Group Co., Ltd. Thin film transistor, array substrate and display device having the same, and method of manufacturing thereof
US9806199B2 (en) 2015-05-12 2017-10-31 Boe Technology Group Co., Ltd. Thin film transistor, array substrate and display device having the same, and method of manufacturing thereof
WO2017028493A1 (zh) * 2015-08-14 2017-02-23 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、显示器件
CN105118864A (zh) * 2015-08-14 2015-12-02 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、显示器件
CN105118864B (zh) * 2015-08-14 2018-06-26 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、显示器件
US10205029B2 (en) 2015-08-14 2019-02-12 Boe Technology Group Co., Ltd. Thin film transistor, manufacturing method thereof, and display device
CN105957872A (zh) * 2016-07-18 2016-09-21 京东方科技集团股份有限公司 阵列基板的制作方法、阵列基板及显示装置
CN106206744A (zh) * 2016-08-30 2016-12-07 武汉华星光电技术有限公司 一种金属氧化物薄膜晶体管及其制备方法
CN107248373A (zh) * 2017-06-08 2017-10-13 京东方科技集团股份有限公司 一种显示面板及制作方法、显示装置
US20190207039A1 (en) * 2017-06-08 2019-07-04 Boe Technology Group Co., Ltd. Display panel and manufacturing method thereof, and display device
CN107248373B (zh) * 2017-06-08 2020-03-06 京东方科技集团股份有限公司 一种显示面板及制作方法、显示装置
US10930788B2 (en) * 2017-06-08 2021-02-23 Boe Technology Group Co., Ltd. Display panel and manufacturing method thereof, and display device
CN110120426A (zh) * 2018-02-07 2019-08-13 南京中电熊猫平板显示科技有限公司 一种薄膜晶体管的制造方法及薄膜晶体管
CN110120426B (zh) * 2018-02-07 2023-01-10 南京京东方显示技术有限公司 一种薄膜晶体管的制造方法及薄膜晶体管
CN109166868A (zh) * 2018-09-03 2019-01-08 深圳市华星光电半导体显示技术有限公司 一种阵列基板及其制备方法、显示面板
CN109166868B (zh) * 2018-09-03 2020-08-11 深圳市华星光电半导体显示技术有限公司 一种阵列基板及其制备方法、显示面板
CN109346526A (zh) * 2018-10-19 2019-02-15 京东方科技集团股份有限公司 氧化物薄膜晶体管及其制备方法、阵列基板及显示装置

Also Published As

Publication number Publication date
WO2016019672A1 (zh) 2016-02-11
US20160365366A1 (en) 2016-12-15
US9627414B2 (en) 2017-04-18

Similar Documents

Publication Publication Date Title
CN104167365A (zh) 金属氧化物薄膜晶体管、阵列基板及制作方法、显示装置
CN102709239B (zh) 显示装置、阵列基板及其制造方法
CN103700665B (zh) 金属氧化物薄膜晶体管阵列基板及其制作方法、显示装置
CN102651341B (zh) 一种tft阵列基板的制造方法
CN103236440B (zh) 薄膜晶体管、阵列基板及其制造方法、显示装置
US8952387B2 (en) Thin film transistor array substrate and method for manufacturing the same
CN101819363A (zh) Tft-lcd阵列基板及其制造方法
CN105226015B (zh) 一种tft阵列基板及其制作方法
CN102723279A (zh) 一种金属氧化物薄膜晶体管的制作方法
CN104835782A (zh) 阵列基板及其制作方法、显示装置
CN103048840B (zh) 阵列基板及其制作方法、液晶显示面板和显示装置
CN103311130A (zh) 一种非晶金属氧化物薄膜晶体管及其制备方法
CN102654698A (zh) 液晶显示器阵列基板及其制造方法、液晶显示器
CN104269413B (zh) 阵列基板及其制作方法、液晶显示装置
CN103094205A (zh) 一种薄膜晶体管、薄膜晶体管驱动背板的制备方法及薄膜晶体管驱动背板
CN105140296A (zh) 一种薄膜晶体管、其制备方法、阵列基板及显示面板
CN105097944A (zh) 薄膜晶体管及其制备方法、阵列基板、显示装置
CN102299104A (zh) Tft阵列基板的制作方法及tft阵列基板
CN102637648A (zh) 薄膜晶体管液晶显示器、阵列基板及其制造方法
CN102629576A (zh) 阵列基板及其制作方法
CN103700663A (zh) 一种阵列基板及其制作方法、显示装置
CN103456747A (zh) 阵列基板及其制作方法、显示装置
CN102693938B (zh) 薄膜晶体管液晶显示器、阵列基板及其制造方法
CN104167447A (zh) 一种薄膜晶体管及其制备方法、显示基板和显示设备
CN104617039A (zh) 阵列基板及其制作方法、显示装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20141126