CN106952927A - 叠层结构及其制备方法 - Google Patents
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- 238000010276 construction Methods 0.000 title claims abstract description 44
- 238000002360 preparation method Methods 0.000 title claims abstract description 39
- 239000000463 material Substances 0.000 claims abstract description 93
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000010408 film Substances 0.000 claims description 28
- 230000015572 biosynthetic process Effects 0.000 claims description 23
- 239000010409 thin film Substances 0.000 claims description 23
- 238000002161 passivation Methods 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 11
- 239000000203 mixture Substances 0.000 claims description 6
- 230000009194 climbing Effects 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 18
- 239000012212 insulator Substances 0.000 description 6
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 4
- 238000003475 lamination Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000004132 cross linking Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- NJWNEWQMQCGRDO-UHFFFAOYSA-N indium zinc Chemical compound [Zn].[In] NJWNEWQMQCGRDO-UHFFFAOYSA-N 0.000 description 2
- 239000000178 monomer Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 239000013039 cover film Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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Abstract
本发明涉及一种叠层结构及其制备方法。所述叠层结构包括:基板;位于所述基板上的至少一个材料层;穿过所述至少一个材料层的至少一部分的过孔,其中,所述过孔具有台阶状的侧表面;以及保形覆盖所述过孔的侧表面的另一材料层。所述至少一个材料层的厚度与所述另一材料层的厚度的比率大于10。本公开实施例提供的叠层结构能够降低材料覆盖过孔时由于材料爬坡困难而发生断线的风险,提高产品良率。
Description
技术领域
本发明的实施例涉及半导体技术领域,尤其涉及一种叠层结构及其制备方法。
背景技术
随着平板显示技术的不断推广,薄膜晶体管(TFT)的技术也得到迅速发展。掩膜层数的不断增加致使TFT制备过程中的过孔现象更为普遍。当过孔深度过大,尤其是对于目前的有机膜过孔,其深度是上方导电层厚度的数十倍,如此高的厚度差很容易使得导电层过孔时由于爬坡困难而存在断线风险。
发明内容
本发明实施例提供了一种叠层结构及其制备方法,能够降低材料覆盖过孔时由于材料爬坡困难而发生断线的风险,提高产品良率。
在本公开的第一方面中,提供一种叠层结构,包括:基板;位于所述基板上的至少一个材料层;穿过所述至少一个材料层的至少一部分的过孔,其中,所述过孔具有台阶状的侧表面;以及保形覆盖所述过孔的侧表面的另一材料层。
在一个实施例中,所述至少一个材料层的厚度与所述另一材料层的厚度的比率大于10。
在一个实施例中,所述叠层结构还包括薄膜晶体管;所述至少一个材料层至少覆盖所述薄膜晶体管;所述过孔暴露所述薄膜晶体管的源/漏极或栅极;以及所述另一材料层包括导电层。
在一个实施例中,所述至少一个材料层包括有机膜层。
在一个实施例中,所述有机膜层的厚度为约20000埃,所述导电层的厚度小于1000埃。
在一个实施例中,所述叠层结构还包括:位于所述导电层上的钝化层;以及位于所述钝化层上的又一导电层。
在本公开的第二方面中,还提供一种叠层结构的制备方法,包括:在基板上形成至少一个材料层;在所述至少一个材料层中形成穿过所述至少一个材料层的至少一部分的过孔,其中,所述过孔具有台阶状的侧表面;以及在所述至少一个材料层上保形形成另一材料层以覆盖所述过孔的侧表面。
在一个实施例中,所述至少一个材料层的厚度与所述另一材料层的厚度的比率大于10。
在一个实施例中,形成所述过孔的方法包括:形成穿过所述至少一个材料层的具有第一宽度的第一过孔,其中,所述第一过孔的深度小于所述至少一个材料层的厚度;以及在所述第一过孔的底部形成穿过所述至少一个材料层的具有第二宽度的第二过孔,
其中,所述第一宽度大于所述第二宽度,所述第二过孔的侧表面与所述第一过孔的侧表面不连续。
在一个实施例中,形成所述过孔的方法包括:形成穿过所述至少一个材料层的具有第三宽度的第三过孔;以及在所述第三过孔的顶部形成穿过所述至少一个材料层的具有第四宽度的第四过孔,
其中,所述第三宽度小于所述第四宽度,所述第三过孔的侧表面与所述第四过孔的侧表面不连续。
在一个实施例中,所述至少一个材料层包括有机膜层。
在一个实施例中,形成所述过孔的方法包括:采用半色调掩膜版一次构图形成具有台阶状的侧表面的所述过孔,其中,所述半色调掩膜版包括全透区、位于所述全透区两侧的半透区和位于所述半透区两侧的全遮区。
在一个实施例中,所述叠层结构的制备方法还包括:在形成所述至少一个材料层之前在所述基板上形成薄膜晶体管,其中,所述过孔暴露所述薄膜晶体管的源/漏极或栅极,所述另一材料层包括导电层;
以及所述叠层结构的制备方法进一步包括:在所述另一材料层上形成钝化层;以及在所述钝化层上形成又一导电层。
在一个实施例中,所述有机膜层的厚度为约20000埃,所述导电层的厚度小于1000埃。
在本文描述的实施例中,形成具有台阶状的侧表面的过孔,以使得当包括过孔的层的厚度远大于过孔上方的层的厚度时,能够降低过孔上方的层覆盖过孔时由于材料爬坡困难而发生断线的风险,从而提高产品良率。
适应性的进一步的方面和范围从本文中提供的描述变得明显。应当理解,本申请的各个方面可以单独或者与一个或多个其他方面组合实施。还应当理解,本文中的描述和特定实施例旨在仅说明的目的并不旨在限制本申请的范围。
附图说明
本文中描述的附图用于仅对所选择的实施例的说明的目的,并不是所有可能的实施方式,并且不旨在限制本申请的范围,其中:
图1示意性示出根据本公开实施例提供的一种叠层结构的截面图;
图2示意性示出根据本公开实施例提供的包括薄膜晶体管的叠层结构的截面图;
图3示意性示出根据本公开实施例的叠层结构的制备方法的形成至少一个材料层的示意图;
图4示意性示出根据本公开实施例的制备方法的形成过孔的示意图;
图5示意性示出根据本公开实施例的制备方法的形成另一材料层的示意图;
图6示意性示出根据本公开实施例的制备方法的形成第一过孔的示意图;
图7示意性示出根据本公开实施例的制备方法的形成第二过孔的示意图;
图8示意性示出根据本公开实施例的制备方法的形成第三过孔的示意图;
图9示意性示出根据本公开实施例的制备方法的形成第四过孔的示意图;
图10示意性示出根据本公开实施例的制备方法的形成过孔的示意图;以及
图11示意性示出根据本公开实施例的制备方法的形成包括薄膜晶体管的叠层结构的示意图。
贯穿这些附图的各个视图,相应的参考编号指示相应的部件或特征。
具体实施方式
首先需要说明的是,除非上下文中另外明确地指出,否则在本文和所附权利要求中所使用的词语的单数形式包括复数,反之亦然。因而,当提及单数时,通常包括相应术语的复数。相似地,措辞“包含”和“包括”将解释为包含在内而不是独占性地。同样地,术语“包括”和“或”应当解释为包括在内的,除非本文中明确禁止这样的解释。在本文中使用术语“示例”之处,特别是当其位于一组术语之后时,所述“示例”仅仅是示例性的和阐述性的,且不应当被认为是独占性的或广泛性的。
此外,在附图中,为了清楚起见夸大了各层的厚度及区域。应当理解的是,当提到层、区域、或组件在别的部分“上”时,指其直接位于别的部分上,或者也可能有别的组件介于其间。相反,当某个组件被提到“直接”位于别的组件上时,指并无别的组件介于其间。
另外,还需要说明的是,当介绍本申请的元素及其实施例时,冠词“一”、“一个”、“该”和“所述”旨在表示存在一个或者多个要素;除非另有说明,“多个”的含义是两个或两个以上;用语“包含”、“包括”、“含有”和“具有”旨在包括性的并且表示可以存在除所列要素之外的另外的要素;术语“第一”、“第二”、“第三”等仅用于描述的目的,而不能理解为指示或暗示相对重要性及形成顺序。
现将参照附图更全面地描述示例性的实施例。
在本文描述的实施例中,提供一种叠层结构,该叠层结构中包括具有台阶状的侧表面的过孔,能够降低过孔上方的层覆盖过孔时由于材料爬坡困难而发生断线的风险,从而提高产品良率。可以理解的是,除非另外声明,在本发明中,术语“叠层”可以包括一个层或多个层。
图1示意性示出根据本公开实施例提供的一种叠层结构10的截面图。如图1所示,叠层结构10包括基板1、位于基板1上的至少一个材料层6、穿过至少一个材料层6的至少一部分的过孔、以及保形覆盖该过孔的侧表面的另一材料层7。基板1可以为玻璃基板。在该实施例中,过孔具有台阶状的侧表面,过孔的侧表面的台阶数大于等于1。在一个示例性实施例中,过孔的侧表面的台阶数等于1。
在一个示例性实施例中,至少一个材料层6的厚度大于另一材料层7的厚度。可选地,至少一个材料层6的厚度与另一材料层7的厚度的比率大于10。
图2示意性示出根据本公开实施例提供的包括薄膜晶体管的叠层结构20的截面图。如图2所示,薄膜晶体管包括:位于基板1上的栅极2;位于基板1和栅极2上的栅极绝缘层3;位于栅极绝缘层3的部分上的有源层5;以及位于有源层4和栅极绝缘层3上的源漏电极层4。在该实施例中,至少一个材料层6至少覆盖薄膜晶体管;过孔暴露源/漏极;另一材料层7包括导电层7。可以理解的是,虽然以底栅型薄膜晶体管为例描述了本发明的实施例,但本发明实施例也同样适应于顶栅型薄膜晶体管的情况,在该情况下,薄膜晶体管包括依次位于基板上的有源层、栅极绝缘层、栅极或源/漏极,其中,过孔暴露栅极或源/漏极。
在一个示例性实施例中,如图2所示,叠层结构20还包括:位于导电层7上的钝化层8;以及位于钝化层8上的又一导电层9。钝化层8起绝缘保护作用,可以防止外界环境的水汽、杂质等对薄膜晶体管的干扰。
在一个示例性实施例中,至少一个材料层6包括有机膜层6。在一个示例性实施例中,有机膜层6的厚度大于导电层7的厚度。可选地,有机膜层6的厚度为约20000埃,导电层的厚度小于1000埃。
在一个示例性实施例中,导电层7可以为像素电极层7;又一导电层9可以为公共电极层9。
在一个示例性实施例中,有机膜层6包括粘合剂、光引发剂、交联单体等;像素电极层7包括氧化铟锡;公共电极层9包括氧化铟锡。
可以理解,像素电极层7和公共电极层9还包括其他导电材料,可选地,诸如包括氧化铟锌等的透明导电氧化物。
在本文描述的实施例中,还提供一种叠层结构的制备方法。制备出的叠层结构包括具有台阶状的侧表面的过孔,能够降低在过孔深度较深的情况下过孔上方的层过孔时发生断线的风险,从而提高产品良率。
现将参照图3至图11详细地描述本公开实施例提供的叠层结构的制备方法。
图3示意性示出根据本公开实施例的叠层结构的制备方法的形成至少一个材料层6的示意图。如图3所示,在基板1上形成至少一个材料层6。基板1可以为玻璃基板。
图4示意性示出根据本公开实施例的制备方法的形成过孔60的示意图。如图4所示,在至少一个材料层6中形成穿过至少一个材料层6的至少一部分的过孔60。在该实施例中,过孔60具有台阶状的侧表面。过孔60的侧表面的台阶数大于等于1。在一个示例性实施例中,过孔60的侧表面的台阶数等于1。
图5示意性示出根据本公开实施例的制备方法的形成另一材料层7的示意图。如图5所示,通过沉积或溅射等方法在至少一个材料层6上保形形成另一材料层7以覆盖过孔60的侧表面。
在该实施例中,至少一个材料层6的厚度大于另一材料层7。可选地,至少一个材料层6的厚度与另一材料层7的厚度的比率大于10。
接下来,参照图6至图10描述形成过孔60的方法。
图6和图7示出形成过孔60的第一种方法。图6示意性示出根据本公开实施例的制备方法的形成第一过孔601的示意图;图7示意性示出根据本公开实施例的制备方法的形成第二过孔602的示意图。
如图6所示,首先,通过构图形成穿过至少一个材料层6的具有第一宽度的第一过孔601。第一过孔601的深度小于至少一个材料层6的厚度。
如图7所示,然后,在第一过孔601的底部构图形成穿过至少一个材料层6的具有第二宽度的第二过孔602。在该实施例中,第一宽度大于第二宽度,第二过孔602的侧表面与第一过孔601的侧表面不连续。第一过孔601和第二过孔602构成具有台阶状的侧表面的过孔60。
图8和图9示出形成过孔60的第二种方法。
图8示意性示出根据本公开实施例的制备方法的形成第三过孔603的示意图;图9示意性示出根据本公开实施例的制备方法的形成第四过孔604的示意图。
如图8所示,首先,通过构图形成穿过至少一个材料层6的具有第三宽度的第三过孔603。在一个示例性实施例中,第三过孔603穿过整个至少一个材料层6。
如图9所示,然后,在第三过孔603的顶部构图形成穿过至少一个材料层6的具有第四宽度的第四过孔604。在该实施例中,第三宽度小于第四宽度,第三过孔603的侧表面与第四过孔604的侧表面不连续。第三过孔603和第四过孔604构成具有台阶状的侧表面的过孔60。
在一个示例性实施例中,至少一个材料层6包括有机膜层6。图10示意性示出在至少一个材料层6包括有机膜层6的情况下形成过孔60的示意图。
如图10所示,采用半色调掩膜版10通过一次构图在有机膜层6中形成具有台阶状的侧表面的过孔60。在该实施例中,半色调掩膜版10包括全透区101、位于全透区101两侧的半透区102和位于半透区102两侧的全遮区103。在曝光过程中,有机膜层6的与全透区101对应的区域完全曝光,有机膜层6的与半透区102对应的区域部分曝光,有机膜层6的与全遮区103对应的区域不曝光。然后,对有机膜层6的被曝光的部分进行显影以形成过孔60。
图11示意性示出根据本公开实施例的制备方法的形成包括薄膜晶体管的叠层结构30的示意图。
如图11所示,在基板1上依次形成栅极2、栅极绝缘层3、有源层5、以及源漏电极层4,其中,栅极2、栅极绝缘层3、有源层5和源漏电极层4构成薄膜晶体管;在薄膜晶体管上形成有机膜层6;在有机膜层6中一次构图形成穿过有机膜层6的过孔,其中,过孔具有台阶状的侧表面,过孔暴露源/漏极;在有机膜层6上保形形成另一材料层7,其中,另一材料层7包括导电层7;在导电层7上保形形成钝化层8;以及在钝化层8上形成又一导电层9。可以理解的是,虽然以底栅型薄膜晶体管为例描述了本发明的实施例,但本发明实施例也同样适应于顶栅型薄膜晶体管的情况,在该情况下,薄膜晶体管包括依次位于基板上的有源层、栅极绝缘层、栅极或源/漏极,其中,过孔暴露栅极或源/漏极。
在一个示例性实施例中,有机膜层6的厚度大于导电层7的厚度。可选地,有机膜层6的厚度为约20000埃,导电层的厚度小于1000埃。
在一个示例性实施例中,导电层7包括像素电极层,又一导电层9包括公共电极层。
在一个示例性实施例中,有机膜层6包括粘合剂、光引发剂、交联单体等;像素电极层7包括氧化铟锡;公共电极层9包括氧化铟锡。
可以理解,像素电极层7和公共电极层9还包括其他导电材料,可选地,诸如包括氧化铟锌等的透明导电氧化物。
在本公开的实施例中,描述了一种叠层结构及其制备方法。该叠层结构包括具有台阶状的侧表面的过孔,能够在包括该过孔的层的厚度大于过孔上方的层的厚度的情况下,降低过孔上方的层覆盖过孔时由于材料爬坡困难而发生断线的风险,从而提高产品良率。
以上为了说明和描述的目的提供了实施例的前述描述。其并不旨在是穷举的或者限制本申请。特定实施例的各个元件或特征通常不限于特定的实施例,但是,在合适的情况下,这些元件和特征是可互换的并且可用在所选择的实施例中,即使没有具体示出或描述。同样也可以以许多方式来改变。这种改变不能被认为脱离了本申请,并且所有这些修改都包含在本申请的范围内。
Claims (14)
1.一种叠层结构,其特征在于,包括:
基板;
位于所述基板上的至少一个材料层;
穿过所述至少一个材料层的至少一部分的过孔,
其中,所述过孔具有台阶状的侧表面;以及
保形覆盖所述过孔的侧表面的另一材料层。
2.根据权利要求1所述的叠层结构,其特征在于,所述至少一个材料层的厚度与所述另一材料层的厚度的比率大于10。
3.根据权利要求2所述的叠层结构,其特征在于,所述叠层结构还包括薄膜晶体管;
所述至少一个材料层至少覆盖所述薄膜晶体管;
所述过孔暴露所述薄膜晶体管的源/漏极或栅极;以及
所述另一材料层包括导电层。
4.根据权利要求3所述的叠层结构,其特征在于,所述至少一个材料层包括有机膜层。
5.根据权利要求4所述的叠层结构,其特征在于,所述有机膜层的厚度为约20000埃,所述导电层的厚度小于1000埃。
6.根据权利要求4所述的叠层结构,其特征在于,还包括:位于所述导电层上的钝化层;以及
位于所述钝化层上的又一导电层。
7.一种叠层结构的制备方法,其特征在于,包括:
在基板上形成至少一个材料层;
在所述至少一个材料层中形成穿过所述至少一个材料层的至少一部分的过孔,其中,所述过孔具有台阶状的侧表面;以及
在所述至少一个材料层上保形形成另一材料层以覆盖所述过孔的侧表面。
8.根据权利要求7所述的叠层结构的制备方法,其特征在于,所述至少一个材料层的厚度与所述另一材料层的厚度的比率大于10。
9.根据权利要求7所述的叠层结构的制备方法,其特征在于,形成所述过孔的方法包括:形成穿过所述至少一个材料层的具有第一宽度的第一过孔,其中,所述第一过孔的深度小于所述至少一个材料层的厚度;以及在所述第一过孔的底部形成穿过所述至少一个材料层的具有第二宽度的第二过孔,
其中,所述第一宽度大于所述第二宽度,所述第二过孔的侧表面与所述第一过孔的侧表面不连续。
10.根据权利要求7所述的叠层结构的制备方法,其特征在于,形成所述过孔的方法包括:形成穿过所述至少一个材料层的具有第三宽度的第三过孔;以及在所述第三过孔的顶部形成穿过所述至少一个材料层的具有第四宽度的第四过孔,
其中,所述第三宽度小于所述第四宽度,所述第三过孔的侧表面与所述第四过孔的侧表面不连续。
11.根据权利要求7所述的叠层结构的制备方法,其特征在于,所述至少一个材料层包括有机膜层。
12.根据权利要求11所述的叠层结构的制备方法,其特征在于,形成所述过孔的方法包括:采用半色调掩膜版一次构图形成具有台阶状的侧表面的所述过孔,其中,所述半色调掩膜版包括全透区、位于所述全透区两侧的半透区和位于所述半透区两侧的全遮区。
13.根据权利要求11所述的叠层结构的制备方法,其特征在于,所述叠层结构的制备方法还包括:在形成所述至少一个材料层之前在所述基板上形成薄膜晶体管,其中,所述过孔暴露所述薄膜晶体管的源/漏极或栅极,所述另一材料层包括导电层;
以及所述叠层结构的制备方法进一步包括:
在所述另一材料层上形成钝化层;以及
在所述钝化层上形成又一导电层。
14.根据权利要求13所述的叠层结构的制备方法,其特征在于,所述有机膜层的厚度为约20000埃,所述导电层的厚度小于1000埃。
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