WO2016061940A1 - Substrat de matrice à transistors à couches minces et procédé de fabrication de celui-ci, et écran d'affichage - Google Patents

Substrat de matrice à transistors à couches minces et procédé de fabrication de celui-ci, et écran d'affichage Download PDF

Info

Publication number
WO2016061940A1
WO2016061940A1 PCT/CN2015/072142 CN2015072142W WO2016061940A1 WO 2016061940 A1 WO2016061940 A1 WO 2016061940A1 CN 2015072142 W CN2015072142 W CN 2015072142W WO 2016061940 A1 WO2016061940 A1 WO 2016061940A1
Authority
WO
WIPO (PCT)
Prior art keywords
thin film
film transistor
conductive layer
array substrate
oxidation
Prior art date
Application number
PCT/CN2015/072142
Other languages
English (en)
Chinese (zh)
Inventor
杨小飞
杨玉清
莫再隆
石天雷
朴承翊
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2016061940A1 publication Critical patent/WO2016061940A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a thin film transistor array substrate, a method of fabricating the same, and a display device.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the TFT-LCD array substrate is one of the important components of the TFT-LCD.
  • the array substrate includes a display area and a non-display area located at a periphery of the display area, and the display area is formed with horizontally intersecting gate lines and data lines to define a plurality of pixel units, wherein each of the pixel units includes a thin film transistor (Thin Film Transistor) , referred to as TFT) and pixel electrodes.
  • TFT Thin Film Transistor
  • the drain electrode of the TFT is electrically connected to the pixel electrode, the source electrode and the data line are electrically connected, and the gate electrode and the gate line are electrically connected.
  • the thin film transistor is turned on by the gate line, and the pixel voltage transmitted on the data line is transmitted to the pixel electrode through the thin film transistor for driving the liquid crystal molecules to deflect to realize display of a specific gray scale.
  • the non-display area includes a PAD area and a GOA (Gate On Array) area.
  • the GOA region is a region in which a gate switching circuit is formed, and a signal line of the gate switching circuit is formed by a conductive layer forming a signal line (a signal line including a gate line, a data line, and the like) on the array substrate, thereby eliminating the gate.
  • the PAD region is a crimping region, and is located on one side or two adjacent sides of the array substrate, and is a region that connects the signal lines such as the gate lines and the data lines on the array substrate to the pins of the external driving circuit board. , including gate line PAD area, data line PAD area, and the like.
  • the signal lines of the PAD region are also formed by a conductive layer forming signal lines on the array substrate, and the uppermost layer is formed of a transparent conductive layer exposed on the surface for crimping with the pins of the driving chip, as shown in FIG.
  • the mainstream resolution of the display screen on the market has been developed to FHD (PPI above 400), and QHD (PPI above 480) has become a trend.
  • PPI PPI above 400
  • QHD PPI above 480
  • the metal signal lines of the array substrate are usually made of a metal alloy layer such as Ti-Al-Ti.
  • the array substrate of the high PPI display mainly adopts the LTPS process.
  • the basic process of the conventional LTPS TFT array substrate is: buffer layer 2 ⁇ polysilicon active layer (not shown) ⁇ gate insulating layer 3 ⁇ gate metal Layer 4 ⁇ interlayer insulating layer 5 ⁇ source/drain metal layer 6 ⁇ flat layer (generally Acrylic Resin material, not shown) ⁇ first transparent conductive layer 7, for the array substrate for driving the electric field to be a transverse electric field, further includes A second transparent conductive layer 8 is formed.
  • the Acrylic Resin layer is only distributed in the display area of the array substrate.
  • the source-drain metal layer of the signal line of the GOA region and the PAD region directly leaks into the environment, and therefore, when AcrylicResin is cured, it is easily oxidized, which greatly affects the GOA region and the PAD.
  • the present disclosure provides a thin film transistor array substrate, a manufacturing method thereof, and a display device for solving a problem that when a metal conductive layer of a non-display region is exposed to the environment and a thin film pattern is formed only in the display region, the metal conductive layer is oxidized. The problem.
  • the present disclosure provides a thin film transistor array substrate including a display area and a non-display area located at a periphery of the display area, the thin film transistor array substrate including a metal conductive layer located in the non-display area, and a cover
  • the first anti-oxidation structure on the surface of the metal conductive layer protects the metal conductive layer from oxidation.
  • the present disclosure also provides a display device including the thin film transistor array substrate as described above.
  • the present disclosure also provides a method for fabricating a thin film transistor array substrate, the thin film transistor array substrate including a display area and a non-display area located at a periphery of the display area, and the manufacturing method includes:
  • a first oxidation resistant structure covering the surface of the metal conductive layer is formed to protect the metal conductive layer from oxidation.
  • the surface of the metal conductive layer of the non-display area of the array substrate is covered with an oxidation resistant structure to prevent the metal conductive layer from being oxidized, so that when the metal conductive layer is exposed to the environment and formed only in the display area
  • the anti-oxidation structure can protect the thin film pattern
  • the metal conductive layer is not oxidized, reducing the transmission resistance of the metal conductive layer, improving the electrical contact characteristics of the metal conductive layer and the subsequently formed conductive layer, thereby improving the quality of the array substrate.
  • 1 is a schematic structural view of an array substrate
  • Figure 2 is a cross-sectional view along line A-A of Figure 1 of the prior art
  • Figure 3 is a cross-sectional view along line A-A of Figure 1 in an embodiment of the present disclosure
  • FIG. 9, and FIG. 10 are schematic diagrams showing a process of fabricating an array substrate in an embodiment of the present disclosure
  • Fig. 8 is a plan view of Fig. 7.
  • the thin film transistor array substrate includes a display area and a non-display area located at a periphery of the display area, and a non-display area is formed with a conductive layer for transmitting signals for providing a display area with a signal required for display.
  • the conductive layer includes a metal conductive layer.
  • the conductive layer of the non-display area and the conductive layer of the display area are formed by a patterning process of the same material film.
  • the metal conductive layer of the non-display region is exposed to the environment at this time, the metal conductive layer has a problem of being easily oxidized.
  • the present disclosure provides a thin film transistor array substrate and a method of fabricating the same, which can protect the metal conductive layer from being oxidized by forming an oxidation resistant structure covering a surface of the metal conductive layer located in the non-display region.
  • the transmission resistance of the metal conductive layer improves the electrical contact characteristics of the metal conductive layer and the subsequently formed conductive layer, thereby improving the quality of the array substrate.
  • a method for fabricating a thin film transistor array substrate includes a display area and a non-display area located at a periphery of the display area, and the manufacturer The law includes:
  • a first oxidation resistant structure covering the surface of the metal conductive layer is formed to protect the metal conductive layer from oxidation.
  • the metal conductive layer of the non-display area can be protected from being oxidized, the transmission resistance of the metal conductive layer is reduced, and the electrical contact characteristics of the metal conductive layer and the subsequently formed conductive layer are improved, thereby improving The quality of the array substrate.
  • an embodiment of the present disclosure further provides a thin film transistor array substrate including a display area and a non-display area located at a periphery of the display area.
  • the thin film transistor array substrate includes a metal conductive layer located in the non-display area, and a first oxidation resistant structure covering a surface of the metal conductive layer.
  • the first oxidation resistant structure serves to protect the metal conductive layer from oxidation.
  • a thin film pattern located only in the display region is formed, thereby being located in the non-display region in the process of forming the thin film pattern located only in the display region.
  • the surface of the metal conductive layer is covered with an oxidation resistant structure to protect the metal conductive layer from oxidation.
  • the conductive layer pattern of the non-display area and the conductive layer pattern of the display area are simultaneously formed by a patterning process for the same material film.
  • a plurality of pixel units are formed in a display region of the thin film transistor array substrate, and each of the pixel units includes a thin film transistor.
  • the thin film transistor includes a gate electrode, a gate insulating layer, an active layer pattern, a source electrode, and a drain electrode.
  • the gate line and the gate electrode are formed by patterning a film of the same gate metal (metals such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, and alloys of these metals), data lines
  • the source electrode and the drain electrode are formed by a patterning process of a thin film of the same source/drain metal (metals such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, and alloys of these metals).
  • the metal conductive layer located in the non-display area in the embodiment of the present disclosure includes a gate metal layer and a source/drain metal layer.
  • the pixel unit of the thin film transistor array substrate further includes a pixel electrode (formed of a transparent conductive film).
  • the conductive layer of the non-display area further includes a transparent conductive layer on the first oxidation resistant structure, and the transparent conductive layer may And electrically contacting the metal conductive layer through the first via in the first oxidation resistant structure. That is, the signal line of the non-display area includes a metal conductive layer and a transparent conductive layer located above the metal conductive layer.
  • the signal line that can set the non-display area includes a gate metal conductive layer, a source/drain metal layer, and a transparent conductive layer.
  • the step of forming the first anti-oxidation structure covering the surface of the metal conductive layer includes:
  • the photoresist semi-reserved area corresponds to a region where the via hole in the first anti-oxidation structure is located, and the photoresist completely reserved region corresponds to a portion of the first anti-oxidation structure from which the first via hole is removed. a region where the photoresist non-reserved region corresponds to other regions;
  • the remaining photoresist is removed.
  • the first via hole in the first anti-oxidation structure and the first anti-oxidation structure may be simultaneously formed by one patterning process, and the first via hole specifically corresponds to the photoresist semi-reserved region.
  • the step of forming the first anti-oxidation structure covering the surface of the metal conductive layer further includes:
  • the thin film pattern located only in the display region After forming the thin film pattern located only in the display region, etching the remaining anti-oxidation film of the photoresist semi-retained region to form the first anti-oxidation structure and the first of the first anti-oxidation structures Through hole. Since the metal conductive layer pattern is covered with the first oxidation resistant structure in the process of forming the thin film only in the display region, it can be effectively protected from oxidation. At the same time, the first via hole in the first anti-oxidation structure can be formed only by the etching process, and the patterning process for fabricating the first via hole is omitted, which simplifies the fabrication process.
  • Thin film transistors can be classified into polycrystalline silicon (Poly-Si, P-Si) TFTs and amorphous silicon (a-Si) TFTs depending on the material of the active layer.
  • the molecular structure of P-Si is in The arrangement in the grain is neat and directional, so the electron mobility is 200-300 times faster than the disordered amorphous silicon.
  • the fabrication process of P-Si mainly includes high temperature polysilicon (HTPS) and low temperature poly-Silicon (LTPS).
  • HTPS high temperature polysilicon
  • LTPS low temperature poly-Silicon
  • the array substrate of the high-resolution display mainly adopts the LTPS process.
  • the non-display area further includes a transparent conductive layer electrically connected to the metal conductive layer to ensure reliable transmission of the electrical signal.
  • the thin film transistor array substrate is an LTPS array substrate including a thin film transistor and a pixel electrode located in the display region, and simultaneously forms a conductive layer of the non-display region in the fabrication process of the thin film transistor and the pixel electrode. Therefore, the method for fabricating the thin film transistor array substrate in the embodiment of the present disclosure further includes:
  • a source/drain metal film Forming a source/drain metal film, patterning the source/drain metal film, forming a source electrode and a drain electrode of the thin film transistor, and a source/drain metal layer located in the non-display region;
  • a source layer and a drain electrode of the thin film transistor are formed, a flat layer located only in the display region is formed.
  • the source/drain metal layer of the non-display region is exposed to the environment, and is easily oxidized when the flat layer is cured.
  • the source/drain metal layer of the non-display region can be effectively protected from oxidation.
  • the specific plan is:
  • a flat layer is formed on the substrate on which the first oxidation resistant structure is formed, the flat layer being located only in a display region of the thin film transistor array substrate.
  • a pixel electrode and a transparent conductive layer located in the non-display region are formed on the substrate on which the flat layer is formed, and the transparent conductive layer and the source/drain metal layer are electrically connected.
  • the transparent conductive layer is a low-temperature transparent conductive layer
  • residue is likely to occur when the transparent conductive film is etched, especially at a position where the film layer difference is large. (Specifically the boundary position of the display area because the flat layer is only located in the display area).
  • the residual transparent conductive film causes adjacent source and drain metal layers to be connected together to form a short circuit.
  • the pixel electrode is in electrical contact with the drain electrode of the thin film transistor through a via hole in the planar layer.
  • the manufacturing process of the flat layer is: coating, exposure development and curing of the Acrylic Resin material, wherein the curing process is performed after the via hole exposing the drain electrode is formed in the flat layer, so that the drain electrode of the thin film transistor exists. Easy to be oxidized.
  • a second oxidation resistant structure covering the drain electrode surface of the thin film transistor is formed to protect the drain electrode Not oxidized.
  • the second anti-oxidation structure and the first anti-oxidation structure may be the same material.
  • a second via hole is formed in the second oxidation resistant structure while forming the first via hole in the first oxidation resistant structure.
  • the pixel electrode is in electrical contact with a drain electrode of the thin film transistor through the second via.
  • the LTPS array substrate of the liquid crystal display device and the driving electric field is a lateral electric field is taken as an example to specifically describe the manufacturing method in the embodiment of the present disclosure.
  • a schematic diagram of a non-display area is shown, and a schematic view of the display area is omitted.
  • a person skilled in the art can obtain a schematic diagram of the display area through a schematic diagram of the non-display area without requiring creative labor.
  • the manufacturing method includes the following steps:
  • Step S1 providing a base substrate 1, which may be a transparent substrate such as a glass substrate, a quartz substrate, or an organic resin substrate, and forming a buffer layer 2 on the base substrate 1, and forming an active layer of the thin film transistor on the buffer layer 2.
  • the pattern is then formed with a gate insulating layer 3 on the active layer pattern.
  • the material of the active layer may be a silicon semiconductor or a metal oxide semiconductor.
  • the material of the buffer layer 2 and the gate insulating layer 3 may be an oxide, a nitride or an oxynitride, and may be a single layer, a double layer or a multilayer structure.
  • the gate insulating layer 3 may be SiNx, SiOx or Si(ON)x.
  • Step S2 simultaneously forming a gate metal layer 4 located in the non-display region, and a gate electrode and a gate located in the display region on the substrate 1 on which the step S1 is completed by patterning the same gate metal film line.
  • a thickness of a thickness of the substrate substrate 1 on which the step S1 is completed may be performed by sputtering or thermal evaporation.
  • the gate metal layer may be a metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, or an alloy of these metals; the gate metal layer may be a single layer structure or a multilayer structure, and the multilayer structure For example, Cu ⁇ Mo, Ti ⁇ Cu ⁇ Ti, Mo ⁇ Al ⁇ Mo, Ti/Al/Ti, and the like.
  • a photoresist is coated on the gate metal film, and the photoresist is exposed and developed by using a mask to form a photoresist non-retained region and a photoresist retention region, wherein the photoresist is retained.
  • the region corresponds to the region where the gate metal layer 4, the gate line and the gate electrode are located, and the photoresist non-retained region corresponds to other regions; the gate metal film of the photoresist non-retained region is completely etched by the etching process, and the remaining portion is peeled off.
  • the photoresist forms a gate metal layer 4, a gate line, and a gate electrode.
  • Step S3 an interlayer insulating layer 5 is formed on the base substrate 1 on which the step S2 is completed, and a via hole is formed in the interlayer insulating layer 5 by a patterning process to expose the gate metal layer 4.
  • the material of the interlayer insulating layer 5 may be an oxide, a nitride or an oxynitride, and may be a single layer, a double layer or a multilayer structure. Specifically, the interlayer insulating layer 5 may be SiNx, SiOx or Si(ON)x.
  • Step S4 forming a source/drain metal layer 6 located in the non-display area, and a source electrode, a drain electrode, and a data line located in the display area on the base substrate 1 completing the step S3 by patterning the same source/drain metal film;
  • the source/drain metal layer 6 is electrically connected to the gate metal layer 4 through via holes in the interlayer insulating layer 5.
  • a thickness of about one layer may be deposited by magnetron sputtering, thermal evaporation, or other film formation method on the substrate 1 on which the step S3 is completed.
  • the source-drain metal film, the source-drain metal film may be a metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, and an alloy of these metals.
  • the source/drain metal layer may be a single layer structure or a multilayer structure such as Cu ⁇ Mo, Ti ⁇ Cu ⁇ Ti, Mo ⁇ Al ⁇ Mo, Ti/Al/Ti, or the like.
  • Step S5 forming an oxidation resistant film 10 on the substrate 1 of the step S4, and performing an patterning process on the oxide film 10 to form the oxidation resistant structure 12;
  • the material of the oxidation resistant film 10 may be an oxide, a nitride or an oxynitride, and may be a single layer, a double layer or a multilayer structure. Specifically, the oxidation resistant film 10 may be SiNx, SiOx or Si(ON)x.
  • the plasma enhanced chemical vapor deposition (PECVD) method can be used to form the oxidation resistant film 10 on the substrate 1 of the step S4;
  • a photoresist 11 is formed on the oxidation resistant film 10;
  • the photoresist 11 is exposed through a gray tone or halftone mask 20 as shown in FIG. 4; wherein the mask 20 includes a semi-transmissive region 13, an opaque region 14, and a fully transparent region 15
  • the exposed photoresist 11 includes a photoresist semi-reserved region 23, a photoresist completely remaining region 24, and a photoresist non-retained region, as shown in FIG.
  • the photoresist semi-reserved region 23 corresponds to the first The area of the first via hole in the oxidation resistant structure 12, the photoresist completely remaining area 24 corresponds to the area where the first anti-oxidation structure 12 removes the portion of the first via hole, and the photoresist non-reserved area corresponds to other areas;
  • the anti-oxidation film 10 of the photoresist non-retained region is etched away;
  • the photoresist of the photoresist semi-retained region 23 is removed by an ashing process, and the photoresist of the photoresist 24 completely retaining the region 24 has a certain thinning effect;
  • a pattern of the first anti-oxidation structure 12 covering the source/drain metal layer 6 of the non-display region and the region of the first via hole in the first anti-oxidation structure 12 is formed, wherein the first via corresponds to the photoresist semi-reserved Area 23.
  • a second anti-oxidation structure (not shown) having the same shape as the first anti-oxidation structure 12 is also formed on the drain electrode of the thin film transistor, covering the surface of the drain electrode because In the fabrication process of the flat layer, the drain electrode is also easily oxidized when exposed to the environment.
  • step S6 a flat layer is formed on the base substrate 1 which is completed in step S5.
  • the material of the flat layer shown is an Acrylic Resin material, which is only located in the display area of the array substrate.
  • the surface of the source/drain metal layer 6 of the non-display region of the array substrate is covered with an anti-oxidation film and is not oxidized.
  • the drain electrode surface of the thin film transistor is also covered with an anti-oxidation film and is not oxidized.
  • the manufacturing process of the flat layer may be:
  • the formed Acrylic Resin film is exposed and developed through a mask to form Acrylic The Resin retention area and the Acrylic Resin non-reserved area, the Acrylic Resin non-retained area at least corresponding to the area where the drain electrode is located, exposing the thinner portion of the second anti-oxidation structure covering the surface of the drain electrode, and the Acrylic Resin reserved area corresponding to other areas ;
  • Step S7 after the step S6 is completed, the thin anti-oxidation film is etched to form the first anti-oxidation structure 12, wherein the first anti-oxidation structure 12 is provided with the first via 30, as shown in FIG. .
  • FIG. 8 is a top view of FIG. 7. It can be seen that the first anti-oxidation structure 12 is formed with a first via hole 30 in the middle thereof to expose the underlying source/drain metal layer 6.
  • the thin portion of the second anti-oxidation structure covering the surface of the drain electrode is simultaneously etched to form a second via hole, and the drain electrode is exposed, so that the subsequently formed pixel electrode and the drain electrode are electrically contacted. And conduct.
  • Step S8 forming a first transparent conductive layer 7 located in the non-display area and a pixel electrode located in the display area on the base substrate 1 completing the step S7 by patterning the same first transparent conductive film, as shown in FIG. .
  • the thickness is deposited by magnetron sputtering, thermal evaporation or other film formation method on the base substrate 1 subjected to step S7.
  • the transparent conductive film, the transparent conductive film may be ITO or IZO.
  • Coating a photoresist on the transparent conductive film exposing and developing the photoresist by using a mask to form a photoresist non-retained region and a photoresist retention region, wherein the photoresist remains
  • the area corresponds to the area where the first transparent conductive layer 7 and the pixel electrode are located, and the photoresist non-reserved area corresponds to other areas; the transparent conductive film of the photoresist non-retained area is completely etched by the etching process, and the remaining lithography is peeled off.
  • the glue forms a first transparent conductive layer 7 and a pixel electrode.
  • the first transparent conductive layer 7 is electrically connected to the source/drain metal layer 6 through the first via hole in the first oxidation resistant structure 12 .
  • the pixel electrode is in electrical contact with the drain electrode of the thin film transistor through the second via hole penetrating the flat layer and the second oxidation resistant structure.
  • Step S9 forming a passivation layer 8 on the substrate 1 on which the step S8 is completed, and forming the passivation layer 8 A patterning process is performed to form passivation layer vias 31.
  • the passivation layer 8 covers at least the active layer of the thin film transistor for ensuring electrical characteristics of the thin film transistor.
  • Step S10 forming a second transparent conductive layer 9 located in the non-display area and a common electrode located in the display area on the base substrate 1 completing the step S9 by patterning the same transparent conductive film, as shown in FIG.
  • the LTPS array substrate formed by the above steps specifically includes:
  • the base substrate 1 is a transparent substrate such as a glass substrate, a quartz substrate, or an organic resin substrate;
  • a gate metal layer 4 formed on the gate insulating layer 3 and located in the non-display region, a gate electrode and a gate line formed on the gate insulating layer 3 and located in the display region, the gate metal layer 4, the gate electrode and the gate line passing through A patterning process of the same gate metal film is formed;
  • a source/drain metal layer 6 formed on the interlayer insulating layer 5 and located in the non-display region, a source electrode, a drain electrode and a data line formed on the interlayer insulating layer 5 and located in the display region, the source/drain metal layer 6, the The source electrode, the drain electrode and the data line are formed by a patterning process on the same source/drain metal film, and the source/drain metal layer 6 is electrically contacted with the gate metal layer 4 through via holes in the interlayer insulating layer 5;
  • a first anti-oxidation structure 12 covering the surface of the source/drain metal layer 6, covering the second anti-oxidation structure on the surface of the drain electrode;
  • the second via in the oxidized structure is in electrical contact with the drain electrode;
  • a patterning process of a transparent conductive film is formed, and the second transparent conductive layer 9 is electrically contacted with the first transparent conductive layer 7 through via holes in the passivation layer 8.
  • the driving electric field of the LTPS array substrate is a transverse electric field
  • the signal line of the non-display area includes the electrically connected gate metal layer 4, the source/drain metal layer 5, the first transparent conductive layer 7, and the second transparent conductive layer 9, which have higher Reliability.
  • the driving electric field is a longitudinal electric field
  • it does not include a passivation layer formed on the pixel electrode and a common electrode formed on the passivation layer, and a fabrication process of the passivation layer and the common electrode is omitted.
  • a display device including the thin film transistor array substrate as described above is also provided in the embodiment of the present disclosure.
  • the display device may be a liquid crystal display device or an active organic light emitting diode display device.
  • the fabrication process of the thin film transistor is the same as described above, and the first oxidation resistant structure covering the surface of the source/drain metal layer of the non-display region can be formed by the same process, and the source/drain metal layer can also be The first via in the first oxidation resistant structure is electrically connected to the subsequently formed conductive layer.
  • the manufacturing process of the organic light emitting diode please refer to the prior art, which will not be described in detail herein.
  • the surface of the metal conductive layer of the non-display area of the array substrate is covered with an oxidation resistant structure to prevent the metal conductive layer from being oxidized, so that when the metal conductive layer is exposed to the environment and formed only When the film pattern of the region is displayed, the oxidation resistant structure can protect the metal conductive layer from being oxidized, reduce the transmission resistance of the metal conductive layer, and improve electrical contact between the metal conductive layer and the subsequently formed conductive layer. characteristic. At the same time, it also facilitates high-density line layout in the non-display area and improves the quality of the array substrate.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention concerne un substrat de matrice à transistors à couches minces, un procédé de fabrication de celui-ci, et un écran d'affichage. La surface d'une couche (6) conductrice métallique dans une zone de non affichage du substrat de réseau est recouverte d'une structure anti-oxydante (12) de manière à empêcher toute oxydation de la couche conductrice métallique (6).
PCT/CN2015/072142 2014-10-24 2015-02-03 Substrat de matrice à transistors à couches minces et procédé de fabrication de celui-ci, et écran d'affichage WO2016061940A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410578332.8 2014-10-24
CN201410578332.8A CN104393001B (zh) 2014-10-24 2014-10-24 薄膜晶体管阵列基板及其制作方法、显示装置

Publications (1)

Publication Number Publication Date
WO2016061940A1 true WO2016061940A1 (fr) 2016-04-28

Family

ID=52610876

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/072142 WO2016061940A1 (fr) 2014-10-24 2015-02-03 Substrat de matrice à transistors à couches minces et procédé de fabrication de celui-ci, et écran d'affichage

Country Status (2)

Country Link
CN (1) CN104393001B (fr)
WO (1) WO2016061940A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106648210A (zh) * 2016-10-19 2017-05-10 合肥鑫晟光电科技有限公司 显示面板及其制备方法、显示装置
CN107731882A (zh) * 2017-11-07 2018-02-23 深圳市华星光电半导体显示技术有限公司 一种有机薄膜晶体管阵列基板及其制备方法、显示装置

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105762112A (zh) * 2016-04-28 2016-07-13 京东方科技集团股份有限公司 薄膜晶体管阵列基板及其制备方法、显示装置
CN107180837A (zh) * 2017-05-17 2017-09-19 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN107179644B (zh) * 2017-05-19 2021-11-09 京东方科技集团股份有限公司 一种显示基板、其制作方法及显示装置
CN107622974A (zh) * 2017-08-28 2018-01-23 武汉华星光电半导体显示技术有限公司 Tft基板的制作方法及tft显示装置的制作方法
CN107579040B (zh) * 2017-09-07 2020-04-21 京东方科技集团股份有限公司 一种掩膜版、阵列基板及其制作方法
CN111384087A (zh) * 2018-12-28 2020-07-07 武汉华星光电半导体显示技术有限公司 有机发光二极管显示面板
CN110931525B (zh) * 2019-11-22 2023-01-10 京东方科技集团股份有限公司 一种oled阵列基板及其制备方法和显示装置
CN113497090B (zh) * 2020-03-20 2023-09-22 合肥鑫晟光电科技有限公司 一种显示基板及其制作方法、显示面板
JP2023533880A (ja) * 2020-05-13 2023-08-07 京東方科技集團股▲ふん▼有限公司 駆動基板及びその製作方法、表示装置
CN111564457B (zh) * 2020-05-28 2022-08-05 武汉华星光电技术有限公司 一种阵列基板及其制备方法、显示面板
CN114171661A (zh) * 2020-09-10 2022-03-11 京东方科技集团股份有限公司 一种发光基板、显示装置及制作方法
CN112687548B (zh) * 2020-12-25 2024-05-24 光华临港工程应用技术研发(上海)有限公司 可转移的柔性互联结构的制备方法以及结构
CN112885850B (zh) * 2021-01-29 2024-04-05 合肥京东方卓印科技有限公司 显示面板、显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1623117A (zh) * 2002-04-04 2005-06-01 三星电子株式会社 用于显示装置的薄膜晶体管阵列板的制造方法
JP2010181474A (ja) * 2009-02-03 2010-08-19 Mitsubishi Electric Corp 薄膜トランジスタアレイ基板、反射型液晶表示装置及びその製造方法
US7838880B2 (en) * 2005-09-30 2010-11-23 Samsung Mobile Display Co., Ltd. Flat panel display device
CN102709239A (zh) * 2012-04-20 2012-10-03 京东方科技集团股份有限公司 显示装置、阵列基板及其制造方法
CN103268047A (zh) * 2012-12-31 2013-08-28 厦门天马微电子有限公司 一种ltps阵列基板及其制造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101196645B (zh) * 2006-12-06 2011-07-20 瀚宇彩晶股份有限公司 Rgbw彩色滤光片的结构及其制作方法
CN103107135B (zh) * 2013-02-19 2016-01-06 京东方科技集团股份有限公司 一种阵列基板的制作方法、阵列基板和显示装置
JP2014191027A (ja) * 2013-03-26 2014-10-06 Sony Corp 表示装置及び電子機器

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1623117A (zh) * 2002-04-04 2005-06-01 三星电子株式会社 用于显示装置的薄膜晶体管阵列板的制造方法
US7838880B2 (en) * 2005-09-30 2010-11-23 Samsung Mobile Display Co., Ltd. Flat panel display device
JP2010181474A (ja) * 2009-02-03 2010-08-19 Mitsubishi Electric Corp 薄膜トランジスタアレイ基板、反射型液晶表示装置及びその製造方法
CN102709239A (zh) * 2012-04-20 2012-10-03 京东方科技集团股份有限公司 显示装置、阵列基板及其制造方法
CN103268047A (zh) * 2012-12-31 2013-08-28 厦门天马微电子有限公司 一种ltps阵列基板及其制造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106648210A (zh) * 2016-10-19 2017-05-10 合肥鑫晟光电科技有限公司 显示面板及其制备方法、显示装置
CN106648210B (zh) * 2016-10-19 2023-11-28 合肥鑫晟光电科技有限公司 显示面板及其制备方法、显示装置
CN107731882A (zh) * 2017-11-07 2018-02-23 深圳市华星光电半导体显示技术有限公司 一种有机薄膜晶体管阵列基板及其制备方法、显示装置

Also Published As

Publication number Publication date
CN104393001A (zh) 2015-03-04
CN104393001B (zh) 2017-10-31

Similar Documents

Publication Publication Date Title
WO2016061940A1 (fr) Substrat de matrice à transistors à couches minces et procédé de fabrication de celui-ci, et écran d'affichage
US8563980B2 (en) Array substrate and manufacturing method
TWI567800B (zh) 平面顯示設備及製造其之方法
US9299763B2 (en) Thin film transistor array substrate and method of manufacturing the same
WO2016119324A1 (fr) Substrat de matrice et procédé de fabrication correspondant, et appareil d'affichage
KR101431136B1 (ko) 박막 트랜지스터 기판의 제조 방법
US10644037B2 (en) Via-hole connection structure and method of manufacturing the same, and array substrate and method of manufacturing the same
WO2016145769A1 (fr) Transistor à couches minces et son procédé de fabrication, substrat matriciel et appareil d'affichage
TWI460516B (zh) 畫素結構及其製作方法
KR102050401B1 (ko) 디스플레이 장치 및 그 제조방법
KR20120039947A (ko) 표시 장치 및 그 제조 방법
TW201418855A (zh) 顯示面板之陣列基板及其製作方法
WO2017020480A1 (fr) Procédé de préparation de transistor à couches minces et de substrat de réseau, substrat de réseau et appareil d'affichage
US20160181278A1 (en) Array substrate, method for manufacturing the same, and display device
US20160358937A1 (en) Array Substrate and Manufacturing Method Thereof and Display Panel
WO2017140058A1 (fr) Substrat de matrice, son procédé de fabrication, écran d'affichage et appareil d'affichage
EP2757589A2 (fr) Procédés de fabrication d'un transistor à film mince et d'un substrat en réseau
US9741861B2 (en) Display device and method for manufacturing the same
US10205029B2 (en) Thin film transistor, manufacturing method thereof, and display device
US20150021608A1 (en) Array substrate and method for manufacturing the same
US8008135B2 (en) Method for manufacturing pixel structure
KR20120043404A (ko) 표시장치 및 이의 제조방법
US8383466B2 (en) Display device and method of manufacturing the same
US10763283B2 (en) Array substrate, manufacturing method thereof, display panel and manufacturing method thereof
KR101978789B1 (ko) 표시장치용 어레이 기판 및 그의 제조 방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15852814

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 20/10/2017)

122 Ep: pct application non-entry in european phase

Ref document number: 15852814

Country of ref document: EP

Kind code of ref document: A1