WO2023108429A1 - Procédé de fabrication de transistor à couches minces, substrat de réseau et écran d'affichage - Google Patents

Procédé de fabrication de transistor à couches minces, substrat de réseau et écran d'affichage Download PDF

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Publication number
WO2023108429A1
WO2023108429A1 PCT/CN2021/137997 CN2021137997W WO2023108429A1 WO 2023108429 A1 WO2023108429 A1 WO 2023108429A1 CN 2021137997 W CN2021137997 W CN 2021137997W WO 2023108429 A1 WO2023108429 A1 WO 2023108429A1
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Prior art keywords
tft
layer
channel
photoresist
microns
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PCT/CN2021/137997
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English (en)
Chinese (zh)
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简锦诚
王海宏
陈旭
古宏刚
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京东方科技集团股份有限公司
南京京东方显示技术有限公司
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Priority to CN202180003961.6A priority Critical patent/CN116615799A/zh
Priority to PCT/CN2021/137997 priority patent/WO2023108429A1/fr
Publication of WO2023108429A1 publication Critical patent/WO2023108429A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present application relates to the field of display technology, in particular to a method for preparing a thin film transistor, an array substrate and a display panel.
  • an electrostatic protection circuit connected to the signal lines will be provided on the array substrate.
  • the electrostatic protection circuit is also generally referred to as an electrostatic discharge (electro static discharge, ESD) circuit.
  • the electrostatic protection circuit in the related art generally includes a plurality of thin film transistors (thin film transistor, TFT), and the plurality of TFTs can be fabricated simultaneously with the TFTs in the pixels of the array substrate.
  • TFT thin film transistor
  • the present application provides a method for preparing a TFT, an array substrate and a display panel, and the technical scheme is as follows:
  • a method for preparing a thin film transistor comprising:
  • the photoresist layer is exposed using a half-tone mask to define a plurality of partially removed regions, a plurality of reserved regions and a plurality of completely removed regions in the photoresist layer, the plurality of partially removed regions
  • the region is the area where the orthographic projection of the multiple half-transmission regions of the half-tone mask on the photoresist layer is located, at least two of the half-transmission regions have different sizes, and the half-transmission regions have different sizes.
  • the transmittance is 25% to 35%;
  • the thickness of the first photoresist pattern is smaller than the thickness of the second photoresist pattern
  • each TFT includes a source electrode and a drain electrode formed by the first metal layer, and an active layer formed by the semiconductor film layer, and the channel in the active layer of each TFT is located in one of the first metal layers.
  • a photoresist pattern is within the orthographic projection of the base substrate, and the length of the channel of the first TFT is greater than the length of the channel of the second TFT.
  • the length of the channel of the first TFT is greater than or equal to 8um, and the length of the channel of the second TFT is 4um to 6um.
  • the length of the channel of the first TFT is 50 microns to 70 microns.
  • the width of the channel of the first TFT and the width of the channel of the second TFT are both 5 to 10 um.
  • the first TFT is a TFT in an electrostatic protection circuit in the array substrate
  • the second TFT is a TFT in a pixel in the array substrate.
  • the thickness of the active layer is greater than or equal to
  • the thickness of the source electrode and the drain electrode are both greater than or equal to
  • the photoresist layer has a thickness of 2 microns to 2.4 microns;
  • the thickness of the first photoresist pattern covering the channel of the first TFT is greater than or equal to 0.5 microns, and the thickness of the first photoresist pattern covering the channel of the second TFT is greater than or equal to 0.7 micrometers. Microns.
  • the method also includes:
  • a gate insulating layer is formed on a side of the gates of the plurality of first TFTs and the gates of the plurality of second TFTs away from the base substrate.
  • the method also includes:
  • the planar layer includes a plurality of spaced planar patterns, and the orthographic projection of each of the planar patterns on the base substrate covers one gate of the TFT;
  • a plurality of via holes are formed in the insulating layer, and the orthographic projection of each of the via holes on the base substrate overlaps with the interval area between two adjacent flat patterns, and the pixel electrode passes through at least one The via hole is connected with the source or the drain.
  • an array substrate in another aspect, includes a base substrate, and a plurality of first thin film transistors TFTs and a plurality of second TFTs located on the base substrate;
  • Each TFT includes a source, a drain, and an active layer, and the length of the channel of the first TFT is greater than the length of the channel of the second TFT;
  • the source electrode, the drain electrode and the active layer of a plurality of said TFTs are prepared by using a half-tone mask, and the half-tone mask has a plurality of semi-transmissive regions, and each of the semi-transmissive regions It is used to define the region where the channel in the active layer of a TFT is located, and the transmittance of the semi-transmissive region is 25% to 35%.
  • the length of the channel of the first TFT is greater than or equal to 8um, and the length of the channel of the second TFT is 4um to 6um.
  • the length of the channel of the first TFT is 50 microns to 70 microns.
  • the width of the channel of the first TFT and the width of the channel of the second TFT are both 5um to 10um.
  • the first TFT is a TFT in an electrostatic protection circuit in the array substrate
  • the second TFT is a TFT in a pixel in the array substrate.
  • the thickness of the semiconductor film layer is greater than or equal to The thickness of the first metal layer is greater than or equal to
  • a display panel in yet another aspect, includes: a driving circuit, and the array substrate described in the above aspect, the driving circuit is configured to provide a driving signal for the array substrate.
  • Fig. 1 is the schematic diagram of the antistatic property of the TFT of a kind of different channel length that the embodiment of the application provides;
  • Fig. 2 is a schematic diagram of the antistatic performance of a TFT with different channel widths provided by an embodiment of the present application;
  • FIG. 3 is a flow chart of a method for preparing a TFT provided in an embodiment of the present application
  • Fig. 4 is a schematic structural view of a base substrate formed with a semiconductor film layer, a first metal layer and a photoresist layer provided by an embodiment of the present application;
  • FIG. 5 is a schematic structural view of a base substrate after etching the first metal layer and the semiconductor film layer not covered by the photoresist pattern provided by the embodiment of the present application;
  • FIG. 6 is a schematic structural view of a base substrate after etching the first metal layer covered by the first photoresist pattern provided by the embodiment of the present application;
  • FIG. 7 is a schematic structural diagram of a first photoresist pattern provided by an embodiment of the present application when the channel length is relatively long;
  • FIG. 8 is a schematic structural diagram of a first photoresist pattern provided by an embodiment of the present application when the channel length is short;
  • FIG. 9 is a flow chart of another method for manufacturing a thin film transistor provided in an embodiment of the present application.
  • FIG. 10 is a schematic structural view of a base substrate formed with a gate provided by an embodiment of the present application.
  • Fig. 11 is a top view of a base substrate formed with a gate provided by an embodiment of the present application.
  • FIG. 12 is a schematic structural view of a base substrate after developing a photoresist layer provided in an embodiment of the present application.
  • FIG. 13 is a schematic structural view of a base substrate after ashing the first photoresist pattern and the second photoresist pattern provided by the embodiment of the present application;
  • FIG. 14 is a schematic structural view of a base substrate after removal of the second photoresist pattern provided by an embodiment of the present application.
  • Fig. 15 is a top view of a base substrate after removal of the second photoresist pattern provided by the embodiment of the present application;
  • Fig. 16 is a schematic structural view of a base substrate formed with a flat layer and a protective layer according to an embodiment of the present application;
  • FIG. 17 is a schematic structural view of a substrate provided with an insulating layer formed in an embodiment of the present application.
  • FIG. 18 is a schematic structural view of a base substrate formed with a pixel electrode provided by an embodiment of the present application.
  • Fig. 19 is a top view of a base substrate provided with an insulating layer according to an embodiment of the present application.
  • Fig. 20 is a top view of a base substrate formed with a pixel electrode according to an embodiment of the present application
  • Fig. 21 is a schematic structural diagram of an array substrate provided by an embodiment of the present application.
  • FIG. 22 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 1 is a schematic diagram of the antistatic performance of a TFT with different channel lengths provided by an embodiment of the present application.
  • the horizontal axis in FIG. 1 is the voltage applied to the gate of the TFT, and the unit is volt (V); the vertical axis shows the current flowing through the TFT (ie, the drain current of the TFT), and the unit is ampere (A).
  • FIG. 1 shows the curves of drain current versus voltage of TFTs whose channel width W is 5 micrometers (um) and channel lengths L are 20um, 30um, 40um, 50um and 60um respectively.
  • FIG. 2 is a schematic diagram of the antistatic performance of a TFT with different channel widths provided by an embodiment of the present application.
  • the horizontal axis in Figure 2 represents different electrostatic protection circuits; the vertical axis represents the maximum voltage that the TFT can withstand, and the unit is V.
  • FIG. 2 shows the maximum voltages that TFTs with a channel length L of 60 um and a channel width W of 5 um and 10 um can withstand in different ESD circuits.
  • the channel width of the TFT also has a certain influence on the antistatic performance of the TFT.
  • the channel length of the TFT has a great influence on the antistatic performance of the TFT.
  • the channel length of the TFT in the pixel of the array substrate is usually short (generally 4um to 6um)
  • the TFT in the electrostatic protection circuit and the TFT in the pixel are prepared at the same time. Therefore, the channel length of the TFT in the prepared electrostatic protection circuit is relatively short, which in turn leads to poor antistatic performance of the electrostatic protection circuit.
  • the examples of this application provide a method for preparing TFTs, which can simultaneously prepare TFTs with different channel lengths.
  • the method includes:
  • Step 101 sequentially forming a semiconductor film layer, a first metal layer and a photoresist layer on a base substrate.
  • the base substrate may be a glass substrate.
  • the semiconductor film layer and the first metal layer may be formed by a physical vapor deposition (Physical Vapor Deposition, PVD) process, and the photoresist layer may be formed by a coating process.
  • the semiconductor film layer can be used to form the active layer of the TFT, and the first metal layer can be used to form the source electrode and the drain electrode of the TFT.
  • FIG. 4 is a schematic structural view of a base substrate formed with a semiconductor film layer, a first metal layer and a photoresist layer provided by an embodiment of the present application. As shown in FIG. 4 , the semiconductor film layer 20 , the first metal layer 30 and the photoresist layer 40 are sequentially stacked in a direction away from the base substrate 10 .
  • FIG. 4 shows cross-sectional views of a pixel area in an array substrate and a gate-driver on array (GOA) area of the array substrate, and a cross-sectional view of a terminal area in a peripheral area, respectively.
  • GOA gate-driver on array
  • Step 102 exposing the photoresist layer by using a half-tone mask to define a plurality of partially removed regions, a plurality of reserved regions and a plurality of completely removed regions in the photoresist layer.
  • the halftone mask 00 has a plurality of semi-transmissive regions 01 , a plurality of opaque regions 02 and a plurality of fully transparent regions 03 . Wherein, at least two semi-transmissive regions 01 have different sizes, and the transmittance of each semi-transmissive region 01 is 25% to 35%.
  • a plurality of partially removed regions 41, a plurality of reserved regions 42 and a plurality of Region 43 is completely removed.
  • each partially removed region 41 is the area where the orthographic projection of a semi-transmissive region 01 of the halftone mask 00 on the photoresist layer is located, and the area covered by each partially removed region 41 is the area of a TFT. The area where the channel is located.
  • Each reserved area 42 is the area where the orthographic projection of an opaque area 02 (or fully transparent area 03 ) of the halftone mask 00 on the photoresist layer 40 is located.
  • Each completely removed area 43 is the area where the orthographic projection of a fully transparent area 03 (or non-transmissive area 02 ) of the halftone mask on the photoresist layer is located.
  • each reserved area 42 is the area where the orthographic projection of an opaque area 02 of the halftone mask 00 on the photoresist layer 40 is located.
  • each reserved area 42 is the area where the orthographic projection of a full transmission area 03 of the halftone mask 00 on the photoresist layer 40 is located.
  • Step 103 developing the exposed photoresist layer to remove parts of the photoresist layer located in multiple completely removed regions, to obtain a plurality of first photoresist patterns located in multiple partially removed regions, and A plurality of second photoresist patterns of the plurality of reserved regions.
  • the developed photoresist layer includes: a plurality of first photoresist patterns 411 located in the plurality of partially removed regions 41 , and a plurality of second photoresist patterns 421 located in the plurality of remaining regions 42 .
  • the region where the first photoresist pattern 411 is located is a semi-transmissive region with a transmittance of 25% to 35%, the photoresist in the semi-transmissive region will also be lost during the developing process. Therefore, the thickness of the first photoresist pattern 411 is smaller than the thickness of the second photoresist pattern 421 .
  • Step 104 etching the first metal layer and the semiconductor film layer not covered by the photoresist pattern.
  • an etching solution may be used to etch the first metal layer and the semiconductor film layer not covered by the first photoresist pattern and the second photoresist pattern. That is, as shown in FIG. 4 , the first metal layer 30 and the semiconductor film layer 20 located in the completely removed region 43 can be etched to obtain the structure shown in FIG. 5 .
  • Step 105 removing the multiple first photoresist patterns, and etching the first metal layer covered by the multiple first photoresist patterns.
  • the first photoresist pattern and the second photoresist pattern may be processed by an ashing process, so as to remove the first photoresist pattern and thin the second photoresist pattern.
  • the first metal layer covered by the plurality of first photoresist patterns can be etched with an etchant, so as to form the source and drain of the TFT and form part of the signal lines.
  • FIG. 6 is a schematic structural view of a base substrate after etching the first metal layer covered by the first photoresist pattern according to the embodiment of the present application. Referring to FIG. 6 , after etching the first metal layer 30 , a source 31 and a drain 32 of the TFT, and a signal line 33 located in the peripheral area can be formed.
  • Step 106 removing the second photoresist pattern to obtain a plurality of first TFTs and a plurality of second TFTs.
  • each TFT may include a source 31 and a drain 32 formed of a first metal layer 30 , and an active layer 21 formed of a semiconductor film layer 20 .
  • the channel in the active layer of each TFT is located within the orthographic projection of the first photoresist pattern on the base substrate. Also, the length of the channel of the first TFT is greater than the length of the channel of the second TFT. Wherein, the length of the channel of the first TFT is relatively long, and the corresponding anti-voltage ability is relatively strong, so the first TFT can be applied to the electrostatic protection circuit to improve the anti-voltage ability of the electrostatic protection circuit.
  • the longitudinal section of the first photoresist pattern is a parabola with an upward opening. That is, the edge region of the first photoresist pattern (ie, the region close to the second photoresist pattern) is thicker, and the central region (ie, the region away from the second photoresist pattern) is thinner.
  • the longitudinal section is a section perpendicular to the bearing surface of the base substrate.
  • Fig. 7 is a schematic structural diagram of the first photoresist pattern provided by the embodiment of the present application when the channel length is relatively long
  • Fig. 8 is a schematic diagram of the first photoresist pattern provided by the embodiment of the present application when the channel length is relatively short.
  • the length of the first photoresist pattern is also longer, which results in a thinner thickness D1 of the central region of the first photoresist pattern.
  • the length of the channel of the TFT to be formed is relatively short, as shown in FIG. 8 , the length of the semi-transmissive region in the half-tone mask is also relatively short.
  • the length of the first photoresist pattern is also shorter, which results in a thicker thickness D2 in the central area of the first photoresist pattern.
  • the second photoresist pattern is longer than the length
  • the thickness difference (ie step difference) between the first photoresist patterns in the short partially removed regions 41 is smaller, that is, the thickness of the first photoresist patterns in the shorter partially removed regions 41 is thicker. If the ashing process is used to process the first photoresist pattern and the second photoresist pattern subsequently, the thickness of the photoresist removed by the ashing process is relatively thin, and it is difficult to remove the short portion of the photoresist in the region 41.
  • the first photoresist pattern is completely removed, so that the etching of the first metal layer in the partially removed region 41 cannot be carried out smoothly, that is, the source and drain of the TFT cannot be successfully obtained.
  • the thickness of the photoresist removed by the ashing process is relatively thick, and the longer part of the removal region 41 may be removed. influence of the first metal layer. For example, part of the first metal layer may be removed, which may cause the semiconductor film layer to be etched away when the first metal layer is subsequently etched, which will affect the performance of the finally formed TFT.
  • the transmittance of the half-transmission area of the half-tone mask is 25%-35%
  • the first photoresist pattern and the second The level difference between the two photoresist patterns can be controlled within a reasonable range. That is, it can be ensured that after subsequent exposure and development of the photoresist layer, the first photoresist pattern with a certain thickness can be formed in the longer partial removal region, and it can also be ensured that after each first photoresist pattern is removed, Partially removed regions with shorter lengths have no photoresist residue.
  • the embodiment of the present application provides a method for preparing a TFT.
  • multiple TFTs with different channel lengths can be prepared simultaneously by controlling the size of the half-transmission region on the half-tone mask and the transmittance of the half-transmission region.
  • the long-channel TFT can be applied to the electrostatic protection circuit to ensure the antistatic performance of the electrostatic protection circuit.
  • a half-tone mask can be used to process the first metal layer and the semiconductor film layer at the same time, so as to prepare the active layer, the source electrode and the drain electrode of the TFT.
  • the transmittance of the half-transmission area of the half-tone mask used in the preparation process is 25% to 35%.
  • the longer part removal area channel for forming the first TFT
  • the longer part removal area channel for forming the first TFT
  • the performances of the first TFT and the second TFT prepared simultaneously are better.
  • the examples of this application provide another method for preparing thin film transistors, which can simultaneously prepare TFTs with different channel lengths.
  • the cross-sectional views shown in the following embodiments all take the TFT in ESD as an example for illustration. Referring to Figure 9, the method includes:
  • Step 201 forming a second metal layer on the base substrate.
  • the base substrate may be a glass substrate.
  • the material of the second metal layer may include at least one of the following materials: titanium (Ti), copper (Cu), molybdenum-niobium alloy (MoNb), molybdenum-copper alloy (MoCu), molybdenum-titanium-nickel alloy (MoTiNi) and Molybdenum-titanium-copper alloy (MoTiCu).
  • the thickness of the second metal layer can be greater than or equal to 2000 Angstroms
  • the second metal layer can be used to form gates of TFTs and other signal lines.
  • Step 202 using a patterning process to process the second metal layer to obtain gates of a plurality of first TFTs and gates of a plurality of second TFTs.
  • the second metal layer may be processed by one patterning process to obtain gates of multiple first TFTs and gates of multiple second TFTs.
  • FIG. 10 and FIG. 11 are schematic structural diagrams of a base substrate formed with a gate provided by an embodiment of the present application, wherein FIG. 11 is a top view of FIG. 10 . As shown in FIGS. 10 and 11 , a gate 50 is formed on the base substrate 10 .
  • FIG. 10 respectively shows a cross-sectional view of the TFT area in the ESD in the array substrate, and a cross-sectional view of the via hole area in the ESD.
  • Step 203 forming a gate insulating layer on a side of the gates of the plurality of first TFTs and the gates of the plurality of second TFTs away from the substrate.
  • a gate insulating layer may be formed by a chemical vapor deposition (chemical vapor deposition, CVD) process.
  • the material of the gate insulating layer may include at least one of silicon dioxide (SiO2) and silicon nitride (SiN x ).
  • the thickness of the gate insulating layer may be greater than or equal to As shown in FIG. 4 , the gate electrode 50 and the gate insulating layer 60 are sequentially stacked in a direction away from the base substrate 10 .
  • Step 204 sequentially forming a semiconductor film layer, a first metal layer and a photoresist layer on the gate insulating layer.
  • the semiconductor film layer can be used to form the active layer (active) of the TFT.
  • the material of the semiconductor film layer may be an oxide semiconductor (oxide semiconductor, OS) material, for example, may be a metal oxide material such as indium gallium zinc oxide (IGZO).
  • the thickness of the semiconductor film layer can be greater than or equal to In order to ensure that the critical dimension loss (critical dimension loss, CD loss) of the semiconductor film layer is relatively small when the semiconductor film layer is etched with an etching solution subsequently.
  • the first metal layer can be used to form the source electrode and the drain electrode of the TFT, and the material of the first metal layer can include at least one of the following materials: titanium, copper, molybdenum-niobium alloy, molybdenum-copper alloy, molybdenum-titanium-nickel alloy Or molybdenum-titanium-copper alloy.
  • the thickness of the first metal layer is greater than or equal to
  • the thickness of the first metal layer is controlled to be greater than or equal to It can be ensured that the CD loss of the first metal layer is relatively small when the first metal layer is etched with an etchant subsequently.
  • the thickness of the photoresist layer may be 2.2 ⁇ 0.2um, that is, the thickness of the photoresist layer may be 2.0um to 2.4um.
  • the semiconductor film layer 20 , the first metal layer 30 and the photoresist layer 40 may be stacked sequentially in a direction away from the base substrate 10 .
  • Step 205 using a half-tone mask to expose the photoresist layer to define a plurality of partially removed regions, a plurality of reserved regions and a plurality of completely removed regions in the photoresist layer.
  • the halftone mask 00 has a plurality of semi-transmissive regions 01 , a plurality of opaque regions 02 and a plurality of fully transparent regions 03 .
  • at least two semi-transmissive regions 01 have different sizes, and the transmittance of each semi-transmissive region 01 is 25% to 35%.
  • each partially removed region 41 is the area where the orthographic projection of a semi-transmissive region 01 of the halftone mask 00 on the photoresist layer is located, and the area covered by each partially removed region 41 is the area of a TFT. The area where the channel is located.
  • Each reserved area 42 is the area where the orthographic projection of an opaque area 02 (or fully transparent area 03 ) of the halftone mask 00 on the photoresist layer 40 is located.
  • Each completely removed area 43 is the area where the orthographic projection of a fully transparent area 03 (or non-transmissive area 02 ) of the halftone mask on the photoresist layer is located.
  • each reserved area 42 is the area where the orthographic projection of an opaque area 02 of the halftone mask 00 on the photoresist layer is located.
  • each reserved area 42 is the area where the orthographic projection of a full transmission area 03 of the halftone mask on the photoresist layer is located.
  • Step 206 developing the exposed photoresist layer to remove the parts of the photoresist layer located in the multiple complete removal regions, to obtain a plurality of first photoresist patterns located in the multiple partial removal regions, and A plurality of second photoresist patterns of the plurality of reserved regions.
  • FIG. 12 is a schematic structural view of a base substrate after developing a photoresist layer according to an embodiment of the present application.
  • the developed photoresist layer 40 has been peeled off in the part located in the complete removal region 43, and the developed photoresist layer includes: a plurality of first photoresist layers located in a plurality of partial removal regions 41
  • the resist pattern 411 and the plurality of second photoresist patterns 421 located in the plurality of reserved regions 42 .
  • the area where each first photoresist pattern 411 is located is the area where a channel of a TFT is located.
  • the region where the first photoresist pattern 411 is located is the projection region of the semi-transmissive region, the photoresist in this region will also be lost during the development process, so the thickness of the first photoresist pattern 411 is smaller than that of the second photoresist pattern 411.
  • the thickness of the glue pattern 421 is the thickness of the glue pattern 421 .
  • the thickness of the photoresist layer formed initially is 2.5um, then a half-tone mask with a transmittance of 25% is used to carry out the photoresist layer.
  • the thickness of the first photoresist pattern located in the partly removed region with a longer length is about 0.8um.
  • the thickness of the first photoresist pattern located in the partially removed region with a shorter length is about 1 ⁇ m. In this case, it is measured that after the subsequent etching of the first metal layer and the semiconductor film layer, the CD loss of the first metal layer and the semiconductor film layer is relatively large.
  • the thickness of the initially formed photoresist layer is 2.0um, after the photoresist layer is exposed and developed using a half-tone mask with a transmittance of 25%, the first part of the longer partial removal area is located The thickness of the photoresist pattern is about 0.5um. The thickness of the first photoresist pattern located in the partially removed region with a shorter length is about 0.7um. In this case, it is measured that after the subsequent etching of the first metal layer and the semiconductor film layer, the CD loss of the first metal layer and the semiconductor film layer is relatively small.
  • the thickness of the initially formed photoresist layer is 2.2 ⁇ 0.2um
  • the thickness of the first photoresist pattern located in the longer partially removed region is greater than or equal to 0.5um.
  • the thickness of the first photoresist pattern located in the partially removed region with a shorter length is greater than or equal to 0.7um, which satisfies the condition that the CD loss of the first metal layer and the semiconductor film layer is small.
  • Step 207 etching the first metal layer and the semiconductor film layer not covered by the photoresist pattern.
  • the first metal layer and the semiconductor film layer not covered by the first photoresist pattern and the second photoresist pattern can be etched by using an etching solution. That is, as shown in FIG. 4 , the first metal layer 30 and the semiconductor film layer 20 located in the completely removed region 43 can be etched to obtain the structure shown in FIG. 5 .
  • the etched first metal layer 30 is used to form the source and drain electrodes of the TFT; the etched semiconductor film layer 20 is used to form the active layer of the TFT.
  • Step 208 removing the plurality of first photoresist patterns, and etching the first metal layer covered by the plurality of first photoresist patterns.
  • the first photoresist pattern and the second photoresist pattern may be processed by an ashing process, so as to remove the first photoresist pattern and thin the second photoresist pattern.
  • FIG. 13 is a schematic structural view of a base substrate after the first photoresist pattern and the second photoresist pattern are ashed according to an embodiment of the present application. Referring to FIG. 13, the first photoresist pattern 411 has been stripped, and the thickness of the second photoresist pattern 421 has been reduced. Afterwards, the first metal layer 30 covered by the plurality of first photoresist patterns 411 can be etched with an etchant, so as to form the source and drain of the TFT and form part of the signal lines. Referring to FIG. 6 , after etching the first metal layer 30 , a source 31 and a drain 32 of the TFT, and a signal line 33 located in the peripheral area can be formed.
  • Step 209 removing the second photoresist pattern to obtain a plurality of first TFTs and a plurality of second TFTs.
  • each TFT includes a source electrode and a drain electrode formed by the first metal layer, and an active layer formed by the semiconductor film layer.
  • the channel in the active layer of each TFT is located in the orthographic projection of the first photoresist pattern on the base substrate, and the length of the channel of the first TFT is longer than that of the second TFT. the length of the road.
  • the length of the channel of the first TFT may be greater than or equal to 8um, for example, may be 50um to 70um, or may be greater than or equal to 60um.
  • the length of the channel of the second TFT may be 4um to 6um.
  • the width of the channel of the first TFT and the width of the channel of the second TFT may both be 5um to 10um.
  • the first TFT Since the first TFT has a longer channel and better antistatic performance, it can be used as a TFT in an electrostatic protection circuit in the array substrate.
  • the second TFT may be a TFT in a pixel in the array substrate or a TFT in a GOA.
  • FIG. 14 is a schematic structural view of a base substrate after removal of the second photoresist pattern provided by an embodiment of the present application
  • FIG. 15 is a top view of FIG. 14
  • the gate 50 , the active layer 21 , and the source and drain of the TFT are sequentially stacked in a direction away from the substrate.
  • the source and drain refer to the source 31 and the drain 32 .
  • the source electrode 31 and the drain electrode 32 overlap the active layer 21 respectively.
  • Step 210 sequentially forming a planar layer, an insulating layer and a pixel electrode on the side of the plurality of first TFTs and the plurality of second TFTs away from the base substrate.
  • FIG. 16 is a schematic structural view of a base substrate provided with a flat layer and a protective layer according to an embodiment of the present application.
  • the planar layer 70 may include a plurality of spaced apart planar patterns 71 , and the orthographic projection of each planar pattern 71 on the base substrate covers a gate 50 of a TFT.
  • the planar layer 70 may be an organic membrane layer (organic membrane), and its material may be acrylic material.
  • the thickness of the planar layer 70 can be greater than or equal to
  • a protective layer 80 can be formed on the side of the TFT away from the substrate by using a film-forming process.
  • the material of the protective layer can be an insulating material, for example, it can include two At least one of silicon oxide and silicon nitride.
  • the thickness of the protective layer 80 can be greater than or equal to
  • FIG. 17 is a schematic structural diagram of a base substrate formed with an insulating layer according to an embodiment of the present application. As shown in FIG. 17 , an insulating layer 90 is formed on the side of the flat layer away from the base substrate 10 .
  • the material of the insulating layer 90 may include at least one of silicon dioxide or silicon nitride. Moreover, the thickness of the insulating layer 90 may be greater than or equal to
  • FIG. 18 is a schematic structural diagram of a base substrate on which a pixel electrode is formed according to an embodiment of the present application.
  • the pixel electrode 100 may be formed on the side of the insulating layer 90 away from the base substrate 10 .
  • the pixel electrode 100 may be a transparent electrode, and its material may include indium tin oxide.
  • the thickness of the pixel electrode 110 may be greater than or equal to
  • FIG. 19 is a top view of a substrate provided with an insulating layer provided by an embodiment of the present application, that is, FIG. 19 is a top view of FIG. 17 . It can be seen from FIG. 17 and FIG. The orthographic projection of the base substrate 10 overlaps with the space region 72 between two adjacent flat patterns 71 .
  • FIG. 20 is a top view of a base substrate provided with a pixel electrode according to an embodiment of the present application, that is, FIG. 20 is a top view of FIG. 18 . It can be seen from FIG. 19 and FIG. 20 that the pixel electrode 100 can be connected to the source electrode 31 or the drain electrode 32 through at least one first via hole 91 . In addition, the pixel electrode 100 can also be connected to the gate 50 through at least one second via hole 92 , thereby realizing the connection between the gate 50 and the source 31 or the drain 32 in the via region.
  • the pixel electrode 100 shown in FIG. 18 is a pixel electrode in the TFT region in ESD, and the pixel electrode 100 is a whole block electrode.
  • the pixel electrode of the pixel TFT includes a plurality of pixel electrode patterns at intervals.
  • the embodiment of the present application provides a method for preparing a TFT.
  • multiple TFTs with different channel lengths can be prepared simultaneously by controlling the size of the half-transmission region on the half-tone mask and the transmittance of the half-transmission region.
  • the long-channel TFT can be applied to the electrostatic protection circuit to ensure the antistatic performance of the electrostatic protection circuit.
  • a half-tone mask can be used to process the first metal layer and the semiconductor film layer at the same time, so as to prepare the active layer, the source electrode and the drain electrode of the TFT.
  • the transmittance of the half-transmission area of the half-tone mask used in the preparation process is 25% to 35%.
  • the longer part removal area channel for forming the first TFT
  • the longer part removal area channel for forming the first TFT
  • the performances of the first TFT and the second TFT prepared simultaneously are better.
  • the embodiment of the present application provides an array substrate, which can be prepared by the method provided in the above method embodiment.
  • the array substrate includes a base substrate 10 , and a plurality of first TFTs and a plurality of second TFTs located on the base substrate 10 .
  • each TFT includes a source 31 , a drain 32 and an active layer 21 , and the length L1 of the channel of the first TFT is greater than the length L2 of the channel of the second TFT.
  • the source, drain and active layers of multiple TFTs are prepared by using a half-tone mask, and the half-tone mask has a plurality of semi-transmissive regions, and each semi-transmissive region is used to define a TFT The region where the channel in the active layer is located, and the transmittance of each semi-transmissive region is 25% to 35%.
  • the length of the channel of the first TFT is greater than or equal to 8um (for example, greater than or equal to 60um), and the length of the channel of the second TFT is 4um to 6um.
  • the length of the channel of the first TFT may be 50um to 70um.
  • the width of the channel of the first TFT and the width of the channel of the second TFT are both 5 um to 10 um.
  • the first TFT is a TFT in an electrostatic protection circuit in the array substrate
  • the second TFT is a TFT in a pixel in the array substrate.
  • the thickness of the active layer 21 is greater than or equal to The thicknesses of the source electrode 31 and the drain electrode 32 are both greater than or equal to
  • each first TFT and each second TFT further includes: a gate insulating layer 60 and a gate 50 located on a side of the active layer 21 close to the base substrate 10 .
  • the gate insulating layer 60 and the gate 50 are sequentially stacked along a direction close to the base substrate 10 .
  • the array substrate further includes: a planar layer 70 sequentially stacked on the side of the plurality of first TFTs and the plurality of second TFTs away from the base substrate 10 , an insulating layer 90 and pixel electrode 100;
  • the flat layer 70 includes a plurality of spaced apart flat patterns 71, and the orthographic projection of each flat pattern 71 on the base substrate 10 covers a gate 50 of a TFT;
  • a plurality of first via holes 91 and a plurality of second via holes 92 are formed in the insulating layer 90 .
  • the interval regions 72 between the patterns 71 overlap, the pixel electrode 100 is connected to the source 31 or the drain 32 through at least one first via hole 91 , and is connected to the gate 50 through at least one second via hole 92 .
  • the embodiment of the present application provides an array substrate including a plurality of TFTs with different channel lengths. Since the source, drain and active layers of the multiple TFTs are prepared using a half-tone mask, the number of masks required in the preparation process is effectively reduced, and the TFT preparation process is simplified. , improving the preparation efficiency of the array substrate. Furthermore, since the transmittance of the half-transmission region of the half-tone mask is 25% to 35%, it can be ensured that TFTs with different channel lengths prepared at the same time have better performances.
  • the display panel includes: a driving circuit 001 , and the array substrate 002 provided in the above-mentioned embodiments.
  • the driving circuit 001 may include a source driving circuit and a gate driving circuit, the source driving circuit is used to provide data signals for the pixels in the array substrate, and the gate driving circuit is used to provide gates for the pixels in the array substrate. drive signal.
  • the gate driving circuit may be a GOA circuit, and the GOA circuit may be formed on the base substrate of the array substrate.
  • the display panel can be various products or components with display functions such as liquid crystal panels, electronic paper, mobile phones, tablet computers, televisions, notebook computers, digital photo frames, and navigators.
  • first and second are used to distinguish the same or similar items with basically the same function and function. It should be understood that “first”, “second” and “nth” There are no logical or timing dependencies, nor are there restrictions on quantity or order of execution.

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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

La présente invention concerne un procédé de fabrication d'un transistor à couches minces (TFT), un substrat de réseau et un écran d'affichage. Selon la solution fournie par la présente invention, la taille et la transmittance d'une zone de semi-transmission sur une plaque de masque en demi-teinte sont commandées, de sorte que des TFT de différentes longueurs de canal peuvent être fabriqués en même temps, des TFT ayant un canal long pouvant être appliqués à un circuit de protection statique pour assurer une performance antistatique. Par ailleurs, une plaque de masque en demi-teinte peut être utilisée pour traiter simultanément une première couche métallique et une couche de film semi-conducteur, et par conséquent, le nombre de plaques de masque utilisées dans le processus de fabrication est efficacement réduit, et le processus de fabrication est simplifié. En outre, un masque en demi-teinte dont la zone de semi-transmission a une transmittance de 25 % à 35 % est utilisé, de sorte qu'il peut être garanti que la performance de TFT fabriqués en même temps est bonne.
PCT/CN2021/137997 2021-12-14 2021-12-14 Procédé de fabrication de transistor à couches minces, substrat de réseau et écran d'affichage WO2023108429A1 (fr)

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PCT/CN2021/137997 WO2023108429A1 (fr) 2021-12-14 2021-12-14 Procédé de fabrication de transistor à couches minces, substrat de réseau et écran d'affichage

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8349630B1 (en) * 2011-06-28 2013-01-08 Shenzhen China Star Optoelectronics Technology Co., Ltd. Methods for manufacturing thin film transistor array substrate and display panel
CN103117224A (zh) * 2013-01-21 2013-05-22 京东方科技集团股份有限公司 一种薄膜晶体管和阵列基板的制作方法
CN103545378A (zh) * 2013-11-05 2014-01-29 京东方科技集团股份有限公司 氧化物薄膜晶体管及其制作方法、阵列基板、显示装置
CN103715201A (zh) * 2013-12-20 2014-04-09 京东方科技集团股份有限公司 一种阵列基板及其制造方法、goa单元以及显示装置
CN113097295A (zh) * 2021-03-30 2021-07-09 合肥维信诺科技有限公司 薄膜晶体管及其制备方法、显示面板

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8349630B1 (en) * 2011-06-28 2013-01-08 Shenzhen China Star Optoelectronics Technology Co., Ltd. Methods for manufacturing thin film transistor array substrate and display panel
CN103117224A (zh) * 2013-01-21 2013-05-22 京东方科技集团股份有限公司 一种薄膜晶体管和阵列基板的制作方法
CN103545378A (zh) * 2013-11-05 2014-01-29 京东方科技集团股份有限公司 氧化物薄膜晶体管及其制作方法、阵列基板、显示装置
CN103715201A (zh) * 2013-12-20 2014-04-09 京东方科技集团股份有限公司 一种阵列基板及其制造方法、goa单元以及显示装置
CN113097295A (zh) * 2021-03-30 2021-07-09 合肥维信诺科技有限公司 薄膜晶体管及其制备方法、显示面板

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