CN103715137B - 阵列基板及其制造方法、显示装置 - Google Patents
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Abstract
本发明涉及一种阵列基板及其制造方法、显示装置,所述阵列基板的制造方法特征在于:采用一道掩膜工序形成所述阵列基板中薄膜晶体管的源极、漏极、有源层及第一透明电极,其中所述有源层和所述第一透明电极由同一金属氧化物层形成,所述源极和漏极位于所述有源层上方,其中所述第一透明电极对应于掩膜板的第一半透光区域,所述薄膜晶体管的沟道区域对应于所述掩膜板的第二半透光区域,所述薄膜晶体管的源极和漏极对应于所述掩膜板的不透光区域,所述掩膜板的第一半透光区域的透光率大于所述掩膜板的第二半透光区域的透光率。
Description
技术领域
本发明涉及显示技术领域,具体涉及一种阵列基板及其制造方法、显示装置。
背景技术
液晶显示装置由于体积小、功耗低、辐射低等优点,被广泛应用于电视、显示器、笔记本电脑、平板电脑等设备上。
目前,在制造超高级超维场转换(HADS,High Advanced Dimension Switch)型阵列基板时,通常需要进行八道掩膜工序,依次为对栅极、栅极绝缘层、蚀刻停止层、源漏金属层、钝化层、公共电极、钝化层和像素电极进行构图。由于对于每一道掩膜工序而言,需要制造成本高昂的掩膜板,还需要执行曝光、显影、蚀刻、灰化等工艺步骤,从而使得现有阵列基板制造工艺复杂,生产成本高。因此,亟需一种能够减少掩膜工序的制造方法。
发明内容
本发明所要解决的技术问题是现有阵列基板制造工艺复杂的问题。
为此目的,本发明提出了一种阵列基板的制造方法,其特征在于,包括:采用一道掩膜工序形成所述阵列基板中薄膜晶体管的源极、漏极、有源层及第一透明电极,其中所述有源层和所述第一透明电极由同一金属氧化物层形成,所述源极和漏极位于所述有源层上方,其中所述第一透明电极对应于掩膜板的第一半透光区域,所述薄膜晶体管的沟道区域对应于所述掩膜板的第二半透光区域,所述薄膜晶体管的源极和漏极对应于所述掩膜板的不透光区域,所述掩膜板的第一半透光区域的透光率大于所述掩膜板的第二半透光区域的透光率。
优选地,所述金属氧化物通过等离子处理形成第一透明电极。
优选地,所述掩膜板的半透光区域为半色调掩膜或灰阶掩膜。
优选地,所述金属氧化物为IGZO或ITZO或两者的混合物。
优选地,在采用一道掩膜工序形成所述阵列基板中薄膜晶体管的源极、漏极、有源层及第一透明电极前,还包括:在阵列基板上形成有源层遮光层和所述第一透明电极的引线,其中所述遮光层对应于薄膜晶体管的有源层区域,所述第一透明电极为公共电极。
优选地,在采用一道掩膜工序形成所述阵列基板中薄膜晶体管的源极、漏极、有源层及第一透明电极后,还包括:形成覆盖所述源极、漏极和所述第一透明电极的绝缘层,所述绝缘层上设置有过孔;形成所述薄膜晶体管的栅极和第二透明电极,其中所述第二透明电极通过所述绝缘层的过孔与所述漏极电连接,所述第二透明电极为狭缝状像素电极。
优选地,在采用一道掩膜工序形成所述阵列基板中薄膜晶体管的源极、漏极、有源层及第一透明电极前,还包括:在所述阵列基板上形成所述薄膜晶体管的栅极和绝缘层。
优选地,在采用一道掩膜工序形成所述阵列基板中薄膜晶体管的源极、漏极、有源层及第一透明电极后,还包括:形成连接所述漏极与所述第一透明电极的导电接触,其中所述第一透明电极是像素电极;形成位于所述导电接触上方的钝化层和第二透明电极,所述第二透明电极为狭缝状公共电极。
本发明进一步提出了一种阵列基板,其特征在于,包括:基板;形成在所述基板上方的有源层和公共电极,所述有源层和所述公共电极由同一金属氧化物层形成;形成在所述有源层上方的源极和漏极;形成在所述源极、漏极和公共电极上方的绝缘层,所述绝缘层上设置有过孔;形成在所述绝缘层上方的像素电极,所述像素电极通过所述绝缘层上的过孔与所述漏极连接;形成在所述绝缘层上方的栅极。
优选地,所述金属氧化物层通过等离子处理形成公共电极。
优选地,所述阵列基板还包括:形成在所述基板与所述有源层之间的遮光层以及与所述公共电极电连接的公共电极引线。
本发明还提出了一种阵列基板,其特征在于,包括:基板;形成在所述基板上方的栅极;覆盖所述基板和所述栅极的绝缘层;形成在所述绝缘层上方的有源层和像素电极,所述有源层和所述像素电极由同一金属氧化物层形成且相互邻接;形成在所述有源层上方的源极和漏极;形成在所述漏极和所述像素电极上的导电接触,用于使所述漏极和所述像素电极电连接;覆盖所述绝缘层、源极、漏极、有源层、导电接触和像素电极的钝化层;形成在所述钝化层上方的公共电极。
优选地,所述金属氧化物通过等离子处理形成像素电极。
本发明还提出了一种显示装置,其包括上述阵列基板。
通过采用本发明所公开的阵列基板制造方法,极大减少了阵列基板的制造工艺步骤,降低了阵列基板的制造成本。
附图说明
通过参考附图会更加清楚的理解本发明的特征和优点,附图是示意性的而不应理解为对本发明进行任何限制,在附图中:
图1示出了根据本发明实施例的阵列基板制造方法的流程图。
图2-23示出了根据本发明实施例的阵列基板制造方法各步骤的示意图,其中图23示出了根据本发明实施例的阵列基板的示意图。
图24示出了根据本发明另一实施例的阵列基板制造方法的流程图;
图25-34根据本发明另一实施例的阵列基板制造方法各步骤的示意图,其中图34示出了根据本发明另一实施例的阵列基板的示意图。
具体实施方式
下面将结合附图对本发明的实施例进行详细描述。
图1示出了根据本发明实施例的阵列基板制造方法的流程图。如图1所示,根据本发明实施例的阵列基板制造方法共采用了四道掩膜工序,比现有制造超高级超维场转换型阵列基板所需的八道掩膜工序减少了四道,大大减小了阵列基板的制造工艺步骤,降低了阵列基板的制造成本。下面将结合图2至17对根据本发明实施例的阵列基板制造方法进行详细说明。
首先,介绍第一道掩膜工序。
步骤S1:在基板1上沉积金属层,如图2所示。
步骤S2:涂覆第一光刻胶层,并采用单色调掩膜对该第一光刻胶层进行曝光显影,图3示出了曝光显影后的第一光刻胶层。
步骤S3:对金属层进行蚀刻,并剥离剩余的第一光刻胶层,从而在待形成薄膜晶体管的区域内形成遮光层,并在像素区域内形成公共电极的引线2,如图4所示。
接下来,介绍第二道掩膜工序。
步骤S4:在基板1上依次沉积形成金属氧化层物3和源漏金属层4,如图5所示。其中,金属氧化物层3可以由IGZO、ITZO或其它具有半导体性质的金属氧化物构成,源漏金属层4可以由铜、铝、钼等金属构成。
步骤S5:首先在源漏金属层4上涂覆第二光刻胶层,然后采用掩膜板来对该第二光刻胶层进行曝光,待形成的公共电极对应于该掩膜板的第一半透光区域,待形成的薄膜晶体管的沟道对应于该掩膜板的第二半透光区域,待形成的薄膜晶体管的源极和漏极对应于该掩膜板的不透光区域,该掩膜板的第一半透光区域的透光率大于第二半透光区域的透光率。掩膜板可以是半色调掩膜板或灰度掩膜板。图6示出了经该掩膜板曝光显影后的第二光刻胶层,该第二光刻胶层在待形成公共电极的区域具有第一厚度,在待形成薄膜晶体管沟道的区域具有第二厚度,在待形成源极和漏极的区域具有第三厚度,其中第一厚度小于第二厚度,第二厚度小于第三厚度。优选地,涂覆的第三光刻胶层的厚度为即第三厚度为经曝光显影后,第一厚度为第二厚度为
步骤S6:对未覆盖有第二光刻胶层的区域进行蚀刻,以去除暴露出的源漏金属层4和金属氧化物层3。优选地,可以采用湿法蚀刻。图7示出了此次蚀刻结束后的示意图。
步骤S7:通过灰化等工艺,使第二光刻胶层在整体上去除第一厚度的厚度,以暴露出待形成公共电极的区域,如图8所示。
步骤S8:采用蚀刻的方式,去除掉暴露出的源漏金属层4,以暴露出其下方的金属氧化物层3,如图9所示。
步骤S9:对暴露出的金属氧化物层3进行等离子处理,使该部分的金属氧化物层具有导电性,从而使该部分金属氧化物层用作为公共电极6,未经等离子处理的金属氧化物层仍然保持半导体性质,用作为有源层5,如图10所示。
步骤S10:再次通过灰化等工艺,使第二光刻胶层在整体上去除第二厚度减去第一厚度的厚度,即经过此次灰化工艺后,原来具有第二厚度的第二光刻胶层被完全去除,暴露出待形成薄膜晶体管沟道的区域。图11示出了此次灰化工艺后的示意图。
步骤S11:对暴露出的源漏金属层4进行蚀刻,直到到达其下方的有源层5,以形成薄膜晶体管的源极7和漏极8,如图12所示。
步骤S12:在此次蚀刻结束后去除剩余的第二光刻胶层,如图13所示。
接下来介绍第三道掩膜工序。
步骤S13:在基板1上沉积绝缘层9以覆盖整个基板1,如图14所示。
步骤S14:在绝缘层9上涂覆第三光刻胶层,并采用单色调掩膜板对该第三光刻胶层进行曝光显影,以暴露出漏极8靠近公共电极6侧的一部分区域上方的绝缘层9,如图15所示。
步骤S15:对暴露出的绝缘层9进行蚀刻,在绝缘层9中形成开口,以暴露出其下方的漏极8靠近公共电极6侧的一部分区域,如图16所示。优选地,暴露出的漏极8的上表面与像素区域内的绝缘层9的上表面齐平。
步骤S16:去除剩余的第三光刻胶层,如图17所示。
接下来介绍第四道掩膜工序。
步骤S17:在基板1上依次沉积第二像素电极层10和栅极金属层11,如图18所示。
步骤S18:在栅极金属层11上涂覆第四光刻胶层,并采用另一灰度或半色调掩膜板来对该第四光刻胶层进行曝光。图19示出了经曝光显影后的第四光刻胶层,其中该第四光刻胶层在待形成像素电极的区域的厚度小于待形成薄膜晶体管栅极的区域的厚度。
步骤S19:对未覆盖有第四光刻胶层的区域进行蚀刻,以去除暴露出的像素电极层10和栅极金属层11,从而完成了对狭缝状像素电极和栅极的构图,如图20所示。
步骤S20:通过灰化等工艺,暴露出像素电极区域的栅极金属层,如图21所示。
步骤S21:去除暴露出的栅极金属层,从而得到像素电极12的图形以及薄膜晶体管的栅极13,如图22所示。
步骤S22:去除剩余的第四光刻胶层,从而完成了整个阵列基板的制造工艺。图23示出了最终形成的阵列基板。
如图23所示,根据本发明的阵列基板包括:基板1;形成在基板1上方的遮光层和公共电极引线2;覆盖遮光层的有源层5和与公共电极引线2电连接的公共电极6,有源层5和公共电极6由同一金属氧化物层形成,有源层5中的金属氧化物层具有半导体性质,公共电极6中的金属氧化物层经受等离子处理而具有导体性质,该金属氧化物层可以是IGZO或ITZO。在有源层5上方形成源极7和漏极8,源极7、漏极8和有源层5通过其上的绝缘层9与栅极13电绝缘,从而构成薄膜晶体管。栅极13与其下方的绝缘层9之间还具有像素电极12。绝缘层9覆盖基板1、源极7、漏极8、有源层5和公共电极6,并且暴露出漏极8的一部分。漏极8暴露出的部分位于靠近公共电极6的一侧,并且暴露出的漏极8的上表面与像素区域内的绝缘层9的上表面齐平。像素电极12形成在绝缘层9上,并且与漏极8电连接。
以上介绍了根据本发明实施例的阵列基板制造方法,该制造方法采用顶栅工艺,极大减少了阵列基板的制造工艺步骤,降低了阵列基板的制造成本。在此基础上,本发明的另一实施例提出了一种采用底栅工艺的阵列基板制造方法,同样也可以减少现有阵列基板的制造工艺步骤。图24示出了根据本发明另一实施例的阵列基板制造方法的流程图,下面将结合图25至34对根据本发明实施例的阵列基板制造方法进行详细说明。
步骤S1:采用第一道掩膜工序,在基板21上形成栅极22,如图25所示。
步骤S2:在基板21上依次形成绝缘层23、金属氧化物层24和源漏金属层25,如图26所示。
步骤S3:首先在源漏金属层25上涂覆光刻胶层,然后采用掩膜板来对该光刻胶层进行曝光,待形成的像素电极对应于该掩膜板的第一半透光区域,待形成的薄膜晶体管的沟道对应于该掩膜板的第二半透光区域,待形成的薄膜晶体管的源极和漏极对应于该掩膜板的不透光区域,该掩膜板的第一半透光区域的透光率大于第二半透光区域的透光率。掩膜板可以是半色调掩膜板或灰度掩膜板。图27示出了经该掩膜板曝光显影后的光刻胶层,该光刻胶层在待形成像素电极的区域具有第一厚度,在待形成薄膜晶体管沟道的区域具有第二厚度,在待形成源极和漏极的区域具有第三厚度,其中第一厚度小于第二厚度,第二厚度小于第三厚度。优选地,第一厚度为第二厚度为第三厚度为
步骤S4:对未覆盖有光刻胶层的区域进行蚀刻,以去除暴露出的源漏金属层25和金属氧化物层24,而不蚀刻绝缘层23。图28示出了此次蚀刻结束后的示意图。
步骤S5:通过灰化等工艺,使该光刻胶层在整体上去除第一厚度的厚度,以暴露出待形成像素电极的区域,如图29所示。
步骤S6:采用蚀刻的方式,去除掉暴露出的源漏金属层25,以暴露出其下方的金属氧化物层24,并对暴露出的金属氧化物层24进行等离子处理,使该部分的金属氧化物层具有导电性,从而使该部分金属氧化物层用作为像素电极26,未经等离子处理的金属氧化物层仍然保持半导体性质,用作为有源层27,如图30所示。
步骤S7:再次通过灰化等工艺,使第二光刻胶层在整体上去除第二厚度减去第一厚度的厚度,即经过此次灰化工艺后,原来具有第二厚度的第二光刻胶层被完全去除,暴露出待形成薄膜晶体管沟道的区域,并对暴露出的源漏金属层25进行蚀刻,直到到达其下方的有源层27,以形成薄膜晶体管的源极28和漏极29。在此次蚀刻结束后去除剩余的该光刻胶层,由此完成第二道掩膜工序,如图31所示。
步骤S8:采用第三道掩膜工序,形成漏极29与像素电极26之间的导电接触30,如图32所示。
步骤S9:在基板21上沉积钝化层31以覆盖整个基板21,如图33所示。
步骤S10:采用第四道掩膜工序,在钝化层31上形成狭缝状公共电极32,如图34所示。
由此,通过采用四道掩膜工序,完成了底栅结构阵列基板的制造。如图34所示,根据本发明实施例的底栅结构的阵列基板包括:基板21;形成在基板21上方的栅极22;覆盖栅极22的绝缘层23;形成在绝缘层23上方且同层设置的有源层27和像素电极26,像素电极26与有源层27由同一金属氧化物层形成且相互邻接,有源层27中的金属氧化物层具有半导体性质,像素电极26中的金属氧化物层经受等离子处理而具有导体性质,该金属氧化物层可以是IGZO或ITZO。在有源层27上方形成源极28和漏极29,从而构成薄膜晶体管。漏极29通过导电接触30与像素电极26电接触。钝化层31覆盖绝缘层23、源极28、漏极29、有源层27和像素电极26。公共电极32形成在钝化层31上。
通过采用本发明所公开的顶栅结构或底栅结构的阵列基板制造方法,极大减少了阵列基板的制造工艺步骤,降低了阵列基板的制造成本。
虽然结合附图描述了本发明的实施方式,但是本领域技术人员可以在不脱离本发明的精神和范围的情况下作出各种修改和变型,这样的修改和变型均落入由所附权利要求所限定的范围之内。
Claims (8)
1.一种阵列基板的制造方法,其特征在于,包括:
采用一道掩膜工序形成所述阵列基板中薄膜晶体管的源极、漏极、有源层及第一透明电极,其中所述有源层和所述第一透明电极由同一金属氧化物层形成,所述源极和漏极位于所述有源层上方,其中所述第一透明电极对应于掩膜板的第一半透光区域,所述薄膜晶体管的沟道区域对应于所述掩膜板的第二半透光区域,所述薄膜晶体管的源极和漏极对应于所述掩膜板的不透光区域,所述掩膜板的第一半透光区域的透光率大于所述掩膜板的第二半透光区域的透光率;
其中,在采用一道掩膜工序形成所述阵列基板中薄膜晶体管的源极、漏极、有源层及第一透明电极前,还包括:
在阵列基板上形成有源层遮光层和所述第一透明电极的引线,其中所述遮光层对应于薄膜晶体管的有源层区域,所述第一透明电极为公共电极;
在采用一道掩膜工序形成所述阵列基板中薄膜晶体管的源极、漏极、有源层及第一透明电极后,还包括:形成覆盖所述源极、漏极和所述第一透明电极的绝缘层;其中,所述绝缘层的上表面与暴露出的所述漏极的上表面平齐。
2.根据权利要求1所述的阵列基板的制造方法,其特征在于,所述金属氧化物通过等离子处理形成第一透明电极。
3.根据权利要求1所述的阵列基板的制造方法,其特征在于,所述掩膜板的半透光区域为半色调掩膜或灰阶掩膜。
4.根据权利要求1所述的阵列基板的制造方法,其特征在于,其中所述金属氧化物为IGZO或ITZO或两者的混合物。
5.根据权利要求1所述的阵列基板的制造方法,其特征在于,所述绝缘层上设置有过孔;
形成所述薄膜晶体管的栅极和第二透明电极,其中所述第二透明电极通过所述绝缘层的过孔与所述漏极电连接,所述第二透明电极为狭缝状像素电极。
6.一种阵列基板,其特征在于,包括:
基板;
形成在所述基板上方的有源层和公共电极,所述有源层和所述公共电极由同一金属氧化物层形成;
形成在所述有源层上方的源极和漏极;
形成在所述源极、漏极和公共电极上方的绝缘层,所述绝缘层上设置有过孔;其中,所述绝缘层的上表面与暴露出的所述漏极的上表面平齐;
形成在所述绝缘层上方的像素电极,所述像素电极通过所述绝缘层上的过孔与所述漏极连接;
形成在所述绝缘层上方的栅极;
其中,所述阵列基板还包括:形成在所述基板与所述有源层之间的遮光层以及与所述公共电极电连接的公共电极引线。
7.根据权利要求6所述阵列基板,其特征在于,所述金属氧化物层通过等离子处理形成公共电极。
8.一种显示装置,其特征在于,包括权利要求6至7中任一项所述的阵列基板。
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