WO2015096314A1 - 阵列基板及其制造方法、显示装置 - Google Patents

阵列基板及其制造方法、显示装置 Download PDF

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Publication number
WO2015096314A1
WO2015096314A1 PCT/CN2014/075870 CN2014075870W WO2015096314A1 WO 2015096314 A1 WO2015096314 A1 WO 2015096314A1 CN 2014075870 W CN2014075870 W CN 2014075870W WO 2015096314 A1 WO2015096314 A1 WO 2015096314A1
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Prior art keywords
layer
array substrate
drain
mask
electrode
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PCT/CN2014/075870
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English (en)
French (fr)
Inventor
崔承镇
金熙哲
宋泳锡
刘圣烈
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京东方科技集团股份有限公司
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Priority to US14/416,005 priority Critical patent/US9685460B2/en
Publication of WO2015096314A1 publication Critical patent/WO2015096314A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate, a method for manufacturing the same, and a display device.
  • Liquid crystal display devices are widely used in televisions, monitors, notebook computers, tablet computers, etc. due to their small size, low power consumption, and low radiation.
  • HADS High Advanced Dimension Switch
  • eight mask processes which are, in order, a pair of electrodes, an insulating layer, an etch stop layer, a source/drain metal layer, The passivation layer, the common electrode, the passivation layer, and the pixel electrode are patterned. Since it is necessary to manufacture a mask having a high cost for each mask process, it is also necessary to perform process steps such as exposure, development, etching, ashing, etc., so that the existing array substrate manufacturing process is complicated and the production cost is high. Therefore, there is a need for a manufacturing method capable of reducing the masking process.
  • the technical problem to be solved by the present invention is that the manufacturing process of the existing array substrate is complicated.
  • the present invention provides a method of fabricating an array substrate, comprising: forming a source, a drain, an active layer, and a first transparent electrode of a thin film transistor in the array substrate by a mask process; Forming the active layer and the first transparent electrode from a same metal oxide layer, the source and drain being located above the active layer, wherein the first transparent electrode corresponds to a mask a first light-transmissive region, a channel region of the thin film transistor corresponding to a second semi-transmissive region of the mask, a source and a drain of the thin film transistor corresponding to the mask being impervious In the light region, the light transmittance of the first semi-transmissive region of the mask is greater than the light transmittance of the second semi-transmissive region of the mask.
  • the thickness of the photoresist layer corresponding to the first semi-transmissive region of the mask is less than that corresponding to the mask.
  • the thickness of the second semi-transmissive region is less than the thickness of the opaque region corresponding to the mask.
  • the metal oxide forms a first transparent electrode by plasma treatment.
  • the semi-transmissive region of the mask is a halftone mask or a gray scale mask.
  • the metal oxide is IGZO or ITZO or a mixture of the two.
  • the method further comprises: forming an active layer light shielding layer and the substrate on the array substrate The lead of the first transparent electrode, wherein the light shielding layer corresponds to an active layer region of the thin film transistor, and the first transparent electrode is a common electrode.
  • the method further includes: forming the source, the drain, and the An insulating layer of the first transparent electrode, the insulating layer is provided with a via hole; forming a » pole and a second transparent electrode of the thin film transistor, wherein the second transparent electrode passes through the via of the insulating layer and the The drain is electrically connected, and the second transparent electrode is a slit-shaped pixel electrode.
  • an upper surface of the drain is flush with an upper surface of the insulating layer on a side close to the first transparent electrode.
  • the method further includes: forming a gate of the thin film transistor on the array substrate Pole and insulation.
  • the method further includes: forming the connection between the drain and the first transparent electrode Conductive contact, wherein the first transparent electrode is a pixel electrode; a passivation layer and a second transparent electrode are formed over the conductive contact, and the second transparent electrode is a slit-shaped common electrode.
  • the present invention further provides an array substrate, comprising: a substrate; an active layer and a common electrode formed over the substrate, wherein the active layer and the common electrode are formed of the same metal oxide layer; a source and a drain formed over the active layer; an insulating layer formed over the source, the drain, and the common electrode, the insulating layer is provided with a via hole; and formed over the insulating layer a pixel electrode, wherein the pixel electrode is connected to the drain through a via hole on the insulating layer; and a gate electrode formed over the insulating layer.
  • the metal oxide layer forms a common electrode by plasma treatment.
  • the array substrate further includes: a cover formed between the substrate and the active layer a light layer and a common electrode lead electrically connected to the common electrode.
  • the present invention also provides an array substrate, comprising: a substrate; a gate formed over the substrate; an insulating layer covering the substrate and the gate; formed above the insulating layer a source layer and a pixel electrode, the active layer and the pixel electrode are formed adjacent to each other by a same metal oxide layer; a source and a drain formed above the active layer; formed at the drain and a conductive contact on the pixel electrode, ffi is electrically connected to the drain and the pixel electrode; a passivation layer covering the insulating layer, the source, the drain, the active layer, the conductive contact, and the pixel electrode; a common electrode above the passivation layer.
  • the metal oxide forms a pixel electrode by plasma treatment.
  • the present invention also proposes a display device comprising the above array substrate.
  • a lithography having a thickness corresponding to a transmittance corresponding to light transmittance is formed after exposure.
  • the adhesive layer then forms a pre-existing device in each subsequent etching step, thereby saving a plurality of mask processes, greatly reducing the manufacturing process of the array substrate, and reducing the manufacturing cost of the array substrate.
  • Fig. 1 shows a flow chart of a method of manufacturing a column substrate according to an embodiment of the present invention.
  • FIGS. 2-23 are schematic views showing steps of a method of fabricating a column substrate according to an embodiment of the present invention, wherein Fig. 23 is a schematic view showing an array substrate according to an embodiment of the present invention.
  • FIG. 24 is a flow chart showing a method of fabricating an array substrate according to another embodiment of the present invention
  • FIGS. 25-34 are schematic views showing steps of a method for fabricating an array substrate according to another embodiment of the present invention, wherein FIG. 34 shows A schematic diagram of an array substrate of another embodiment of the invention.
  • FIG. 1 shows a flow chart of a method of fabricating an array substrate in accordance with an embodiment of the present invention.
  • the array substrate manufacturing method according to the embodiment of the present invention has a total of four masking processes, which reduces the number of mask processes required for the existing ultra-high-grade super-dimensional field-converting array substrate by four, and greatly reduces The manufacturing process steps of the array substrate reduce the manufacturing cost of the array substrate. The following will be combined with the map
  • the final fabricated array substrate structure is shown, wherein 2 is a pixel electrode and 13 is a » pole of a thin film transistor, so the left side portion of the figure will be referred to as a region Ft forming a thin film transistor, The portion on the right side is referred to as a region Fp forming a pixel for convenience of explanation.
  • Step S deposits a metal layer on the substrate 1, as shown in FIG.
  • Step S2 coating the first photoresist layer PR, and exposing and developing the first photoresist layer by using a monotone mask, and FIG. 3 shows the first photoresist layer PR after exposure and development.
  • Step S3 etching the metal layer, and stripping the remaining first photoresist layer, thereby forming a light shielding layer (:, and forming a common electrode lead 2 in the pixel region Fp in the region Ft where the thin film transistor is to be formed, such as Figure 4 shows.
  • Step S4 depositing a metal oxide layer 3 and a source/drain metal layer 4 on the substrate 1 in sequence, as shown in FIG.
  • the metal oxide layer 3 may be composed of IGZO, ITZO or other metal oxide having a semiconducting property
  • the source/drain metal layer 4 may be made of a metal such as copper, aluminum or molybdenum.
  • Step S5 first coating a second photoresist layer on the source/drain metal layer 4, and then absorbing a mask layer to expose the second photoresist layer, and the common electrode to be formed corresponds to the mask layer a half of the light-transmissive area PRa, the channel of the thin film transistor to be formed corresponds to the second semi-transmissive region PRb of the mask, and the source and the drain of the thin film transistor to be formed correspond to the opaque of the mask
  • the light area PRc, the light transmittance of the first semi-transmissive region of the mask is greater than the light transmittance of the second semi-transmissive region.
  • the mask can be a halftone mask or a grayscale mask.
  • the light transmittance of the mask can result in different thicknesses of the exposed photoresist layer.
  • 6 shows a second photoresist layer after exposure and development through the mask, the second photoresist layer having a first thickness t1 in a region where a common electrode is to be formed, in a region where a thin film transistor channel is to be formed There is a second thickness t2 having a third thickness t3 in a region where the source and the drain are to be formed, wherein the first thickness is smaller than the second thickness, and the second thickness is smaller than the third thickness.
  • the thickness of the third photoresist layer coated corresponding to the portion of the mask PRc is 20,000-30000 A, That is, the third thickness t3 is 20000-30000A, and after exposure and development, the first thickness t1 of the first photoresist layer corresponding to the portion of the mask PRa is 2000-6000A, and the second photoresist corresponding to the portion of the mask PRb The second thickness t2 of the layer is 6000-10000A.
  • Step S6 etching a region not covered with the second photoresist layer to remove the exposed source/drain metal layer 4 and the metal oxide layer 3.
  • wet etching can be employed.
  • Fig. 7 shows a schematic view after the end of this etching.
  • Step S7 removing the thickness t1 of the first thickness as a whole by a process such as ashing to expose a region where the common electrode is to be formed (the right half of the substrate in the figure), as shown in FIG. Show.
  • Step S8 removing the exposed source/drain metal layer 4 by etching to expose the metal oxide layer 3 underneath, as shown in FIG.
  • Step S9 performing plasma treatment on the exposed metal oxide layer 3 so that the metal oxide layer of the portion is electrically conductive, and the portion of the metal oxide layer is used as the common electrode 6, and the metal is not oxidized by plasma treatment.
  • the layer remains crystalline and is used as the active layer 5, as shown in FIG.
  • Step S10 the second photoresist layer is removed by the ashing process to reduce the thickness of the first thickness by a total thickness, that is, after the ashing process, the second light having the second thickness
  • the portion of the dicing layer PRb is completely removed, exposing the region where the thin film transistor channel is to be formed.
  • Figure 11 shows a schematic view of the ashing process.
  • Step SH The exposed source/drain metal layer 4 is etched until it reaches the active layer 5 below it to form the source 7 and drain 8 of the thin film transistor, as shown in FIG.
  • Step S12 removing the remaining second photoresist layer after the end of the etching, as shown in FIG. Next, the third mask process will be introduced.
  • Step An insulating layer 9 is deposited on the substrate 1 to cover the entire substrate 1, as shown in FIG. Step S14: applying a third photoresist layer on the insulating layer 9, and exposing and developing the third photoresist layer by using a monotone mask to expose a portion of the drain 8 near the side of the common electrode 6.
  • the step of etching the exposed insulating layer 9 forms an opening (via) in the insulating layer 9 to expose a portion of the drain 8 below it close to the side of the common electrode 6, as shown in FIG.
  • the exposed upper surface of the drain 8 is flush with the upper surface of the insulating layer 9 in the pixel region Flat.
  • Step S] 6 The remaining third photoresist layer is removed, as shown in FIG.
  • Step S The second pixel electrode layer 10 and the gate metal layer 11 are sequentially deposited on the substrate 1, as shown in FIG.
  • the fourth photoresist layer is coated on the gate metal layer 11, and the fourth photoresist layer is exposed using another grayscale or halftone mask.
  • Fig. 19 shows a fourth photoresist layer after exposure development, wherein the thickness of the fourth photoresist layer in the region Fp where the pixel electrode is to be formed is smaller than the thickness of the region Ft where the gate of the thin film transistor is to be formed.
  • Step S19 engraving a region not covered with the fourth photoresist layer to remove the exposed pixel electrode layer 10 and the »electrode metal layer, and complete the pair of slit-shaped pixel electrodes and the gate electrode Composition, as shown in Figure 20.
  • Step S20 exposing the gate metal layer of the pixel electrode region by a process such as ashing, as shown in FIG.
  • Step S21 removing the exposed gate metal layer 11, thereby obtaining a pattern of the pixel electrode 12 and a gate electrode 13 of the thin film transistor, as shown in FIG.
  • Step S22 removing the remaining fourth photoresist layer, thereby completing the manufacturing process of the entire array substrate.
  • Figure 23 shows the final formed array substrate.
  • the array substrate according to the present invention includes: a substrate 1; a light shielding layer C and a common electrode lead 2 formed over the substrate 1, an active layer 5 covering the light shielding layer C, and an electrical connection with the common electrode lead 2.
  • the common electrode 6, the active layer 5 and the common electrode 6 are formed of the same metal oxide layer, the metal oxide layer in the active layer 5 has semiconductor properties, and the metal oxide layer in the common electrode 6 is subjected to plasma treatment to have conductor properties.
  • the metal oxide layer may be IGZO or ITZC.
  • the source electrode 7 and the drain electrode 8 are formed over the active layer 5.
  • the source electrode 7, the drain electrode 8 and the active layer 5 are electrically connected to the gate electrode 13 through the insulating layer 9 and the gate electrode 13 thereon.
  • the pixel electrode 12 is further provided between the gate electrode 13 and the insulating layer 9 therebelow.
  • the insulating layer 9 covers the substrate 1, the source 7, the drain 8, the active layer 5, and the common electrode 6, and exposes a portion of the drain 8.
  • the exposed portion of the drain 8 is located on the side close to the common electrode 6, and the exposed upper surface of the drain 8 is flush with the upper surface of the insulating layer 9 in the pixel region.
  • the pixel electrode 12 is formed on the insulating layer 9 and is electrically connected to the drain 8.
  • FIG. 24 is a flow chart showing a method of manufacturing a column substrate according to another embodiment of the present invention. A method of fabricating an array substrate according to an embodiment of the present invention will be described in detail below with reference to Figs.
  • Step S 1 ' ⁇ ⁇
  • Step S2' An insulating layer 23, a metal oxide layer 24, and a source/drain metal layer 25 are sequentially formed on the substrate 2, as shown in FIG.
  • Step S3' first coating a photoresist layer on the source/drain metal layer 25, and then exposing the photoresist layer using a mask, the pixel electrode to be formed corresponding to the first half of the mask
  • the light region PRa', the channel of the thin film transistor to be formed corresponds to the:::::: semi-transmissive region PRb' of the mask, and the source and the drain of the thin film transistor to be formed correspond to the mask
  • the opaque area PRc', the transmittance of the first semi-transmissive region of the mask is greater than the transmittance of the second semi-transmissive region.
  • the mask can be a halftone mask or a grayscale mask.
  • Figure 27 is a view showing a photoresist layer exposed and developed through the mask, the photoresist layer having a first thickness ti ' in a region where the pixel electrode is to be formed, i.e., a portion of the film transistor to be formed.
  • the region, that is, the PRb' portion has a second thickness t2'
  • the portion where the source and drain are to be formed, that is, PRc has a third thickness t3, wherein the first thickness is smaller than the second thickness, and the second thickness is smaller than the third thickness.
  • the first thickness is 2000-6000A
  • the second thickness is 6000-10000A
  • the third thickness is 20000-30000A.
  • Step S4' etching the region not covered with the photoresist layer to remove the exposed source/drain metal layer 25 and the metal oxide layer 24 without etching the insulating layer 23.
  • Fig. 28 shows a schematic view after the end of the etching.
  • Step S5' the photoresist layer is entirely removed in thickness by a process such as ashing to expose a region where the pixel electrode is to be formed, as shown in FIG.
  • Step S6' removing the exposed source/drain metal layer 25 by etching to expose the metal oxide layer 24 underneath, and plasma-treating the exposed metal oxide layer 24 to make the portion
  • the metal oxide layer is electrically conductive so that the portion of the metal oxide layer is used as an image
  • the steps of forming the pixel electrode 26 and the active layer 17 described herein are similar to the above-described steps S8 and S9, and thus the specific steps and figures are not repeatedly described.
  • Step S7' again pass the ashing or the like to remove the second thickness of the second photoresist layer as a whole minus the thickness of the first thickness, that is, after the ashing process, the second layer having the second thickness
  • the photoresist layer is completely removed, exposing the region of the thin film transistor channel to be formed, and etching the exposed source/drain metal layer 25 until reaching the active layer 27 underneath to form the source 28 of the thin film transistor. And drain 29. After the end of the etching, the remaining photoresist layer is removed, thereby completing the second masking process, as shown in FIG.
  • the processing performed here is similar to the above steps S 10-S12.
  • Step S8' A third mask process is performed to form a conductive contact 30 between the drain electrode 29 and the pixel electrode 26, as shown in FIG.
  • Step S9' A passivation layer 31 is deposited on the substrate 21 to cover the entire substrate 21 by a fourth masking process, as shown in FIG.
  • Step S10' A slit-shaped common electrode 32 is formed on the passivation layer 31 as shown in FIG.
  • the fabrication of the bottom gate structure array substrate is completed by using four mask processes.
  • the array substrate of the bottom gate structure according to the embodiment of the present invention includes: a gate electrode 22 formed on the substrate 21 by the substrate 21U; an insulating layer 23 covering the gate electrode 22; formed on the insulating layer 23 and in the same layer
  • the active layer 27 and the pixel electrode 26 are disposed, and the pixel electrode 26 and the active layer 27 are formed of the same metal oxide layer and adjacent to each other, and the metal oxide layer in the active layer 27 has semiconductor properties, and the metal in the pixel electrode 26
  • the oxide layer is subjected to plasma treatment to have a conductor property, and the metal oxide layer may be IGZO or ITZO.
  • a source 28 and a drain 29 are formed over the active layer 27 to form a thin film transistor.
  • the drain 29 is in electrical contact with the pixel electrode 26 through the conductive contact 30.
  • the passivation layer 31 covers the insulating layer 23, the source electrode 28, the drain electrode 29, the active layer 27, and the pixel electrode 26.
  • the common electrode 32 is formed on the passivation layer 31.
  • the manufacturing process of the array substrate is greatly reduced, and the manufacturing cost of the array substrate is reduced.

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Abstract

一种阵列基板及其制造方法、显示装置，该阵列基板的制造方法特征在于：采用一道掩膜工序形成该阵列基板中薄膜晶体管的源极、漏极、有源层及第一透明电极，其中由同一金属氧化物层形成该有源层和该第一透明电极，该源极和漏极位于该有源层上方，其中该第一透明电极对应于掩膜板的第一半透光区域，该薄膜晶体管的沟道区域对应于该掩膜板的第二半透光区域，该薄膜晶体管的源极和漏极对应于该掩膜板的不透光区域，该掩膜板的第一半透光区域的透光率大于该掩膜板的第二半透光区域的透光率。

Description

本发明涉及显示技术领域， 具体涉及一种阵列基板及其制造方法、 显示 装置。
液晶显示装置由于体积小、功耗低、辐射低等优点，被广泛应^于电视、 显示器、 笔记本电脑、 平板电脑等设备上。
目前，在制造超高级超维场转换 HADS, High Advanced Dimension Switch ) 型阵列基板时， 通常需要进行八道掩膜工序， 依次为对»极、 »极绝缘层、 蚀刻停止层、源漏金属层、钝化层、公共电极、钝化层和像素电极进行构图。 由于对于每一道掩膜工序而言， 需要制造成本高昂的掩膜板， 还需要执行曝 光、 显影、 蚀刻、 灰化等工艺步骤， 丛而使得现有阵列基板制造工艺复杂， 生产成本高。 因此， 亟需一种能够减少掩膜工序的制造方法。
本发明所要解决的技术问题是现有阵列基板制造工艺复杂的问题。
为此目的，本发明提出了一种阵列基板的制造方法，其特征在于，包括： 采用一道掩膜工序形成所述阵列基板中薄膜晶体管的源极、 漏极、 有源层及 第一透明电极， 其中由同一金属氧化物层形成所述有源层和所述第一透明电 极， 所述源极和漏极位于所述有源层上方， 其中所述第一透明电极对应于掩 膜板的第一半透光区域， 所述薄膜晶体管的沟道区域对应于所述掩膜板的第 二半透光区域， 所述薄膜晶体管的源极和漏极对应于所述掩膜板的不透光区 域， 所述掩膜板的第一半透光区域的透光率大于所述掩膜板的第二半透光区 域的透光率。
优选的， 在所述掩膜工序中， 使用所述掩膜板进行曝光后， 光刻胶层对 应于所述掩膜板的第一半透光区域的厚度小于对应于所述掩膜板的第二半透 光区域的厚度， 并— .小于对应于所述掩膜板的不透光区域的厚度。 优选地， 所述金属氧化物通过等离子处理形成第一透明电极。
优选地， 所述掩膜板的半透光区域为半色调掩膜或灰阶掩膜。
优选地， 所述金属氧化物为 IGZO或 ITZO或两者的混合物。
优选地， 在釆用一道掩膜工序形成所述阵列基板中薄膜晶体管的源极、 漏极、 有源层及第一透明电极前， 还包括： 在阵列基板上形成有源层遮光层 和所述第一透明电极的引线， 其中所述遮光层对应于薄膜晶体管的有源层区 域， 所述第一透明电极为公共电极。
优选地， 在釆用一道掩膜工序形成所述阵列基板中薄膜晶体管的源极、 漏极、 有源层及第一透明电极后， 还包括： 形成覆盖所述源极、 漏极和所述 第一透明电极的绝缘层， 所述绝缘层上设置有过孔； 形成所述薄膜晶体管的 »极和第二透明电极， 其中所述第二透明电极通过所述绝缘层的过孔与所述 漏极电连接， 所述第二透明电极为狭缝状像素电极。
优选地， 所述漏极的上表面与在靠近第一透明电极一侧的所述绝缘层的 上表面平齐。
优选地， 在采用一道掩膜工序形成所述阵列基板中薄膜晶体管的源极、 漏极、 有源层及第一透明电极前， 还包括： 在所述阵列基板上形成所述薄膜 晶体管的栅极和绝缘层。
优选地， 在采用一道掩膜工序形成所述阵列基板中薄膜晶体管的源极、 漏极、 有源层及第一透明电极后， 还包括： 形成连接所述漏极与所述第一透 明电极的导电接触， 其中所述第一透明电极是像素电极； 形成位于所述导电 接触上方的钝化层和第二透明电极， 所述第二透明电极为狭缝状公共电极。
本发明进一步提出了一种阵列基板， 其特征在于， 包括： 基板； 形成在 所述基板上方的有源层和公共电极， 所述有源层和所述公共电极由同一金属 氧化物层形成； 形成在所述有源层上方的源极和漏极； 形成在所述源极、 漏 极和公共电极上方的绝缘层， 所述绝缘层上设置有过孔； 形成在所述绝缘层 上方的像素电极， 所述像素电极通过所述绝缘层上的过孔与所述漏极连接； 形成在所述绝缘层上方的栅极。
优选地， 所述金属氧化物层通过等离子处理形成公共电极。
优选地， 所述阵列基板还包括： 形成在所述基板与所述有源层之间的遮 光层以及与所述公共电极电连接的公共电极引线。
本发明还提出了一种阵列基板， 其特征在于， 包括： 基板； 形成在所述 基板上方的栅极； 覆盖所述基板和所述栅极的绝缘层； 形成在所述绝缘层上 方的有源层和像素电极， 所述有源层和所述像素电极由同一金属氧化物层形 成旦相互邻接； 形成在所述有源层上方的源极和漏极； 形成在所述漏极和所 述像素电极上的导电接触， ffi于使所述漏极和所述像素电极电连接； 覆盖所 述绝缘层、 源极、 漏极、 有源层、 导电接触和像素电极的钝化层； 形成在所 述钝化层上方的公共电极。
优选地， 所述金属氧化物通过等离子处理形成像素电极。
本发明还提出了一种显示装置， 其包括上述阵列基板。
通过采用本发明所公开的阵列基板制造方法， 在一次掩膜过程中， 通过 使用不同部分具有的不同透光率的掩膜板， 在曝光后形成与透光率相对应的 厚度不同的光刻胶层， 然后在后续的各个蚀刻步骤中分别形成先要的器件， 丛而节省了多次掩膜处理， 极大减少了阵列基板的制造工艺歩骤， 降低了阵 列基板的制造成本。
通过参考附图会更加清楚的理解本发明的特征和优点， 險图是示意性的 而不应理解为对本发明进行任何限制， 在附图中：
图 1示出了根据本发明实施例的 列基板制造方法的流程图。
图 2-23 示出了根据本发明实施例的 列基板制造方法各步骤的示意图， 其中图 23示出了根据本发明实施例的阵列基板的示意图。
图 24示出了根据本发明另一实施例的阵列基板制造方法的流程图； 图 25-34根据本发明另一实施例的阵列基板制造方法各步骤的示意图， 其中图 34示出了根据本发明另一实施例的阵列基板的示意图。
下面将结合 ffi图对本发明的实施例进行详细描述。
图 1示出了根据本发明实施例的阵列基板制造方法的流程图。 如图 1所 示， 根据本发明实施例的阵列基板制造方法共采^了四道掩膜工序， 比现有 制造超高级超维场转换型阵列基板所需的八道掩膜工序减少了四道， 大大减 小了阵列基板的制造工艺步骤， 降低了阵列基板的制造成本。 下面将结合图
2至 17对根据本发明实施例的阵列基板制造方法进行详细说明。
首先参照图 23， 显示了最终制成的阵列基板结构， 其中的 】2为像素电 极， 13为薄膜晶体管的 »极， 因此以下将图中靠左侧部分称为形成薄膜晶体 管的区域 Ft， 将靠右侧部分称为形成像素的区域 Fp以便于进行说明。
首先， 介绍第一道掩膜工序。
步骤 S 在基板 1上沉积金属层， 如图 2所示。
步骤 S2 : 涂覆第一光刻胶层 PR， 并采用单色调掩膜对该第一光刻胶层 进行曝光显影， 图 3示出了曝光显影后的第一光刻胶层 PR。
步骤 S3 : 对金属层进行蚀刻， 并剥离剩余的第一光刻胶层， 从而在待形 成薄膜晶体管的区域 Ft内形成遮光层（：， 并在像素区域 Fp内形成公共电极 的引线 2， 如图 4所示。
接下来， 介绍第二道掩膜工序。
步骤 S4 ; 在基板 1上依次沉积形成金属氧化层物 3和源漏金属层 4， 如 图 5所示。 其中， 金属氧化物层 3可以由 IGZO、 ITZO或其它具有半导体性 质的金属氧化物构成， 源漏金属层 4可以由铜、 铝、 钼等金属构成。
步骤 S5 : 首先在源漏金属层 4上涂覆第二光刻胶层， 然后采 掩膜板来 对该第二光刻胶层进行曝光， 待形成的公共电极对应于该掩膜板的第一半透 光区域 PRa , 待形成的薄膜晶体管的沟道对应于该掩膜板的第二半透光区域 PRb , 待形成的薄膜晶体管的源极和漏极对应于该掩膜板的不透光区域 PRc , 该掩膜板的第一半透光区域的透光率大于第二半透光区域的透光率。 掩膜板 可以是半色调掩膜板或灰度掩膜板。 如同本领域公知的， 掩膜板的透光率会 导致曝光后的光刻胶层的厚度不同。 图 6示出了经该掩膜板曝光显影后的第 二光刻胶层， 该第二光刻胶层在待形成公共电极的区域具有第一厚度 tl， 在 待形成薄膜晶体管沟道的区域具有第二厚度 t2， 在待形成源极和漏极的区域 具有第三厚度 t3， 其中第一厚度小于第二厚度， 第二厚度小于第三厚度。 优 选地，涂覆的对应于掩膜板 PRc部分的第三光刻胶层的厚度为 20000-30000 A， 即第三厚度 t3为 20000- 30000A, 经曝光显影后， 对应掩膜板 PRa部分的第 一光刻胶层的第一厚度 tl为 2000- 6000A， 对应掩膜板 PRb部分的第二光刻 胶层的第二厚度 t2为 6000- 10000A。
步骤 S6: 对未覆盖有第二光刻胶层的区域进行蚀刻， 以去除暴露出的源 漏金属层 4和金属氧化物层 3。 优选地， 可以采用湿法蚀刻。 图 7示出了此 次蚀刻结束后的示意图。
步骤 S7: 通过灰化等工艺， 使第二光刻胶层在整体上去除第一厚度的厚 度 tl，以暴露出待形成公共电极的区域（图中基板的右半部分），如图 8所示。
步骤 S8: 采用蚀刻的方式， 去除掉暴露出的源漏金属层 4， 以暴露出其 下方的金属氧化物层 3， 如图 9所示。
步骤 S9: 对暴露出的金属氧化物层 3进行等离子处理， 使该部分的金属 氧化物层具有导电性， 丛而使该部分金属氧化物层用作为公共电极 6， 未经 等离子处理的金属氧化物层仍然保持半导体性质， 用作为有源层 5， 如图 10 所示。
步骤 S10: 再次通过灰化等工艺， 使第二光刻胶层在整体上去除第二厚 度减去第一厚度的厚度， 即经过此次灰化工艺后， 原来具有第二厚度的第二 光刻胶层 PRb部分被完全去除， 暴露出待形成薄膜晶体管沟道的区域。 图 11 示出了此次灰化工艺后的示意图。
步骤 SH : 对暴露出的源漏金属层 4进行蚀亥 ^， 直到到达其下方的有源 层 5， 以形成薄膜晶体管的源极 7和漏极 8， 如图 12所示。
步骤 S12: 在此次蚀刻结束后去除剩余的第二光刻胶层， 如图 13所示。 接下来介绍第三道掩膜工序。
步骤 在基板 1上沉积绝缘层 9以覆盖整个基板 1， 如图 14所示。 步骤 S14: 在绝缘层 9上涂覆第三光刻胶层， 并采用单色调掩膜板对该 第三光刻胶层进行曝光显影， 以暴露出漏极 8靠近公共电极 6侧的一部分区 域上方的绝缘层 9， 如图 15所示。
步骤 对暴露出的绝缘层 9进行蚀刻， 在绝缘层 9中形成开口 （过 孔）， 以暴露出其下方的漏极 8靠近公共电极 6侧的一部分区域， 如图 16所 示。 优选地， 暴露出的漏极 8的上表面与像素区域内的绝缘层 9的上表面齐 平。
步骤 S】6: 去除剩余的第三光刻胶层， 如图 17所示。
接下来介绍第四道掩膜工序。
步骤 S : 在基板 1上依次沉积第二像素电极层 10和栅极金属层 11， 如 图 18所示。
步骤 在栅极金属层 11上涂覆第四光刻胶层， 并采用另一灰度或半 色调掩膜板来对该第四光刻胶层进行曝光。图 19示出了经曝光显影后的第四 光刻胶层，其中该第四光刻胶层在待形成像素电极的区域 Fp的厚度小于待形 成薄膜晶体管栅极的区域 Ft的厚度。
步骤 S19: 对未覆盖有第四光刻胶层的区域进行馊刻， 以去除暴露出的 像素电极层 10和»极金属层 〗1， 丛而完成了对狭缝状像素电极和栅极的构 图， 如图 20所示。
步骤 S20: 通过灰化等工艺， 暴露出像素电极区域的栅极金属层， 如图 21所示。
步骤 S21 : 去除暴露出的栅极金属层 11， 从而得到像素电极 12的图形以 及薄膜晶体管的栅极 13， 如图 22所示。
步骤 S22: 去除剩余的第四光刻胶层， 从而完成了整个阵列基板的制造 工艺。 图 23示出了最终形成的阵列基板。
如图 23所示， 根据本发明的阵列基板包括： 基板 1 ; 形成在基板 1上方 的遮光层 C和公共电极引线 2; 覆盖遮光层 C的有源层 5和与公共电极引线 2电连接的公共电极 6， 有源层 5和公共电极 6由同一金属氧化物层形成， 有 源层 5中的金属氧化物层具有半导体性质， 公共电极 6中的金属氧化物层经 受等离子处理而具有导体性质， 该金属氧化物层可以是 IGZO或 ITZC 在有 源层 5上方形成源极 7和漏极 8, 源极 7、漏极 8和有源层 5通过其上的绝缘 层 9与栅极 13电绝缘， 从而构成薄膜晶体管。 栅极 13与其下方的绝缘层 9 之间还具有像素电极 12。 绝缘层 9覆盖基板 1、 源极 7、 漏极 8、 有源层 5和 公共电极 6， 并且暴露出漏极 8的一部分。 漏极 8暴露出的部分位于靠近公 共电极 6的一侧， 并且暴露出的漏极 8的上表面与像素区域内的绝缘层 9的 上表面齐平。 像素电极 12形成在绝缘层 9上， 并且与漏极 8电连接。 以上介绍了根据本发明实施例的阵列基板制造方法， 该制造方法采用顶 櫥工艺，极大减少了阵列基板的制造工艺步骤，降低了 列基板的制造成本。
在此基础上， 本发明的另一实施例提出了一种采用底栅工艺的阵列基板 制造方法， 同样 ffi可以减少现有阵列基板的制造工艺步骤。 图 24示出了根据 本发明另一实施例的 列基板制造方法的流程图， 下面将结合图 25至 34对 根据本发明实施例的阵列基板制造方法进行详细说明。
步骤 S 1 ' : 釆^第一道掩膜工序， 在基板 21上形成 »极 22， 如图 25所 示。 该步骤与上述步骤 S 1 S3的步骤相似， 在此不在赘述。
步骤 S2' : 在基板 2】上依次形成绝缘层 23、 金属氧化物层 24和源漏金 属层 25， 如图 26所示。
步骤 S3 ' : 首先在源漏金属层 25上涂覆光刻胶层， 然后采用掩膜板来对 该光刻胶层进行曝光， 待形成的像素电极对应于该掩膜板的第一半透光区域 PRa'， 待形成的薄膜晶体管的沟道对应于该掩膜板的第::：::半透光区域 PRb'， 待形成的薄膜晶体管的源极和漏极对应于该掩膜板的不透光区域 PRc'， 该掩 膜板的第一半透光区域的透光率大于第二半透光区域的透光率。 掩膜板可以 是半色调掩膜板或灰度掩膜板。图 27示出了经该掩膜板曝光显影后的光刻胶 层， 该光刻胶层在待形成像素电极的区域即 PRa'部分具有第一厚度 ti '，在待 形成薄膜晶体管沟道的区域即 PRb'部分具有第二厚度 t2'，在待形成源极和漏 极的区域即 PRc，部分具有第三厚度 t3，，其中第一厚度小于第二厚度， 第二厚 度小于第三厚度。优选地，第一厚度为 2000- 6000A,第二厚度为 6000- 10000A, 第三厚度为 20000-30000 A。
步骤 S4' :对未覆盖有光刻胶层的区域进行蚀刻， 以去除暴露出的源漏金 属层 25和金属氧化物层 24 , 而不蚀刻绝缘层 23。 图 28示出了此次蚀刻结束 后的示意图。
步骤 S5 ' :通过灰化等工艺，使该光刻胶层在整体上去除第一厚度的厚度， 以暴露出待形成像素电极的区域， 如图 29所示。
步骤 S6' : 采用蚀刻的方式， 去除掉暴露出的源漏金属层 25， 以暴露出 其下方的金属氧化物层 24 ,并对暴露出的金属氧化物层 24进行等离子处理， 使该部分的金属氧化物层具有导电性， 从而使该部分金属氧化物层用作为像 素电极 26， 未经等离子处理的金属氧化物层仍然保持半导体性质， 用作为有 源层 27， 如图 30所示。 这里所述的形成像素电极 26和有源层 17的步骤与 上述步骤 S8和 S9相类似， 因此不在重复说明具体步骤和 f†图。
步骤 S7' :再次通过灰化等工艺，使第二光刻胶层在整体上去除第二厚度 减去第一厚度的厚度， 即经过此次灰化工艺后， 原来具有第二厚度的第二光 刻胶层被完全去除， 暴露出待形成薄膜晶体管沟道的区域， 并对暴露出的源 漏金属层 25进行蚀刻， 直到到达其下方的有源层 27， 以形成薄膜晶体管的 源极 28和漏极 29。 在此次蚀刻结束后去除剩余的该光刻胶层， 由此完成第 二道掩膜工序， 如图 31所示。 这里进行的处理与上述步骤 S 10- S 12相类似。
步骤 S8' :采用第三道掩膜工序，形成漏极 29与像素电极 26之间的导电 接触 30， 如图 32所示。
步骤 S9' : 采用第四道掩膜工序， 在基板 21上沉积钝化层 31以覆盖整 个基板 21， 如图 33所示。
步骤 S 10' : 在钝化层 31上形成狭缝状公共电极 32， 如图 34所示。
由此， 通过采用四道掩膜工序， 完成了底栅结构阵列基板的制造。 如图 34所示， 根据本发明实施例的底栅结构的阵列基板包括； 基板 21U 形成在基 板 21上方的栅极 22 ; 覆盖栅极 22的绝缘层 23 ; 形成在绝缘层 23上方且同 层设置的有源层 27和像素电极 26， 像素电极 26与有源层 27由同一金属氧 化物层形成且相互邻接， 有源层 27中的金属氧化物层具有半导体性质， 像素 电极 26中的金属氧化物层经受等离子处理而具有导体性质，该金属氧化物层 可以是 IGZO或 ITZO。在有源层 27上方形成源极 28和漏极 29，丛而构成薄 膜晶体管。 漏极 29通过导电接触 30与像素电极 26电接触。 钝化层 31覆盖 绝缘层 23、 源极 28、 漏极 29、 有源层 27和像素电极 26。 公共电极 32形成 在钝化层 31上。
通过采用本发明所公开的顶栅结构或底栅结构的阵列基板制造方法， 极 大减少了阵列基板的制造工艺歩骤， 降低了阵列基板的制造成本。
以上所述仅是本发明的优选实施方式， 应当指出， 对于本技术领域的普 通技术人员来说， 在不脱离本发明原理的前提下， 还可以做出若干改进和润 饰， 这些改进和润饰也应视本发明的保护范围。

Claims

1、 一种阵列基板的制造方法， 其特征在于， 包括：
采用一道掩膜工序形成所述阵列基板中薄膜晶体管的源极、 漏极、 有源 层及第一透明电极， 其中由同一金属氧化物层形成所述有源层和所述第一透 明电极， 所述源极和漏极位于所述有源层上方， 其中所述第一透明电极对应 于掩膜板的第一半透光区域， 所述薄膜晶体管的沟道区域对应于所述掩膜板 的第二半透光区域， 所述薄膜晶体管的源极和漏极对应于所述掩膜板的不透 光区域， 所述掩膜板的第一半透光区域的透光率大于所述掩膜板的第二半透 光区域的透光率。
2、 根据权利要求 1所述的阵列基板的制造方法， 其特征在于， 在所述掩 膜工序中， 使 ffi所述掩膜板进行曝光后， 光刻胶层对应于所述掩膜板的第一 半透光区域的厚度小于对应于所述掩膜板的第二半透光区域的厚度， 并― 小 于对应于所述掩膜板的不透光区域的厚度。
3、 根据权利要求 1所述的阵列基板的制造方法， 其特征在于， 所述掩膜 板的半透光区域为半色调掩膜或灰阶掩膜。
4、 根根据权利要求 1所述的阵列基板的制造方法， 其特征在于， 所述金 属氧化物通过等离子处理形成第一透明电极。
5、 根据权利要求 1所述的阵列基板的制造方法， 其特征在于， 其中所述 金属氧化物为 IGZO或 ITZO或两者的混合物。
6、 根据权利要求 1至 5任一所述的 列基板的制造方法， 其特征在于， 在采用一道掩膜工序形成所述阵列基板中薄膜晶体管的源极、 漏极、 有源层 及第一透明电极前， 还包括；
在阵列基板上形成有源层遮光层和所述第一透明电极的引线， 其中所述 遮光层对应于薄膜晶体管的有源层区域， 所述第一透明电极为公共电极。
7、 根据权利要求 6所述的阵列基板的制造方法， 其特征在于， 在采用一 道掩膜工序形成所述阵列基板中薄膜晶体管的源极、 漏极、 有源层及第一透 明电极后， 还包括：
形成覆盖所述源极、 漏极和所述第一透明电极的绝缘层， 所述绝缘层上 设置有过孔；
形成所述薄膜晶体管的栅极和第二透明电极， 其中所述第二透明电极通 过所述绝缘层的过孔与所述漏极电连接， 所述第二透明电极为狭缝状像素电 极。
8、 根据权利要求 7所述的阵列基板的制造方法， 其特征在于， 所述漏极 的上表面与在靠近第一透明电极一侧的所述绝缘层的上表面平齐。
9、 根据权利要求 1至 5任一所述的阵列基板的制造方法， 其特征在于， 在釆用一道掩膜工序形成所述阵列基板中薄膜晶体管的源极、 漏极、 有源层 及第一透明电极前， 还包括：
在所述阵列基板上形成所述薄膜晶体管的栅极和绝缘层。
1 0、 根据权利要求 8所述的 列基板的制造方法， 其特征在于， 在采用 一道掩膜工序形成所述阵列基板中薄膜晶体管的源极、 漏极、 有源层及第一 透明电极后， 还包括：
形成连接所述漏极与所述第一透明电极的导电接触， 其中所述第一透明 电极是像素电极；
形成位于所述导电接触上方的钝化层和第二透明电极， 所述第二透明电 极为狭缝状公共电极。
1 一种阵列基板， 其特征在于， 包括：
基板；
形成在所述基板上方的有源层和公共电极， 所述有源层和所述公共电极 由同一金属氧化物层形成；
形成在所述有源层上方的源极和漏极；
形成在所述源极、 漏极和公共电极上方的绝缘层， 所述绝缘层上设置有 过孔；
形成在所述绝缘层上方的像素电极， 所述像素电极通过所述绝缘层上的 过孔与所述漏极连接；
12、 根据权利要求 11所述阵列基板， 其特征在于， 所述金属氧化物层通 过等离子处理形成公共电极。 1 3、 根据权利要求 1】或 12所述阵列基板， 还包括： 形成在所述基板与 所述有源层之间的遮光层以及与所述公共电极电连接的公共电极引线。
14、 一种阵列基板， 其特征在于， 包括：
基板；
形成在所述基板上方的栅极；
覆盖所述基板和所述栅极的绝缘层；
形成在所述绝缘层上方的有源层和像素电极， 所述有源层和所述像素电 极由同一金属氧化物层形成且相互邻接；
形成在所述有源层上方的源极和漏极；
形成在所述漏极和所述像素电极上的导电接触， 用于使所述漏极和所述 像素电极电连接；
覆盖所述绝缘层、源极、漏极、有源层、导电接触和像素电极的钝化层； 形成在所述钝化层上方的公共电极。
15 , 根据权利要求 14所述阵列基板， 其特征在于， 所述金属氧化物通过 等离子处理形成像素电极。
16 , 一种显示装置， 其特征在于， 包括权利要求 11至 15中任一项所述 的阵列基板。
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CN103715137A (zh) * 2013-12-26 2014-04-09 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置

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