CN105137672B - 阵列基板及其制造方法 - Google Patents

阵列基板及其制造方法 Download PDF

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CN105137672B
CN105137672B CN201510487237.1A CN201510487237A CN105137672B CN 105137672 B CN105137672 B CN 105137672B CN 201510487237 A CN201510487237 A CN 201510487237A CN 105137672 B CN105137672 B CN 105137672B
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oxide semiconductor
pixel electrode
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electrode
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CN105137672A (zh
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刘洋
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/897,677 priority patent/US10566458B2/en
Priority to PCT/CN2015/088713 priority patent/WO2017024640A1/zh
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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Abstract

本发明公开了一种阵列基板及其制造方法，属于显示技术领域，解决了现有的阵列基板的制造过程过于复杂的技术问题。该阵列基板包括形成于衬底基板上的多个子像素单元，每个所述子像素单元中包括薄膜晶体管和第二像素电极；所述薄膜晶体管的有源层和所述第二像素电极位于同一图层；所述有源层的材料为氧化物半导体；所述第二像素电极的材料为经等离子体处理的氧化物半导体。本发明可用于IPS型或FFS型液晶显示器中。

Description

阵列基板及其制造方法
技术领域
本发明涉及显示技术领域，具体的说，涉及一种阵列基板及其制造方法。
背景技术
随着显示技术的发展，液晶显示器已经成为最为常见的显示装置。
平面转换(In-Plane Switching，简称IPS)技术及边缘场开关(Fringe FieldSwitching，简称FFS)技术中，第一像素电极和第二像素电极均设置在阵列基板上，从而能够以水平方向的电场驱动液晶，因此具有宽视角，高亮度，高对比度，快速响应等优点。
现有的IPS型、FFS型液晶显示器的阵列基板，需要依次利用掩膜版构图工艺形成栅极金属层、有源层、源漏极金属层、第一透明电极层、过孔图案、第二透明电极层，共需要进行六次掩膜版构图工艺，因此存在制造过程过于复杂的技术问题。
发明内容
本发明的目的在于提供一种阵列基板及其制造方法，以解决现有的阵列基板的制造过程过于复杂的技术问题。
本发明提供一种阵列基板的制造方法，包括：
在衬底基板上形成扫描线、公共电极线、薄膜晶体管的栅极和第一像素电极；
覆盖一层栅极绝缘层；
在所述栅极绝缘层上形成氧化物半导体图形、数据线和薄膜晶体管的源极，其中，所述氧化物半导体图形包括薄膜晶体管的有源层和第二像素电极图形；
覆盖一层钝化层；
对所述钝化层进行蚀刻，露出所述氧化物半导体图形中的第二像素电极图形；
对所述氧化物半导体图形中的第二像素电极图形进行等离子体处理，形成第二像素电极。
进一步的是，对所述氧化物半导体图形中的第二像素电极图形进行等离子体处理，具体为：
利用SF6、N2、Ar或He，对所述氧化物半导体图形中的第二像素电极图形进行等离子体处理。
优选的是，在衬底基板上形成扫描线、公共电极线、薄膜晶体管的栅极和第一像素电极，具体为：
在衬底基板上依次形成透明电极层和第一金属层；
在所述第一金属层上覆盖光刻胶，并利用半色调掩膜版、灰色调掩模版或单狭缝掩膜版进行曝光、显影；
对所述第一金属层和所述透明电极层进行蚀刻，形成扫描线、公共电极线和薄膜晶体管的栅极；
对光刻胶进行灰化；
对所述第一金属层进行蚀刻，形成第一像素电极；
剥离剩余的光刻胶。
优选的是，在所述栅极绝缘层上形成氧化物半导体图形、数据线和薄膜晶体管的源极，具体为：
在栅极绝缘层上依次形成氧化物半导体层和第二金属层；
在所述第二金属层上覆盖光刻胶，并利用半色调掩膜版、灰色调掩模版或单狭缝掩膜版进行曝光、显影；
对所述第二金属层和所述氧化物半导体层进行蚀刻，形成数据线和薄膜晶体管的源极；
对光刻胶进行灰化；
对所述第二金属层进行蚀刻，形成氧化物半导体图形；
剥离剩余的光刻胶。
优选的是，对所述钝化层进行蚀刻，露出所述氧化物半导体图形中的第二像素电极图形，具体为：
在所述钝化层上覆盖光刻胶，并利用掩膜版进行曝光、显影；
对所述钝化层进行蚀刻，露出所述氧化物半导体图形中的第二像素电极图形；
剥离剩余的光刻胶。
进一步的是，对所述钝化层进行蚀刻，具体为：
利用六氟化硫，对所述钝化层进行蚀刻。
本发明还提供一种阵列基板，包括形成于衬底基板上的多个子像素单元，每个所述子像素单元中包括薄膜晶体管和第二像素电极；
所述薄膜晶体管的有源层和所述第二像素电极位于同一图层；
所述有源层的材料为氧化物半导体，所述第二像素电极的材料为经等离子体处理的氧化物半导体。
进一步的是，所述薄膜晶体管的栅极形成于所述衬底基板上，所述有源层位于所述栅极上方，且所述有源层与所述栅极之间形成有栅极绝缘层；
所述薄膜晶体管的源极形成于所述有源层上。
进一步的是，该阵列基板还包括公共电极线、扫描线和数据线；
所述公共电极线和所述扫描线均与所述栅极位于同一图层；
所述数据线与所述源极位于同一图层。
进一步的是，该阵列基板还包括形成于所述衬底基板上的第一像素电极。
本发明带来了以下有益效果：本发明提供的阵列基板中，有源层和第二像素电极位于同一图层，并且第二像素电极的材料是经等离子体处理的氧化物半导体，而有源层的材料是氧化物半导体。在阵列基板的制造过程中，可以在同一次掩膜版构图工艺中形成包括有源层和第二像素电极图形的氧化物半导体图形。再对该第二像素电极图形进行等离子体处理，以提高氧化物半导体的电导率，使其电导率达到像素电极的要求，即可形成第二像素电极。因此，本发明提供的技术方案能够减少掩膜版构图工艺的次数，从而解决了现有的阵列基板的制造过程过于复杂的技术问题，并且能够提高生产效率，降低生产成本。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分的从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
为了更清楚的说明本发明实施例中的技术方案，下面将对实施例描述中所需要的附图做简单的介绍：
图1是本发明实施例提供的阵列基板的示意图；
图2a是发明实施例提供的阵列基板的制造过程中形成透明电极层和第一金属层的示意图；
图2b是发明实施例提供的阵列基板的制造过程中形成扫描线、公共电极线、栅极和第一像素电极的示意图；
图2c是发明实施例提供的阵列基板的制造过程中形成栅极绝缘层的示意图；
图2d是发明实施例提供的阵列基板的制造过程中形成氧化物半导体层和第二金属层的示意图；
图2e是发明实施例提供的阵列基板的制造过程中形成氧化物半导体图形、数据线和源极的示意图；
图2f是发明实施例提供的阵列基板的制造过程中形成钝化层的示意图；
图2g是发明实施例提供的阵列基板的制造过程中形成钝化层和第二像素电极的图形的示意图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是，只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形成的技术方案均在本发明的保护范围之内。
本发明实施例提供一种阵列基板，可应用于IPS型或FFS型液晶显示器中。该阵列基板包括形成于衬底基板上的多个子像素单元，每个子像素单元中包括薄膜晶体管、第一像素电极和第二像素电极。该阵列基板还包括与每行子像素单元对应的公共电极线和扫描线，以及与每列子像素单元对应的数据线。
如图1所示，第一像素电极101直接形成于衬底基板100上，是由透明电极层经过蚀刻形成的。
公共电极线102、扫描线(图中未示出)和薄膜晶体管的栅极103位于同一图层，都是由第一金属层经过蚀刻形成的，而第一金属层形成于透明电极层上。也可以认为，公共电极线102、扫描线和栅极103是由透明电极层和第一金属层的双层结构经过蚀刻形成的，并且也是形成于衬底基板100上的。
薄膜晶体管的有源层105位于栅极103上方，且有源层105与栅极103之间形成有栅极绝缘层104。此外，第一像素电极101、公共电极线102、扫描线也都被栅极绝缘层104所覆盖。
本实施例中，有源层105和第二像素电极106位于同一图层。其中，有源层105的材料为氧化物半导体，第二像素电极106的材料为经等离子体处理的氧化物半导体。
薄膜晶体管的源极107形成于有源层105上，数据线(图中未示出)与源极107位于同一图层，均是由第二金属层经过蚀刻形成的。此外，数据线、源极107和有源层105上还覆盖有钝化层108。
本发明实施例提供的阵列基板中，有源层105和第二像素电极106位于同一图层，并且第二像素电极106的材料是经等离子体处理的氧化物半导体，而有源层105的材料是氧化物半导体。在阵列基板的制造过程中，可以在同一次掩膜版构图工艺中形成包括有源层105和第二像素电极图形的氧化物半导体图形。再对该第二像素电极图形进行等离子体处理，以提高氧化物半导体的电导率，使其电导率达到像素电极的要求，即可形成第二像素电极106。因此，在阵列基板的制造过程中，能够减少掩膜版构图工艺的次数，从而解决了现有的阵列基板的制造过程过于复杂的技术问题，并且能够提高生产效率，降低生产成本。
另外，本实施例中，有源层105和第二像素电极106直接连接，所以有源层105中与第二像素电极106直接相连，使数据线的信号直接写入第二像素电极106上，因此不需要使用金属材料形成漏极。因此，本发明实施例提供的阵列基板还提高了子像素单元的开口率。
本发明实施例还相应的提供了上述阵列基板的制造方法，包括以下步骤：
S1：在衬底基板上形成第一像素电极、扫描线、公共电极线和薄膜晶体管的栅极。
扫描线、公共电极线、栅极和第一像素电极在一次掩膜版构图工艺中形成，具体为：
S11：如图2a所示，在衬底基板100上依次形成透明电极层110和第一金属层120。
透明电极层110可采用氧化铟锡(ITO)、氧化铟锌(IZO)、氧化铝锌(AZO)等材料，厚度可以在100至之间。第一金属层120可采用铝(Al)、钼(Mo)、铜(Cu)、银(Ag)等材料，厚度可以在3000至之间。
S12：在第一金属层上覆盖光刻胶，并利用半色调掩膜版、灰色调掩模版或单狭缝掩膜版进行曝光、显影。
曝光、显影后，一部分区域的光刻胶全部保留，对应于扫描线、公共电极线和栅极；一部分区域的光刻胶被部分去除，对应于第一像素电极；其余区域的光刻胶被全部去除。
S13：对第一金属层和透明电极层进行蚀刻，形成扫描线、公共电极线、薄膜晶体管的栅极。
扫描线、公共电极线和栅极均是由第一金属层和透明电极层组成的双层结构经过蚀刻形成的。另外，此时第一像素电极的形状也已形成，但第一像素电极上仍覆盖有第一金属层。
S14：对光刻胶进行灰化。
利用灰化工艺，将第一像素电极对应区域的光刻胶全部去除。同时，扫描线、公共电极线和栅极对应区域的光刻胶也会被部分去除。
S15：对第一金属层进行蚀刻，形成第一像素电极。
将第一像素电极上覆盖的第一金属层蚀刻掉，即可形成第一像素电极层。
S16：剥离剩余的光刻胶。
如图2b所示，经过第一次掩膜版构图工艺，即可形成第一像素电极101、扫描线、公共电极线102和栅极103。
S2：如图2c所示，在完成上述步骤的基础上，覆盖一层栅极绝缘层104。
栅极绝缘层104的材料可以采用氧化硅(SiOx)、氮化硅(SiNx)或二者的混合物，厚度可以在2000至之间。
S3：在栅极绝缘层上形成氧化物半导体图形、数据线和薄膜晶体管的源极。
其中，氧化物半导体图形包括薄膜晶体管的有源层和第二像素电极图形。本实施例中，氧化物半导体图形、数据线和源极也可以在一次掩膜版构图工艺中形成，具体为：
S31：如图2d所示，在栅极绝缘层104上依次形成氧化物半导体层150和第二金属层170。
氧化物半导体层150可以采用ZnO基、SnO2基、In2O3基等透明氧化物半导体材料，厚度可以在200至之间。第二金属层170的材料、厚度可以与第一金属层相同。
S32：在第二金属层上覆盖光刻胶，并利用半色调掩膜版、灰色调掩模版或单狭缝掩膜版进行曝光、显影。
曝光、显影后，一部分区域的光刻胶全部保留，对应于数据线和源极；一部分区域的光刻胶被部分去除，对应于氧化物半导体图形；其余区域的光刻胶被全部去除。
S33：对第二金属层和氧化物半导体层进行蚀刻，形成数据线和薄膜晶体管的源极。
所形成的数据线和源极均是由第二金属层经过蚀刻形成的。另外，此时氧化物半导体图形的形状也已形成，但氧化物半导体图形上仍覆盖有第二金属层。
S34：对光刻胶进行灰化。
利用灰化工艺，将氧化物半导体图形对应区域的光刻胶全部去除。同时，数据线和源极对应区域的光刻胶也会被部分去除。
S35：对第二金属层进行蚀刻，形成氧化物半导体图形。
将氧化物半导体图形上覆盖的第二金属层蚀刻掉，即可形成氧化物半导体图形。
S36：剥离剩余的光刻胶。
如图2e所示，经过第二次掩膜版构图工艺，即可形成氧化物半导体图形、数据线和源极107。其中，氧化物半导体图形包括薄膜晶体管的有源层105和第二像素电极图形160。
S4：如图2f所示，在完成上述步骤的基础上，覆盖一层钝化层108。
钝化层108的材料可以采用氧化硅(SiOx)、氮化硅(SiNx)或二者的混合物，厚度可以在2000至之间。
S5：对钝化层进行蚀刻，露出氧化物半导体图形中的第二像素电极图形。具体包括：
S51：在钝化层上覆盖光刻胶，并利用掩膜版进行曝光、显影。
曝光、显影后，一部分区域光刻胶被去除，对应于第二像素电极图形，其余区域的光刻胶保留。
S52：对钝化层进行蚀刻，露出氧化物半导体图形中的第二像素电极图形。
利用六氟化硫(SF6)，对第二像素电极图形对应区域的钝化层进行蚀刻，使第二像素电极图形暴露出来。
S53：剥离剩余的光刻胶。
如图2g所示，经过第三次掩膜版构图工艺，即可形成钝化层108的图形，并且露出第二像素电极图形160。
S6：对氧化物半导体图形中的第二像素电极图形进行等离子体处理，形成第二像素电极。
可以利用SF6、N2、Ar、He等作为等离子体，对第二像素电极图形进行等离子体处理，以提高透明金属氧化物半导体的电导率，使其电导率达到像素电极的要求，从而形成第二像素电极。其中，SF6既可以对钝化层进行蚀刻，也可以对第二像素电极图形进行等离子体处理，并且为了提高等离子体处理的效果，在SF6中加入了N2、Ar、He。
如图1所示，经过上述步骤，即可形成本发明实施例提供的阵列基板。本发明实施例提供的阵列基板的制造方法中，仅使用了三次掩膜版构图工艺，从而解决了现有的阵列基板的制造过程过于复杂的技术问题，并且能够提高生产效率，降低生产成本。
应当说明的是，在其他实施方式中，也可以单独通过一次掩膜版构图工艺形成第一像素电极，再单独通过一次掩膜版构图工艺形成扫描线、公共电极线和栅极。则阵列基板的制造过程中共使用四次掩膜版构图工艺，但相比于现有技术中使用六次掩膜版构图工艺，仍然能够有效简化阵列基板的制造过程。
虽然本发明所公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (6)

1.一种阵列基板的制造方法，包括：
在衬底基板上形成扫描线、公共电极线、薄膜晶体管的栅极和第一像素电极；
覆盖一层栅极绝缘层；
在所述栅极绝缘层上形成氧化物半导体图形、数据线和薄膜晶体管的源极，其中，所述氧化物半导体图形包括薄膜晶体管的有源层和第二像素电极图形，所述有源层和所述第二像素电极位于同一图层；
覆盖一层钝化层；
对所述钝化层进行蚀刻，露出所述氧化物半导体图形中的第二像素电极图形；
对所述氧化物半导体图形中的第二像素电极图形进行等离子体处理，形成第二像素电极。
2.根据权利要求1所述的方法，其特征在于，对所述氧化物半导体图形中的第二像素电极图形进行等离子体处理，具体为：
利用SF6、N2、Ar或He，对所述氧化物半导体图形中的第二像素电极图形进行等离子体处理。
3.根据权利要求1所述的方法，其特征在于，在衬底基板上形成扫描线、公共电极线、薄膜晶体管的栅极和第一像素电极，具体为：
在衬底基板上依次形成透明电极层和第一金属层；
在所述第一金属层上覆盖光刻胶，并利用半色调掩膜版、灰色调掩模版或单狭缝掩膜版进行曝光、显影；
对所述第一金属层和所述透明电极层进行蚀刻，形成扫描线、公共电极线和薄膜晶体管的栅极；
对光刻胶进行灰化；
对所述第一金属层进行蚀刻，形成第一像素电极；
剥离剩余的光刻胶。
4.根据权利要求1所述的方法，其特征在于，在所述栅极绝缘层上形成氧化物半导体图形、数据线和薄膜晶体管的源极，具体为：
在栅极绝缘层上依次形成氧化物半导体层和第二金属层；
在所述第二金属层上覆盖光刻胶，并利用半色调掩膜版、灰色调掩模版或单狭缝掩膜版进行曝光、显影；
对所述第二金属层和所述氧化物半导体层进行蚀刻，形成数据线和薄膜晶体管的源极；
对光刻胶进行灰化；
对所述第二金属层进行蚀刻，形成氧化物半导体图形；
剥离剩余的光刻胶。
5.根据权利要求1所述的方法，其特征在于，对所述钝化层进行蚀刻，露出所述氧化物半导体图形中的第二像素电极图形，具体为：
在所述钝化层上覆盖光刻胶，并利用掩膜版进行曝光、显影；
对所述钝化层进行蚀刻，露出所述氧化物半导体图形中的第二像素电极图形；
剥离剩余的光刻胶。
6.根据权利要求5所述的方法，其特征在于，对所述钝化层进行蚀刻，具体为：
利用六氟化硫，对所述钝化层进行蚀刻。
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