CN105549278B - Ips型tft‑lcd阵列基板的制作方法及ips型tft‑lcd阵列基板 - Google Patents

Ips型tft‑lcd阵列基板的制作方法及ips型tft‑lcd阵列基板 Download PDF

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CN105549278B
CN105549278B CN201610016787.XA CN201610016787A CN105549278B CN 105549278 B CN105549278 B CN 105549278B CN 201610016787 A CN201610016787 A CN 201610016787A CN 105549278 B CN105549278 B CN 105549278B
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China
Prior art keywords
layer
electrode
insulating protective
protective layer
lcd array
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CN201610016787.XA
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CN105549278A (zh
Inventor
徐向阳
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to CN201610016787.XA priority Critical patent/CN105549278B/zh
Priority to PCT/CN2016/074503 priority patent/WO2017121009A1/zh
Priority to JP2018519435A priority patent/JP6572388B2/ja
Priority to US15/026,254 priority patent/US10073308B2/en
Priority to KR1020187006541A priority patent/KR101981904B1/ko
Priority to GB1802102.2A priority patent/GB2556762B/en
Publication of CN105549278A publication Critical patent/CN105549278A/zh
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
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Abstract

本发明提供一种IPS型TFT‑LCD阵列基板的制作方法及IPS型TFT‑LCD阵列基板。本发明的IPS型TFT‑LCD阵列基板的制作方法，将像素电极和公共电极采用同一透明导电层制得，且像素电极和公共电极下方的绝缘保护层上设有数个相互平行的条状的沟道，像素电极与公共电极沿沟道两侧的凸台交替分布且延伸至沟道的侧壁上，从而增大了像素电极和公共电极在垂直于基板方向的面积，增加了水平电场，同时也增大了存储电容，进而提高了液晶面板的显示质量。

Description

IPS型TFT-LCD阵列基板的制作方法及IPS型TFT-LCD阵列基板
技术领域
本发明涉及显示技术领域，尤其涉及一种IPS型TFT-LCD阵列基板的制作方法及IPS型TFT-LCD阵列基板。
背景技术
随着显示技术的发展，薄膜晶体管液晶显示器(Thin Film Transistor LiquidCrystal Display，TFT-LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
现有市场上的液晶显示装置大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlight module)。液晶显示面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，两片玻璃基板中间有许多垂直和水平的细小电线，通过通电与否来控制液晶分子改变方向，将背光模组的光线折射出来产生画面。通常液晶显示面板由彩膜(CF，ColorFilter)基板、阵列基板、夹于彩膜基板与阵列基板之间的液晶(LC，Liquid Crystal)及密封胶框(Sealant)组成，其成型工艺一般包括：前段阵列(Array)制程(薄膜、黄光、蚀刻及剥膜)、中段成盒(Cell)制程(阵列基板与CF基板贴合)及后段模组组装制程(驱动IC与印刷电路板压合)。其中，前段Array制程主要是形成阵列基板，以便于控制液晶分子的运动；中段Cell制程主要是在阵列基板与CF基板之间添加液晶；后段模组组装制程主要是驱动IC压合与印刷电路板的整合，进而驱动液晶分子转动，显示图像。
液晶面板的阵列基板上设置有数条扫描线、数条数据线、和数条公共电极走线，该数条扫描线和数条数据线限定出多个像素单元，每个像素单元内设置有薄膜晶体管和像素电极，薄膜晶体管的栅极与相应的栅线相连，当栅线上的电压达到开启电压时，薄膜晶体管的源极和漏极导通，从而将数据线上的数据电压输入至像素电极。
目前主流市场上的TFT-LCD，就液晶的驱动模式而言，可分为三种类型，分别是扭曲向列(Twisted Nematic，TN)或超扭曲向列(Super Twisted Nematic，STN)型，面内转换(In-Plane Switching，IPS)型、及垂直配向(Vertical Alignment，VA)型。其中IPS模式是利用与基板面大致平行的电场驱动液晶分子沿基板面内转动以响应的模式，由于具有优异的视角特性，所以被用于各种TV显示用途当中。
在IPS模式中，通过像素电极或公共电极边缘所产生的平行电场以及像素电极与公共电极之间产生的纵向电场形成多维电场，使液晶盒内像素电极间或公共电极间、像素电极正上方或公共电极正上方所有取向的液晶分子都能够产生旋转转换，从而可提高平面取向系液晶的工作效率并增大透光效率。如图1所示，为传统的IPS型TFT-LCD阵列基板的结构，其上的每一像素单元包括设于基板100上的栅极101、设于栅极101及基板100上栅极绝缘层102、设于栅极绝缘层102上的半导体层103、设于半导体层103、及栅极绝缘层102上的源极104和漏极105、设于所述源极104、漏极105、半导体层103、及栅极绝缘层102上绝缘保护层106、及形成于所述绝缘保护层106上的像素电极107；且在该TFT阵列基板上，公共电极层120与栅极101和栅极扫描线110为同一金属层制得，像素电极107通过绝缘保护层106上的过孔结构连接到漏极105。
然而，随着技术的进步，消费者对电子产品的显示效果提出了更高的要求，人们不断追求显示器件具有更好的显示效果及更高的透过率。
发明内容
本发明的目的在于提供一种IPS型TFT-LCD阵列基板的制作方法，像素电极和公共电极采用同一透明导电层制得，且像素电极和公共电极下方的绝缘保护层上设有数个相互平行的条状的沟道，像素电极与公共电极沿沟道两侧的凸台交替分布且延伸至沟道的侧壁上，从而增大像素电极和公共电极在垂直于基板方向的面积，增加水平电场，增大存储电容，提高液晶面板的显示质量。
本发明的目的还在于提供一种IPS型TFT-LCD阵列基板，像素电极和公共电极下方的绝缘保护层上设有数个相互平行的条状的沟道，像素电极与公共电极沿沟道两侧的凸台交替分布且延伸至沟道的侧壁上，从而增大像素电极和公共电极在垂直于基板方向的面积，增加水平电场，增大存储电容，进而提高液晶面板的显示质量。
为实现上述目的，本发明提供一种IPS型TFT-LCD阵列基板的制作方法，包括如下步骤：
步骤1、提供基板，在所述基板上沉积栅极金属层，并对所述栅极金属层进行图案化处理，得到栅极及栅极扫描线；
步骤2、在栅极金属层上沉积栅极绝缘层，在所述栅极绝缘层上沉积一层非晶硅层，并对非晶硅层进行N型掺杂后，对所述非晶硅层进行图案化处理，得到对应于所述栅极上方的半导体层；
步骤3、在所述半导体层、及栅极绝缘层上沉积源漏极金属层，并对所述源漏极金属层进行图案化处理，得到源极、漏极、及数据线，所述源极和漏极分别与所述半导体层的两端相接触；其中，数据线与栅极扫描线围出数个像素区域；
步骤4、在所述源漏极金属层上形成绝缘保护层，并对绝缘保护层进行图案化处理，在所述绝缘保护层上形成对应于所述漏极上方的过孔和位于像素区域内的数个相互平行的条状的沟道；
步骤5、在所述绝缘保护层上沉积一层透明导电层，并对所述透明导电层进行图案化处理，得到像素电极及公共电极，所述像素电极通过过孔与漏极相接触，所述像素电极与公共电极间隔设置，在每一像素区域内，所述像素电极与公共电极沿沟道两侧的凸台交替分布且延伸至沟道的侧壁上。
所述步骤1中通过物理气相沉积法沉积栅极金属层，所沉积的栅极金属层的膜厚为所述栅极金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；对所述栅极金属层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、湿法蚀刻、及光阻剥离。
所述步骤2中通过等离子体增强化学气相沉积法沉积栅极绝缘层和非晶硅层，所沉积的栅极绝缘层的膜厚为所沉积的非晶硅层的膜厚为所述栅极绝缘层为氮化硅层，对所述非晶硅层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、干法蚀刻、及光阻剥离。
所述步骤3中通过物理气相沉积法沉积源漏极金属层，所沉积的源漏极金属层的膜厚为所述源漏极金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合，对所述源漏极金属层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、湿法蚀刻、及光阻剥离。
所述步骤4中形成的绝缘保护层16包括氮化硅层、及设于氮化硅层上的有机膜层；所述绝缘保护层16的氮化硅层的膜厚为通过化学气相沉积法形成；所述绝缘保护层16的有机膜层的膜厚为0.2～0.4μm，通过涂布工艺形成；对所述绝缘保护层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、干法蚀刻、及光阻剥离。
所述步骤5中通过物理气相沉积法沉积透明导电层，所沉积透明导电层的膜厚为所述透明导电层的材料为铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物中的一种或多种；对所述透明导电层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、湿法蚀刻、及光阻剥离。
本发明还提供一种IPS型TFT-LCD阵列基板，包括：基板、设于所述基板上的数条栅极扫描线、数条数据线、及由数条栅极扫描线与数条数据线相互绝缘交错划分出的多个阵列排布的像素单元；
每一像素单元均包括形成于基板上的栅极、形成于栅极及基板上栅极绝缘层、对应于栅极上方且形成于栅极绝缘层上的半导体层、形成于半导体层、及栅极绝缘层上的源极和漏极、形成于所述源极、漏极、半导体层、及栅极绝缘层上绝缘保护层、及形成于所述绝缘保护层上的像素电极和公共电极；
所述源极、漏极分别与所述半导体层的两端相接触；
所述绝缘保护层上对应所述漏极的上方设有过孔，所述像素电极通过过孔与所述漏极相接触；
所述绝缘保护层上设有位于像素单元范围内的数个相互平行的条状的沟道；
所述像素电极与公共电极由同一透明导电层经图案化后得到，所述像素电极与公共电极间隔设置，每一像素单元范围内，所述像素电极与公共电极沿沟道两侧的凸台交替分布且延伸至沟道的侧壁上。
所述像素电极与公共电极的材料为透明导电材料，所述透明导电材料为铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物中的一种或多种；所述像素电极与公共电极的膜厚为
所述源漏极金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合，所述源漏极金属层的膜厚为
所述绝缘保护层包括氮化硅层、及设于氮化硅层上的有机膜层，所述绝缘保护层的氮化硅层的膜厚为所述绝缘保护层的有机膜层的膜厚为0.2～0.4μm。
本发明的有益效果：本发明的IPS型TFT-LCD阵列基板的制作方法，将像素电极和公共电极采用同一透明导电层制得，且像素电极和公共电极下方的绝缘保护层上设有数个相互平行的条状的沟道，像素电极与公共电极沿沟道两侧的凸台交替分布且延伸至沟道的侧壁上，从而增大了像素电极和公共电极在垂直于基板方向的面积，增加了水平电场，同时也增大了存储电容，进而提高了液晶面板的显示质量；本发明的IPS型TFT-LCD阵列基板，像素电极与公共电极采用同层的设计，且像素电极和公共电极下方的绝缘保护层上设有数个相互平行的条状的沟道，像素电极与公共电极沿沟道两侧的凸台交替分布且延伸至沟道的侧壁上，从而增大了像素电极和公共电极在垂直于基板方向的面积，增加了水平电场，同时也增大了存储电容，进而提高了液晶面板的显示质量。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的IPS型TFT-LCD阵列基板的结构示意图；
图2为本发明的IPS型TFT-LCD阵列基板的制作方法的示意流程图；
图3-4为本发明的IPS型TFT-LCD阵列基板的制作方法的步骤1的示意图；
图5-6为本发明的IPS型TFT-LCD阵列基板的制作方法的步骤2的示意图；
图7-8为本发明的IPS型TFT-LCD阵列基板的制作方法的步骤3的示意图；
图9-10为本发明的IPS型TFT-LCD阵列基板的制作方法的步骤4的示意图；
图11为本发明的IPS型TFT-LCD阵列基板的制作方法的步骤5的示意图；
图12为本发明的IPS型TFT-LCD阵列基板的制作方法的步骤5中一像素区域内所形成的像素电极与公共电极的示意图；
图13为本发明的IPS型TFT-LCD阵列基板的制作方法的步骤5的示意图暨本发明的IPS型TFT-LCD阵列基板的结构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图2，本发明提供一种IPS型TFT-LCD阵列基板的制作方法，包括如下步骤：
步骤1、如图3-4所示，提供基板10，在所述基板10上沉积栅极金属层，并对所述栅极金属层进行图案化处理，得到栅极11及栅极扫描线20。
具体的，所述步骤1中通过物理气相沉积法(Physical Vapor Deposition，PVD)沉积栅极金属层，所沉积的栅极金属层的膜厚为所述栅极金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；对所述栅极金属层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、湿法蚀刻、及光阻剥离。
步骤2、如图5-6所示，在栅极金属层上沉积栅极绝缘层12，在所述栅极绝缘层12上沉积一层非晶硅层，并对非晶硅层进行N型掺杂后，对所述非晶硅层进行图案化处理，得到对应于栅极上方的半导体层13。
具体的，所述步骤2中通过化学气相沉积法(Chemical Vapor Deposition，CVD)沉积栅极绝缘层12和非晶硅层，所沉积的栅极绝缘层12的膜厚为所沉积的非晶硅层的膜厚为对所述非晶硅层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、干法蚀刻、及光阻剥离。
优选的，所述栅极绝缘层12为氮化硅层。
步骤3、如图7-8所示，在所述半导体层13、及栅极绝缘层12上沉积源漏极金属层，并对所述源漏极金属层进行图案化处理，得到源极14、漏极15、及数据线30，所述源极14和漏极15分别与所述半导体层13的两端相接触；其中，数据线30与栅极扫描线20围出数个像素区域。
具体的，所述步骤3中通过物理气相沉积法沉积的源漏极金属层，所沉积的源漏极金属层的膜厚为所述源漏极金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合，对所述源漏极金属层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、湿法蚀刻、及光阻剥离。
步骤4、如图9-10所示，在所述源漏极金属层上形成绝缘保护层16，并对绝缘保护层16进行图案化处理，在所述绝缘保护层16上形成对应于所述漏极15上方的过孔161和位于像素区域内的数个相互平行的条状的沟道162。
具体的，所述步骤4中形成的绝缘保护层16包括氮化硅层、及设于氮化硅层上的有机膜层；所述绝缘保护层16氮化硅层的膜厚为通过化学气相沉积法形成；所述绝缘保护层16的有机膜层的膜厚为0.2～0.4μm，通过涂布工艺形成。其中，所述绝缘保护层16的有机膜层用于增加绝缘保护层16的厚度，进而增加所形成的沟道162的深度，从而增加后续步骤5中所形成的像素电极17与公共电极18在沟道162的侧壁上延伸的长度，进而增加了像素电极17和公共电极18在垂直于基板方向的面积。
具体的，对所述绝缘保护层16进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、干法蚀刻、及光阻剥离。
步骤5、如图11-13所示，在所述绝缘保护层16上沉积一层透明导电层，并对所述透明导电层进行图案化处理，得到像素电极17及公共电极18，所述像素电极17通过过孔161与漏极15相接触，所述像素电极17与公共电极18间隔设置，在每一像素区域内，所述像素电极17与公共电极18沿沟道162两侧的凸台交替分布且延伸至沟道162的侧壁上。
具体的，所述步骤5中通过物理气相沉积法沉积透明导电层，所沉积的透明导电层的膜厚为所述透明导电层的材料为铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物中的一种或多种；对所述透明导电层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、湿法蚀刻、及光阻剥离。
优选的，所沉积透明导电层的材料为铟锡氧化物(ITO)。
请参阅图13，基于以上IPS型TFT-LCD阵列基板的制作方法，本发明还提供一种IPS型TFT-LCD阵列基板，包括：基板10、设于基板10上的数条栅极扫描线20、数条数据线30、及由数条栅极扫描线20与数条数据线30相互绝缘交错划分出的多个阵列排布的像素单元；
每一像素单元均包括：形成于基板10上的栅极11、形成于栅极11及基板10上栅极绝缘层12、对应于栅极11上方且形成于栅极绝缘层12上的半导体层13、形成于半导体层13、及栅极绝缘层12上的源极14和漏极15、形成于所述源极14、漏极15、半导体层13、及栅极绝缘层12上绝缘保护层16、及形成于所述绝缘保护层16上的像素电极17和公共电极18；
所述源极14、漏极15分别与所述半导体层13的两端相接触；
所述绝缘保护层16上对应所述漏极15的上方设有过孔161，所述像素电极17通过过孔161与所述漏极15相接触；
所述绝缘保护层16上设有位于像素单元范围内的数个相互平行的条状的沟道162；
所述像素电极17与公共电极18由同一透明导电层经图案化后得到，所述像素电极17与公共电极18间隔设置，每一像素单元范围内，所述像素电极17与公共电极18沿沟道162两侧的凸台交替分布且延伸至沟道162的侧壁上。
具体的，所述像素电极17与公共电极18的材料为透明导电材料，所述透明导电材料为铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物中的一种或多种；所述像素电极17与公共电极18的膜厚为
优选的，所述像素电极17与公共电极18的材料为铟锡氧化物。
具体的，所述源漏极金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合，所述源漏极金属层的膜厚为
具体的，所述绝缘保护层16包括氮化硅层、及设于氮化硅层上的有机膜层，所述绝缘保护层16的氮化硅层的膜厚为所述绝缘保护层16的有机膜层的膜厚为0.2～0.4μm。其中，所述绝缘保护层16的有机膜层用于增加绝缘保护层16的厚度，进而增加所形成的沟道162的深度，从而增加后续步骤5中所形成的像素电极17与公共电极18在沟道162的侧壁上延伸的长度，进而增加了像素电极17和公共电极18在垂直于基板方向的面积。
综上所述，本发明的IPS型TFT-LCD阵列基板的制作方法，将像素电极和公共电极采用同一透明导电层制得，且像素电极和公共电极下方的绝缘保护层上设有数个相互平行的条状的沟道，像素电极与公共电极沿沟道两侧的凸台交替分布且延伸至沟道的侧壁上，从而增大了像素电极和公共电极在垂直于基板方向的面积，增加了水平电场，同时也增大了存储电容，进而提高了液晶面板的显示质量；本发明的IPS型TFT-LCD阵列基板，像素电极与公共电极采用同层的设计，且像素电极和公共电极下方的绝缘保护层上设有数个相互平行的条状的沟道，像素电极与公共电极沿沟道两侧的凸台交替分布且延伸至沟道的侧壁上，从而增大了像素电极和公共电极在垂直于基板方向的面积，增加了水平电场，同时也增大了存储电容，进而提高了液晶面板的显示质量。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

1.一种IPS型TFT-LCD阵列基板的制作方法，其特征在于，包括如下步骤：
步骤1、提供基板(10)，在所述基板(10)上沉积栅极金属层，并对所述栅极金属层进行图案化处理，得到栅极(11)及栅极扫描线(20)；
步骤2、在栅极金属层上沉积栅极绝缘层(12)，所述栅极绝缘层(12)上沉积一层非晶硅层，并对非晶硅层进行N型掺杂后，对所述非晶硅层进行图案化处理，得到对应于所述栅极(11)上方的半导体层(13)；
步骤3、在所述半导体层(13)、及栅极绝缘层(12)上沉积源漏极金属层，并对所述源漏极金属层进行图案化处理，得到源极(14)、漏极(15)、及数据线(30)，所述源极(14)和漏极(15)分别与所述半导体层(13)的两端相接触；其中，数据线(30)与栅极扫描线(20)围出数个像素区域；
步骤4、在所述源漏极金属层上形成绝缘保护层(16)，并对绝缘保护层(16)进行图案化处理，在所述绝缘保护层(16)上形成对应于所述漏极(15)上方的过孔(161)和位于像素区域内的数个相互平行的条状的沟道(162)；
步骤5、在所述绝缘保护层(16)上沉积一层透明导电层，并对所述透明导电层进行图案化处理，得到像素电极(17)及公共电极(18)，所述像素电极(17)通过过孔(161)与漏极(15)相接触，所述像素电极(17)与公共电极(18)间隔设置，在每一像素区域内，所述像素电极(17)与公共电极(18)沿沟道(162)两侧的凸台交替分布且延伸至沟道(162)的侧壁上。
2.如权利要求1所述的IPS型TFT-LCD阵列基板的制作方法，其特征在于，所述步骤1中通过物理气相沉积法沉积栅极金属层，所沉积的栅极金属层的膜厚为所述栅极金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；对所述栅极金属层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、湿法蚀刻、及光阻剥离。
3.如权利要求1所述的IPS型TFT-LCD阵列基板的制作方法，其特征在于，所述步骤2中通过化学气相沉积法沉积栅极绝缘层(12)和非晶硅层，所沉积的栅极绝缘层(12)的膜厚为所沉积的非晶硅层的膜厚为所述栅极绝缘层(12)为氮化硅层，对所述非晶硅层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、干法蚀刻、及光阻剥离。
4.如权利要求1所述的IPS型TFT-LCD阵列基板的制作方法，其特征在于，所述步骤3中通过物理气相沉积法沉积源漏极金属层，所沉积的源漏极金属层的膜厚为所述源漏极金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合，对所述源漏极金属层进行图案化处理的步骤包括依次进行的光阻涂布、曝光显影、湿法蚀刻、及光阻剥离。
5.如权利要求1所述的IPS型TFT-LCD阵列基板的制作方法，其特征在于，所述步骤4中形成的绝缘保护层(16)包括氮化硅层、及设于氮化硅层上的有机膜层；所述绝缘保护层(16)的氮化硅层的膜厚为通过化学气相沉积法形成；所述绝缘保护层(16)的有机膜层的膜厚为0.2～0.4μm，通过涂布工艺形成；对所述绝缘保护层(16)进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、干法蚀刻、及光阻剥离。
6.如权利要求1所述的IPS型TFT-LCD阵列基板的制作方法，其特征在于，所述步骤5中通过物理气相沉积法沉积透明导电层，所沉积透明导电层的膜厚为所述透明导电层的材料为铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物中的一种或多种；对所述透明导电层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、湿法蚀刻、及光阻剥离。
7.一种IPS型TFT-LCD阵列基板，包括：基板(10)、设于所述基板(10)上的数条栅极扫描线(20)、数条数据线(30)、及由数条栅极扫描线(20)与数条数据线(30)相互绝缘交错划分出的多个阵列排布的像素单元；每一像素单元包括形成于基板(10)上的栅极(11)、形成于栅极(11)及基板(10)上栅极绝缘层(12)、对应于栅极(11)上方且形成于栅极绝缘层(12)上的半导体层(13)、形成于半导体层(13)、及栅极绝缘层(12)上的源极(14)和漏极(15)、形成于所述源极(14)、漏极(15)、半导体层(13)、及栅极绝缘层(12)上绝缘保护层(16)、及形成于所述绝缘保护层(16)上的像素电极(17)和公共电极(18)；所述源极(14)、漏极(15)分别与所述半导体层(13)的两端相接触；所述绝缘保护层(16)上对应所述漏极(15)的上方设有过孔(161)，所述像素电极(17)通过过孔(161)与所述漏极(15)相接触；所述绝缘保护层(16)上设有位于像素单元范围内的数个相互平行的条状的沟道(162)；其特征在于，所述像素电极(17)与公共电极(18)由同一透明导电层经图案化后得到，所述像素电极(17)与公共电极(18)间隔设置，每一像素单元范围内，所述像素电极(17)与公共电极(18)沿沟道(162)两侧的凸台交替分布且延伸至沟道(162)的侧壁上。
8.如权利要求7所述的IPS型TFT-LCD阵列基板，其特征在于，所述像素电极(17)与公共电极(18)的材料为透明导电材料，所述透明导电材料为铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物中的一种或多种；所述像素电极(17)与公共电极(18)的膜厚为
9.如权利要求7所述的IPS型TFT-LCD阵列基板，其特征在于，所述源漏极金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合，所述源漏极金属层的膜厚为
10.如权利要求7所述的IPS型TFT-LCD阵列基板，其特征在于，所述绝缘保护层(16)包括氮化硅层、及设于氮化硅层上的有机膜层，所述绝缘保护层(16)的氮化硅层的膜厚为所述绝缘保护层(16)的有机膜层的膜厚为0.2～0.4μm。
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