WO2017121009A1 - Ips型tft-lcd阵列基板的制作方法及ips型tft-lcd阵列基板 - Google Patents

Ips型tft-lcd阵列基板的制作方法及ips型tft-lcd阵列基板 Download PDF

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WO2017121009A1
WO2017121009A1 PCT/CN2016/074503 CN2016074503W WO2017121009A1 WO 2017121009 A1 WO2017121009 A1 WO 2017121009A1 CN 2016074503 W CN2016074503 W CN 2016074503W WO 2017121009 A1 WO2017121009 A1 WO 2017121009A1
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Prior art keywords
layer
gate
drain
source
pixel electrode
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PCT/CN2016/074503
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English (en)
French (fr)
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徐向阳
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深圳市华星光电技术有限公司
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Priority to GB1802102.2A priority Critical patent/GB2556762B/en
Priority to US15/026,254 priority patent/US10073308B2/en
Priority to JP2018519435A priority patent/JP6572388B2/ja
Priority to KR1020187006541A priority patent/KR101981904B1/ko
Publication of WO2017121009A1 publication Critical patent/WO2017121009A1/zh

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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/122—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode having a particular pattern
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/103—Materials and properties semiconductor a-Si

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating an IPS type TFT-LCD array substrate and an IPS type TFT-LCD array substrate.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • liquid crystal display devices which include a liquid crystal display panel and a backlight module.
  • the working principle of the liquid crystal display panel is to place liquid crystal molecules in two parallel glass substrates. There are many vertical and horizontal small wires between the two glass substrates, and the liquid crystal molecules are controlled to change direction by energizing or not, and the light of the backlight module is changed. Refracted to produce a picture.
  • the liquid crystal display panel is composed of a CF (Color Filter) substrate, an array substrate, a liquid crystal (LC) sandwiched between the color filter substrate and the array substrate, and a sealant frame (Sealant), and the molding process generally includes : Array process (film, yellow light, etching and stripping), middle cell (Cell process) (array substrate and CF substrate) and rear module assembly process (drive IC and printed circuit board voltage) Combined).
  • the front Array process mainly forms an array substrate to control the movement of the liquid crystal molecules;
  • the middle Cell process mainly adds liquid crystal between the array substrate and the CF substrate;
  • the rear module assembly process is mainly to drive the IC to press and print the circuit.
  • the integration of the plates drives the liquid crystal molecules to rotate and display images.
  • the array substrate of the liquid crystal panel is provided with a plurality of scan lines, a plurality of data lines, and a plurality of common electrode traces, wherein the plurality of scan lines and the plurality of data lines define a plurality of pixel units, and each of the pixel units is provided with a thin film a transistor and a pixel electrode, the gate of the thin film transistor is connected to the corresponding gate line.
  • the voltage on the gate line reaches the turn-on voltage, the source and the drain of the thin film transistor are turned on, thereby inputting the data voltage on the data line to the pixel. electrode.
  • the TFT-LCD in the mainstream market can be divided into three types according to the driving mode of the liquid crystal, which is a twisted nematic (TN) or a super twisted nematic (Super Twisted).
  • TN twisted nematic
  • Super Twisted super twisted nematic
  • IPS mode is a mode in which liquid crystal molecules are driven to rotate in the plane of the substrate in response to an electric field substantially parallel to the substrate surface, and is used in various TV display applications because of its excellent viewing angle characteristics.
  • the structure of a conventional IPS type TFT-LCD array substrate includes a gate electrode 101 disposed on the substrate 100 and a gate insulating layer disposed on the gate electrode 101 and the substrate 100.
  • the line 110 is made of the same metal layer, and the pixel electrode 107 is connected to the drain electrode 105 through a via structure on the insulating protective layer 106.
  • An object of the present invention is to provide a method for fabricating an IPS type TFT-LCD array substrate.
  • the pixel electrode and the common electrode are made of the same transparent conductive layer, and the pixel electrode and the insulating protective layer under the common electrode are provided with several parallel lines.
  • a strip-shaped channel, the pixel electrode and the common electrode are alternately distributed along the land on both sides of the channel and extend to the sidewall of the channel, thereby increasing the area of the pixel electrode and the common electrode in a direction perpendicular to the substrate, and increasing the horizontal electric field Increase the storage capacitance and improve the display quality of the LCD panel.
  • Another object of the present invention is to provide an IPS type TFT-LCD array substrate, wherein the pixel electrode and the insulating protective layer under the common electrode are provided with a plurality of mutually parallel strip-shaped channels, and the pixel electrode and the common electrode are along both sides of the channel.
  • the bumps are alternately distributed and extend to the sidewalls of the channel, thereby increasing the area of the pixel electrode and the common electrode in a direction perpendicular to the substrate, increasing the horizontal electric field, increasing the storage capacitance, and thereby improving the display quality of the liquid crystal panel.
  • the present invention provides a method for fabricating an IPS type TFT-LCD array substrate, comprising the following steps:
  • Step 1 Providing a substrate, depositing a gate metal layer on the substrate, and depositing the gate metal The layer is patterned to obtain gate and gate scan lines;
  • Step 2 depositing a gate insulating layer on the gate metal layer, depositing an amorphous silicon layer on the gate insulating layer, and performing N-type doping on the amorphous silicon layer, and the amorphous silicon Performing a patterning process on the layer to obtain a semiconductor layer corresponding to the upper portion of the gate;
  • Step 3 depositing a source and drain metal layer on the semiconductor layer and the gate insulating layer, and patterning the source and drain metal layers to obtain a source, a drain, and a data line, the source The pole and the drain are respectively in contact with the two ends of the semiconductor layer; wherein the data line and the gate scan line enclose a plurality of pixel regions;
  • Step 4 forming an insulating protective layer on the source/drain metal layer, and patterning the insulating protective layer, forming a via corresponding to the drain over the insulating protective layer and located in the pixel region a plurality of mutually parallel strip-shaped channels;
  • Step 5 depositing a transparent conductive layer on the insulating protective layer, and patterning the transparent conductive layer to obtain a pixel electrode and a common electrode, wherein the pixel electrode is in contact with the drain through the via hole.
  • the pixel electrode is spaced apart from the common electrode.
  • the pixel electrode and the common electrode are alternately distributed along the land on both sides of the channel and extend to the sidewall of the channel.
  • the gate metal layer is deposited by physical vapor deposition, and the film thickness of the deposited gate metal layer is
  • the material of the gate metal layer is a stack combination of one or more of molybdenum, titanium, aluminum, copper; the step of patterning the gate metal layer includes photoresist coating and exposure sequentially , development, wet etching, and photoresist stripping.
  • a gate insulating layer and an amorphous silicon layer are deposited by plasma enhanced chemical vapor deposition, and the film thickness of the deposited gate insulating layer is The film thickness of the deposited amorphous silicon layer is The gate insulating layer is a silicon nitride layer, and the step of patterning the amorphous silicon layer includes photoresist coating, exposure, development, dry etching, and photoresist stripping which are sequentially performed.
  • the source and drain metal layers are deposited by physical vapor deposition, and the film thickness of the deposited source and drain metal layers is
  • the material of the source/drain metal layer is a stack combination of one or more of molybdenum, titanium, aluminum, and copper, and the step of patterning the source and drain metal layers includes sequentially performing photoresist coating , exposure, development, wet etching, and photoresist stripping.
  • the insulating protective layer 16 formed in the step 4 includes a silicon nitride layer and an organic film layer disposed on the silicon nitride layer; and the film thickness of the silicon nitride layer of the insulating protective layer 16 is Formed by a chemical vapor deposition method; the film thickness of the organic film layer of the insulating protective layer 16 is 0.2 to 0.4 ⁇ m, which is formed by a coating process; and the step of patterning the insulating protective layer includes sequentially performing photoresist Coating, exposure, development, dry etching, and photoresist stripping.
  • a transparent conductive layer is deposited by physical vapor deposition, and the film thickness of the deposited transparent conductive layer is
  • the transparent conductive layer is made of one or more of indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium antimony zinc oxide; and the transparent conductive layer is patterned.
  • the steps of the treatment include photoresist coating, exposure, development, wet etching, and photoresist stripping in sequence.
  • the present invention also provides an IPS type TFT-LCD array substrate, comprising: a substrate, a plurality of gate scan lines disposed on the substrate, a plurality of data lines, and a plurality of gate scan lines and a plurality of data lines Pixel cells arranged in a plurality of arrays interleaved with each other;
  • Each of the pixel units includes a gate formed on the substrate, a gate insulating layer formed on the gate and the substrate, a semiconductor layer corresponding to the gate and formed on the gate insulating layer, formed on the semiconductor layer, and the gate a source and a drain on the pole insulating layer, an insulating protective layer formed on the source, the drain, the semiconductor layer, and the gate insulating layer, and a pixel electrode and a common electrode formed on the insulating protective layer;
  • the source and the drain are respectively in contact with both ends of the semiconductor layer
  • a via hole is disposed on the insulating protection layer corresponding to the drain, and the pixel electrode is in contact with the drain through a via hole;
  • the insulating protection layer is provided with a plurality of mutually parallel strip-shaped channels in the range of the pixel unit;
  • the pixel electrode and the common electrode are obtained by patterning the same transparent conductive layer, and the pixel electrode is spaced apart from the common electrode. Within each pixel unit, the pixel electrode and the common electrode are along the both sides of the channel. Alternately distributed and extended to the sidewalls of the channel.
  • the material of the pixel electrode and the common electrode is a transparent conductive material, and the transparent conductive material is one of indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium antimony zinc oxide or a plurality of; the film thickness of the pixel electrode and the common electrode is
  • the material of the source/drain metal layer is a stack combination of one or more of molybdenum, titanium, aluminum, and copper, and the film thickness of the source/drain metal layer is
  • the insulating protective layer includes a silicon nitride layer and an organic film layer disposed on the silicon nitride layer, and a thickness of the silicon nitride layer of the insulating protective layer is The film thickness of the organic film layer of the insulating protective layer is 0.2 to 0.4 ⁇ m.
  • the present invention also provides an IPS type TFT-LCD array substrate, comprising: a substrate, a plurality of gate scan lines disposed on the substrate, a plurality of data lines, and a plurality of gate scan lines and a plurality of data lines Pixel cells arranged in a plurality of arrays interleaved with each other;
  • Each of the pixel units includes a gate formed on the substrate, a gate insulating layer formed on the gate and the substrate, a semiconductor layer corresponding to the gate and formed on the gate insulating layer, and formed on the semiconductor a source and a drain on the layer and the gate insulating layer, an insulating protective layer formed on the source, the drain, the semiconductor layer, and the gate insulating layer, and a pixel electrode formed on the insulating protective layer And a common electrode;
  • the source and the drain are respectively in contact with both ends of the semiconductor layer
  • a via hole is disposed on the insulating protection layer corresponding to the drain, and the pixel electrode is in contact with the drain through a via hole;
  • the insulating protection layer is provided with a plurality of mutually parallel strip-shaped channels in the range of the pixel unit;
  • the pixel electrode and the common electrode are obtained by patterning the same transparent conductive layer, and the pixel electrode is spaced apart from the common electrode. Within each pixel unit, the pixel electrode and the common electrode are along the both sides of the channel. Alternatingly distributed and extending to the sidewalls of the channel;
  • the material of the pixel electrode and the common electrode is a transparent conductive material
  • the transparent conductive material is one of indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium antimony zinc oxide. Or a plurality of; the film thickness of the pixel electrode and the common electrode is
  • the material of the source/drain metal layer is a stack combination of one or more of molybdenum, titanium, aluminum, and copper, and the film thickness of the source/drain metal layer is
  • the insulating protective layer includes a silicon nitride layer and an organic film layer disposed on the silicon nitride layer, and a thickness of the silicon nitride layer of the insulating protective layer is The film thickness of the organic film layer of the insulating protective layer is 0.2 to 0.4 ⁇ m.
  • the pixel electrode and the common electrode are formed by using the same transparent conductive layer, and the pixel electrode and the insulating protective layer under the common electrode are provided with a plurality of mutual Parallel strip-shaped channels, the pixel electrodes and the common electrodes are alternately distributed along the land on both sides of the channel and extend to the sidewalls of the channel, thereby increasing the area of the pixel electrode and the common electrode in a direction perpendicular to the substrate, The horizontal electric field is increased, and the storage capacitance is also increased, thereby improving the display quality of the liquid crystal panel.
  • the IPS type TFT-LCD array substrate of the present invention has the same layer design of the pixel electrode and the common electrode, and the pixel electrode and the common electrode.
  • the lower insulating protective layer is provided with a plurality of mutually parallel strip-shaped channels, and the pixel electrode and the common electrode are alternately distributed along the land on both sides of the channel and extend to the sidewall of the channel, thereby increasing the pixel electrode and
  • the area of the common electrode in the direction perpendicular to the substrate increases the horizontal electric field and also increases the storage capacitance, thereby improving the display quality of the liquid crystal panel.
  • FIG. 1 is a schematic structural view of a conventional IPS type TFT-LCD array substrate
  • FIG. 2 is a schematic flow chart of a method for fabricating an IPS type TFT-LCD array substrate according to the present invention
  • 3-4 is a schematic diagram of step 1 of a method for fabricating an IPS type TFT-LCD array substrate according to the present invention
  • 5-6 is a schematic diagram of step 2 of a method for fabricating an IPS type TFT-LCD array substrate according to the present invention
  • 7-8 is a schematic diagram of step 3 of a method for fabricating an IPS type TFT-LCD array substrate according to the present invention.
  • FIGS. 9-10 are schematic diagrams showing a step 4 of a method for fabricating an IPS type TFT-LCD array substrate according to the present invention.
  • step 5 is a schematic diagram of step 5 of a method for fabricating an IPS type TFT-LCD array substrate according to the present invention.
  • FIG. 12 is a schematic diagram of a pixel electrode and a common electrode formed in a pixel region in step 5 of the method for fabricating an IPS type TFT-LCD array substrate according to the present invention
  • FIG. 13 is a schematic view showing the step 5 of the method for fabricating the IPS type TFT-LCD array substrate of the present invention and the structure of the IPS type TFT-LCD array substrate of the present invention.
  • the present invention provides a method for fabricating an IPS type TFT-LCD array substrate, which includes the following steps:
  • Step 1 as shown in FIG. 3-4, a substrate 10 is provided, a gate metal layer is deposited on the substrate 10, and the gate metal layer is patterned to obtain a gate 11 and a gate scan line 20. .
  • the gate metal layer is deposited by a physical vapor deposition (PVD), and the deposited gate metal layer has a film thickness of
  • the material of the gate metal layer is a stack combination of one or more of molybdenum, titanium, aluminum, copper; the step of patterning the gate metal layer includes photoresist coating and exposure sequentially , development, wet etching, and photoresist stripping.
  • Step 2 depositing a gate insulating layer 12 on the gate metal layer, depositing an amorphous silicon layer on the gate insulating layer 12, and performing an N-type on the amorphous silicon layer. After doping, the amorphous silicon layer is patterned to obtain a semiconductor layer 13 corresponding to the upper portion of the gate.
  • the gate insulating layer 12 and the amorphous silicon layer are deposited by chemical vapor deposition (CVD), and the deposited gate insulating layer 12 has a film thickness of The film thickness of the deposited amorphous silicon layer is
  • the step of patterning the amorphous silicon layer includes photoresist coating, exposure, development, dry etching, and photoresist peeling which are sequentially performed.
  • the gate insulating layer 12 is a silicon nitride layer.
  • Step 3 depositing a source/drain metal layer on the semiconductor layer 13 and the gate insulating layer 12, and patterning the source and drain metal layers to obtain a source 14
  • the drain electrode 15 and the data line 30 are respectively in contact with both ends of the semiconductor layer 13; wherein the data line 30 and the gate scan line 20 surround a plurality of pixel regions.
  • the film thickness of the deposited source/drain metal layer is The material of the source/drain metal layer is a stack combination of one or more of molybdenum, titanium, aluminum, and copper, and the step of patterning the source and drain metal layers includes sequentially performing photoresist coating , exposure, development, wet etching, and photoresist stripping.
  • Step 4 as shown in FIG. 9-10, forming an insulating protective layer 16 on the source and drain metal layers, and patterning the insulating protective layer 16 to form corresponding to the insulating protective layer 16 A via 161 above the drain 15 and a plurality of mutually parallel strip-shaped channels 162 are located in the pixel region.
  • the insulating protective layer 16 formed in the step 4 includes a silicon nitride layer and an organic film layer disposed on the silicon nitride layer; and the film thickness of the silicon nitride layer of the insulating protective layer 16 is It is formed by a chemical vapor deposition method; the organic film layer of the insulating protective layer 16 has a film thickness of 0.2 to 0.4 ⁇ m and is formed by a coating process.
  • the organic film layer of the insulating protective layer 16 is used to increase the thickness of the insulating protective layer 16, thereby increasing the depth of the formed trench 162, thereby increasing the pixel electrode 17 and the common electrode 18 formed in the subsequent step 5.
  • the length extending over the sidewalls of the trench 162, in turn, increases the area of the pixel electrode 17 and the common electrode 18 in a direction perpendicular to the substrate.
  • the step of patterning the insulating protective layer 16 includes photoresist coating, exposure, development, dry etching, and photoresist stripping which are sequentially performed.
  • Step 5 depositing a transparent conductive layer on the insulating protective layer 16, and patterning the transparent conductive layer to obtain a pixel electrode 17 and a common electrode 18, the pixel
  • the electrode 17 is in contact with the drain 15 through the via 161.
  • the pixel electrode 17 is spaced apart from the common electrode 18.
  • the pixel electrode 17 and the common electrode 18 are along the land on both sides of the channel 162. Alternately distributed and extending to the sidewalls of the channel 162.
  • a transparent conductive layer is deposited by physical vapor deposition, and the film thickness of the deposited transparent conductive layer is
  • the transparent conductive layer is made of one or more of indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium antimony zinc oxide; and the transparent conductive layer is patterned.
  • the steps of the treatment include photoresist coating, exposure, development, wet etching, and photoresist stripping in sequence.
  • the material of the deposited transparent conductive layer is indium tin oxide (ITO).
  • the present invention further provides an IPS type TFT-LCD array substrate, comprising: a substrate 10, and a plurality of gate scan lines 20 disposed on the substrate 10, based on the above IPS type TFT-LCD array substrate manufacturing method. a plurality of data lines 30, and a plurality of arrays of pixel units arranged by insulating and interleaving between the plurality of gate scan lines 20 and the plurality of data lines 30;
  • Each of the pixel units includes a gate electrode 11 formed on the substrate 10, a gate insulating layer 12 formed on the gate electrode 11 and the substrate 10, and a semiconductor layer formed on the gate insulating layer 12 corresponding to the gate electrode 11. 13.
  • the pixel electrode 17 and the common electrode 18 formed on the insulating protective layer 16;
  • the source 14 and the drain 15 are respectively in contact with both ends of the semiconductor layer 13;
  • a via 161 is disposed on the insulating protective layer 16 corresponding to the drain 15 , and the pixel electrode 17 is in contact with the drain 15 through the via 161 ;
  • the insulating protective layer 16 is provided with a plurality of mutually parallel strip-shaped channels 162 located within the range of the pixel unit;
  • the pixel electrode 17 and the common electrode 18 are obtained by patterning the same transparent conductive layer, and the pixel electrode 17 is spaced apart from the common electrode 18. In the range of each pixel unit, the pixel electrode 17 and the common electrode 18 are along the trench. The bosses on both sides of the track 162 are alternately distributed and extend to the side walls of the channel 162.
  • the material of the pixel electrode 17 and the common electrode 18 is a transparent conductive material, and the transparent conductive material is indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium antimony zinc oxide.
  • the transparent conductive material is indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium antimony zinc oxide.
  • One or more of the films; the film thickness of the pixel electrode 17 and the common electrode 18 is
  • the material of the pixel electrode 17 and the common electrode 18 is indium tin oxide.
  • the material of the source/drain metal layer is a stack combination of one or more of molybdenum, titanium, aluminum, and copper, and the film thickness of the source/drain metal layer is
  • the insulating protective layer 16 includes a silicon nitride layer and an organic film layer disposed on the silicon nitride layer, and a thickness of the silicon nitride layer of the insulating protective layer 16 is The film thickness of the organic film layer of the insulating protective layer 16 is 0.2 to 0.4 ⁇ m.
  • the organic film layer of the insulating protective layer 16 is used to increase the thickness of the insulating protective layer 16, thereby increasing the depth of the formed trench 162, thereby increasing the pixel electrode 17 and the common electrode 18 formed in the subsequent step 5.
  • the method for fabricating the IPS type TFT-LCD array substrate of the present invention is that the pixel electrode and the common electrode are made of the same transparent conductive layer, and the pixel electrode and the insulating protective layer under the common electrode are provided with several parallel sides. a strip-shaped channel, the pixel electrode and the common electrode are alternately distributed along the land on both sides of the channel and extend to the sidewall of the channel, thereby increasing the area of the pixel electrode and the common electrode in a direction perpendicular to the substrate, increasing The horizontal electric field also increases the storage capacitance, thereby improving the display quality of the liquid crystal panel.
  • the pixel electrode and the common electrode are designed in the same layer, and the pixel electrode and the common electrode are under
  • the insulating protective layer is provided with a plurality of mutually parallel strip-shaped channels, and the pixel electrode and the common electrode are alternately distributed along the land on both sides of the channel and extend to the sidewall of the channel, thereby increasing the pixel electrode and the common
  • the area of the electrode in the direction perpendicular to the substrate increases the horizontal electric field and also increases the storage capacitance, thereby improving the display quality of the liquid crystal panel.

Abstract

一种TFT-LCD阵列基板的制作方法，将像素电极(17)和公共电极(18)采用同一透明导电层制得，且像素电极(17)和公共电极(18)下方的绝缘保护层(16)上设有数个相互平行的条状的沟道(162)，像素电极(17)与公共电极(18)沿沟道(162)两侧的凸台交替分布且延伸至沟道(162)的侧壁上，从而增大了像素电极(17)和公共电极(18)在垂直于基板方向的面积，增加了水平电场，同时也增大了存储电容，进而提高了液晶面板的显示质量。

Description

IPS型TFT-LCD阵列基板的制作方法及IPS型TFT-LCD阵列基板 技术领域
本发明涉及显示技术领域，尤其涉及一种IPS型TFT-LCD阵列基板的制作方法及IPS型TFT-LCD阵列基板。
背景技术
随着显示技术的发展，薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display，TFT-LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
现有市场上的液晶显示装置大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlight module)。液晶显示面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，两片玻璃基板中间有许多垂直和水平的细小电线，通过通电与否来控制液晶分子改变方向，将背光模组的光线折射出来产生画面。通常液晶显示面板由彩膜(CF，Color Filter)基板、阵列基板、夹于彩膜基板与阵列基板之间的液晶(LC，Liquid Crystal)及密封胶框(Sealant)组成，其成型工艺一般包括：前段阵列(Array)制程(薄膜、黄光、蚀刻及剥膜)、中段成盒(Cell)制程(阵列基板与CF基板贴合)及后段模组组装制程(驱动IC与印刷电路板压合)。其中，前段Array制程主要是形成阵列基板，以便于控制液晶分子的运动；中段Cell制程主要是在阵列基板与CF基板之间添加液晶；后段模组组装制程主要是驱动IC压合与印刷电路板的整合，进而驱动液晶分子转动，显示图像。
液晶面板的阵列基板上设置有数条扫描线、数条数据线、和数条公共电极走线，该数条扫描线和数条数据线限定出多个像素单元，每个像素单元内设置有薄膜晶体管和像素电极，薄膜晶体管的栅极与相应的栅线相连，当栅线上的电压达到开启电压时，薄膜晶体管的源极和漏极导通，从而将数据线上的数据电压输入至像素电极。
目前主流市场上的TFT-LCD，就液晶的驱动模式而言，可分为三种类型，分别是扭曲向列(Twisted Nematic，TN)或超扭曲向列(Super Twisted  Nematic，STN)型，面内转换(In-Plane Switching，IPS)型、及垂直配向(Vertical Alignment，VA)型。其中IPS模式是利用与基板面大致平行的电场驱动液晶分子沿基板面内转动以响应的模式，由于具有优异的视角特性，所以被用于各种TV显示用途当中。
在IPS模式中，通过像素电极或公共电极边缘所产生的平行电场以及像素电极与公共电极之间产生的纵向电场形成多维电场，使液晶盒内像素电极间或公共电极间、像素电极正上方或公共电极正上方所有取向的液晶分子都能够产生旋转转换，从而可提高平面取向系液晶的工作效率并增大透光效率。如图1所示，为传统的IPS型TFT-LCD阵列基板的结构，其上的每一像素单元包括设于基板100上的栅极101、设于栅极101及基板100上栅极绝缘层102、设于栅极绝缘层102上的半导体层103、设于半导体层103、及栅极绝缘层102上的源极104和漏极105、设于所述源极104、漏极105、半导体层103、及栅极绝缘层102上绝缘保护层106、及形成于所述绝缘保护层106上的像素电极107；且在该TFT阵列基板上，公共电极层120与栅极101和栅极扫描线110为同一金属层制得，像素电极107通过绝缘保护层106上的过孔结构连接到漏极105。
然而，随着技术的进步，消费者对电子产品的显示效果提出了更高的要求，人们不断追求显示器件具有更好的显示效果及更高的透过率。
发明内容
本发明的目的在于提供一种IPS型TFT-LCD阵列基板的制作方法，像素电极和公共电极采用同一透明导电层制得，且像素电极和公共电极下方的绝缘保护层上设有数个相互平行的条状的沟道，像素电极与公共电极沿沟道两侧的凸台交替分布且延伸至沟道的侧壁上，从而增大像素电极和公共电极在垂直于基板方向的面积，增加水平电场，增大存储电容，提高液晶面板的显示质量。
本发明的目的还在于提供一种IPS型TFT-LCD阵列基板，像素电极和公共电极下方的绝缘保护层上设有数个相互平行的条状的沟道，像素电极与公共电极沿沟道两侧的凸台交替分布且延伸至沟道的侧壁上，从而增大像素电极和公共电极在垂直于基板方向的面积，增加水平电场，增大存储电容，进而提高液晶面板的显示质量。
为实现上述目的，本发明提供一种IPS型TFT-LCD阵列基板的制作方法，包括如下步骤：
步骤1、提供基板，在所述基板上沉积栅极金属层，并对所述栅极金属 层进行图案化处理，得到栅极及栅极扫描线；
步骤2、在栅极金属层上沉积栅极绝缘层，在所述栅极绝缘层上沉积一层非晶硅层，并对非晶硅层进行N型掺杂后，对所述非晶硅层进行图案化处理，得到对应于所述栅极上方的半导体层；
步骤3、在所述半导体层、及栅极绝缘层上沉积源漏极金属层，并对所述源漏极金属层进行图案化处理，得到源极、漏极、及数据线，所述源极和漏极分别与所述半导体层的两端相接触；其中，数据线与栅极扫描线围出数个像素区域；
步骤4、在所述源漏极金属层上形成绝缘保护层，并对绝缘保护层进行图案化处理，在所述绝缘保护层上形成对应于所述漏极上方的过孔和位于像素区域内的数个相互平行的条状的沟道；
步骤5、在所述绝缘保护层上沉积一层透明导电层，并对所述透明导电层进行图案化处理，得到像素电极及公共电极，所述像素电极通过过孔与漏极相接触，所述像素电极与公共电极间隔设置，在每一像素区域内，所述像素电极与公共电极沿沟道两侧的凸台交替分布且延伸至沟道的侧壁上。
所述步骤1中通过物理气相沉积法沉积栅极金属层，所沉积的栅极金属层的膜厚为
Figure PCTCN2016074503-appb-000001
所述栅极金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；对所述栅极金属层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、湿法蚀刻、及光阻剥离。
所述步骤2中通过等离子体增强化学气相沉积法沉积栅极绝缘层和非晶硅层，所沉积的栅极绝缘层的膜厚为
Figure PCTCN2016074503-appb-000002
所沉积的非晶硅层的膜厚为
Figure PCTCN2016074503-appb-000003
所述栅极绝缘层为氮化硅层，对所述非晶硅层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、干法蚀刻、及光阻剥离。
所述步骤3中通过物理气相沉积法沉积源漏极金属层，所沉积的源漏极金属层的膜厚为
Figure PCTCN2016074503-appb-000004
所述源漏极金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合，对所述源漏极金属层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、湿法蚀刻、及光阻剥离。
所述步骤4中形成的绝缘保护层16包括氮化硅层、及设于氮化硅层上的有机膜层；所述绝缘保护层16的氮化硅层的膜厚为
Figure PCTCN2016074503-appb-000005
通过化学气相沉积法形成；所述绝缘保护层16的有机膜层的膜厚为0.2～0.4μm，通过涂布工艺形成；对所述绝缘保护层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、干法蚀刻、及光阻剥离。
所述步骤5中通过物理气相沉积法沉积透明导电层，所沉积透明导电层的膜厚为
Figure PCTCN2016074503-appb-000006
所述透明导电层的材料为铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物中的一种或多种；对所述透明导电层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、湿法蚀刻、及光阻剥离。
本发明还提供一种IPS型TFT-LCD阵列基板，包括：基板、设于所述基板上的数条栅极扫描线、数条数据线、及由数条栅极扫描线与数条数据线相互绝缘交错划分出的多个阵列排布的像素单元；
每一像素单元均包括形成于基板上的栅极、形成于栅极及基板上栅极绝缘层、对应于栅极上方且形成于栅极绝缘层上的半导体层、形成于半导体层、及栅极绝缘层上的源极和漏极、形成于所述源极、漏极、半导体层、及栅极绝缘层上绝缘保护层、及形成于所述绝缘保护层上的像素电极和公共电极；
所述源极、漏极分别与所述半导体层的两端相接触；
所述绝缘保护层上对应所述漏极的上方设有过孔，所述像素电极通过过孔与所述漏极相接触；
所述绝缘保护层上设有位于像素单元范围内的数个相互平行的条状的沟道；
所述像素电极与公共电极由同一透明导电层经图案化后得到，所述像素电极与公共电极间隔设置，每一像素单元范围内，所述像素电极与公共电极沿沟道两侧的凸台交替分布且延伸至沟道的侧壁上。
所述像素电极与公共电极的材料为透明导电材料，所述透明导电材料为铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物中的一种或多种；所述像素电极与公共电极的膜厚为
Figure PCTCN2016074503-appb-000007
所述源漏极金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合，所述源漏极金属层的膜厚为
Figure PCTCN2016074503-appb-000008
所述绝缘保护层包括氮化硅层、及设于氮化硅层上的有机膜层，所述绝缘保护层的氮化硅层的膜厚为
Figure PCTCN2016074503-appb-000009
所述绝缘保护层的有机膜层的膜厚为0.2～0.4μm。
本发明还提供一种IPS型TFT-LCD阵列基板，包括：基板、设于所述基板上的数条栅极扫描线、数条数据线、及由数条栅极扫描线与数条数据线相互绝缘交错划分出的多个阵列排布的像素单元；
每一像素单元包括形成于基板上的栅极、形成于栅极及基板上栅极绝缘层、对应于栅极上方且形成于栅极绝缘层上的半导体层、形成于半导体 层、及栅极绝缘层上的源极和漏极、形成于所述源极、漏极、半导体层、及栅极绝缘层上绝缘保护层、及形成于所述绝缘保护层上的像素电极和公共电极；
所述源极、漏极分别与所述半导体层的两端相接触；
所述绝缘保护层上对应所述漏极的上方设有过孔，所述像素电极通过过孔与所述漏极相接触；
所述绝缘保护层上设有位于像素单元范围内的数个相互平行的条状的沟道；
所述像素电极与公共电极由同一透明导电层经图案化后得到，所述像素电极与公共电极间隔设置，每一像素单元范围内，所述像素电极与公共电极沿沟道两侧的凸台交替分布且延伸至沟道的侧壁上；
其中，所述像素电极与公共电极的材料为透明导电材料，所述透明导电材料为铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物中的一种或多种；所述像素电极与公共电极的膜厚为
Figure PCTCN2016074503-appb-000010
其中，所述源漏极金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合，所述源漏极金属层的膜厚为
Figure PCTCN2016074503-appb-000011
其中，所述绝缘保护层包括氮化硅层、及设于氮化硅层上的有机膜层，所述绝缘保护层的氮化硅层的膜厚为
Figure PCTCN2016074503-appb-000012
所述绝缘保护层的有机膜层的膜厚为0.2～0.4μm。
本发明的有益效果：本发明的IPS型TFT-LCD阵列基板的制作方法，将像素电极和公共电极采用同一透明导电层制得，且像素电极和公共电极下方的绝缘保护层上设有数个相互平行的条状的沟道，像素电极与公共电极沿沟道两侧的凸台交替分布且延伸至沟道的侧壁上，从而增大了像素电极和公共电极在垂直于基板方向的面积，增加了水平电场，同时也增大了存储电容，进而提高了液晶面板的显示质量；本发明的IPS型TFT-LCD阵列基板，像素电极与公共电极采用同层的设计，且像素电极和公共电极下方的绝缘保护层上设有数个相互平行的条状的沟道，像素电极与公共电极沿沟道两侧的凸台交替分布且延伸至沟道的侧壁上，从而增大了像素电极和公共电极在垂直于基板方向的面积，增加了水平电场，同时也增大了存储电容，进而提高了液晶面板的显示质量。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发 明加以限制。
附图中，
图1为现有的IPS型TFT-LCD阵列基板的结构示意图；
图2为本发明的IPS型TFT-LCD阵列基板的制作方法的示意流程图；
图3-4为本发明的IPS型TFT-LCD阵列基板的制作方法的步骤1的示意图；
图5-6为本发明的IPS型TFT-LCD阵列基板的制作方法的步骤2的示意图；
图7-8为本发明的IPS型TFT-LCD阵列基板的制作方法的步骤3的示意图；
图9-10为本发明的IPS型TFT-LCD阵列基板的制作方法的步骤4的示意图；
图11为本发明的IPS型TFT-LCD阵列基板的制作方法的步骤5的示意图；
图12为本发明的IPS型TFT-LCD阵列基板的制作方法的步骤5中一像素区域内所形成的像素电极与公共电极的示意图；
图13为本发明的IPS型TFT-LCD阵列基板的制作方法的步骤5的示意图暨本发明的IPS型TFT-LCD阵列基板的结构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图2，本发明提供一种IPS型TFT-LCD阵列基板的制作方法，包括如下步骤：
步骤1、如图3-4所示，提供基板10，在所述基板10上沉积栅极金属层，并对所述栅极金属层进行图案化处理，得到栅极11及栅极扫描线20。
具体的，所述步骤1中通过物理气相沉积法(Physical Vapor Deposition，PVD)沉积栅极金属层，所沉积的栅极金属层的膜厚为
Figure PCTCN2016074503-appb-000013
所述栅极金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；对所述栅极金属层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、湿法蚀刻、及光阻剥离。
步骤2、如图5-6所示，在栅极金属层上沉积栅极绝缘层12，在所述栅极绝缘层12上沉积一层非晶硅层，并对非晶硅层进行N型掺杂后，对所述非晶硅层进行图案化处理，得到对应于栅极上方的半导体层13。
具体的，所述步骤2中通过化学气相沉积法(Chemical Vapor Deposition，CVD)沉积栅极绝缘层12和非晶硅层，所沉积的栅极绝缘层12的膜厚为
Figure PCTCN2016074503-appb-000014
所沉积的非晶硅层的膜厚为
Figure PCTCN2016074503-appb-000015
对所述非晶硅层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、干法蚀刻、及光阻剥离。
优选的，所述栅极绝缘层12为氮化硅层。
步骤3、如图7-8所示，在所述半导体层13、及栅极绝缘层12上沉积源漏极金属层，并对所述源漏极金属层进行图案化处理，得到源极14、漏极15、及数据线30，所述源极14和漏极15分别与所述半导体层13的两端相接触；其中，数据线30与栅极扫描线20围出数个像素区域。
具体的，所述步骤3中通过物理气相沉积法沉积的源漏极金属层，所沉积的源漏极金属层的膜厚为
Figure PCTCN2016074503-appb-000016
所述源漏极金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合，对所述源漏极金属层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、湿法蚀刻、及光阻剥离。
步骤4、如图9-10所示，在所述源漏极金属层上形成绝缘保护层16，并对绝缘保护层16进行图案化处理，在所述绝缘保护层16上形成对应于所述漏极15上方的过孔161和位于像素区域内的数个相互平行的条状的沟道162。
具体的，所述步骤4中形成的绝缘保护层16包括氮化硅层、及设于氮化硅层上的有机膜层；所述绝缘保护层16氮化硅层的膜厚为
Figure PCTCN2016074503-appb-000017
通过化学气相沉积法形成；所述绝缘保护层16的有机膜层的膜厚为0.2～0.4μm，通过涂布工艺形成。其中，所述绝缘保护层16的有机膜层用于增加绝缘保护层16的厚度，进而增加所形成的沟道162的深度，从而增加后续步骤5中所形成的像素电极17与公共电极18在沟道162的侧壁上延伸的长度，进而增加了像素电极17和公共电极18在垂直于基板方向的面积。
具体的，对所述绝缘保护层16进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、干法蚀刻、及光阻剥离。
步骤5、如图11-13所示，在所述绝缘保护层16上沉积一层透明导电层，并对所述透明导电层进行图案化处理，得到像素电极17及公共电极18，所述像素电极17通过过孔161与漏极15相接触，所述像素电极17与公共电极18间隔设置，在每一像素区域内，所述像素电极17与公共电极18沿沟道162两侧的凸台交替分布且延伸至沟道162的侧壁上。
具体的，所述步骤5中通过物理气相沉积法沉积透明导电层，所沉积 的透明导电层的膜厚为
Figure PCTCN2016074503-appb-000018
所述透明导电层的材料为铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物中的一种或多种；对所述透明导电层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、湿法蚀刻、及光阻剥离。
优选的，所沉积透明导电层的材料为铟锡氧化物(ITO)。
请参阅图13，基于以上IPS型TFT-LCD阵列基板的制作方法，本发明还提供一种IPS型TFT-LCD阵列基板，包括：基板10、设于基板10上的数条栅极扫描线20、数条数据线30、及由数条栅极扫描线20与数条数据线30相互绝缘交错划分出的多个阵列排布的像素单元；
每一像素单元均包括：形成于基板10上的栅极11、形成于栅极11及基板10上栅极绝缘层12、对应于栅极11上方且形成于栅极绝缘层12上的半导体层13、形成于半导体层13、及栅极绝缘层12上的源极14和漏极15、形成于所述源极14、漏极15、半导体层13、及栅极绝缘层12上绝缘保护层16、及形成于所述绝缘保护层16上的像素电极17和公共电极18；
所述源极14、漏极15分别与所述半导体层13的两端相接触；
所述绝缘保护层16上对应所述漏极15的上方设有过孔161，所述像素电极17通过过孔161与所述漏极15相接触；
所述绝缘保护层16上设有位于像素单元范围内的数个相互平行的条状的沟道162；
所述像素电极17与公共电极18由同一透明导电层经图案化后得到，所述像素电极17与公共电极18间隔设置，每一像素单元范围内，所述像素电极17与公共电极18沿沟道162两侧的凸台交替分布且延伸至沟道162的侧壁上。
具体的，所述像素电极17与公共电极18的材料为透明导电材料，所述透明导电材料为铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物中的一种或多种；所述像素电极17与公共电极18的膜厚为
Figure PCTCN2016074503-appb-000019
优选的，所述像素电极17与公共电极18的材料为铟锡氧化物。
具体的，所述源漏极金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合，所述源漏极金属层的膜厚为
Figure PCTCN2016074503-appb-000020
具体的，所述绝缘保护层16包括氮化硅层、及设于氮化硅层上的有机膜层，所述绝缘保护层16的氮化硅层的膜厚为
Figure PCTCN2016074503-appb-000021
所述绝缘保护层16的有机膜层的膜厚为0.2～0.4μm。其中，所述绝缘保护层16的有机膜层用于增加绝缘保护层16的厚度，进而增加所形成的沟道162的深 度，从而增加后续步骤5中所形成的像素电极17与公共电极18在沟道162的侧壁上延伸的长度，进而增加了像素电极17和公共电极18在垂直于基板方向的面积。
综上所述，本发明的IPS型TFT-LCD阵列基板的制作方法，将像素电极和公共电极采用同一透明导电层制得，且像素电极和公共电极下方的绝缘保护层上设有数个相互平行的条状的沟道，像素电极与公共电极沿沟道两侧的凸台交替分布且延伸至沟道的侧壁上，从而增大了像素电极和公共电极在垂直于基板方向的面积，增加了水平电场，同时也增大了存储电容，进而提高了液晶面板的显示质量；本发明的IPS型TFT-LCD阵列基板，像素电极与公共电极采用同层的设计，且像素电极和公共电极下方的绝缘保护层上设有数个相互平行的条状的沟道，像素电极与公共电极沿沟道两侧的凸台交替分布且延伸至沟道的侧壁上，从而增大了像素电极和公共电极在垂直于基板方向的面积，增加了水平电场，同时也增大了存储电容，进而提高了液晶面板的显示质量。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (11)

  1. 一种IPS型TFT-LCD阵列基板的制作方法，包括如下步骤：
    步骤1、提供基板，在所述基板上沉积栅极金属层，并对所述栅极金属层进行图案化处理，得到栅极及栅极扫描线；
    步骤2、在栅极金属层上沉积栅极绝缘层，所述栅极绝缘层上沉积一层非晶硅层，并对非晶硅层进行N型掺杂后，对所述非晶硅层进行图案化处理，得到对应于所述栅极上方的半导体层；
    步骤3、在所述半导体层、及栅极绝缘层上沉积源漏极金属层，并对所述源漏极金属层进行图案化处理，得到源极、漏极、及数据线，所述源极和漏极分别与所述半导体层的两端相接触；其中，数据线与栅极扫描线围出数个像素区域；
    步骤4、在所述源漏极金属层上形成绝缘保护层，并对绝缘保护层进行图案化处理，在所述绝缘保护层上形成对应于所述漏极上方的过孔和位于像素区域内的数个相互平行的条状的沟道；
    步骤5、在所述绝缘保护层上沉积一层透明导电层，并对所述透明导电层进行图案化处理，得到像素电极及公共电极，所述像素电极通过过孔与漏极相接触，所述像素电极与公共电极间隔设置，在每一像素区域内，所述像素电极与公共电极沿沟道两侧的凸台交替分布且延伸至沟道的侧壁上。
  2. 如权利要求1所述的IPS型TFT-LCD阵列基板的制作方法，其中，所述步骤1中通过物理气相沉积法沉积栅极金属层，所沉积的栅极金属层的膜厚为
    Figure PCTCN2016074503-appb-100001
    所述栅极金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；对所述栅极金属层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、湿法蚀刻、及光阻剥离。
  3. 如权利要求1所述的IPS型TFT-LCD阵列基板的制作方法，其中，所述步骤2中通过化学气相沉积法沉积栅极绝缘层和非晶硅层，所沉积的栅极绝缘层的膜厚为
    Figure PCTCN2016074503-appb-100002
    所沉积的非晶硅层的膜厚为
    Figure PCTCN2016074503-appb-100003
    所述栅极绝缘层为氮化硅层，对所述非晶硅层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、干法蚀刻、及光阻剥离。
  4. 如权利要求1所述的IPS型TFT-LCD阵列基板的制作方法，其中，所述步骤3中通过物理气相沉积法沉积源漏极金属层，所沉积的源漏极金属层的膜厚为
    Figure PCTCN2016074503-appb-100004
    所述源漏极金属层的材料为钼、钛、铝、铜中 的一种或多种的堆栈组合，对所述源漏极金属层进行图案化处理的步骤包括依次进行的光阻涂布、曝光显影、湿法蚀刻、及光阻剥离。
  5. 如权利要求1所述的IPS型TFT-LCD阵列基板的制作方法，其中，所述步骤4中形成的绝缘保护层包括氮化硅层、及设于氮化硅层上的有机膜层；所述绝缘保护层的氮化硅层的膜厚为
    Figure PCTCN2016074503-appb-100005
    通过化学气相沉积法形成；所述绝缘保护层的有机膜层的膜厚为0.2～0.4μm，通过涂布工艺形成；对所述绝缘保护层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、干法蚀刻、及光阻剥离。
  6. 如权利要求1所述的IPS型TFT-LCD阵列基板的制作方法，其中，所述步骤5中通过物理气相沉积法沉积透明导电层，所沉积透明导电层的膜厚为
    Figure PCTCN2016074503-appb-100006
    所述透明导电层的材料为铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物中的一种或多种；对所述透明导电层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、湿法蚀刻、及光阻剥离。
  7. 一种IPS型TFT-LCD阵列基板，包括：基板、设于所述基板上的数条栅极扫描线、数条数据线、及由数条栅极扫描线与数条数据线相互绝缘交错划分出的多个阵列排布的像素单元；
    每一像素单元包括形成于基板上的栅极、形成于栅极及基板上栅极绝缘层、对应于栅极上方且形成于栅极绝缘层上的半导体层、形成于半导体层、及栅极绝缘层上的源极和漏极、形成于所述源极、漏极、半导体层、及栅极绝缘层上绝缘保护层、及形成于所述绝缘保护层上的像素电极和公共电极；
    所述源极、漏极分别与所述半导体层的两端相接触；
    所述绝缘保护层上对应所述漏极的上方设有过孔，所述像素电极通过过孔与所述漏极相接触；
    所述绝缘保护层上设有位于像素单元范围内的数个相互平行的条状的沟道；
    所述像素电极与公共电极由同一透明导电层经图案化后得到，所述像素电极与公共电极间隔设置，每一像素单元范围内，所述像素电极与公共电极沿沟道两侧的凸台交替分布且延伸至沟道的侧壁上。
  8. 如权利要求7所述的IPS型TFT-LCD阵列基板，其中，所述像素电极与公共电极的材料为透明导电材料，所述透明导电材料为铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物中的一种或多种；所述像素电极与公共电极的膜厚为
    Figure PCTCN2016074503-appb-100007
  9. 如权利要求7所述的IPS型TFT-LCD阵列基板，其中，所述源漏极金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合，所述源漏极金属层的膜厚为
    Figure PCTCN2016074503-appb-100008
  10. 如权利要求7所述的IPS型TFT-LCD阵列基板，其中，所述绝缘保护层包括氮化硅层、及设于氮化硅层上的有机膜层，所述绝缘保护层的氮化硅层的膜厚为
    Figure PCTCN2016074503-appb-100009
    所述绝缘保护层的有机膜层的膜厚为0.2～0.4μm。
  11. 一种IPS型TFT-LCD阵列基板，包括：基板、设于所述基板上的数条栅极扫描线、数条数据线、及由数条栅极扫描线与数条数据线相互绝缘交错划分出的多个阵列排布的像素单元；
    每一像素单元包括形成于基板上的栅极、形成于栅极及基板上栅极绝缘层、对应于栅极上方且形成于栅极绝缘层上的半导体层、形成于半导体层、及栅极绝缘层上的源极和漏极、形成于所述源极、漏极、半导体层、及栅极绝缘层上绝缘保护层、及形成于所述绝缘保护层上的像素电极和公共电极；
    所述源极、漏极分别与所述半导体层的两端相接触；
    所述绝缘保护层上对应所述漏极的上方设有过孔，所述像素电极通过过孔与所述漏极相接触；
    所述绝缘保护层上设有位于像素单元范围内的数个相互平行的条状的沟道；
    所述像素电极与公共电极由同一透明导电层经图案化后得到，所述像素电极与公共电极间隔设置，每一像素单元范围内，所述像素电极与公共电极沿沟道两侧的凸台交替分布且延伸至沟道的侧壁上；
    其中，所述像素电极与公共电极的材料为透明导电材料，所述透明导电材料为铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物中的一种或多种；所述像素电极与公共电极的膜厚为
    Figure PCTCN2016074503-appb-100010
    其中，所述源漏极金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合，所述源漏极金属层的膜厚为
    Figure PCTCN2016074503-appb-100011
    其中，所述绝缘保护层包括氮化硅层、及设于氮化硅层上的有机膜层，所述绝缘保护层的氮化硅层的膜厚为
    Figure PCTCN2016074503-appb-100012
    所述绝缘保护层的有机膜层的膜厚为0.2～0.4μm。
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