WO2017121008A1 - Ips型tft-lcd阵列基板的制作方法及ips型tft-lcd阵列基板 - Google Patents

Ips型tft-lcd阵列基板的制作方法及ips型tft-lcd阵列基板 Download PDF

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Publication number
WO2017121008A1
WO2017121008A1 PCT/CN2016/074502 CN2016074502W WO2017121008A1 WO 2017121008 A1 WO2017121008 A1 WO 2017121008A1 CN 2016074502 W CN2016074502 W CN 2016074502W WO 2017121008 A1 WO2017121008 A1 WO 2017121008A1
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layer
gate
source
common electrode
deposited
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PCT/CN2016/074502
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English (en)
French (fr)
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徐向阳
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深圳市华星光电技术有限公司
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Priority to US15/026,253 priority Critical patent/US10310338B2/en
Publication of WO2017121008A1 publication Critical patent/WO2017121008A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
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Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating an IPS type TFT-LCD array substrate and an IPS type TFT-LCD array substrate.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • liquid crystal display devices which include a liquid crystal display panel and a backlight module.
  • the working principle of the liquid crystal display panel is to place liquid crystal molecules in two parallel glass substrates. There are many vertical and horizontal small wires between the two glass substrates, and the liquid crystal molecules are controlled to change direction by energizing or not, and the light of the backlight module is changed. Refracted to produce a picture.
  • the liquid crystal display panel is composed of a CF (Color Filter) substrate, an array substrate, a liquid crystal (LC) sandwiched between the color filter substrate and the array substrate, and a sealant frame (Sealant), and the molding process generally includes : Array process (film, yellow light, etching and stripping), middle cell (Cell process) (array substrate and CF substrate) and rear module assembly process (drive IC and printed circuit board voltage) Combined).
  • the front Array process mainly forms an array substrate to control the movement of the liquid crystal molecules;
  • the middle Cell process mainly adds liquid crystal between the array substrate and the CF substrate;
  • the rear module assembly process is mainly to drive the IC to press and print the circuit.
  • the integration of the plates drives the liquid crystal molecules to rotate and display images.
  • the array substrate of the TFT-LCD is provided with a plurality of scan lines, a plurality of data lines, and a plurality of common electrode traces, wherein the plurality of scan lines and the plurality of data lines define a plurality of pixel units, and each of the pixel units is disposed a thin film transistor and a pixel electrode, the gate of the thin film transistor is connected to the corresponding gate line.
  • the voltage on the gate line reaches the turn-on voltage, the source and the drain of the thin film transistor are turned on, thereby inputting the data voltage on the data line to Pixel electrode.
  • the TFT-LCD in the mainstream market can be divided into three types according to the driving mode of the liquid crystal, which is a twisted nematic (TN) or a super twisted nematic (Super Twisted).
  • TN twisted nematic
  • Super Twisted super twisted nematic
  • IPS mode is a mode in which liquid crystal molecules are driven to rotate in the plane of the substrate in response to an electric field substantially parallel to the substrate surface, and is used in various TV display applications because of its excellent viewing angle characteristics.
  • Each pixel unit on the substrate includes a gate electrode 101 disposed on the substrate 100, and a gate insulating layer disposed on the gate electrode 101 and the substrate 100.
  • the common electrode layer 120 and the gate electrode 101 and the gate scan line 110 is made of the same metal layer, and the pixel electrode 107 is connected to the drain electrode 105 through a via structure on the insulating protective layer 106, and since the impedance between the pixel electrode 107 and the drain electrode 105 affects the charging efficiency of the pixel electrode 107, If the impedance is too large, the pixel electrode 107 cannot be charged to a desired voltage within one scan time, thereby affecting the display effect. There are many factors that affect the contact resistance of the via, such as the interface electron barrier height, the via size, and the via overlap.
  • An object of the present invention is to provide a method for fabricating an IPS type TFT-LCD array substrate, which is formed by using the same metal layer as the pixel electrode and the drain, using a transparent conductive material for the common electrode, and connecting the common electrode trace through the via hole. , thereby improving the charging efficiency of the pixel electrode.
  • the object of the present invention is to provide an IPS type TFT-LCD array substrate, wherein the pixel electrode and the drain belong to the same metal layer, the common electrode adopts a transparent conductive material, and is connected with the common electrode trace through the via hole, and the charging efficiency of the pixel electrode high.
  • the present invention provides a method for fabricating an IPS type TFT-LCD array substrate, comprising the following steps:
  • Step 1 providing a substrate, depositing a gate metal layer on the substrate, and patterning the gate metal layer to obtain a gate, a common electrode trace, and a gate scan line;
  • Step 2 depositing a gate insulating layer on the gate metal layer, depositing an amorphous silicon layer on the gate insulating layer, and performing N-type doping on the amorphous silicon layer, and the amorphous silicon
  • the layer is patterned to obtain a semiconductor layer corresponding to the upper portion of the gate;
  • Step 3 depositing a source/drain metal layer on the semiconductor layer and the gate insulating layer, and patterning the source and drain metal layers to obtain a source, a drain, a pixel electrode, and a data line.
  • the source and the drain are respectively in contact with both ends of the semiconductor layer;
  • Step 4 depositing an insulating protective layer on the source and drain metal layers, and patterning the insulating protective layer and the gate insulating layer, forming corresponding to the common on the insulating protective layer and the gate insulating layer a via above the electrode trace;
  • Step 5 depositing a transparent conductive layer on the insulating protective layer, and patterning the transparent conductive layer to obtain a common electrode, and the common electrode is in contact with the common electrode trace through the via hole.
  • the gate metal layer is deposited by physical vapor deposition, and the film thickness of the deposited gate metal layer is
  • the material of the gate metal layer is a stack combination of one or more of molybdenum, titanium, aluminum, copper; the step of patterning the gate metal layer includes photoresist coating and exposure sequentially Development, wet etching, and photoresist stripping.
  • a gate insulating layer and an amorphous silicon layer are deposited by a chemical vapor deposition method, and a film thickness of the deposited gate insulating layer is The film thickness of the deposited amorphous silicon layer is The gate insulating layer is a silicon nitride layer, and the step of patterning the amorphous silicon layer includes photoresist coating, exposure, development, dry etching, and photoresist stripping which are sequentially performed.
  • the source and drain metal layers are deposited by physical vapor deposition, and the film thickness of the deposited source and drain metal layers is
  • the material of the source/drain metal layer is a stack combination of one or more of molybdenum, titanium, aluminum, and copper, and the step of patterning the source and drain metal layers includes sequentially performing photoresist coating , exposure, development, wet etching, and photoresist stripping.
  • an insulating protective layer is deposited by chemical vapor deposition, and the deposited insulating protective layer has a film thickness of
  • the insulating protective layer is a silicon nitride layer
  • the step of patterning the insulating protective layer and the gate insulating layer comprises sequential photoresist coating, exposure, development, dry etching, and light Resistance to peeling.
  • a transparent conductive layer is deposited by physical vapor deposition, and the film thickness of the deposited transparent conductive layer is
  • the transparent conductive layer is made of one or more of indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium antimony zinc oxide; and the transparent conductive layer is patterned.
  • the steps of the treatment include photoresist coating, exposure, development, wet etching, and photoresist stripping in sequence.
  • the present invention also provides an IPS type TFT-LCD array substrate, comprising: a substrate, a plurality of gate scan lines disposed on the substrate, a plurality of data lines, a plurality of common electrode traces, and a plurality of gate electrodes a scanning unit and a plurality of data lines are insulated and interleaved by a plurality of pixel units arranged in an array;
  • Each of the pixel units includes: a gate formed on the substrate, a gate insulating layer formed on the gate and the substrate, a semiconductor layer corresponding to the gate and formed on the gate insulating layer, formed on the semiconductor layer, and the gate a source, a drain, and a pixel electrode on the insulating layer, an insulating protective layer formed on the source, the drain, the pixel electrode, the semiconductor layer, and the gate insulating layer, and formed on the insulating layer a common electrode on the sheath;
  • the pixel electrode, the source, the drain, and the data line are obtained by patterning a source/drain metal layer, and the common electrode trace and the gate and gate scan lines are patterned by a gate metal layer get;
  • a via hole is disposed on the insulating protective layer and the gate insulating layer corresponding to the common electrode trace, and the common electrode is in contact with the common electrode trace through the via hole;
  • the source and the drain are respectively in contact with both ends of the semiconductor layer.
  • the material of the common electrode is a transparent conductive material, and the transparent conductive material is one or more of indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium antimony zinc oxide;
  • the film thickness of the common electrode is
  • the material of the source/drain metal layer is a stack combination of one or more of molybdenum, titanium, aluminum, and copper, and the film thickness of the source/drain metal layer is
  • the present invention also provides a method for fabricating an IPS type TFT-LCD array substrate, comprising the following steps:
  • Step 1 providing a substrate, depositing a gate metal layer on the substrate, and patterning the gate metal layer to obtain a gate, a common electrode trace, and a gate scan line;
  • Step 2 depositing a gate insulating layer on the gate metal layer, depositing an amorphous silicon layer on the gate insulating layer, and performing N-type doping on the amorphous silicon layer, and the amorphous silicon
  • the layer is patterned to obtain a semiconductor layer corresponding to the upper portion of the gate;
  • Step 3 depositing a source/drain metal layer on the semiconductor layer and the gate insulating layer, and patterning the source and drain metal layers to obtain a source, a drain, a pixel electrode, and a data line.
  • the source and the drain are respectively in contact with both ends of the semiconductor layer;
  • Step 4 depositing an insulating protective layer on the source and drain metal layers, and patterning the insulating protective layer and the gate insulating layer, forming corresponding to the common on the insulating protective layer and the gate insulating layer a via above the electrode trace;
  • Step 5 depositing a transparent conductive layer on the insulating protective layer, and patterning the transparent conductive layer to obtain a common electrode, wherein the common electrode is in contact with the common electrode trace through the via hole;
  • the gate metal layer is deposited by physical vapor deposition, and the film thickness of the deposited gate metal layer is
  • the material of the gate metal layer is a stack combination of one or more of molybdenum, titanium, aluminum, copper;
  • the step of patterning the gate metal layer includes photoresist coating and exposure sequentially , development, wet etching, and photoresist stripping;
  • the gate insulating layer and the amorphous silicon layer are deposited by chemical vapor deposition, and the film thickness of the deposited gate insulating layer is The film thickness of the deposited amorphous silicon layer is The gate insulating layer is a silicon nitride layer, and the step of patterning the amorphous silicon layer includes photoresist coating, exposure development, dry etching, and photoresist stripping;
  • the source and drain metal layers are deposited by physical vapor deposition, and the film thickness of the deposited source and drain metal layers is
  • the material of the source/drain metal layer is a stack combination of one or more of molybdenum, titanium, aluminum, and copper, and the step of patterning the source and drain metal layers includes sequentially performing photoresist coating , exposure, development, wet etching, and photoresist stripping;
  • the insulating protective layer is deposited by chemical vapor deposition, and the deposited insulating protective layer has a film thickness of
  • the insulating protective layer is a silicon nitride layer
  • the step of patterning the insulating protective layer and the gate insulating layer comprises sequential photoresist coating, exposure, development, dry etching, and light Resistance peeling
  • the transparent conductive layer is deposited by physical vapor deposition, and the film thickness of the deposited transparent conductive layer is
  • the transparent conductive layer is made of one or more of indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium antimony zinc oxide; and the transparent conductive layer is patterned.
  • the steps of the treatment include photoresist coating, exposure, development, wet etching, and photoresist stripping in sequence.
  • the invention has the beneficial effects that the IPS type TFT-LCD array substrate of the invention is prepared by using the same layer of metal as the common electrode trace and the gate, and the pixel electrode and the drain are made of the same layer of metal, and are insulated. Forming a via hole corresponding to the upper surface of the common electrode trace on the protective layer and the gate insulating layer, forming a common electrode of a transparent conductive material on the insulating protective layer, so that the common electrode contacts the common electrode trace through the via hole Therefore, the charging efficiency of the pixel electrode can be improved.
  • the pixel electrode and the drain are made of the same layer of metal, and the common electrode trace and the gate are made of the same metal layer, and the common electrode is formed.
  • the transparent conductive material is located on the insulating protective layer, and the common electrode is in contact with the common electrode trace through the insulating protective layer and the via hole on the gate insulating layer, and the charging efficiency of the pixel electrode is high, and the display of the IPS type liquid crystal display panel can be improved. effect.
  • FIG. 1 is a schematic structural view of a conventional IPS type TFT-LCD array substrate
  • FIG. 2 is a schematic flow chart of a method for fabricating an IPS type TFT-LCD array substrate according to the present invention
  • FIG. 3 is a schematic diagram of step 1 of a method for fabricating an IPS type TFT-LCD array substrate of the present invention.
  • step 2 is a schematic diagram of step 2 of a method for fabricating an IPS type TFT-LCD array substrate according to the present invention
  • step 3 is a schematic diagram of step 3 of a method for fabricating an IPS type TFT-LCD array substrate according to the present invention
  • FIG. 6 is a schematic diagram of step 4 of a method for fabricating an IPS type TFT-LCD array substrate according to the present invention.
  • FIG. 7 is a schematic view showing the step 5 of the method for fabricating the IPS type TFT-LCD array substrate of the present invention and the structure of the IPS type TFT-LCD array substrate of the present invention.
  • the present invention provides a method for fabricating an IPS type TFT-LCD array substrate, which includes the following steps:
  • Step 1 as shown in FIG. 3, providing a substrate 10, depositing a gate metal layer on the substrate 10, and patterning the gate metal layer to obtain a gate electrode 11, a common electrode trace 20, and Gate scan line 30;
  • the gate metal layer is deposited by a physical vapor deposition (PVD), and the deposited gate metal layer has a film thickness of
  • the material of the gate metal layer is a stack combination of one or more of molybdenum, titanium, aluminum, copper; the step of patterning the gate metal layer includes photoresist coating and exposure sequentially , development, wet etching, and photoresist stripping.
  • Step 2 depositing a gate insulating layer 12 on the gate metal layer, depositing an amorphous silicon layer on the gate insulating layer 12, and performing N-type doping on the amorphous silicon layer. Afterwards, the amorphous silicon layer is patterned to obtain a semiconductor layer 13 corresponding to the upper portion of the gate electrode 11;
  • the gate insulating layer 12 and the amorphous silicon layer are deposited by chemical vapor deposition (CVD), and the deposited gate insulating layer 12 has a film thickness of The film thickness of the deposited amorphous silicon layer is
  • the step of patterning the amorphous silicon layer includes photoresist coating, exposure, development, dry etching, and photoresist peeling which are sequentially performed;
  • the gate insulating layer 12 is a silicon nitride layer.
  • Step 3 depositing a source/drain metal layer on the semiconductor layer 13 and the gate insulating layer 12, and patterning the source and drain metal layers to obtain a source electrode 14 and a drain electrode. Extreme 15.
  • the pixel electrode 16 and the data line, the source 14 and the drain 15 are respectively in contact with both ends of the semiconductor layer 13;
  • the source and drain metal layers are deposited by physical vapor deposition, and the film thickness of the deposited source and drain metal layers is
  • the material of the source/drain metal layer is a stack combination of one or more of molybdenum, titanium, aluminum, and copper
  • the step of patterning the source and drain metal layers includes sequentially performing photoresist coating , exposure, development, wet etching, and photoresist stripping.
  • Step 4 depositing an insulating protective layer 17 on the source/drain metal layer, and patterning the insulating protective layer 17 and the gate insulating layer 12 on the insulating protective layer 17 and the gate. Forming a via 201 above the common electrode trace 20 on the pole insulating layer 12;
  • the insulating protective layer 17 is deposited by chemical vapor deposition, and the deposited insulating protective layer 17 has a film thickness of
  • the step of patterning the insulating protective layer 17 and the gate insulating layer 12 includes photoresist coating, exposure development, dry etching, and photoresist stripping which are sequentially performed;
  • the insulating protective layer 17 is a silicon nitride layer.
  • Step 5 As shown in FIG. 7, a transparent conductive layer is deposited on the insulating protective layer 17, and the transparent conductive layer is patterned to obtain a common electrode 21, and the common electrode 21 passes through the via 201. Contact with the common electrode trace 20.
  • a transparent conductive layer is deposited by physical vapor deposition, and the film thickness of the deposited transparent conductive layer is
  • the material of the transparent conductive layer is one or more of indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium antimony zinc oxide;
  • the material of the deposited transparent conductive layer is indium tin oxide (ITO);
  • the step of patterning the transparent conductive layer includes photoresist coating, exposure, development, wet etching, and photoresist stripping which are sequentially performed.
  • the present invention further provides an IPS type TFT-LCD array substrate, including: a substrate 10 and a plurality of gate scans disposed on the substrate 10 , based on the above IPS type TFT-LCD array substrate manufacturing method. a line 30, a plurality of data lines (not shown), a plurality of common electrode traces 20, and a plurality of arrays of pixel units arranged by insulating and interleaving between the plurality of gate scan lines and the plurality of data lines;
  • Each of the pixel units includes a gate electrode 11 formed on the substrate 10, a gate insulating layer 12 formed on the gate electrode 11 and the substrate 10, and a semiconductor layer formed on the gate insulating layer 12 corresponding to the gate electrode 11. 13.
  • the source electrode 14 , the drain electrode 15 , and the pixel electrode 16 formed on the semiconductor layer 13 and the gate insulating layer 12 are formed on the source electrode 14 , the drain electrode 15 , the pixel electrode 16 , the semiconductor layer 13 , and the gate electrode
  • the pixel electrode 16, the source 14, the drain 15 and the data line are obtained by patterning a source/drain metal layer, and the common electrode trace 20 and the gate 11 and the gate scan line 30 are gated.
  • the metal layer is obtained by patterning;
  • a via 201 is disposed on the insulating protective layer 17 and the gate insulating layer 12 corresponding to the common electrode trace 20, and the common electrode 21 is in contact with the common electrode trace 20 through the via 201;
  • the source 14 and the drain 15 are in contact with both ends of the semiconductor layer 13, respectively.
  • the material of the common electrode 21 is a transparent conductive material, and the transparent conductive material is one of indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium antimony zinc oxide. Or a plurality of; the film thickness of the common electrode 21 is
  • the material of the common electrode 21 is indium tin oxide.
  • the material of the source/drain metal layer is a stack combination of one or more of molybdenum, titanium, aluminum, and copper, and the film thickness of the source/drain metal layer is
  • the method for fabricating the IPS type TFT-LCD array substrate of the present invention is that the common electrode trace and the gate are made of the same layer of metal, and the pixel electrode and the drain are made of the same layer of metal, and the insulation protection is performed. Forming a via hole corresponding to the upper surface of the common electrode trace on the layer and the gate insulating layer, forming a common electrode of a transparent conductive material on the insulating protective layer, so that the common electrode contacts the common electrode trace through the via hole, Therefore, the charging efficiency of the pixel electrode can be improved.
  • the pixel electrode and the drain are made of the same layer of metal, and the common electrode trace and the gate are made of the same metal layer, and the common electrode is
  • the transparent conductive material is located on the insulating protective layer, and the common electrode is in contact with the common electrode trace through the insulating protective layer and the via hole on the gate insulating layer, and the charging efficiency of the pixel electrode is high, and the display effect of the IPS type liquid crystal display panel can be improved.

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Abstract

一种IPS型TFT-LCD阵列基板的制作方法及IPS型TFT-LCD阵列基板。IPS型TFT-LCD阵列基板的制作方法，将公共电极走线(20)与栅极(11)采用同层金属制得，将像素电极(16)与漏极(15)采用同层金属制得，在绝缘保护层(17)及栅极绝缘层(12)上形成对应于所述公共电极走线(20)上方的过孔(201)，在所述绝缘保护层(17)上形成透明导电材料的公共电极(21)，使公共电极(21)通过过孔(201)与公共电极走线(20)相接触，从而能够提升像素电极(16)的充电效率；TFT阵列基板中，像素电极(16)与漏极(15)采用同层金属制得，公共电极走线(20)与栅极(11)采用同一层金属层制得，公共电极(21)为透明导电材料并位于绝缘保护层(17)上，公共电极(21)通过绝缘保护层(17)及栅极绝缘层(12)上的过孔(201)与公共电极走线(20)相接触，像素电极(16)的充电效率高，能够提高IPS型液晶显示面板的显示效果。

Description

IPS型TFT-LCD阵列基板的制作方法及IPS型TFT-LCD阵列基板 技术领域
本发明涉及显示技术领域，尤其涉及一种IPS型TFT-LCD阵列基板的制作方法及IPS型TFT-LCD阵列基板。
背景技术
随着显示技术的发展，薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display，TFT-LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
现有市场上的液晶显示装置大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlight module)。液晶显示面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，两片玻璃基板中间有许多垂直和水平的细小电线，通过通电与否来控制液晶分子改变方向，将背光模组的光线折射出来产生画面。通常液晶显示面板由彩膜(CF，Color Filter)基板、阵列基板、夹于彩膜基板与阵列基板之间的液晶(LC，Liquid Crystal)及密封胶框(Sealant)组成，其成型工艺一般包括：前段阵列(Array)制程(薄膜、黄光、蚀刻及剥膜)、中段成盒(Cell)制程(阵列基板与CF基板贴合)及后段模组组装制程(驱动IC与印刷电路板压合)。其中，前段Array制程主要是形成阵列基板，以便于控制液晶分子的运动；中段Cell制程主要是在阵列基板与CF基板之间添加液晶；后段模组组装制程主要是驱动IC压合与印刷电路板的整合，进而驱动液晶分子转动，显示图像。TFT-LCD的阵列基板上设置有数条扫描线、数条数据线、和数条公共电极走线，该数条扫描线和数条数据线限定出多个像素单元，每个像素单元内设置有薄膜晶体管和像素电极，薄膜晶体管的栅极与相应的栅线相连，当栅线上的电压达到开启电压时，薄膜晶体管的源极和漏极导通，从而将数据线上的数据电压输入至像素电极。
目前主流市场上的TFT-LCD，就液晶的驱动模式而言，可分为三种类型，分别是扭曲向列(Twisted Nematic，TN)或超扭曲向列(Super Twisted  Nematic，STN)型，面内转换(In-Plane Switching，IPS)型、及垂直配向(Vertical Alignment，VA)型。其中IPS模式是利用与基板面大致平行的电场驱动液晶分子沿基板面内转动以响应的模式，由于具有优异的视角特性，所以被用于各种TV显示用途当中。
现有的IPS型TFT-LCD的阵列基板的结构如图1所示，其上的每一像素单元包括设于基板100上的栅极101、设于栅极101及基板100上栅极绝缘层102、设于栅极绝缘层102上的半导体层103、设于半导体层103、及栅极绝缘层102上的源极104和漏极105、设于所述源极104、漏极105、半导体层103、及栅极绝缘层102上绝缘保护层106、及形成于所述绝缘保护层106上的像素电极107；且在该阵列基板上，公共电极层120与栅极101和栅极扫描线110为同一金属层制得，像素电极107通过绝缘保护层106上的过孔结构连接到漏极105，而由于像素电极107与漏极105之间的阻抗会影响到像素电极107的充电效率，如果阻抗过大会使得像素电极107无法在一行的扫描时间内充电到理想的电压，进而影响显示效果。影响过孔接触阻抗的因素很多，如界面电子势垒高度、过孔大小以及过孔重叠(overlap)。
发明内容
本发明的目的在于提供一种IPS型TFT-LCD阵列基板的制作方法，将像素电极与漏极采用同一金属层制作得到，将公共电极采用透明导电材料，并与公共电极走线通过过孔连接，从而提升像素电极的充电效率。
本发明的目的还在于提供一种IPS型TFT-LCD阵列基板，像素电极与漏极属于同一金属层，公共电极采用透明导电材料，并与公共电极走线通过过孔连接，像素电极的充电效率高。
为实现上述目的，本发明提供一种IPS型TFT-LCD阵列基板的制作方法，包括如下步骤：
步骤1、提供基板，在所述基板上沉积栅极金属层，并对所述栅极金属层进行图案化处理，得到栅极、公共电极走线、及栅极扫描线；
步骤2、在栅极金属层上沉积栅极绝缘层，在所述栅极绝缘层上沉积一层非晶硅层，并对非晶硅层进行N型掺杂后，对所述非晶硅层进行图案化处理，得到对应于栅极上方的半导体层；
步骤3、在所述半导体层、及栅极绝缘层上沉积源漏极金属层，并对所述源漏极金属层进行图案化处理，得到源极、漏极、像素电极、及数据线，所述源极和漏极分别与所述半导体层的两端相接触；
步骤4、在所述源漏极金属层上沉积绝缘保护层，并对绝缘保护层及栅极绝缘层进行图案化处理，在所述绝缘保护层及栅极绝缘层上形成对应于所述公共电极走线上方的过孔；
步骤5、在所述绝缘保护层上沉积一层透明导电层，并对所述透明导电层进行图案化处理，得到公共电极，所述公共电极通过过孔与公共电极走线相接触。
所述步骤1中通过物理气相沉积法沉积栅极金属层，所沉积的栅极金属层的膜厚为
Figure PCTCN2016074502-appb-000001
所述栅极金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；对所述栅极金属层进行图案化处理的步骤包括依次进行的光阻涂布、曝光显影、湿法蚀刻、及光阻剥离。
所述步骤2中通过化学气相沉积法沉积栅极绝缘层和非晶硅层，所沉积的栅极绝缘层的膜厚为
Figure PCTCN2016074502-appb-000002
所沉积的非晶硅层的膜厚为
Figure PCTCN2016074502-appb-000003
所述栅极绝缘层为氮化硅层，对所述非晶硅层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、干法蚀刻、及光阻剥离。
所述步骤3中通过物理气相沉积法沉积源漏极金属层，所沉积的源漏极金属层的膜厚为
Figure PCTCN2016074502-appb-000004
所述源漏极金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合，对所述源漏极金属层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、湿法蚀刻、及光阻剥离。
所述步骤4中通过化学气相沉积法沉积绝缘保护层，所沉积的绝缘保护层为膜厚为
Figure PCTCN2016074502-appb-000005
的，所述的绝缘保护层为氮化硅层，对所述绝缘保护层及栅极绝缘层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、干法蚀刻、及光阻剥离。
所述步骤5中通过物理气相沉积法沉积透明导电层，所沉积透明导电层的膜厚为
Figure PCTCN2016074502-appb-000006
所述透明导电层的材料为铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物中的一种或多种；对所述透明导电层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、湿法蚀刻、及光阻剥离。
本发明还提供一种IPS型TFT-LCD阵列基板，包括：基板、设于所述基板上的数条栅极扫描线、数条数据线、数条公共电极走线、及由数条栅极扫描线与数条数据线相互绝缘交错划分出的多个阵列排布的像素单元；
每一像素单元包括：形成于基板上的栅极、形成于栅极及基板上栅极绝缘层、对应于栅极上方且形成于栅极绝缘层上的半导体层、形成于半导体层、及栅极绝缘层上的源极、漏极和像素电极、形成于所述源极、漏极、像素电极、半导体层、及栅极绝缘层上绝缘保护层、及形成于所述绝缘保 护层上的公共电极；
所述像素电极、源极、漏极和数据线由源漏极金属层经图案化后得到，所述公共电极走线与所述栅极和栅极扫描线由栅极金属层经图案化后得到；
所述绝缘保护层和栅极绝缘层上对应所述公共电极走线的上方设有过孔，所述公共电极通过过孔与公共电极走线相接触；
所述源极、漏极分别与所述半导体层的两端相接触。
所述公共电极的材料为透明导电材料，所述透明导电材料为铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物中的一种或多种；所述公共电极的膜厚为
Figure PCTCN2016074502-appb-000007
所述源漏极金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合，所述源漏极金属层的膜厚为
Figure PCTCN2016074502-appb-000008
本发明还提供一种IPS型TFT-LCD阵列基板的制作方法，包括如下步骤：
步骤1、提供基板，在所述基板上沉积栅极金属层，并对所述栅极金属层进行图案化处理，得到栅极、公共电极走线、及栅极扫描线；
步骤2、在栅极金属层上沉积栅极绝缘层，在所述栅极绝缘层上沉积一层非晶硅层，并对非晶硅层进行N型掺杂后，对所述非晶硅层进行图案化处理，得到对应于栅极上方的半导体层；
步骤3、在所述半导体层、及栅极绝缘层上沉积源漏极金属层，并对所述源漏极金属层进行图案化处理，得到源极、漏极、像素电极、及数据线，所述源极和漏极分别与所述半导体层的两端相接触；
步骤4、在所述源漏极金属层上沉积绝缘保护层，并对绝缘保护层及栅极绝缘层进行图案化处理，在所述绝缘保护层及栅极绝缘层上形成对应于所述公共电极走线上方的过孔；
步骤5、在所述绝缘保护层上沉积一层透明导电层，并对所述透明导电层进行图案化处理，得到公共电极，所述公共电极通过过孔与公共电极走线相接触；
其中，所述步骤1中通过物理气相沉积法沉积栅极金属层，所沉积的栅极金属层的膜厚为
Figure PCTCN2016074502-appb-000009
所述栅极金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；对所述栅极金属层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、湿法蚀刻、及光阻剥离；
其中，所述步骤2中通过化学气相沉积法沉积栅极绝缘层和非晶硅层，所沉积的栅极绝缘层的膜厚为
Figure PCTCN2016074502-appb-000010
所沉积的非晶硅层的膜厚为
Figure PCTCN2016074502-appb-000011
所述栅极绝缘层为氮化硅层，对所述非晶硅层进行图案化处理的步骤包括依次进行的光阻涂布、曝光显影、干法蚀刻、及光阻剥离；
其中，所述步骤3中通过物理气相沉积法沉积源漏极金属层，所沉积的源漏极金属层的膜厚为
Figure PCTCN2016074502-appb-000012
所述源漏极金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合，对所述源漏极金属层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、湿法蚀刻、及光阻剥离；
其中，所述步骤4中通过化学气相沉积法沉积绝缘保护层，所沉积的绝缘保护层为膜厚为
Figure PCTCN2016074502-appb-000013
的，所述的绝缘保护层为氮化硅层，对所述绝缘保护层及栅极绝缘层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、干法蚀刻、及光阻剥离；
其中，所述步骤5中通过物理气相沉积法沉积透明导电层，所沉积透明导电层的膜厚为
Figure PCTCN2016074502-appb-000014
所述透明导电层的材料为铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物中的一种或多种；对所述透明导电层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、湿法蚀刻、及光阻剥离。
本发明的有益效果：本发明的IPS型TFT-LCD阵列基板的制作方法，将公共电极走线与栅极采用同层金属制得，将像素电极与漏极采用同层金属制得，在绝缘保护层及栅极绝缘层上形成对应于所述公共电极走线上方的过孔，在所述绝缘保护层上形成透明导电材料的公共电极，使公共电极通过过孔与公共电极走线相接触，从而能够提升像素电极的充电效率；本发明的IPS型TFT-LCD阵列基板，像素电极与漏极采用同层金属制得，公共电极走线与栅极采用同一层金属层制得，公共电极为透明导电材料并位于绝缘保护层上，公共电极通过绝缘保护层及栅极绝缘层上的过孔与公共电极走线相接触，像素电极的充电效率高，能够提高IPS型液晶显示面板的显示效果。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的IPS型TFT-LCD阵列基板的结构示意图；
图2为本发明的IPS型TFT-LCD阵列基板的制作方法的示意流程图；
图3为本发明的IPS型TFT-LCD阵列基板的制作方法的步骤1的示意 图；
图4为本发明的IPS型TFT-LCD阵列基板的制作方法的步骤2的示意图；
图5为本发明的IPS型TFT-LCD阵列基板的制作方法的步骤3的示意图；
图6为本发明的IPS型TFT-LCD阵列基板的制作方法的步骤4的示意图；
图7为本发明的IPS型TFT-LCD阵列基板的制作方法的步骤5的示意图暨本发明的IPS型TFT-LCD阵列基板的结构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图2，本发明提供一种IPS型TFT-LCD阵列基板的制作方法，包括如下步骤：
步骤1、如图3所示，提供基板10，在所述基板10上沉积栅极金属层，并对所述栅极金属层进行图案化处理，得到栅极11、公共电极走线20、及栅极扫描线30；
具体的，所述步骤1中通过物理气相沉积法(Physical Vapor Deposition，PVD)沉积栅极金属层，所沉积的栅极金属层的膜厚为
Figure PCTCN2016074502-appb-000015
所述栅极金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；对所述栅极金属层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、湿法蚀刻、及光阻剥离。
步骤2、如图4所示，在栅极金属层上沉积栅极绝缘层12，在所述栅极绝缘层12上沉积一层非晶硅层，并对非晶硅层进行N型掺杂后，对所述非晶硅层进行图案化处理，得到对应于栅极11上方的的半导体层13；
具体的，所述步骤2中通过化学气相沉积法(Chemical Vapor Deposition，CVD)沉积栅极绝缘层12和非晶硅层，所沉积的栅极绝缘层12的膜厚为
Figure PCTCN2016074502-appb-000016
所沉积的非晶硅层的膜厚为
Figure PCTCN2016074502-appb-000017
对所述非晶硅层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、干法蚀刻、及光阻剥离；
优选的，所述栅极绝缘层12为氮化硅层。
步骤3、如图5所示，在所述半导体层13、及栅极绝缘层12上沉积源漏极金属层，并对所述源漏极金属层进行图案化处理，得到源极14、漏极 15、像素电极16、及数据线，所述源极14和漏极15分别与所述半导体层13的两端相接触；
具体的，所述步骤3中通过物理气相沉积法沉积源漏极金属层，所沉积的源漏极金属层的膜厚为
Figure PCTCN2016074502-appb-000018
所述源漏极金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合，对所述源漏极金属层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、湿法蚀刻、及光阻剥离。
步骤4、如图6所示，在所述源漏极金属层上沉积绝缘保护层17，并对绝缘保护层17及栅极绝缘层12进行图案化处理，在所述绝缘保护层17及栅极绝缘层12上形成对应于所述公共电极走线20上方的过孔201；
具体的，所述步骤4中通过化学气相沉积法沉积绝缘保护层17，所沉积的绝缘保护层17为膜厚为
Figure PCTCN2016074502-appb-000019
的，对所述绝缘保护层17及栅极绝缘层12进行图案化处理的步骤包括依次进行的光阻涂布、曝光显影、干法蚀刻、及光阻剥离；
优选的，所述的绝缘保护层17为氮化硅层。
步骤5、如图7所示，在所述绝缘保护层17上沉积一层透明导电层，并对所述透明导电层进行图案化处理，得到公共电极21，所述公共电极21通过过孔201与公共电极走线20相接触。
具体的，所述步骤5中通过物理气相沉积法沉积透明导电层，所沉积透明导电层的膜厚为
Figure PCTCN2016074502-appb-000020
所述透明导电层的材料为铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物中的一种或多种；
优选的，所沉积透明导电层的材料为铟锡氧化物(ITO)；
具体的，对所述透明导电层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、湿法蚀刻、及光阻剥离。
请参阅图7，基于以上IPS型TFT-LCD阵列基板的制作方法，本发明还提供一种IPS型TFT-LCD阵列基板，包括：基板10、设于所述基板10上的数条栅极扫描线30、数条数据线(未图示)、数条公共电极走线20、及由数条栅极扫描线与数条数据线相互绝缘交错划分出的多个阵列排布的像素单元；
每一像素单元均包括：形成于基板10上的栅极11、形成于栅极11及基板10上栅极绝缘层12、对应于栅极11上方且形成于栅极绝缘层12上的半导体层13、形成于半导体层13、及栅极绝缘层12上的源极14、漏极15和像素电极16、形成于所述源极14、漏极15、像素电极16、半导体层13、及栅极绝缘层12上绝缘保护层17、及形成于所述绝缘保护层17上的公共 电极21；
所述像素电极16、源极14、漏极15和数据线由源漏极金属层经图案化后得到，所述公共电极走线20与所述栅极11和栅极扫描线30由栅极金属层经图案化后得到；
所述绝缘保护层17和栅极绝缘层12上对应所述公共电极走线20的上方设有过孔201，所述公共电极21通过过孔201与公共电极走线20相接触；
所述源极14、漏极15分别与所述半导体层13的两端相接触。
具体的，所述公共电极21的材料为透明导电材料，所述透明导电材料为铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物中的一种或多种；所述公共电极21的膜厚为
Figure PCTCN2016074502-appb-000021
优选的，所述公共电极21的材料为铟锡氧化物。
具体的，所述源漏极金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合，所述源漏极金属层的膜厚为
Figure PCTCN2016074502-appb-000022
综上所述，本发明的IPS型TFT-LCD阵列基板的制作方法，将公共电极走线与栅极采用同层金属制得，将像素电极与漏极采用同层金属制得，在绝缘保护层及栅极绝缘层上形成对应于所述公共电极走线上方的过孔，在所述绝缘保护层上形成透明导电材料的公共电极，使公共电极通过过孔与公共电极走线相接触，从而能够提升像素电极的充电效率；本发明的IPS型TFT-LCD阵列基板，像素电极与漏极采用同层金属制得，公共电极走线与栅极采用同一层金属层制得，公共电极为透明导电材料并位于绝缘保护层上，公共电极通过绝缘保护层及栅极绝缘层上的过孔与公共电极走线相接触，像素电极的充电效率高，能够提高IPS型液晶显示面板的显示效果。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

  1. 一种IPS型TFT-LCD阵列基板的制作方法，包括如下步骤：
    步骤1、提供基板，在所述基板上沉积栅极金属层，并对所述栅极金属层进行图案化处理，得到栅极、公共电极走线、及栅极扫描线；
    步骤2、在栅极金属层上沉积栅极绝缘层，在所述栅极绝缘层上沉积一层非晶硅层，并对非晶硅层进行N型掺杂后，对所述非晶硅层进行图案化处理，得到对应于栅极上方的半导体层；
    步骤3、在所述半导体层、及栅极绝缘层上沉积源漏极金属层，并对所述源漏极金属层进行图案化处理，得到源极、漏极、像素电极、及数据线，所述源极和漏极分别与所述半导体层的两端相接触；
    步骤4、在所述源漏极金属层上沉积绝缘保护层，并对绝缘保护层及栅极绝缘层进行图案化处理，在所述绝缘保护层及栅极绝缘层上形成对应于所述公共电极走线上方的过孔；
    步骤5、在所述绝缘保护层上沉积一层透明导电层，并对所述透明导电层进行图案化处理，得到公共电极，所述公共电极通过过孔与公共电极走线相接触。
  2. 如权利要求1所述的IPS型TFT-LCD阵列基板的制作方法，其中，所述步骤1中通过物理气相沉积法沉积栅极金属层，所沉积的栅极金属层的膜厚为
    Figure PCTCN2016074502-appb-100001
    所述栅极金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；对所述栅极金属层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、湿法蚀刻、及光阻剥离。
  3. 如权利要求1所述的IPS型TFT-LCD阵列基板的制作方法，其中，所述步骤2中通过化学气相沉积法沉积栅极绝缘层和非晶硅层，所沉积的栅极绝缘层的膜厚为
    Figure PCTCN2016074502-appb-100002
    所沉积的非晶硅层的膜厚为
    Figure PCTCN2016074502-appb-100003
    所述栅极绝缘层为氮化硅层，对所述非晶硅层进行图案化处理的步骤包括依次进行的光阻涂布、曝光显影、干法蚀刻、及光阻剥离。
  4. 如权利要求1所述的IPS型TFT-LCD阵列基板的制作方法，其中，所述步骤3中通过物理气相沉积法沉积源漏极金属层，所沉积的源漏极金属层的膜厚为
    Figure PCTCN2016074502-appb-100004
    所述源漏极金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合，对所述源漏极金属层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、湿法蚀刻、及光阻剥离。
  5. 如权利要求1所述的IPS型TFT-LCD阵列基板的制作方法，其中， 所述步骤4中通过化学气相沉积法沉积绝缘保护层，所沉积的绝缘保护层为膜厚为
    Figure PCTCN2016074502-appb-100005
    的，所述的绝缘保护层为氮化硅层，对所述绝缘保护层及栅极绝缘层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、干法蚀刻、及光阻剥离。
  6. 如权利要求1所述的IPS型TFT-LCD阵列基板的制作方法，其中，所述步骤5中通过物理气相沉积法沉积透明导电层，所沉积透明导电层的膜厚为
    Figure PCTCN2016074502-appb-100006
    所述透明导电层的材料为铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物中的一种或多种；对所述透明导电层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、湿法蚀刻、及光阻剥离。
  7. 一种IPS型TFT-LCD阵列基板，包括：基板、设于基板上的数条栅极扫描线、数条数据线、数条公共电极走线、及由数条栅极扫描线与数条数据线相互绝缘交错划分出的多个阵列排布的像素单元；
    每一像素单元均包括：形成于基板上的栅极、形成于栅极及基板上栅极绝缘层、对应于栅极上方且形成于栅极绝缘层上的半导体层、形成于半导体层、及栅极绝缘层上的源极、漏极和像素电极、形成于所述源极、漏极、像素电极、半导体层、及栅极绝缘层上绝缘保护层、及形成于所述绝缘保护层上的公共电极；
    所述像素电极、源极、漏极和数据线由源漏极金属层经图案化后得到，所述公共电极走线与所述栅极和栅极扫描线由栅极金属层经图案化后得到；
    所述绝缘保护层和栅极绝缘层上对应所述公共电极走线的上方设有过孔，所述公共电极通过过孔与公共电极走线相接触；
    所述源极、漏极分别与所述半导体层的两端相接触。
  8. 如权利要求7所述的IPS型TFT-LCD阵列基板，其中，所述公共电极的材料为透明导电材料，所述透明导电材料为铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物中的一种或多种；所述公共电极的膜厚为
    Figure PCTCN2016074502-appb-100007
  9. 如权利要求7所述的IPS型TFT-LCD阵列基板，其中，所述源漏极金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合，所述源漏极金属层的膜厚为
    Figure PCTCN2016074502-appb-100008
  10. 一种IPS型TFT-LCD阵列基板的制作方法，包括如下步骤：
    步骤1、提供基板，在所述基板上沉积栅极金属层，并对所述栅极金属层进行图案化处理，得到栅极、公共电极走线、及栅极扫描线；
    步骤2、在栅极金属层上沉积栅极绝缘层，在所述栅极绝缘层上沉积一层非晶硅层，并对非晶硅层进行N型掺杂后，对所述非晶硅层进行图案化处理，得到对应于栅极上方的半导体层；
    步骤3、在所述半导体层、及栅极绝缘层上沉积源漏极金属层，并对所述源漏极金属层进行图案化处理，得到源极、漏极、像素电极、及数据线，所述源极和漏极分别与所述半导体层的两端相接触；
    步骤4、在所述源漏极金属层上沉积绝缘保护层，并对绝缘保护层及栅极绝缘层进行图案化处理，在所述绝缘保护层及栅极绝缘层上形成对应于所述公共电极走线上方的过孔；
    步骤5、在所述绝缘保护层上沉积一层透明导电层，并对所述透明导电层进行图案化处理，得到公共电极，所述公共电极通过过孔与公共电极走线相接触；
    其中，所述步骤1中通过物理气相沉积法沉积栅极金属层，所沉积的栅极金属层的膜厚为
    Figure PCTCN2016074502-appb-100009
    所述栅极金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；对所述栅极金属层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、湿法蚀刻、及光阻剥离；
    其中，所述步骤2中通过化学气相沉积法沉积栅极绝缘层和非晶硅层，所沉积的栅极绝缘层的膜厚为
    Figure PCTCN2016074502-appb-100010
    所沉积的非晶硅层的膜厚为
    Figure PCTCN2016074502-appb-100011
    所述栅极绝缘层为氮化硅层，对所述非晶硅层进行图案化处理的步骤包括依次进行的光阻涂布、曝光显影、干法蚀刻、及光阻剥离；
    其中，所述步骤3中通过物理气相沉积法沉积源漏极金属层，所沉积的源漏极金属层的膜厚为
    Figure PCTCN2016074502-appb-100012
    所述源漏极金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合，对所述源漏极金属层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、湿法蚀刻、及光阻剥离；
    其中，所述步骤4中通过化学气相沉积法沉积绝缘保护层，所沉积的绝缘保护层为膜厚为
    Figure PCTCN2016074502-appb-100013
    的，所述的绝缘保护层为氮化硅层，对所述绝缘保护层及栅极绝缘层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、干法蚀刻、及光阻剥离；
    其中，所述步骤5中通过物理气相沉积法沉积透明导电层，所沉积透明导电层的膜厚为
    Figure PCTCN2016074502-appb-100014
    所述透明导电层的材料为铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物中的一种或多种；对所述透明导电层进行图案化处理的步骤包括依次进行的光阻涂布、曝光、显影、湿法蚀刻、及光阻剥离。
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