WO2019100495A1 - Ffs型薄膜晶体管阵列基板及其制作方法 - Google Patents

Ffs型薄膜晶体管阵列基板及其制作方法 Download PDF

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Publication number
WO2019100495A1
WO2019100495A1 PCT/CN2017/117346 CN2017117346W WO2019100495A1 WO 2019100495 A1 WO2019100495 A1 WO 2019100495A1 CN 2017117346 W CN2017117346 W CN 2017117346W WO 2019100495 A1 WO2019100495 A1 WO 2019100495A1
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Prior art keywords
layer
drain
common electrode
gate
passivation layer
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PCT/CN2017/117346
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English (en)
French (fr)
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周志超
夏慧
陈梦
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深圳市华星光电半导体显示技术有限公司
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Priority to US15/749,107 priority Critical patent/US10304866B1/en
Publication of WO2019100495A1 publication Critical patent/WO2019100495A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1296—Multistep manufacturing methods adapted to increase the uniformity of device parameters

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an FFS type thin film transistor array substrate and a method of fabricating the same.
  • LCDs liquid crystal displays
  • Various consumer electronic products such as digital assistants, digital cameras, notebook computers, and desktop computers have become mainstream in display devices.
  • liquid crystal display devices which include a liquid crystal display panel and a backlight module.
  • a liquid crystal display panel comprises a CF (Color Filter) substrate, a thin film transistor (TFT) substrate, a liquid crystal (LC) sandwiched between the color filter substrate and the thin film transistor substrate, and a sealant frame ( Sealant) composition.
  • CF Color Filter
  • TFT thin film transistor
  • LC liquid crystal
  • Sealant sealant frame
  • the thin film transistor liquid crystal display can be classified into a vertical electric field type and a horizontal electric field type.
  • the vertical electric field type TFT-LCD needs to form a pixel electrode on the thin film transistor array substrate to form a common electrode on the color film substrate; and the horizontal electric field type TFT-LCD needs to simultaneously form the pixel electrode and the common electrode on the thin film transistor array substrate.
  • the vertical electric field type TFT-LCD includes a twisted nematic (TN) type TFT-LCD;
  • the horizontal electric field type TFT-LCD includes: Fringe Field Switching (FFS) type TFT-LCD, total In-Plane Switching (referred to as IPS) type TFT-LCD.
  • FFS Fringe Field Switching
  • IPS In-Plane Switching
  • the horizontal electric field type TFT-LCD, especially the FFS type TFT-LCD has the advantages of high light transmittance, wide viewing angle, fast response speed and low power consumption, and is widely used in the field of liquid crystal displays.
  • the fabrication method of the FFS type thin film transistor array substrate generally adopts a six-mask process, and the fabrication cost of the FFS type thin film transistor array substrate is high due to the high fabrication cost of the photomask and the long process time of the six-mask process. .
  • Another object of the present invention is to provide an FFS type thin film transistor array substrate, and a manufacturing process thereof Simple, low production cost, and excellent electrical properties.
  • the present invention provides a method for fabricating an FFS type thin film transistor array substrate, including:
  • Source/drain metal layer on the active layer and the gate insulating layer, and patterning the source and drain metal layers by using a third mask process to obtain a source, a drain, and a data line;
  • the source and the drain are respectively in contact with the active layer, and the data line is connected to the source;
  • the steps of forming the gate, the scan line, the common electrode and the common electrode line on the substrate by using the first mask process include:
  • the material of the first transparent conductive layer comprises a transparent conductive metal oxide; the first metal
  • the material of the layer includes copper.
  • a process of plating a first metal layer on the predetermined pattern of the gate and the predetermined pattern of the scan lines is an electroplating process.
  • the material of the passivation layer includes one or more of silicon oxide and silicon nitride, and the material of the flat layer is an organic photoresist material.
  • the fourth mask process includes a photoresist, exposure, development, dry etching, and photoresist stripping process
  • the fourth mask process includes exposure and development And dry etching process.
  • the invention also provides an FFS type thin film transistor array substrate, comprising:
  • a gate a scan line, a common electrode, and a common electrode line disposed on the base substrate; wherein the gate is connected to the scan line, and the common electrode is connected to the common electrode line;
  • a gate insulating layer disposed on the gate, the scan line, the common electrode, the common electrode line, and the base substrate;
  • a source and a drain provided on the active layer and the gate insulating layer, and a data line disposed on the gate insulating layer; wherein the source and the drain are respectively opposite to the active layer Contacted, the data line is connected to the source;
  • a passivation layer disposed on the source, the drain, the data line, the active layer and the gate insulating layer, wherein the passivation layer is provided with a first via corresponding to the top of the drain; a pixel electrode on the passivation layer, the pixel electrode being connected to the drain through a first via hole on the passivation layer; or
  • a passivation layer disposed on the source, the drain, the data line, the active layer, and the gate insulating layer, and a planar layer disposed on the passivation layer, wherein the passivation layer and the flat layer are disposed Corresponding to a second via disposed above the drain; a pixel electrode disposed on the planar layer, the pixel electrode passing through a second via located on the passivation layer and the planar layer and the drain Connected.
  • the common electrode and the common electrode line include a first transparent conductive layer disposed on the base substrate, and the gate and the scan line include a first transparent conductive layer disposed on the base substrate and disposed at the a first metal layer on the first transparent conductive layer; wherein the first metal layer has a conductivity higher than that of the first transparent conductive layer.
  • the material of the first transparent conductive layer comprises a transparent conductive metal oxide; the material of the first metal layer comprises copper.
  • the material of the passivation layer includes one or more of silicon oxide and silicon nitride, and the material of the flat layer is an organic photoresist material.
  • the invention also provides a method for fabricating an FFS type thin film transistor array substrate, comprising:
  • Source/drain metal layer on the active layer and the gate insulating layer, and patterning the source and drain metal layers by using a third mask process to obtain a source, a drain, and a data line;
  • the source and the drain are respectively in contact with the active layer, and the data line is connected to the source;
  • the step of forming a gate, a scan line, a common electrode, and a common electrode line on the base substrate by using a first mask process includes:
  • the material of the first transparent conductive layer comprises a transparent conductive metal oxide; a metal layer material comprising copper;
  • the process of plating the first metal layer on the predetermined pattern of the gate and the predetermined pattern of the scan line is an electroplating process
  • the material of the passivation layer comprises one or more of silicon oxide and silicon nitride
  • the material of the flat layer is an organic photoresist material
  • the fabrication method of the FFS type thin film transistor array substrate of the present invention comprises: forming a gate electrode, a scan line, a common electrode and a common electrode line in a mask process, which simplifies the process compared with the prior art.
  • the process the number of masks used is small, the process time is short, and the production cost is low.
  • the FFS type thin film transistor array substrate of the present invention has a simple manufacturing process, low production cost, and excellent electrical properties.
  • FIG. 1 is a flow chart showing a method of fabricating an FFS type thin film transistor array substrate of the present invention
  • FIG. 2 is a schematic plan view showing a process of the step S11 of the method for fabricating the FFS type thin film transistor array substrate of the present invention
  • Figure 3 is a cross-sectional view of Figure 2;
  • step S12 is a schematic plan view showing a process of step S12 of the method for fabricating an FFS-type thin film transistor array substrate of the present invention
  • Figure 5 is a cross-sectional view of Figure 4.
  • step S2 is a schematic plan view showing a process of step S2 of the method for fabricating an FFS type thin film transistor array substrate of the present invention
  • Figure 7 is a cross-sectional view of Figure 6;
  • step S3 is a schematic plan view showing a process of step S3 of the method for fabricating an FFS type thin film transistor array substrate of the present invention
  • Figure 9 is a cross-sectional view of Figure 8.
  • step S4 of the method for fabricating an FFS type thin film transistor array substrate of the present invention
  • Figure 11a and Figure 11b are schematic cross-sectional views of Figure 10;
  • step S5 is a schematic plan view showing a process of step S5 of the method for fabricating an FFS type thin film transistor array substrate of the present invention
  • FIG. 13a and 13b are schematic cross-sectional views of Fig. 12.
  • the present invention provides a method for fabricating an FFS type thin film transistor array substrate, which includes the following steps:
  • a substrate substrate 10 is provided, and a gate electrode 21, a scan line 22, a common electrode 23, and a common electrode line 24 are formed on the substrate substrate 10 by a first mask process;
  • the gate 21 is connected to the scan line 22, and the common electrode 23 is connected to the common electrode line 24.
  • the steps of forming the gate electrode 21, the scan line 22, the common electrode 23, and the common electrode line 24 on the base substrate 10 by using a first mask process include:
  • a first transparent conductive layer 11 is deposited on the base substrate 10, and the first transparent conductive layer 11 is patterned by a first mask process to obtain a gate.
  • the first metal layer 12 is plated on the predetermined pattern 15 of the gate and the predetermined pattern 16 of the scan line to obtain a gate 21 and a scan line 22, wherein the first metal
  • the electrical conductivity of the layer 12 is greater than the electrical conductivity of the first transparent conductive layer 11.
  • the material of the first transparent conductive layer 11 includes a transparent conductive metal oxide such as indium tin oxide (ITO), and the first transparent conductive layer 11 is deposited by physical vapor deposition (PVD).
  • ITO indium tin oxide
  • PVD physical vapor deposition
  • the material of the first metal layer 12 includes copper.
  • the electrical performance requirement can be satisfied only by the first transparent conductive layer 11; since the gate 21 and the scan line 22 need to have low resistance, A transparent conductive layer 11 is plated with a first metal layer 12 (preferably copper) having better conductivity to prepare the gate electrode 21 and the scan line 22, and the resistance value thereof can be lowered to meet the corresponding electrical performance requirements.
  • a first metal layer 12 preferably copper
  • a process of plating the first metal layer 12 on the predetermined gate pattern 15 and the scan line predetermined pattern 16 is an electroplating process.
  • the predetermined pattern 15 of the gate and the predetermined pattern 16 of the scan line are energized, and the common electrode 23 and the common electrode line 24 are not energized, so that only the predetermined pattern 15 of the gate and the predetermined pattern of the scan line are realized.
  • Plated with the first metal layer 12 instead of The common electrode 23 and the common electrode line 24 are plated with the first metal layer 12.
  • the present invention can improve the conductive properties of the prepared gate electrode 21 and the scan line 22 by plating the first metal layer 12 on the predetermined pattern 16 of the gate and the predetermined pattern 16 of the scan line.
  • the base substrate 10 is a glass substrate.
  • the first mask process includes photoresisting, exposure, development, wet etching, and photoresist stripping processes.
  • a gate insulating layer 30 is deposited on the gate electrode 21, the scan line 22, the common electrode 23, the common electrode line 24, and the base substrate 10, and the gate insulating layer is The semiconductor layer 35 is deposited on the third layer, and the semiconductor layer 35 is patterned by a second mask process to obtain an active layer 40 corresponding to the upper portion of the gate electrode 21.
  • the material of the gate insulating layer 30 includes one or more of silicon oxide (SiO x ) and silicon nitride (SiN x ).
  • the material of the semiconductor layer 35 includes one or more of amorphous silicon, polycrystalline silicon, and metal oxide.
  • the deposition methods of the gate insulating layer 30 and the semiconductor layer 35 are both chemical vapor deposition (CVD).
  • the second mask process includes photoresisting, exposure, development, dry etching, and photoresist stripping processes.
  • a source/drain metal layer 45 is deposited on the active layer 40 and the gate insulating layer 30, and the source/drain metal layer 45 is patterned by a third mask process.
  • the source 51, the drain 52, and the data line 53 are obtained.
  • the source 51 and the drain 52 are respectively in contact with the active layer 40, and the data line 53 is connected to the source 51. .
  • the deposition method of the source/drain metal layer 45 is a physical vapor deposition method (PVD).
  • the third mask process includes a photoresist, exposure, development, wet etching, and photoresist stripping process.
  • a passivation layer 60 is formed on the source 51, the drain 52, the data line 53, the active layer 40, and the gate insulating layer 30, and the fourth mask process is used.
  • the passivation layer 60 is patterned to obtain a first via hole 61 on the passivation layer 60, and the first via hole 61 is disposed above the drain electrode 52;
  • a passivation layer 60 is formed on the source 51, the drain 52, the data line 53, the active layer 40, and the gate insulating layer 30, and is provided on the passivation layer.
  • the planarization layer 70 on the 60, the passivation layer 60 and the planarization layer 70 are patterned by a fourth mask process to obtain a second via hole 72 on the passivation layer 60 and the planarization layer 70.
  • the second via hole 72 is disposed above the drain 52.
  • the material of the passivation layer 60 includes one or more of silicon oxide (SiO x ) and silicon nitride (SiN x ), and the passivation layer 60 is formed by chemical vapor deposition (CVD). ).
  • the material of the flat layer 70 is an organic photoresist material, and the formation method of the flat layer 70 is a coating film process.
  • the fourth mask process includes photoresisting, exposure, development, dry etching, and photoresist stripping processes.
  • a passivation layer 60 is formed on the source 51, the drain 52, the data line 53, the active layer 40, and the gate insulating layer 30, and is disposed on the passivation layer 60.
  • the fourth reticle process includes an exposure, development, and dry etch process.
  • the flat layer 70 on the passivation layer 60 the flatness of the subsequently fabricated pixel electrode 80 can be improved, thereby improving the stability of the liquid crystal display panel.
  • a second transparent conductive layer 75 is deposited on the flat layer 70, and the second transparent conductive layer 75 is patterned by a fifth mask process to obtain the A pixel electrode 80 on the flat layer 70 is connected to the drain electrode 52 through a second via 72 located on the passivation layer 60 and the planarization layer 70.
  • the material of the second transparent conductive layer 75 includes a transparent conductive metal oxide such as indium tin oxide (ITO), and the second transparent conductive layer 75 is deposited by physical vapor deposition (PVD).
  • ITO indium tin oxide
  • PVD physical vapor deposition
  • the fifth mask process includes photoresisting, exposure, development, wet etching, and photoresist stripping processes.
  • the method for fabricating the FFS type thin film transistor array substrate of the present invention comprises: forming the gate electrode 21, the scan line 22, the common electrode 23 and the common electrode line 24 in a mask process, which simplifies the process process compared with the prior art.
  • the number of masks used is small and the process time is short, so the production cost is low.
  • the present invention further provides an FFS-type thin film transistor array substrate based on the method for fabricating the FFS-type thin film transistor array substrate, comprising:
  • a gate insulating layer 30 disposed on the gate electrode 21, the scan line 22, the common electrode 23, the common electrode line 24, and the base substrate 10;
  • a source 51 and a drain 52 disposed on the active layer 40 and the gate insulating layer 30, and a data line 53 disposed on the gate insulating layer 30; wherein the source 51 and the drain 52 Separably in contact with the active layer 40, the data line 53 is connected to the source 51;
  • a passivation layer 60 disposed on the source 51, the drain 52, the data line 53, the active layer 40, and the gate insulating layer 30.
  • the passivation layer 60 is disposed above the drain 52. a first via hole 61; and a pixel electrode 80 disposed on the passivation layer 60, the pixel electrode 80 being connected to the drain electrode 52 through a first via hole 61 on the passivation layer 60 (as shown in Figure 13a); or,
  • a passivation layer 60 disposed on the source 51, the drain 52, the data line 53, the active layer 40, and the gate insulating layer 30, and a flat layer 70 disposed on the passivation layer 60, the blunt a second via hole 72 corresponding to the upper surface of the drain electrode 52; and a pixel electrode 80 disposed on the flat layer 70, the pixel electrode 80 passing through the blunt
  • the second via 72 on the planarization layer 60 and the planarization layer 70 is connected to the drain 52 (as shown in Figure 13b).
  • the common electrode 23 and the common electrode line 24 include a first transparent conductive layer 11 disposed on the base substrate 10, and the gate electrode 21 and the scan line 22 are disposed on the base substrate 10. a first transparent conductive layer 11 and a first metal layer 12 disposed on the first transparent conductive layer 11; wherein, the conductive property of the first metal layer 12 is greater than that of the first transparent conductive layer 11 .
  • the material of the first transparent conductive layer 11 includes a transparent conductive metal oxide such as indium tin oxide (ITO).
  • ITO indium tin oxide
  • the material of the first metal layer 12 includes copper.
  • the base substrate 10 is a glass substrate.
  • the material of the gate insulating layer 30 includes one or more of silicon oxide (SiO x ) and silicon nitride (SiN x ).
  • the material of the active layer 40 includes one or more of amorphous silicon, polycrystalline silicon, and metal oxide.
  • the material of the passivation layer 60 includes one or more of silicon oxide (SiO x ) and silicon nitride (SiN x ), and the material of the flat layer 70 is an organic photoresist material.
  • the material of the pixel electrode 80 includes a transparent conductive metal oxide such as indium tin oxide (ITO).
  • ITO indium tin oxide
  • the FFS type thin film transistor array substrate of the present invention has a simple manufacturing process, low production cost, and excellent electrical properties.
  • the present invention provides an FFS type thin film transistor array substrate and a method of fabricating the same.
  • the manufacturing method of the FFS type thin film transistor array substrate of the present invention comprises: forming a gate electrode, a scan line, a common electrode and a common electrode line in a mask process, which simplifies the process process and uses the photomask as compared with the prior art. The number is small and the process time is short, so the production cost is low.
  • the FFS type thin film transistor array substrate of the present invention has a simple manufacturing process, low production cost, and excellent electrical properties.

Abstract

一种FFS型薄膜晶体管阵列基板及其制作方法，该制作方法包括：在一道光罩工艺中形成栅极、扫描线、公共电极及公共电极线（S1），与现有技术相比，简化了工艺制程，采用的光罩数量较少，制程时间较短，因此生产成本低。制作工艺简单，生产成本低，且具有优异的电学性能。

Description

FFS型薄膜晶体管阵列基板及其制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种FFS型薄膜晶体管阵列基板及其制作方法。
背景技术
随着显示技术的发展，液晶显示器(Liquid Crystal Display，LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
现有市场上的液晶显示装置大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(Backlight Module)。通常液晶显示面板由彩膜(CF，Color Filter)基板、薄膜晶体管(TFT，Thin Film Transistor)基板、夹于彩膜基板与薄膜晶体管基板之间的液晶(LC，Liquid Crystal)及密封胶框(Sealant)组成。
根据驱动液晶的电场方向，薄膜晶体管液晶显示器(TFT-LCD)可分为垂直电场型和水平电场型。其中，垂直电场型TFT-LCD需要在薄膜晶体管阵列基板上形成像素电极，在彩膜基板上形成公共电极；而水平电场型TFT-LCD需要在薄膜晶体管阵列基板上同时形成像素电极和公共电极。垂直电场型TFT-LCD包括：扭曲向列(Twist Nematic，简称为TN)型TFT-LCD；水平电场型TFT-LCD包括：边缘电场切换(Fringe Field Switching，简称为FFS)型TFT-LCD、共平面切换(In-Plane Switching，简称为IPS)型TFT-LCD。水平电场型TFT-LCD，尤其是FFS型TFT-LCD具有高透光率、广视角、响应速度快及低功耗等优点，广泛应用于液晶显示器领域。但是目前FFS型薄膜晶体管阵列基板的制作方法通常采用6道光罩工艺，由于光罩的制作成本较高且6道光罩工艺的制程时间较长，因此目前FFS型薄膜晶体管阵列基板的制作成本较高。
发明内容
本发明的目的在于提供一种FFS型薄膜晶体管阵列基板的制作方法，使用光罩工艺的次数较少，生产成本低。
本发明的目的还在于提供一种FFS型薄膜晶体管阵列基板，制作工艺 简单，生产成本低，且具有优异的电学性能。
为实现上述目的，本发明提供一种FFS型薄膜晶体管阵列基板的制作方法，包括：
提供衬底基板，采用第一道光罩工艺在所述衬底基板上形成栅极、扫描线、公共电极及公共电极线；其中，所述栅极与扫描线相连，所述公共电极与公共电极线相连；
在所述栅极、扫描线、公共电极、公共电极线及衬底基板上沉积栅极绝缘层，在所述栅极绝缘层上沉积半导体层，采用第二道光罩工艺对所述半导体层进行图形化处理，得到对应于所述栅极上方的有源层；
在所述有源层与栅极绝缘层上沉积源漏极金属层，采用第三道光罩工艺对所述源漏极金属层进行图形化处理，得到源极、漏极及数据线；其中，所述源极与漏极分别与所述有源层相接触，所述数据线与所述源极相连；
在所述源极、漏极、数据线、有源层及栅极绝缘层上形成钝化层，采用第四道光罩工艺对所述钝化层进行图形化处理，得到位于所述钝化层上的第一通孔，所述第一通孔对应于所述漏极上方设置；在所述钝化层上沉积第二透明导电层，采用第五道光罩工艺对所述第二透明导电层进行图形化处理，得到位于所述钝化层上的像素电极，所述像素电极通过位于所述钝化层上的第一通孔与所述漏极相连；或者，
在所述源极、漏极、数据线、有源层及栅极绝缘层上形成钝化层与设于所述钝化层上的平坦层，采用第四道光罩工艺对所述钝化层和平坦层进行图形化处理，得到位于所述钝化层和平坦层上的第二通孔，所述第二通孔对应于所述漏极上方设置；在所述平坦层上沉积第二透明导电层，采用第五道光罩工艺对所述第二透明导电层进行图形化处理，得到位于所述平坦层上的像素电极，所述像素电极通过位于所述钝化层与平坦层上的第二通孔与所述漏极相连。
采用第一道光罩工艺在所述衬底基板上形成栅极、扫描线、公共电极及公共电极线的步骤包括：
在所述衬底基板上沉积第一透明导电层，采用第一道光罩工艺对所述第一透明导电层进行图形化处理，得到栅极预定图案与扫描线预定图案以及公共电极与公共电极线；
在所述栅极预定图案与扫描线预定图案上镀上第一金属层，得到栅极与扫描线，其中，所述第一金属层的导电性能大于所述第一透明导电层的导电性能。
所述第一透明导电层的材料包括透明导电金属氧化物；所述第一金属 层的材料包括铜。
在所述栅极预定图案与扫描线预定图案上镀上第一金属层的工艺为电镀工艺。
所述钝化层的材料包括氧化硅与氮化硅中的一种或多种，所述平坦层的材料为有机光阻材料。
在所述源极、漏极、数据线、有源层及栅极绝缘层上形成钝化层后，所述第四道光罩工艺包括涂光阻、曝光、显影、干蚀刻及光阻剥离制程；
在所述源极、漏极、数据线、有源层及栅极绝缘层上形成钝化层与设于所述钝化层上的平坦层后，所述第四道光罩工艺包括曝光、显影及干蚀刻制程。
本发明还提供一种FFS型薄膜晶体管阵列基板，包括：
衬底基板；
设于所述衬底基板上的栅极、扫描线、公共电极及公共电极线；其中，所述栅极与扫描线相连，所述公共电极与公共电极线相连；
设于所述栅极、扫描线、公共电极、公共电极线及衬底基板上的栅极绝缘层；
设于所述栅极绝缘层上且对应于所述栅极上方的有源层；
设于所述有源层与栅极绝缘层上的源极与漏极、设于所述栅极绝缘层上的数据线；其中，所述源极与漏极分别与所述有源层相接触，所述数据线与所述源极相连；
设于所述源极、漏极、数据线、有源层及栅极绝缘层上的钝化层，所述钝化层上设有对应于所述漏极上方设置的第一通孔；设于所述钝化层上的像素电极，所述像素电极通过位于所述钝化层上的第一通孔与所述漏极相连；或者，
设于所述源极、漏极、数据线、有源层及栅极绝缘层上的钝化层与设于所述钝化层上的平坦层，所述钝化层和平坦层上设有对应于所述漏极上方设置的第二通孔；设于所述平坦层上的像素电极，所述像素电极通过位于所述钝化层与平坦层上的第二通孔与所述漏极相连。
所述公共电极与公共电极线包括设于所述衬底基板上的第一透明导电层，所述栅极与扫描线包括设于所述衬底基板上的第一透明导电层与设于所述第一透明导电层上的第一金属层；其中，所述第一金属层的导电性能大于所述第一透明导电层的导电性能。
所述第一透明导电层的材料包括透明导电金属氧化物；所述第一金属层的材料包括铜。
所述钝化层的材料包括氧化硅与氮化硅中的一种或多种，所述平坦层的材料为有机光阻材料。
本发明还提供一种FFS型薄膜晶体管阵列基板的制作方法，包括：
提供衬底基板，采用第一道光罩工艺在所述衬底基板上形成栅极、扫描线、公共电极及公共电极线；其中，所述栅极与扫描线相连，所述公共电极与公共电极线相连；
在所述栅极、扫描线、公共电极、公共电极线及衬底基板上沉积栅极绝缘层，在所述栅极绝缘层上沉积半导体层，采用第二道光罩工艺对所述半导体层进行图形化处理，得到对应于所述栅极上方的有源层；
在所述有源层与栅极绝缘层上沉积源漏极金属层，采用第三道光罩工艺对所述源漏极金属层进行图形化处理，得到源极、漏极及数据线；其中，所述源极与漏极分别与所述有源层相接触，所述数据线与所述源极相连；
在所述源极、漏极、数据线、有源层及栅极绝缘层上形成钝化层，采用第四道光罩工艺对所述钝化层进行图形化处理，得到位于所述钝化层上的第一通孔，所述第一通孔对应于所述漏极上方设置；在所述钝化层上沉积第二透明导电层，采用第五道光罩工艺对所述第二透明导电层进行图形化处理，得到位于所述钝化层上的像素电极，所述像素电极通过位于所述钝化层上的第一通孔与所述漏极相连；或者，
在所述源极、漏极、数据线、有源层及栅极绝缘层上形成钝化层与设于所述钝化层上的平坦层，采用第四道光罩工艺对所述钝化层和平坦层进行图形化处理，得到位于所述钝化层和平坦层上的第二通孔，所述第二通孔对应于所述漏极上方设置；在所述平坦层上沉积第二透明导电层，采用第五道光罩工艺对所述第二透明导电层进行图形化处理，得到位于所述平坦层上的像素电极，所述像素电极通过位于所述钝化层与平坦层上的第二通孔与所述漏极相连；
其中，采用第一道光罩工艺在所述衬底基板上形成栅极、扫描线、公共电极及公共电极线的步骤包括：
在所述衬底基板上沉积第一透明导电层，采用第一道光罩工艺对所述第一透明导电层进行图形化处理，得到栅极预定图案与扫描线预定图案以及公共电极与公共电极线；
在所述栅极预定图案与扫描线预定图案上镀上第一金属层，得到栅极与扫描线，其中，所述第一金属层的导电性能大于所述第一透明导电层的导电性能；
其中，所述第一透明导电层的材料包括透明导电金属氧化物；所述第 一金属层的材料包括铜；
其中，在所述栅极预定图案与扫描线预定图案上镀上第一金属层的工艺为电镀工艺；
其中，所述钝化层的材料包括氧化硅与氮化硅中的一种或多种，所述平坦层的材料为有机光阻材料。
本发明的有益效果：本发明的FFS型薄膜晶体管阵列基板的制作方法包括：在一道光罩工艺中形成栅极、扫描线、公共电极及公共电极线，与现有技术相比，简化了工艺制程，采用的光罩数量较少，制程时间较短，因此生产成本低。本发明的FFS型薄膜晶体管阵列基板的制作工艺简单，生产成本低，且具有优异的电学性能。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为本发明的FFS型薄膜晶体管阵列基板的制作方法的流程图；
图2为本发明的FFS型薄膜晶体管阵列基板的制作方法的步骤S11制程的俯视示意图；
图3为图2的剖视示意图；
图4为本发明的FFS型薄膜晶体管阵列基板的制作方法的步骤S12制程的俯视示意图；
图5为图4的剖视示意图；
图6为本发明的FFS型薄膜晶体管阵列基板的制作方法的步骤S2制程的俯视示意图；
图7为图6的剖视示意图；
图8为本发明的FFS型薄膜晶体管阵列基板的制作方法的步骤S3制程的俯视示意图；
图9为图8的剖视示意图；
图10为本发明的FFS型薄膜晶体管阵列基板的制作方法的步骤S4制程的俯视示意图；
图11a与图11b为图10的剖视示意图；
图12为本发明的FFS型薄膜晶体管阵列基板的制作方法的步骤S5制程的俯视示意图；
图13a与图13b为图12的剖视示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，本发明提供一种FFS型薄膜晶体管阵列基板的制作方法，包括如下步骤：
S1、如图2至图5所示，提供衬底基板10，采用第一道光罩工艺在所述衬底基板10上形成栅极21、扫描线22、公共电极23及公共电极线24；其中，所述栅极21与扫描线22相连，所述公共电极23与公共电极线24相连。
具体的，采用第一道光罩工艺在所述衬底基板10上形成栅极21、扫描线22、公共电极23及公共电极线24的步骤包括：
S11、如图2与图3所示，在所述衬底基板10上沉积第一透明导电层11，采用第一道光罩工艺对所述第一透明导电层11进行图形化处理，得到栅极预定图案15与扫描线预定图案16以及公共电极23与公共电极线24；
S12、如图4与图5所示，在所述栅极预定图案15与扫描线预定图案16上镀上第一金属层12，得到栅极21与扫描线22，其中，所述第一金属层12的导电性能大于所述第一透明导电层11的导电性能。
具体的，所述第一透明导电层11的材料包括透明导电金属氧化物，如氧化铟锡(ITO)，所述第一透明导电层11的沉积方法为物理气相沉积法(PVD)。
具体的，所述第一金属层12的材料包括铜。
由于公共电极23与公共电极线24不需要具有低电阻，因此，仅由第一透明导电层11构成即可满足其电学性能要求；由于栅极21与扫描线22需要具有低电阻，因此在第一透明导电层11上镀上导电性能更好的第一金属层12(优选为铜)来制备栅极21与扫描线22，能够降低其电阻值，使其满足相应的电学性能要求。
具体的，在所述栅极预定图案15与扫描线预定图案16上镀上第一金属层12的工艺为电镀工艺。电镀过程中，对所述栅极预定图案15与扫描线预定图案16通电，对所述公共电极23与公共电极线24不通电，即可实现只在栅极预定图案15与扫描线预定图案16镀上第一金属层12而不在公 共电极23与公共电极线24镀上第一金属层12。
具体的，本发明通过在栅极预定图案15与扫描线预定图案16上镀上第一金属层12，可以提升制得的栅极21与扫描线22的导电性能。
具体的，所述衬底基板10为玻璃基板。
具体的，所述第一道光罩工艺包括涂光阻、曝光、显影、湿蚀刻及光阻剥离制程。
S2、如图6与图7所示，在所述栅极21、扫描线22、公共电极23、公共电极线24及衬底基板10上沉积栅极绝缘层30，在所述栅极绝缘层30上沉积半导体层35，采用第二道光罩工艺对所述半导体层35进行图形化处理，得到对应于所述栅极21上方的有源层40。
具体的，所述栅极绝缘层30的材料包括氧化硅(SiOx)与氮化硅(SiNx)中的一种或多种。
具体的，所述半导体层35的材料包括非晶硅、多晶硅及金属氧化物中的一种或多种。
具体的，所述栅极绝缘层30与半导体层35的沉积方法均为化学气相沉积法(CVD)。
具体的，所述第二道光罩工艺包括涂光阻、曝光、显影、干蚀刻及光阻剥离制程。
S3、如图8与图9所示，在所述有源层40与栅极绝缘层30上沉积源漏极金属层45，采用第三道光罩工艺对所述源漏极金属层45进行图形化处理，得到源极51、漏极52及数据线53；其中，所述源极51与漏极52分别与所述有源层40相接触，所述数据线53与所述源极51相连。
具体的，所述源漏极金属层45的沉积方法为物理气相沉积方法(PVD)。
具体的，所述第三道光罩工艺包括涂光阻、曝光、显影、湿蚀刻及光阻剥离制程。
S4、如图10与图11a所示，在所述源极51、漏极52、数据线53、有源层40及栅极绝缘层30上形成钝化层60，采用第四道光罩工艺对所述钝化层60进行图形化处理，得到位于所述钝化层60上的第一通孔61，所述第一通孔61对应于所述漏极52上方设置；
或者，如图10与图11b所示，在所述源极51、漏极52、数据线53、有源层40及栅极绝缘层30上形成钝化层60与设于所述钝化层60上的平坦层70，采用第四道光罩工艺对所述钝化层60和平坦层70进行图形化处理，得到位于所述钝化层60和平坦层70上的第二通孔72，所述第二通孔72对应于所述漏极52上方设置。
具体的，所述钝化层60的材料包括氧化硅(SiOx)与氮化硅(SiNx)中的一种或多种，所述钝化层60的形成方法为化学气相沉积法(CVD)。
具体的，所述平坦层70的材料为有机光阻材料，所述平坦层70的形成方法为涂膜工艺。
具体的，所述步骤S4中，如图10与图11a所示，在所述源极51、漏极52、数据线53、有源层40及栅极绝缘层30上形成钝化层60后，所述第四道光罩工艺包括涂光阻、曝光、显影、干蚀刻及光阻剥离制程。
如图10与图11b所示，在所述源极51、漏极52、数据线53、有源层40及栅极绝缘层30上形成钝化层60与设于所述钝化层60上的平坦层70后，所述第四道光罩工艺包括曝光、显影及干蚀刻制程。
具体的，通过在所述钝化层60上引入平坦层70，可以提高后续制作的像素电极80的平坦性，进而提升液晶显示面板的稳定性。
S5、如图12与图13a所示，在所述钝化层60上沉积第二透明导电层75，采用第五道光罩工艺对所述第二透明导电层75进行图形化处理，得到位于所述钝化层60上的像素电极80，所述像素电极80通过位于所述钝化层60上的第一通孔61与所述漏极52相连；
或者，如图12与图13b所示，在所述平坦层70上沉积第二透明导电层75，采用第五道光罩工艺对所述第二透明导电层75进行图形化处理，得到位于所述平坦层70上的像素电极80，所述像素电极80通过位于所述钝化层60与平坦层70上的第二通孔72与所述漏极52相连。
具体的，所述第二透明导电层75的材料包括透明导电金属氧化物，如氧化铟锡(ITO)，所述第二透明导电层75的沉积方法为物理气相沉积法(PVD)。
具体的，所述第五道光罩工艺包括涂光阻、曝光、显影、湿蚀刻及光阻剥离制程。
本发明的FFS型薄膜晶体管阵列基板的制作方法包括：在一道光罩工艺中形成栅极21、扫描线22、公共电极23及公共电极线24，与现有技术相比，简化了工艺制程，采用的光罩数量较少，制程时间较短，因此生产成本低。
请参阅图12、图13a与图13b，基于上述FFS型薄膜晶体管阵列基板的制作方法，本发明还提供一种FFS型薄膜晶体管阵列基板，包括：
衬底基板10；
设于所述衬底基板10上的栅极21、扫描线22、公共电极23及公共电极线24；其中，所述栅极21与扫描线22相连，所述公共电极23与公共电 极线24相连；
设于所述栅极21、扫描线22、公共电极23、公共电极线24及衬底基板10上的栅极绝缘层30；
设于所述栅极绝缘层30上且对应于所述栅极21上方的有源层40；
设于所述有源层40与栅极绝缘层30上的源极51与漏极52、设于所述栅极绝缘层30上的数据线53；其中，所述源极51与漏极52分别与所述有源层40相接触，所述数据线53与所述源极51相连；
设于所述源极51、漏极52、数据线53、有源层40及栅极绝缘层30上的钝化层60，所述钝化层60上设有对应于所述漏极52上方设置的第一通孔61；以及设于所述钝化层60上的像素电极80，所述像素电极80通过位于所述钝化层60上的第一通孔61与所述漏极52相连(如图13a所示)；或者，
设于所述源极51、漏极52、数据线53、有源层40及栅极绝缘层30上的钝化层60与设于所述钝化层60上的平坦层70，所述钝化层60和平坦层70上设有对应于所述漏极52上方设置的第二通孔72；以及设于所述平坦层70上的像素电极80，所述像素电极80通过位于所述钝化层60与平坦层70上的第二通孔72与所述漏极52相连(如图13b所示)。
具体的，所述公共电极23与公共电极线24包括设于所述衬底基板10上的第一透明导电层11，所述栅极21与扫描线22包括设于所述衬底基板10上的第一透明导电层11与设于所述第一透明导电层11上的第一金属层12；其中，所述第一金属层12的导电性能大于所述第一透明导电层11的导电性能。
具体的，所述第一透明导电层11的材料包括透明导电金属氧化物，如氧化铟锡(ITO)。
具体的，所述第一金属层12的材料包括铜。
具体的，所述衬底基板10为玻璃基板。
具体的，所述栅极绝缘层30的材料包括氧化硅(SiOx)与氮化硅(SiNx)中的一种或多种。
具体的，所述有源层40的材料包括非晶硅、多晶硅及金属氧化物中的一种或多种。
具体的，所述钝化层60的材料包括氧化硅(SiOx)与氮化硅(SiNx)中的一种或多种，所述平坦层70的材料为有机光阻材料。
具体的，所述像素电极80的材料包括透明导电金属氧化物，如氧化铟锡(ITO)。
本发明的FFS型薄膜晶体管阵列基板的制作工艺简单，生产成本低，且具有优异的电学性能。
综上所述，本发明提供一种FFS型薄膜晶体管阵列基板及其制作方法。本发明的FFS型薄膜晶体管阵列基板的制作方法包括：在一道光罩工艺中形成栅极、扫描线、公共电极及公共电极线，与现有技术相比，简化了工艺制程，采用的光罩数量较少，制程时间较短，因此生产成本低。本发明的FFS型薄膜晶体管阵列基板的制作工艺简单，生产成本低，且具有优异的电学性能。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (12)

  1. 一种FFS型薄膜晶体管阵列基板的制作方法，包括：
    提供衬底基板，采用第一道光罩工艺在所述衬底基板上形成栅极、扫描线、公共电极及公共电极线；其中，所述栅极与扫描线相连，所述公共电极与公共电极线相连；
    在所述栅极、扫描线、公共电极、公共电极线及衬底基板上沉积栅极绝缘层，在所述栅极绝缘层上沉积半导体层，采用第二道光罩工艺对所述半导体层进行图形化处理，得到对应于所述栅极上方的有源层；
    在所述有源层与栅极绝缘层上沉积源漏极金属层，采用第三道光罩工艺对所述源漏极金属层进行图形化处理，得到源极、漏极及数据线；其中，所述源极与漏极分别与所述有源层相接触，所述数据线与所述源极相连；
    在所述源极、漏极、数据线、有源层及栅极绝缘层上形成钝化层，采用第四道光罩工艺对所述钝化层进行图形化处理，得到位于所述钝化层上的第一通孔，所述第一通孔对应于所述漏极上方设置；在所述钝化层上沉积第二透明导电层，采用第五道光罩工艺对所述第二透明导电层进行图形化处理，得到位于所述钝化层上的像素电极，所述像素电极通过位于所述钝化层上的第一通孔与所述漏极相连；或者，
    在所述源极、漏极、数据线、有源层及栅极绝缘层上形成钝化层与设于所述钝化层上的平坦层，采用第四道光罩工艺对所述钝化层和平坦层进行图形化处理，得到位于所述钝化层和平坦层上的第二通孔，所述第二通孔对应于所述漏极上方设置；在所述平坦层上沉积第二透明导电层，采用第五道光罩工艺对所述第二透明导电层进行图形化处理，得到位于所述平坦层上的像素电极，所述像素电极通过位于所述钝化层与平坦层上的第二通孔与所述漏极相连。
  2. 如权利要求1所述的FFS型薄膜晶体管阵列基板的制作方法，其中，采用第一道光罩工艺在所述衬底基板上形成栅极、扫描线、公共电极及公共电极线的步骤包括：
    在所述衬底基板上沉积第一透明导电层，采用第一道光罩工艺对所述第一透明导电层进行图形化处理，得到栅极预定图案与扫描线预定图案以及公共电极与公共电极线；
    在所述栅极预定图案与扫描线预定图案上镀上第一金属层，得到栅极与扫描线，其中，所述第一金属层的导电性能大于所述第一透明导电层的 导电性能。
  3. 如权利要求2所述的FFS型薄膜晶体管阵列基板的制作方法，其中，所述第一透明导电层的材料包括透明导电金属氧化物；所述第一金属层的材料包括铜。
  4. 如权利要求2所述的FFS型薄膜晶体管阵列基板的制作方法，其中，在所述栅极预定图案与扫描线预定图案上镀上第一金属层的工艺为电镀工艺。
  5. 如权利要求1所述的FFS型薄膜晶体管阵列基板的制作方法，其中，所述钝化层的材料包括氧化硅与氮化硅中的一种或多种，所述平坦层的材料为有机光阻材料。
  6. 如权利要求1所述的FFS型薄膜晶体管阵列基板的制作方法，其中，在所述源极、漏极、数据线、有源层及栅极绝缘层上形成钝化层后，所述第四道光罩工艺包括涂光阻、曝光、显影、干蚀刻及光阻剥离制程；
    在所述源极、漏极、数据线、有源层及栅极绝缘层上形成钝化层与设于所述钝化层上的平坦层后，所述第四道光罩工艺包括曝光、显影及干蚀刻制程。
  7. 一种FFS型薄膜晶体管阵列基板，包括：
    衬底基板；
    设于所述衬底基板上的栅极、扫描线、公共电极及公共电极线；其中，所述栅极与扫描线相连，所述公共电极与公共电极线相连；
    设于所述栅极、扫描线、公共电极、公共电极线及衬底基板上的栅极绝缘层；
    设于所述栅极绝缘层上且对应于所述栅极上方的有源层；
    设于所述有源层与栅极绝缘层上的源极与漏极、设于所述栅极绝缘层上的数据线；其中，所述源极与漏极分别与所述有源层相接触，所述数据线与所述源极相连；
    设于所述源极、漏极、数据线、有源层及栅极绝缘层上的钝化层，所述钝化层上设有对应于所述漏极上方设置的第一通孔；以及设于所述钝化层上的像素电极，所述像素电极通过位于所述钝化层上的第一通孔与所述漏极相连；或者，
    设于所述源极、漏极、数据线、有源层及栅极绝缘层上的钝化层与设于所述钝化层上的平坦层，所述钝化层和平坦层上设有对应于所述漏极上方设置的第二通孔；以及设于所述平坦层上的像素电极，所述像素电极通过位于所述钝化层与平坦层上的第二通孔与所述漏极相连。
  8. 如权利要求7所述的FFS型薄膜晶体管阵列基板，其中，所述公共电极与公共电极线包括设于所述衬底基板上的第一透明导电层，所述栅极与扫描线包括设于所述衬底基板上的第一透明导电层与设于所述第一透明导电层上的第一金属层；其中，所述第一金属层的导电性能大于所述第一透明导电层的导电性能。
  9. 如权利要求8所述的FFS型薄膜晶体管阵列基板，其中，所述第一透明导电层的材料包括透明导电金属氧化物；所述第一金属层的材料包括铜。
  10. 如权利要求7所述的FFS型薄膜晶体管阵列基板，其中，所述钝化层的材料包括氧化硅与氮化硅中的一种或多种，所述平坦层的材料为有机光阻材料。
  11. 一种FFS型薄膜晶体管阵列基板的制作方法，包括：
    提供衬底基板，采用第一道光罩工艺在所述衬底基板上形成栅极、扫描线、公共电极及公共电极线；其中，所述栅极与扫描线相连，所述公共电极与公共电极线相连；
    在所述栅极、扫描线、公共电极、公共电极线及衬底基板上沉积栅极绝缘层，在所述栅极绝缘层上沉积半导体层，采用第二道光罩工艺对所述半导体层进行图形化处理，得到对应于所述栅极上方的有源层；
    在所述有源层与栅极绝缘层上沉积源漏极金属层，采用第三道光罩工艺对所述源漏极金属层进行图形化处理，得到源极、漏极及数据线；其中，所述源极与漏极分别与所述有源层相接触，所述数据线与所述源极相连；
    在所述源极、漏极、数据线、有源层及栅极绝缘层上形成钝化层，采用第四道光罩工艺对所述钝化层进行图形化处理，得到位于所述钝化层上的第一通孔，所述第一通孔对应于所述漏极上方设置；在所述钝化层上沉积第二透明导电层，采用第五道光罩工艺对所述第二透明导电层进行图形化处理，得到位于所述钝化层上的像素电极，所述像素电极通过位于所述钝化层上的第一通孔与所述漏极相连；或者，
    在所述源极、漏极、数据线、有源层及栅极绝缘层上形成钝化层与设于所述钝化层上的平坦层，采用第四道光罩工艺对所述钝化层和平坦层进行图形化处理，得到位于所述钝化层和平坦层上的第二通孔，所述第二通孔对应于所述漏极上方设置；在所述平坦层上沉积第二透明导电层，采用第五道光罩工艺对所述第二透明导电层进行图形化处理，得到位于所述平坦层上的像素电极，所述像素电极通过位于所述钝化层与平坦层上的第二通孔与所述漏极相连；
    其中，采用第一道光罩工艺在所述衬底基板上形成栅极、扫描线、公共电极及公共电极线的步骤包括：
    在所述衬底基板上沉积第一透明导电层，采用第一道光罩工艺对所述第一透明导电层进行图形化处理，得到栅极预定图案与扫描线预定图案以及公共电极与公共电极线；
    在所述栅极预定图案与扫描线预定图案上镀上第一金属层，得到栅极与扫描线，其中，所述第一金属层的导电性能大于所述第一透明导电层的导电性能；
    其中，所述第一透明导电层的材料包括透明导电金属氧化物；所述第一金属层的材料包括铜；
    其中，在所述栅极预定图案与扫描线预定图案上镀上第一金属层的工艺为电镀工艺；
    其中，所述钝化层的材料包括氧化硅与氮化硅中的一种或多种，所述平坦层的材料为有机光阻材料。
  12. 如权利要求11所述的FFS型薄膜晶体管阵列基板的制作方法，其中，在所述源极、漏极、数据线、有源层及栅极绝缘层上形成钝化层后，所述第四道光罩工艺包括涂光阻、曝光、显影、干蚀刻及光阻剥离制程；
    在所述源极、漏极、数据线、有源层及栅极绝缘层上形成钝化层与设于所述钝化层上的平坦层后，所述第四道光罩工艺包括曝光、显影及干蚀刻制程。
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