CN108140646A - 阵列基板制造方法 - Google Patents

阵列基板制造方法 Download PDF

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CN108140646A
CN108140646A CN201680049260.5A CN201680049260A CN108140646A CN 108140646 A CN108140646 A CN 108140646A CN 201680049260 A CN201680049260 A CN 201680049260A CN 108140646 A CN108140646 A CN 108140646A
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何家伟
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Shenzhen Royole Technologies Co Ltd
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Abstract

提供一种阵列基板制造方法，包括提供一形成有显示区及走线区的基板；其中显示区形成有源极及漏极，走线区形成有外围桥接金属线；在显示区的源极及漏极及走线区形的外围桥接金属线上形成绝缘层及层叠于绝缘层的光阻层；通过半色调掩膜图案化光阻层，在光阻层上形成位于显示区的第一过孔定义区及位于走线区的第二孔定义区；其中第一过孔定义区到绝缘层的厚度大于第二过孔定义区到绝缘层的厚度；蚀刻第一过孔定义区及第二孔定义区，以形成于源极或漏极连接的第一过孔及与外围桥接金属线连接的第二过孔；去除光阻层。

Description

阵列基板制造方法
技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板制造方法。
背景技术
在阵列基板的制程中，阵列基板的电极层需要连接到显示区的源/漏极以及外围区的金属走线层上，通过连接金属来导通电路，因此需要在显示区的绝缘层用干蚀刻的方式打孔才可以连通。现有的干刻方法可用物理垂直轰击法和光阻后退法；由于源/漏极处开孔比栅极所处位置的孔少一层有源层，在走线区的孔完成时显示区的源/漏极金属层已经被轰击过度会造成损伤。
发明内容
基于上述问题，本申请提供一种阵列基板制造方法，减少因蚀刻对所述显示区的源漏极的损伤。
本申请提供的一种阵列基板制造方法，包括提供一形成有显示区及走线区的基板；其中显示区形成有源极及漏极，所述走线区形成有外围桥接金属线；
在所述显示区的源极及漏极及所述走线区形的外围桥接金属线上形成绝缘层及层叠于所述绝缘层的光阻层；
通过半色调掩膜图案化所述光阻层，在所述光阻层上形成位于所述显示区的第一过孔定义区及位于所述走线区的第二孔定义区；其中第一过孔定义区到所述绝缘层的厚度大于所述第二过孔定义区到所述绝缘层的厚度；
蚀刻所述第一过孔定义区及第二孔定义区，以形成于所述源极或漏极连接的第一过孔及与所述外围桥接金属线连接的第二过孔；
去除光阻层。
其中，所述步骤通过半色调掩膜图案化所述光阻层，在所述光阻层上形成位于所述显示区的第一过孔定义区及位于所述走线区的第二孔定义区，包括：
提供包括遮光区、全透区及半透区的所述半色调掩膜，
光照所述半色调掩膜，在所述光阻层上对应所述半透区的位置形成所述第一过孔定义区图案，对应所述全透区的位置形成所述第二孔定义区图案；
去除半色调掩膜并通过显影在所述光阻层上形成所述第一过孔定义区及第二孔定义区。
其中，所述第二孔定义区露出所述绝缘层。
其中，所述步骤蚀刻所述第一过孔定义区及第二孔定义区，是通过物理垂直轰击方式对所述第一过孔定义区及第二孔定义区同时干刻。
其中，所述显示区形成有栅极及与源极及漏极连接的半导体层，所述走线区的外围桥接金属线与所述栅极位于同一层并同时形成。
其中，所述方法包括在形成有第一过孔及第二过孔的绝缘层上形成像素电极层，所述像素电极层通过所述第一过孔与所述源极或漏极连接，通过第二过孔与所述外围桥接金属线连接。
其中，所述步骤蚀刻所述第一过孔定义区及第二孔定义区中，蚀刻的时间相同。
其中，所述光阻层的厚度为2.0μm。
本申请所述的阵列基板制造方法中，采用半色调掩膜先定义出第一过孔区域与第二过孔区域，第一过孔区域与第二过孔区域到绝缘层的厚度不相同，在蚀刻的过程中，第一过孔与第二过孔同时蚀刻形成，如此就不会因为蚀刻工艺而损伤源极或者漏极。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请的阵列基板制造方法流程图。
图2至图6是本申请阵列基板制作方法的各个步骤的基板截面示意图。
具体实施方式
下面将结合本申请实施方式中的附图，对本申请实施方式中的技术方案进行清楚、完整地描述。
请参阅图1与图2，本申请提供一种阵列基板制造方法，用于制造OLED(OrganicLight-Emitting Diode,有机发光二极管)显示器的阵列基板，其包括：
步骤S1，提供一形成有显示区A及走线区P的基板10；其中显示区A形成有源极15及漏极16，所述走线区P形成有外围桥接金属线20。
具体的，所述基板10为玻璃基板。基板10上位于所述显示区A形成有栅极14及与源极15及漏极16连接的半导体层17，所述走线区P的外围桥接金属线20与所述栅极14位于同一层并同时形成。栅极14及外围桥接金属线20上覆盖有栅极绝缘层141，半导体层17形成于栅极绝缘层141上与栅极14相对位置。其中，栅极14、源极15、漏极16、半导体层17及外围桥接金属线20通过光罩显影蚀刻等制图工艺形成，在此不做赘述。
请参阅图3，步骤S2，在所述显示区A的源极15及漏极16及所述走线区P形的外围桥接金属线20上形成绝缘层12及层叠于所述绝缘层12的光阻层13。其中，所述光阻层的厚度为2.0μm，此厚度适中，便于通过进行半色调掩膜光罩图案工艺。
请参阅图4，步骤S3，通过半色调掩膜30图案化所述光阻层13，在所述光阻层13上形成位于所述显示区A的第一过孔定义区131及位于所述走线区P的第二孔定义区132；其中第一过孔定义区131到所述绝缘层的厚度大于所述第二过孔定义区132到所述绝缘层12的厚度。具体的，包括：
提供包括遮光区31、全透区32及半透区33的所述半色调掩膜30。
光照所述半色调掩膜30，在所述光阻层13上对应所述半透区33的位置形成所述第一过孔定义区图案，对应所述全透区32的位置形成所述第二孔定义区图案；
去除半色调掩膜并通过显影在所述光阻层13上形成所述第一过孔定义区131及第二孔定义区132。如此就使所述第一过孔定义区的光阻层并未全部去除而保留覆盖所述源极或者漏极的部分。本实施例中，所述第二孔定义区132露出所述绝缘层12。在其它实施方式中，所述第二孔定义区132与所述绝缘层12也可以保光阻层部分，只要保证在蚀刻时第一过孔区域的光阻层可以保护所述源极及漏极即可。
请参阅图5，步骤S4，蚀刻所述第一过孔定义区131及第二孔定义区132，以形成于所述源极15或漏极16连接的第一过孔133及与所述外围桥接金属线20连接的第二过孔134。本步骤中，蚀刻主要指干蚀刻，具体采用的是通过物理垂直轰击方式对所述第一过孔定义区131及第二孔定义区132同时干刻，并且采用相同的时间，形成贯穿所述绝缘层12的第一过孔133及贯穿所述绝缘层12及栅极绝缘层141的第二过孔134。
所述的物理垂直轰击法时调大上下电极间电压，使粒子在电场中受到较大力获得较大动能垂直轰击基板。现有技术中，物理轰击法会由于源极或漏极处开孔比外围桥接金属线处少一层栅极绝缘层，从而在走线P的第二过孔打好时，显示区的第一过孔位置已经对源极或漏极的金属层造成损伤，而现有技术的光阻后退法会对光阻进行蚀刻从而使得连接像素电极与源极/漏极的尺寸相对较大，为了保证与源漏极的接触，源漏极的面积也会随之增大面积，从而影响透光率。而本申请所述的阵列基板制造方法中，采用半色调掩膜先定义出第一过孔与第二过孔区域，第一过孔区域不贯穿所述光阻层，那么在蚀刻的过程中，第一过孔区域不贯穿所述光阻层的部分作为遮挡部分，当第二过孔134贯穿所述绝缘层12及栅极绝缘层141时，第一过孔133刚好贯穿第一过孔区域的剩余遮挡部分及绝缘层而露出所源极或者漏极，如此就不会因为蚀刻工艺而损伤源极或者漏极。同时避免了光阻后退法对于开口率的降低。
请参阅图6，步骤S5，去除光阻层13。
步骤S6，在形成有第一过孔133及第二过孔134的绝缘层13上形成像素电极层18，所述像素电极层18通过所述第一过孔133与所述源极15或漏极16连接，通过第二过孔134与所述外围桥接金属线20连接。
以上所述是本申请的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本申请的保护范围。

Claims (8)

1.一种阵列基板制造方法，其特征在于，包括提供一形成有显示区及走线区的基板；其中显示区形成有源极及漏极，所述走线区形成有外围桥接金属线；
在所述显示区的源极及漏极及所述走线区形的外围桥接金属线上形成绝缘层及层叠于所述绝缘层的光阻层；
通过半色调掩膜图案化所述光阻层，在所述光阻层上形成位于所述显示区的第一过孔定义区及位于所述走线区的第二孔定义区；其中第一过孔定义区到所述绝缘层的厚度大于所述第二过孔定义区到所述绝缘层的厚度；
蚀刻所述第一过孔定义区及第二孔定义区，以形成于所述源极或漏极连接的第一过孔及与所述外围桥接金属线连接的第二过孔；
去除光阻层。
2.如权利要求1所述的阵列基板制造方法，其特征在于，所述步骤通过半色调掩膜图案化所述光阻层，在所述光阻层上形成位于所述显示区的第一过孔定义区及位于所述走线区的第二孔定义区，包括：
提供包括遮光区、全透区及半透区的所述半色调掩膜，
光照所述半色调掩膜，在所述光阻层上对应所述半透区的位置形成所述第一过孔定义区图案，对应所述全透区的位置形成所述第二孔定义区图案；
去除半色调掩膜并通过显影在所述光阻层上形成所述第一过孔定义区及第二孔定义区。
3.如权利要求2所述的阵列基板制造方法，其特征在于，所述第二孔定义区露出所述绝缘层。
4.如权利要求1所述的阵列基板制造方法，其特征在于，所述步骤蚀刻所述第一过孔定义区及第二孔定义区，是通过物理垂直轰击方式对所述第一过孔定义区及第二孔定义区同时干刻。
5.如权利要求1所述的阵列基板制造方法，其特征在于，所述显示区形成有栅极及与源极及漏极连接的半导体层，所述走线区的外围桥接金属线与所述栅极位于同一层并同时形成。
6.如权利要求1所述的阵列基板制造方法，其特征在于，所述方法包括在形成有第一过孔及第二过孔的绝缘层上形成像素电极层，所述像素电极层通过所述第一过孔与所述源极或漏极连接，通过第二过孔与所述外围桥接金属线连接。
7.如权利要求4所述的阵列基板制造方法，其特征在于，所述步骤蚀刻所述第一过孔定义区及第二孔定义区中，蚀刻的时间相同。
8.如权利要求1所述的阵列基板制造方法，其特征在于，所述光阻层的厚度为2.0μm。
CN201680049260.5A 2016-12-24 2016-12-24 阵列基板制造方法 Pending CN108140646A (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020047882A1 (zh) * 2018-09-03 2020-03-12 深圳市华星光电半导体显示技术有限公司 一种阵列基板及其制备方法、显示面板
CN111769044A (zh) * 2020-05-27 2020-10-13 英诺赛科（珠海）科技有限公司 高电子迁移率晶体管及其制造方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113192426B (zh) * 2021-04-27 2023-08-25 Oppo广东移动通信有限公司 显示面板、显示模组及电子设备

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1804709A (zh) * 2000-05-12 2006-07-19 株式会社日立制作所 液晶显示装置及其制造方法
CN101614917A (zh) * 2008-06-25 2009-12-30 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法
CN104576542A (zh) * 2015-01-26 2015-04-29 合肥鑫晟光电科技有限公司 阵列基板及其制作方法、显示装置
CN104576523A (zh) * 2013-10-16 2015-04-29 北京京东方光电科技有限公司 一种阵列基板及其制作方法和显示装置
CN104637874A (zh) * 2015-03-16 2015-05-20 京东方科技集团股份有限公司 阵列基板及其制作方法
CN105514032A (zh) * 2016-01-11 2016-04-20 深圳市华星光电技术有限公司 Ips型tft-lcd阵列基板的制作方法及ips型tft-lcd阵列基板
CN105679714A (zh) * 2016-01-27 2016-06-15 深圳市华星光电技术有限公司 阵列基板及其制作方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100511651C (zh) * 2006-01-27 2009-07-08 胜华科技股份有限公司 薄膜晶体管阵列基板及其制作方法
CN101090095A (zh) * 2006-06-15 2007-12-19 中华映管股份有限公司 主动组件数组基板及其制造方法
CN101330062B (zh) * 2008-07-25 2010-08-18 友达光电股份有限公司 薄膜晶体管阵列基板的制作方法
CN102832226B (zh) * 2011-10-06 2016-06-01 友达光电股份有限公司 主动元件阵列基板及其制造方法
CN103489826B (zh) * 2013-09-26 2015-08-05 京东方科技集团股份有限公司 阵列基板、制备方法以及显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1804709A (zh) * 2000-05-12 2006-07-19 株式会社日立制作所 液晶显示装置及其制造方法
CN101614917A (zh) * 2008-06-25 2009-12-30 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法
CN104576523A (zh) * 2013-10-16 2015-04-29 北京京东方光电科技有限公司 一种阵列基板及其制作方法和显示装置
CN104576542A (zh) * 2015-01-26 2015-04-29 合肥鑫晟光电科技有限公司 阵列基板及其制作方法、显示装置
CN104637874A (zh) * 2015-03-16 2015-05-20 京东方科技集团股份有限公司 阵列基板及其制作方法
CN105514032A (zh) * 2016-01-11 2016-04-20 深圳市华星光电技术有限公司 Ips型tft-lcd阵列基板的制作方法及ips型tft-lcd阵列基板
CN105679714A (zh) * 2016-01-27 2016-06-15 深圳市华星光电技术有限公司 阵列基板及其制作方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020047882A1 (zh) * 2018-09-03 2020-03-12 深圳市华星光电半导体显示技术有限公司 一种阵列基板及其制备方法、显示面板
CN111769044A (zh) * 2020-05-27 2020-10-13 英诺赛科（珠海）科技有限公司 高电子迁移率晶体管及其制造方法

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