WO2019041829A1 - 薄膜晶体管及制作方法、显示基板及制作方法、显示装置 - Google Patents

薄膜晶体管及制作方法、显示基板及制作方法、显示装置 Download PDF

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WO2019041829A1
WO2019041829A1 PCT/CN2018/083535 CN2018083535W WO2019041829A1 WO 2019041829 A1 WO2019041829 A1 WO 2019041829A1 CN 2018083535 W CN2018083535 W CN 2018083535W WO 2019041829 A1 WO2019041829 A1 WO 2019041829A1
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pattern
conductive
gate
layer
thin film
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PCT/CN2018/083535
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English (en)
French (fr)
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刘威
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京东方科技集团股份有限公司
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Priority to US16/326,257 priority Critical patent/US10943984B2/en
Publication of WO2019041829A1 publication Critical patent/WO2019041829A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present disclosure relates to the field of display devices, and in particular, to a thin film transistor and a method of fabricating the same, a display substrate, a method of fabricating the same, and a display device.
  • TFT Thin Film Transistor
  • Embodiments of the present disclosure provide a thin film transistor, a method of fabricating the same, a display substrate, a method of fabricating the same, and a display device.
  • an embodiment of the present disclosure provides a thin film transistor including an active layer pattern disposed on a substrate, a gate insulating pattern disposed on the active layer pattern, and a gate insulating pattern disposed on the gate insulating pattern Upper gate;
  • a conductive pattern is disposed between the gate and the gate insulating pattern, and the conductive pattern is electrically connected to the gate;
  • the conductive pattern coincides with an orthographic projection of the gate insulating pattern on the base substrate.
  • the gate and the orthographic projection of the conductive pattern on the substrate are not completely coincident (the orthographic projection of the gate on the substrate is located within the orthographic projection of the conductive pattern on the substrate) ).
  • the conductive pattern comprises a non-metallic conductive material.
  • the conductive pattern comprises a graphene material or a carbon nanotube.
  • a buffer layer is further disposed between the substrate substrate and the active layer pattern.
  • the thin film transistor further includes an interlayer dielectric layer covering the gate, and a source and a drain disposed on the interlayer dielectric layer, wherein the source and the drain respectively pass A hole is electrically connected to the active layer pattern.
  • an embodiment of the present disclosure provides a display substrate, including the thin film transistor of any one of the above.
  • the display substrate further includes a pixel electrode, and the pixel electrode is disposed in the same material as the conductive pattern;
  • the pixel electrode is electrically connected to a drain of the thin film transistor.
  • the display substrate further includes a first insulation pattern, and the first insulation pattern is disposed in the same layer as the gate insulation pattern.
  • the display substrate further includes a color film disposed between the first insulation pattern and the pixel electrode.
  • the display substrate further includes an etch stop retention pattern disposed at an edge position of the pixel electrode;
  • the etch stop retention pattern is disposed in the same material as the gate.
  • the display substrate further includes a passivation layer covering the thin film transistor, and a pixel defining layer disposed on the passivation layer.
  • an embodiment of the present disclosure provides a display device comprising the display substrate of any one of the above.
  • an embodiment of the present disclosure provides a method of fabricating a thin film transistor, including:
  • the conductive pattern coincides with an orthographic projection of the gate insulating pattern on the substrate; and the gate is located on the conductive pattern and is electrically connected to the conductive pattern.
  • the forming the gate insulating pattern, the conductive pattern, and the gate layer which are sequentially stacked and distributed include:
  • the insulating film and the first conductive film are etched by a dry etching process to form the gate insulating pattern and the conductive pattern.
  • the method further includes:
  • the method further includes:
  • a source and a drain are formed on the interlayer dielectric layer, and the source and the drain are electrically connected to the active layer pattern through via holes, respectively.
  • an embodiment of the present disclosure provides a method for fabricating a display substrate, including:
  • the first conductive layer includes a conductive pattern and a pixel electrode
  • the second conductive layer includes a gate and an etch barrier retention pattern
  • the conductive pattern and the gate insulating pattern are positive on the substrate
  • the projections coincide, and the gate is on the conductive pattern and is electrically connected to the conductive pattern.
  • the method further includes:
  • a pixel defining layer is formed on the passivation layer.
  • FIG. 1 is a schematic cross-sectional structural view of a top gate TFT provided by the related art
  • FIG. 2 is a schematic cross-sectional structural view of a top gate TFT according to an embodiment of the present disclosure
  • FIG. 3 is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 5 is a third schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 8 is a cross-sectional structural view 6 of a display substrate according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic cross-sectional view IX of a display substrate according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 13 is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 14 is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 15 is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure.
  • 16 is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 17 is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 1 shows a top gate TFT in the related art, comprising an active layer pattern 02 formed on a base substrate 01, a gate insulating pattern 03 formed on the active layer pattern 02, formed in a gate insulating layer A gate electrode 04 on the pattern 03, and a source electrode 05 and a drain electrode 06 connected to the active layer pattern 02 through via holes.
  • the gate electrode 04 is usually formed by a wet etching process, and the gate insulating pattern 03 is patterned by dry etching.
  • the gate electrode 04 is shorter than the gate insulating pattern 03.
  • the small distance that is, the orthographic projection of the gate electrode 04 and the gate insulating pattern 03 on the substrate substrate 01 cannot completely coincide. Since the gate electrode 04 is not above the small distance, the active layer pattern 02 under the gate insulating pattern 03 lacking the gate 04 coverage is not regulated by the gate electrode 04, thereby causing insufficient opening current of the TFT of the top gate structure. Thereby affecting the electrical characteristics of the top gate TFT, the display effect of the display device is also affected.
  • An embodiment of the present disclosure provides a thin film transistor including, as shown in FIG. 2, an active layer pattern 121 disposed on a base substrate 11, a gate insulating pattern 131 disposed on the active layer pattern 121, and a gate insulating pattern 131 disposed on the gate a gate electrode 141 on the pole insulating pattern 131; a conductive pattern 151 disposed between the gate electrode 141 and the gate insulating pattern 131, the conductive pattern 151 being electrically connected to the gate electrode 141; the conductive pattern 151 and the gate insulating pattern 131 on the base substrate
  • the orthographic projections on 11 coincide.
  • the thin film transistor is a TFT of a top gate structure, and the TFT may be an oxide TFT or a polysilicon TFT, which is not limited in the embodiment of the present disclosure.
  • Oxide TFTs are preferred for the production of large-size, high-resolution AMOLED (Active Matrix Organic Light Emitting Diode) display devices due to their low parasitic capacitance and excellent electrical characteristics.
  • An oxide TFT of course, an oxide TFT can also be applied to other display devices.
  • the insulating film 13, the first conductive film 15, and the second conductive film may be sequentially formed on the base substrate 11 including the active layer pattern 121. 14, as shown in FIG. 7; then coating photoresist 30 (as shown in FIG. 8), exposing, developing, and etching the second conductive film 14 by a wet etching process to form a gate electrode 141, as shown in FIG.
  • the insulating film 13 and the first conductive film 15 are then etched by a dry etching process to form a gate insulating pattern 131 and a conductive pattern 151, as shown in FIG. 10; finally, the photoresist on the gate 141 is stripped off. 30. Since the conductive pattern 151 and the gate insulating pattern 131 are both formed by etching by a dry etching process, the orthographic projection of the conductive pattern 151 and the gate insulating pattern 131 on the substrate substrate 11 can be ensured.
  • the thin film transistor provided by the embodiment of the present disclosure provides a conductive pattern by etching between the gate and the gate insulating pattern, since the gate can be formed by wet etching.
  • a conductive pattern and a gate insulating pattern by a dry etching process, thereby ensuring an orthographic projection of the conductive pattern and the gate insulating pattern on the substrate, that is, a position on the upper surface of the gate insulating pattern
  • a conductive pattern that compensates for a defect of no gate at a small distance above the edge of the gate insulating pattern in the related art, so that the corresponding active layer pattern region under the entire gate insulating pattern can be regulated, such that The electrical characteristics of the thin film transistor are enhanced, and the display effect of the display device is improved.
  • the conductive pattern 151 is composed of a non-metallic conductive material. This can prevent the etching liquid from affecting the conductive pattern 151 when the gate metal is etched by the wet etching process. Since both the graphene material and the carbon nanotube network have good electrical conductivity, in one embodiment, the conductive pattern 151 includes a graphene material or a carbon nanotube network.
  • a buffer layer 16 is further disposed between the base substrate 11 and the active layer pattern 121; the thin film transistor further includes an interlayer dielectric layer 17 covering the gate electrode 141, and is disposed on the interlayer dielectric layer 17
  • the source 181 and the drain 182, the source 181 and the drain 182 are connected to the active layer pattern 121 through via holes, respectively.
  • the buffer layer 16 is generally an inorganic thin film made of SiOx material for isolating the base substrate 11 to prevent impurity ions in the base substrate 11 from diffusing into the upper structure; the interlayer dielectric layer 17 is also called an insulating layer, usually It is made of insulating material and is generally used to isolate two adjacent conductive layers.
  • the display substrate may be a common array substrate, that is, an array substrate without a color film; and may be a COA (Color-filter on Array) substrate, which is not limited in the embodiment of the present disclosure.
  • the thin film transistor in the embodiment of the present disclosure compensates for a defect of no gate at a small distance above the edge of the gate insulating pattern in the related art by providing a conductive pattern between the gate and the gate insulating pattern, so that the entire gate is insulated.
  • the corresponding active layer pattern regions under the pattern can be adjusted, which enhances the electrical characteristics of the thin film transistor and improves the display effect of the display device.
  • the buffer layer 16 and the active layer pattern 121 may be sequentially formed on the base substrate 11, as shown in FIGS. 3 to 4.
  • the insulating film 13 , the color film 19 , the first conductive film 15 , and the second conductive film 14 may be sequentially formed on the base substrate 11 including the active layer pattern 121 , such as Figure 7; then coating the photoresist 30, exposing, developing, and etching the second conductive film 14 by a wet etching process to form a gate electrode 141 and an etch stop retention pattern 142, as shown in FIG.
  • the insulating film 13 and the first conductive film 15 are etched by a dry etching process to form a gate insulating pattern 131 and a conductive pattern 151, and a first insulating pattern 132 and a pixel electrode 152, as shown in FIG. 10; Engraved 30. Since the conductive pattern 151 and the gate insulating pattern 131 are both formed by etching by a dry etching process, the orthographic projection of the conductive pattern 151 and the gate insulating pattern 131 on the substrate substrate 11 can be ensured.
  • the display substrate includes a first insulation pattern 132, and the first insulation pattern 132 is disposed in the same layer as the gate insulation pattern 131.
  • the first insulating pattern 132 and the gate insulating pattern 131 are disposed in the same layer, it can be fabricated by one patterning process, which simplifies the manufacturing process and saves the manufacturing cost of the process.
  • the display substrate further includes a pixel electrode 152, and the pixel electrode 152 is disposed in the same material as the conductive pattern 151.
  • the pixel electrode 152 and the conductive pattern 151 are disposed in the same layer and the same material, it can be fabricated by one patterning process, which simplifies the manufacturing process and saves the manufacturing cost of the process. Since both the graphene material and the carbon nanotube network have better conductivity and transmittance, in one embodiment, the pixel electrode 152 and the conductive pattern 151 each include a graphene material or a carbon nanotube network.
  • the display substrate may include a plurality of OLED (Organic Light-Emitting Diode) devices, and the plurality of OLED devices may be arranged in an array. If the plurality of OLED devices are common cathodes (ie, the cathodes of the plurality of OLED devices are connected to form a full-surface electrode), the pixel electrode 152 is an anode of the OLED device; if the plurality of OLED devices are common anodes (ie, The anode connections of the plurality of OLED devices form a full-face electrode, and the pixel electrode 152 is the cathode of the OLED device.
  • OLED Organic Light-Emitting Diode
  • the color film 19 is disposed between the first insulating pattern 132 and the pixel electrode 152. It should be noted that, in practical applications, when three OLED sub-pixel luminescent layers in the display substrate emit light of different colors, it is not necessary to fabricate the color film 19.
  • the display substrate adopts a WOLED (white OLED) device, a color film 19 needs to be formed, but the color film 19 can be formed under the pixel electrode 152 (ie, the bottom emission structure, as shown in FIG. 11), or can be used in the light-emitting layer.
  • the upper side ie, the top emission structure
  • the embodiment of the present disclosure does not limit this. For convenience of description, the embodiment of the present disclosure is described by taking the color film 19 under the pixel electrode 152 (ie, the bottom emission structure) as an example.
  • the display substrate further includes an etch stop retention pattern 142 disposed on the pixel electrode 152; the etch barrier retention pattern 142 is disposed in the same material as the gate 141.
  • the etch barrier retention pattern 142 it is possible to prevent the pixel electrode 152 from being affected when the interlayer dielectric layer 17 is etched.
  • the etch barrier retention pattern 142 and the gate electrode 141 are disposed in the same layer and the same material, it can be fabricated by one patterning process, which simplifies the manufacturing process and saves the manufacturing cost.
  • the display substrate further includes a passivation layer 20 covering the thin film transistor, and a pixel defining layer 21 disposed on the passivation layer 20.
  • the photoresist 30 is first coated, as shown in FIG. 13; then exposure and development are performed, and then the passivation layer 20 is etched by a dry etching process, as shown in FIG.
  • the etch stop retention pattern 142 is then etched using a wet etch process to expose the pixel electrode 152 as shown in FIG.
  • the drain 182 and the pixel electrode 152 are electrically connected by an etch stop retention pattern 142 located at an edge position of the pixel electrode 152.
  • a pixel defining layer 21 is formed on the passivation layer 20 as shown in FIG.
  • Another embodiment of the present disclosure provides a method for fabricating a thin film transistor, including:
  • Step 101 forming an active layer pattern 121 on the base substrate 11, as shown in FIG.
  • a semiconductor thin film may be formed on the base substrate 11, and then the active layer pattern 121 may be formed by performing a patterning process on the semiconductor thin film.
  • Step 102 forming a gate insulating pattern 131, a conductive pattern 151, and a gate electrode 141 which are sequentially stacked and distributed on the base substrate 11 including the active layer pattern 121.
  • the conductive pattern 151 and the gate insulating pattern 131 are on the base substrate 11.
  • the positive projections coincide; the gate 141 is located on the conductive pattern 151 and is electrically connected to the conductive pattern 151.
  • the insulating film 13, the first conductive film 15 and the second conductive film 14 are sequentially formed on the base substrate 11 including the active layer pattern 121, as shown in FIG. 5 and FIG. 7; then, the insulating film 13 is included.
  • the base substrate 11 of the first conductive film 15 and the second conductive film 14 is coated with a photoresist 30 as shown in FIG. 8; then exposed, developed, and etched the second conductive film 14 by a wet etching process.
  • a gate electrode 141 is formed as shown in FIG. 9; then the insulating film 13 and the first conductive film 15 are etched by a dry etching process to form a gate insulating pattern 131 and a conductive pattern 151, as shown in FIG. 10;
  • the photoresist 30 on the gate 141 is removed.
  • the conductive pattern 151 and the gate insulating pattern 131 are both formed by etching by a dry etching process, the orthographic projection of the conductive pattern 151 and the gate insulating pattern 131 on the substrate substrate 11 can be ensured, that is, the gate insulating film is insulated.
  • a conductive pattern 151 is present at various positions on the upper surface of the pattern 131.
  • the conductive pattern 151 compensates for a defect of no gate at a small distance above the edge of the gate insulating pattern in the related art, so that the entire gate insulating pattern corresponds to the lower surface.
  • the active layer pattern regions can be adjusted, which enhances the electrical characteristics of the thin film transistor and improves the display effect of the display device.
  • the method further includes:
  • Step 103 forming a buffer layer 16 on the base substrate 11, as shown in FIG. 3; wherein the buffer layer 16 is generally an inorganic thin film made of SiOx material.
  • the method further includes:
  • Step 104 forming an interlayer dielectric layer 17 covering the gate electrode 141, as shown in FIG. 12; wherein the interlayer dielectric layer 17 is also referred to as an insulating layer, and is usually composed of an insulating material.
  • Step 105 forming a source electrode 181 and a drain electrode 182 on the interlayer dielectric layer 17, and the source electrode 181 and the drain electrode 182 are electrically connected to the active layer pattern 121 through via holes, respectively, as shown in FIG.
  • a further embodiment of the present disclosure provides a method of fabricating a display substrate, including:
  • Step 201 forming a semiconductor layer on the base substrate 11, the semiconductor layer including the active layer pattern 121; as shown in FIG.
  • a semiconductor thin film may be formed on the base substrate 11, and then the semiconductor thin film is patterned to form a semiconductor layer, and the semiconductor layer includes an active layer pattern 121, as shown in FIG.
  • Step 202 forming an insulating layer, a first conductive layer, and a second conductive layer which are sequentially stacked and distributed on the base substrate 11 including the semiconductor layer; wherein the insulating layer includes a gate insulating pattern 131 and a first insulating pattern 132.
  • the first conductive layer includes a conductive pattern 151 and a pixel electrode 152.
  • the second conductive layer includes a gate electrode 141 and an etch barrier retention pattern 142.
  • the conductive pattern 151 and the gate insulating pattern 131 are on the substrate substrate 11.
  • the orthographic projections coincide, and the gate electrode 141 is located on the conductive pattern 151 and electrically connected to the conductive pattern 151.
  • an insulating film 13, a first conductive film 15, and a second conductive film 14 are sequentially formed on the base substrate 11 including the semiconductor layer, as shown in FIG. 5 and FIG. 7; then, the insulating film 13, the first A conductive film 15 and a second conductive film 14 are patterned, wherein the second conductive film 14 is etched by a wet etching process to form a gate electrode 141 and an etch stop retention pattern 142, as shown in FIG. 9; The etching process etches the insulating film 13 and the first conductive film 15, forms the gate insulating pattern 131 and the conductive pattern 151, and the first insulating pattern 132 and the pixel electrode 152, as shown in FIG. 10; finally, the photoresist 30 is peeled off. .
  • the conductive pattern 151 and the gate insulating pattern 131 are formed by a dry etching process, it is ensured that the conductive pattern 151 and the gate insulating pattern 131 are orthogonally projected on the substrate substrate 11, that is, the gate insulating pattern.
  • a conductive pattern 151 is present at various positions on the upper surface of the 131.
  • the conductive pattern 151 compensates for a defect of no gate above the edge of the gate insulating pattern in the related art, so that the entire gate insulating pattern has a corresponding underside
  • the source layer pattern regions can be adjusted, which enhances the electrical characteristics of the thin film transistor and improves the display effect of the display device.
  • the method further includes:
  • Step 203 forming an interlayer dielectric layer 17 covering the second conductive layer, as shown in FIG. 12; wherein the interlayer dielectric layer 17 is also referred to as an insulating layer, and is usually composed of an insulating material.
  • Step 204 forming a source 181 and a drain 182 on the interlayer dielectric layer 17, as shown in FIG.
  • the drain 182 and the pixel electrode 152 are electrically connected by the etch stop retention pattern 142.
  • Step 205 forming a passivation layer 20 covering the source 181 and the drain 182;
  • the passivation layer 20 and the etch stop retention pattern 142 may be etched by a process of dry etching and then wet etching.
  • the pixel electrode 152 is exposed.
  • Step 206 forming a pixel defining layer 21 on the passivation layer 20, as shown in FIG.
  • a further embodiment of the present disclosure provides a method for fabricating a bottom emission display substrate, including:
  • Step 301 forming a buffer layer 16 on the base substrate 11, as shown in FIG.
  • the buffer layer 16 is generally an inorganic thin film made of SiOx material.
  • Step 302 forming a semiconductor layer on the buffer layer 16, the semiconductor layer including the active layer pattern 121, as shown in FIG.
  • a semiconductor thin film may be formed on a base substrate, and then the semiconductor thin film is patterned to form a semiconductor layer, and the semiconductor layer includes an active layer pattern 121, as shown in FIG.
  • Step 303 forming an insulating film 13 covering the semiconductor layer, as shown in FIG.
  • Step 304 forming a color film 19 in the pixel region of the base substrate 11 including the insulating film 13, as shown in FIG.
  • the color film 19 is generally produced by a COA process.
  • Step 305 sequentially forming a first conductive film 15 and a second conductive film 14 covering the laminated film of the color film 19, as shown in FIG.
  • Step 306 performing patterning processing on the second conductive film 14, the first conductive film 15, and the insulating film 13 to form an insulating layer, a first conductive layer, and a second conductive layer which are sequentially stacked and distributed; wherein the insulating layer includes a gate insulating pattern 131 including a conductive pattern 151 and a pixel electrode 152, the second conductive layer including a gate electrode 141 and an etch barrier retention pattern 142, the conductive pattern 151 and the gate
  • the orthographic projections of the pole insulating patterns 131 on the base substrate 11 coincide, and the gate electrodes 141 are located on the conductive patterns 151 and electrically connected to the conductive patterns 151.
  • a photoresist 30 is coated on the base substrate 11 including the insulating film 13, the first conductive film 15, and the second conductive film 14, as shown in FIG. 8; then exposure, development, and wet etching are performed.
  • the etching process etches the second conductive film 14 to form a second conductive layer, the second conductive layer including the gate electrode 141 and the etch stop retention pattern 142, as shown in FIG.
  • etching is performed by a dry etching process
  • the film 13 and the first conductive film 15 to form a first conductive layer including a gate insulating pattern 131 and a first insulating pattern 132, and a first insulating pattern 132, the first conductive layer including the conductive pattern 151 and the pixel electrode 152
  • the photoresist 30 on the second conductive layer is peeled off, as shown in FIG. Since the conductive pattern 151 and the gate insulating pattern 131 are formed by etching by a dry etching process, it is possible to ensure that the conductive pattern 151 and the positive projection of the gate insulating pattern 131 on the base substrate 11 coincide.
  • Step 307 forming an interlayer dielectric layer 17 covering the second conductive layer, as shown in FIG. 12; wherein the interlayer dielectric layer 17 is also referred to as an insulating layer, and is usually composed of an insulating material.
  • Step 308 forming a source 181 and a drain 182 on the interlayer dielectric layer 17, as shown in FIG.
  • the drain 182 and the pixel electrode 152 are electrically connected by the etch stop retention pattern 142.
  • Step 309 forming a passivation layer 20 covering the source 181 and the drain 182.
  • the photoresist 30 is first coated, as shown in FIG. 13; then exposure and development are performed, and then the passivation layer 20 is etched by a dry etching process. As shown in FIG. 14 , the drain 182 and the etch stop retention pattern 142 are then etched by a wet etching process, as shown in FIG. 15 , so that the pixel electrode 152 is exposed; finally, the photoresist 30 is peeled off. As shown in Figure 16.
  • Step 310 forming a pixel defining layer 21 on the passivation layer 20, as shown in FIG.
  • the conductive pattern 151 and the gate insulating pattern 131 are formed by a dry etching process, the orthographic projection of the conductive pattern 151 and the gate insulating pattern 131 on the substrate 11 can be ensured.
  • a conductive pattern 151 exists at various positions on the upper surface of the gate insulating pattern 131, and the conductive pattern 151 compensates for a defect of no gate at a small distance above the edge of the gate insulating pattern in the related art, so that the entire gate
  • the corresponding active layer pattern regions under the pole insulating pattern can be adjusted, which enhances the electrical characteristics of the thin film transistor and improves the display effect of the display device.
  • the thin film transistor includes a substrate substrate, an active layer pattern disposed on the substrate, and an active layer pattern a gate insulating pattern thereon, and a gate disposed on the gate insulating pattern; a conductive pattern disposed between the gate and the gate insulating pattern, the conductive pattern being electrically connected to the gate; the conductive pattern and the gate insulating pattern being lined
  • the orthographic projections on the base substrate coincide.
  • the thin film transistor provided by the embodiment of the present disclosure forms a conductive pattern between the gate and the gate insulating pattern, because the gate can be formed by a wet etching process, and then formed by a dry etching process.
  • the conductive pattern and the gate insulating pattern can ensure the orthographic projection of the conductive pattern and the gate insulating pattern on the substrate, that is, the conductive pattern exists at various positions on the upper surface of the gate insulating pattern, and the conductive pattern compensates
  • a small distance from the edge of the gate insulating pattern is free of gate defects, so that the corresponding active layer pattern region under the entire gate insulating pattern can be adjusted, thereby enhancing the electrical characteristics of the thin film transistor and improving the performance. Display the display effect of the device.

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Abstract

提供了一种薄膜晶体管及制作方法、显示基板及制作方法、显示装置。本公开实施例的薄膜晶体管包括设置在衬底基板上的有源层图案、设置在有源层图案上的栅极绝缘图案，以及设置在栅极绝缘图案上的栅极；栅极与栅极绝缘图案之间设置有导电图案，导电图案与栅极电连接；导电图案与栅极绝缘图案在衬底基板上的正投影重合。

Description

薄膜晶体管及制作方法、显示基板及制作方法、显示装置
相关申请的交叉引用
本申请要求2017年8月31日提交的、发明名称为“薄膜晶体管及制作方法、显示基板及制作方法、显示装置”的中国专利申请No.201710778593.8的优先权，其全部内容通过引用结合在此。
技术领域
本公开涉及显示装置技术领域，尤其涉及薄膜晶体管及制作方法、显示基板及制作方法、显示装置。
背景技术
由于顶栅结构的TFT(Thin Film Transistor，薄膜晶体管)具有较低的寄生电容，较优良的电学特性，因此被广泛应用于显示装置中。
发明内容
本公开的实施例提供一种薄膜晶体管及制作方法、显示基板及制作方法、显示装置。
一方面，本公开实施例提供一种薄膜晶体管，包括设置在衬底基板上的有源层图案、设置在所述有源层图案上的栅极绝缘图案，以及设置在所述栅极绝缘图案上的栅极；其中
所述栅极与所述栅极绝缘图案之间设置有导电图案，所述导电图案与所述栅极电连接；
所述导电图案与所述栅极绝缘图案在所述衬底基板上的正投影重合。
可选的，所述栅极与所述导电图案在所述衬底基板上的正投影不完全重合(栅极在衬底基板上的正投影位于导电图案在衬底基板上的正投影之内)。
可选的，所述导电图案包括非金属导电材料。
可选的，所述导电图案包括石墨烯材料或碳纳米管。
可选的，所述衬底基板和所述有源层图案之间还设置有缓冲层。
可选的，所述薄膜晶体管还包括覆盖所述栅极的层间介质层，以及设置在所述层间介质层上的源极和漏极，所述源极和所述漏极分别通过过孔与所述有源层图案电连接。
另一方面，本公开实施例提供一种显示基板，包括上述任意一种所述的薄膜晶体管。
可选的，所述显示基板还包括像素电极，所述像素电极与所述导电图案同层同材料设置；
所述像素电极与所述薄膜晶体管的漏极电连接。
可选的，所述显示基板还包括第一绝缘图案，所述第一绝缘图案与所述栅极绝缘图案同层设置。
可选的，所述显示基板还包括设置在第一绝缘图案与像素电极之间的彩膜。
可选的，所述显示基板还包括设置在所述像素电极的边缘位置上的刻蚀阻挡保留图案；
所述刻蚀阻挡保留图案与所述栅极同层同材料设置。
可选的，所述显示基板还包括覆盖所述薄膜晶体管的钝化层，以及设置在所述钝化层上的像素界定层。
再一方面，本公开实施例提供一种显示装置，包括上述任意一种所述的显示基板。
又一方面，本公开实施例提供一种薄膜晶体管的制作方法，包括：
在衬底基板上形成有源层图案；
在所述衬底基板上形成有所述有源层图案的一侧上形成依次层叠分布的栅极绝缘图案、导电图案和栅极，
其中，所述导电图案与所述栅极绝缘图案在所述衬底基板上的正投影重合；并且所述栅极位于所述导电图案上且与所述导电图案电连接。
可选的，所述形成依次层叠分布的栅极绝缘图案、导电图案和栅极包括：
在所述衬底基板的形成有所述有源层图案的一侧上依次制作绝缘薄膜、第一导电薄膜和第二导电薄膜；
采用湿法刻蚀工艺刻蚀所述第二导电薄膜以形成所述栅极；
采用干法刻蚀工艺刻蚀所述绝缘薄膜和第一导电薄膜以形成所述栅极绝缘图案和所述导电图案。
可选的，在形成所述有源层图案之前，所述方法还包括：
在所述衬底基板上形成缓冲层；
可选的，在形成所述栅极后，所述方法还包括：
形成覆盖所述栅极的层间介质层；
在所述层间介质层上形成源极和漏极，所述源极和所述漏极分别通过过孔与所述有源层图案电连接。
再一方面，本公开实施例提供一种显示基板的制作方法，包括：
在衬底基板上形成半导体层，所述半导体层包括有源层图案；
在所述衬底基板形成有所述半导体层的一侧上形成依次层叠分布的绝缘层、第一导电层、第二导电层；其中，所述绝缘层包括栅极绝缘图案和第一绝缘图案，所述第一导电层包括导电图案和像素电极，所述第二导电层包括栅极和刻蚀阻挡保留图案，所述导电图案与所述栅极绝缘图案在所述衬底基板上的正投影重合，并且所述栅极位于所述导电图案上且与所述导电图案电连接。
可选的，在形成所述第二导电层后，所述方法还包括：
形成覆盖所述第二导电层的层间介质层；
在所述层间介质层上形成源极和漏极；
形成覆盖所述源极和所述漏极的钝化层；和
在所述钝化层上形成像素界定层。
附图说明
为了更清楚地说明本公开实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域 普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术提供的顶栅TFT的剖面结构示意图；
图2为本公开实施例提供的顶栅TFT的剖面结构示意图；
图3为本公开实施例提供的显示基板的剖面结构示意图一；
图4为本公开实施例提供的显示基板的剖面结构示意图二；
图5为本公开实施例提供的显示基板的剖面结构示意图三；
图6为本公开实施例提供的显示基板的剖面结构示意图四；
图7为本公开实施例提供的显示基板的剖面结构示意图五；
图8为本公开实施例提供的显示基板的剖面结构示意图六；
图9为本公开实施例提供的显示基板的剖面结构示意图七；
图10为本公开实施例提供的显示基板的剖面结构示意图八；
图11为本公开实施例提供的显示基板的剖面结构示意图九；
图12为本公开实施例提供的显示基板的剖面结构示意图十；
图13为本公开实施例提供的显示基板的剖面结构示意图十一；
图14为本公开实施例提供的显示基板的剖面结构示意图十二；
图15为本公开实施例提供的显示基板的剖面结构示意图十三；
图16为本公开实施例提供的显示基板的剖面结构示意图十四；
图17为本公开实施例提供的显示基板的剖面结构示意图十五。
具体实施方式
图1所示为相关技术中的一种顶栅TFT，包括形成于衬底基板01上的有源层图案02，形成于有源层图案02上的栅极绝缘图案03，形成于栅极绝缘图案03上的栅极04，以及通过过孔与有源层图案02连接的源极05和漏极06。在制作顶栅结构的TFT时，由于要采用到栅极04与栅极绝缘图案03的自对准工艺，而通常栅极04采用湿法刻蚀工艺制作，栅极绝缘图案03通过干法刻蚀工艺制作，在利用湿法刻蚀工艺刻蚀栅极04时，由于刻蚀液会在光刻胶下面多刻蚀一小 段距离，这样导致栅极04相比栅极绝缘图案03短出一小段距离，即栅极04与栅极绝缘图案03在衬底基板01上的正投影不能完全重合。由于这一小段距离没有栅极04在上方，导致缺少栅极04覆盖的栅极绝缘图案03下方的有源层图案02没有被栅极04调控，进而导致顶栅结构的TFT的开启电流不足，从而影响顶栅TFT的电学特性，使得显示装置的显示效果也受到影响。
本公开实施例提供一种薄膜晶体管，如图2所示，包括设置在衬底基板11上的有源层图案121、设置在有源层图案121上的栅极绝缘图案131，以及设置在栅极绝缘图案131上的栅极141；栅极141与栅极绝缘图案131之间设置有导电图案151，导电图案151与栅极141电连接；导电图案151与栅极绝缘图案131在衬底基板11上的正投影重合。
所述薄膜晶体管为顶栅结构的TFT，所述TFT可以是氧化物TFT，也可以是多晶硅TFT，本公开实施例对此不做限定。由于氧化物TFT具有较低的寄生电容、较优良的电学特性，因而在制造大尺寸高分辨率的AMOLED(Active Matrix Organic Light Emitting Diode，有源矩阵有机发光二极体面板)显示装置时首选采用氧化物TFT，当然氧化物TFT也可以应用于其他显示装置中。
参考图2、图5、图7至图11所示，在实际制作中，可以在包含有源层图案121的衬底基板11上依次制作绝缘薄膜13、第一导电薄膜15和第二导电薄膜14，如图7所示；然后涂覆光刻胶30(如图8所示)、曝光、显影，并采用湿法刻蚀工艺刻蚀第二导电薄膜14，形成栅极141，如图9所示；然后采用干法刻蚀工艺刻蚀绝缘薄膜13和第一导电薄膜15，形成栅极绝缘图案131和导电图案151，如图10所示；最后剥离掉栅极141上的光刻胶30。由于导电图案151与栅极绝缘图案131都是通过干法刻蚀工艺刻蚀形成的，因而可以保证导电图案151与栅极绝缘图案131在衬底基板11上的正投影重合。
这样一来，相较于如图1所示的相关技术，本公开实施例提供的薄膜晶体管通过在栅极和栅极绝缘图案之间设置导电图案，由于可以先通过湿刻工艺刻蚀形成栅极，然后通过干刻工艺刻蚀形成导电图案和栅极绝缘图案，因而可以保证导电图案与栅极绝缘图案在衬底基板 上的正投影重合，即栅极绝缘图案上表面上各处位置均存在导电图案，所述导电图案弥补了相关技术中栅极绝缘图案边缘处的上方一小段距离无栅极的缺陷，使得整个栅极绝缘图案下面对应的有源层图案区域都可以被调控，这样增强了薄膜晶体管的电学特性，提高了显示装置的显示效果。
进一步的，导电图案151由非金属导电材料构成。这样可以防止在利用湿法刻蚀工艺刻蚀栅极金属时，刻蚀液对导电图案151造成影响。由于石墨烯材料和碳纳米管网络均具有较好的导电性，因而在一个实施例中，导电图案151包括石墨烯材料或碳纳米管网络。
参考图2所示，衬底基板11和有源层图案121之间还设置有缓冲层16；所述薄膜晶体管还包括覆盖栅极141的层间介质层17，以及设置在层间介质层17上的源极181和漏极182，源极181和漏极182分别通过过孔与有源层图案121连接。其中，缓冲层16一般为SiOx材料构成的无机薄膜，用于隔离衬底基板11，防止衬底基板11中的杂质离子扩散到上层结构中；层间介质层17也称为绝缘层，通常由绝缘材料构成，一般用于隔离相邻的两个导电层。
本公开另一实施例提供一种显示基板，包括上述本公开实施例的薄膜晶体管。所述显示基板可以是普通阵列基板，即不设彩膜的阵列基板；还可以是COA(Color-filter on Array，彩膜制作在阵列基板上)基板，本公开实施例对此不做限定。本公开实施例中的薄膜晶体管通过在栅极和栅极绝缘图案之间设置导电图案，弥补了相关技术中栅极绝缘图案边缘处的上方一小段距离无栅极的缺陷，使得整个栅极绝缘图案下面对应的有源层图案区域都可以被调控，这样增强了薄膜晶体管的电学特性，提高了显示装置的显示效果。
在实际制作中，可以在衬底基板11依次制作缓冲层16和有源层图案121，如图3至图4所示。
可选的，参考图5至图11所示，可以在包含有源层图案121的衬底基板11上依次制作绝缘薄膜13、彩膜19、第一导电薄膜15和第二导电薄膜14，如图7所示；然后涂覆光刻胶30、曝光、显影，并采用湿法刻蚀工艺刻蚀第二导电薄膜14，形成栅极141和刻蚀阻挡保留图案142，如图9所示；然后采用干法刻蚀工艺刻蚀绝缘薄膜 13和第一导电薄膜15，形成栅极绝缘图案131和导电图案151，以及第一绝缘图案132和像素电极152，如图10所示；最后剥离光刻胶30。由于导电图案151与栅极绝缘图案131都是通过干法刻蚀工艺刻蚀形成的，因而可以保证导电图案151与栅极绝缘图案131在衬底基板11上的正投影重合。
参考图10所示，所述显示基板包括第一绝缘图案132，第一绝缘图案132与栅极绝缘图案131同层设置。
由于第一绝缘图案132与栅极绝缘图案131是同层设置的，因而可以通过一次构图工艺进行制作，这样简化了制作工艺，节省了工艺制作成本。
另外，所述显示基板还包括像素电极152，像素电极152与导电图案151同层同材料设置。
由于像素电极152和导电图案151是同层同材料设置的，因而可以通过一次构图工艺进行制作，这样简化了制作工艺，节省了工艺制作成本。由于石墨烯材料和碳纳米管网络均具有较好的导电性和透过率，因而在一个实施例中，像素电极152和导电图案151均包括石墨烯材料或碳纳米管网络。
以AMOLED显示基板为例，显示基板可包含多个OLED(Organic Light-Emitting Diode，有机发光二极管)器件，所述多个OLED器件可以是阵列排布。若所述多个OLED器件是共阴极(即所述多个OLED器件的阴极连接形成整面电极)的，像素电极152为OLED器件的阳极；若所述多个OLED器件是共阳极(即所述多个OLED器件的阳极连接形成整面电极)的，像素电极152为OLED器件的阴极。
图10和11显示了彩膜19设置在第一绝缘图案132与像素电极152之间的情况。需要说明的是，在实际应用时，当显示基板中三种OLED子像素发光层发出不同颜色的光时，不需要制作彩膜19。当显示基板采用WOLED(白光OLED)器件时需要制作彩膜19，但是彩膜19既可以做在像素电极152的下方(即底发射结构，如图11所示)，也可以做在发光层的上方(即顶发射结构)或者设置在与所述显示基板对合的对合基板上。本公开实施例对此不做限定。为了方便描述， 本公开实施例以彩膜19制作在像素电极152的下方(即底发射结构)为例进行说明。
进一步的，参考图12至图15所示，所述显示基板还包括设置在像素电极152上的刻蚀阻挡保留图案142；刻蚀阻挡保留图案142与栅极141同层同材料设置。通过设置刻蚀阻挡保留图案142可以防止在刻蚀层间介质层17时对像素电极152造成影响。同时，由于刻蚀阻挡保留图案142和栅极141同层同材料设置，因而可以通过一次构图工艺进行制作，这样可以简化制作工艺，节省工艺制作成本。
参考图13至图17所示，所述显示基板还包括覆盖所述薄膜晶体管的钝化层20，以及设置在钝化层20上的像素界定层21。
在对钝化层20进行图形化时，首先涂覆光刻胶30，如图13所示；然后进行曝光和显影，接着利用干法刻蚀工艺对钝化层20进行刻蚀，如图14所示；然后利用湿法刻蚀工艺对刻蚀阻挡保留图案142进行刻蚀，从而使得像素电极152暴露出来，如图15所示。漏极182与像素电极152通过位于在像素电极152的边缘位置上的刻蚀阻挡保留图案142电连接。最后在钝化层20上制作像素界定层21，如图17所示。
本公开另一实施例提供一种薄膜晶体管的制作方法，包括：
步骤101、在衬底基板11上形成有源层图案121，如图4所示。
在实际制作中，可以在衬底基板11上先制作半导体薄膜，然后对所述半导体薄膜经过一次构图工艺形成有源层图案121。
步骤102、在包含有源层图案121的衬底基板11上形成依次层叠分布的栅极绝缘图案131、导电图案151和栅极141；导电图案151与栅极绝缘图案131在衬底基板11上的正投影重合；栅极141位于导电图案151上且与导电图案151电连接。
具体的，在包含有源层图案121的衬底基板11上依次制作绝缘薄膜13、第一导电薄膜15和第二导电薄膜14，如图5和图7所示；然后在包含绝缘薄膜13、第一导电薄膜15和第二导电薄膜14的衬底基板11上涂覆光刻胶30，如图8所示；接着进行曝光、显影，并采用湿法刻蚀工艺刻蚀第二导电薄膜14，形成栅极141，如图9所示； 然后采用干法刻蚀工艺刻蚀绝缘薄膜13和第一导电薄膜15，形成栅极绝缘图案131和导电图案151，如图10所示；最后剥离掉栅极141上的光刻胶30。
由于导电图案151与栅极绝缘图案131都是通过干法刻蚀工艺刻蚀形成的，因而可以保证导电图案151与栅极绝缘图案131在衬底基板11上的正投影重合，即栅极绝缘图案131上表面上各处位置均存在导电图案151，所述导电图案151弥补了相关技术中栅极绝缘图案边缘处的上方一小段距离无栅极的缺陷，使得整个栅极绝缘图案下面对应的有源层图案区域都可以被调控，这样增强了薄膜晶体管的电学特性，提高了显示装置的显示效果。
进一步的，在形成有源层图案121之前，所述方法还包括：
步骤103、在衬底基板11上形成缓冲层16，如图3所示；其中，缓冲层16一般为SiOx材料构成的无机薄膜。
在形成栅极141后，所述方法还包括：
步骤104、形成覆盖栅极141的层间介质层17，如图12所示；其中，层间介质层17也称为绝缘层，通常由绝缘材料构成。
步骤105、在层间介质层17上形成源极181和漏极182，源极181和漏极182分别通过过孔与有源层图案121电连接，如图12所示。
本公开又一实施例提供一种显示基板的制作方法，包括：
步骤201、在衬底基板11上形成半导体层，所述半导体层包括有源层图案121；如图4所示。
在实际制作中，可以先在衬底基板11上制作半导体薄膜，接着对所述半导体薄膜进行图形化形成半导体层，所述半导体层包括有源层图案121，如图4所示。
步骤202、在包含所述半导体层的衬底基板11上形成依次层叠分布的绝缘层、第一导电层、第二导电层；其中，所述绝缘层包括栅极绝缘图案131和第一绝缘图案132，所述第一导电层包括导电图案151和像素电极152，所述第二导电层包括栅极141和刻蚀阻挡保留图案142，导电图案151与栅极绝缘图案131在衬底基板11上的正 投影重合，栅极141位于导电图案151上且与导电图案151电连接。
具体的，首先在包含所述半导体层的衬底基板11上依次制作绝缘薄膜13、第一导电薄膜15和第二导电薄膜14，如图5和图7所示；然后对绝缘薄膜13、第一导电薄膜15和第二导电薄膜14进行图形化，其中采用湿法刻蚀工艺刻蚀第二导电薄膜14，形成栅极141和刻蚀阻挡保留图案142，如图9所示；采用干法刻蚀工艺刻蚀绝缘薄膜13和第一导电薄膜15，形成栅极绝缘图案131和导电图案151，以及第一绝缘图案132和像素电极152，如图10所示；最后剥离掉光刻胶30。
由于导电图案151与栅极绝缘图案131是通过干法刻蚀工艺刻蚀形成的，因而可以保证导电图案151与栅极绝缘图案131在衬底基板11上的正投影重合，即栅极绝缘图案131上表面上各处位置均存在导电图案151，所述导电图案151弥补了相关技术中栅极绝缘图案边缘处的上方一小段距离无栅极的缺陷，使得整个栅极绝缘图案下面对应的有源层图案区域都可以被调控，这样增强了薄膜晶体管的电学特性，提高了显示装置的显示效果。
进一步的，在形成所述第二导电层后，所述方法还包括：
步骤203、形成覆盖所述第二导电层的层间介质层17，如图12所示；其中，层间介质层17也称为绝缘层，通常由绝缘材料构成。
步骤204、在层间介质层17上形成源极181和漏极182，如图12所示。其中，漏极182与像素电极152通过刻蚀阻挡保留图案142电连接。
步骤205、形成覆盖源极181和漏极182的钝化层20；
实际制作中，参考图13至图16所示，在对钝化层20进行图形化时，可以通过先干刻再湿刻的工艺对钝化层20和刻蚀阻挡保留图案142进行刻蚀，以使像素电极152暴露出来。
步骤206、在钝化层20上形成像素界定层21，如图17所示。
本公开再一实施例提供一种底发射显示基板的制作方法，包括：
步骤301、在衬底基板11上形成缓冲层16，如图3所示。其中，缓冲层16一般为SiOx材料构成的无机薄膜。
步骤302、在缓冲层16上形成半导体层，所述半导体层包括有源层图案121，如图4所示。
在实际制作中，可以先在衬底基板上制作半导体薄膜，接着对所述半导体薄膜进行图形化以形成半导体层，所述半导体层包括有源层图案121，如图4所示。
步骤303、形成覆盖半导体层的绝缘薄膜13，如图5所示。
步骤304、在包含绝缘薄膜13的衬底基板11的像素区域形成彩膜19，如图6所示。其中，彩膜19一般通过COA工艺制作。
步骤305、依次形成覆盖彩膜19的层叠分布的第一导电薄膜15和第二导电薄膜14，如图7所示。
步骤306、对第二导电薄膜14、第一导电薄膜15和绝缘薄膜13进行图形化处理，以形成依次层叠分布的绝缘层、第一导电层、第二导电层；其中，所述绝缘层包括栅极绝缘图案131和第一绝缘图案132，所述第一导电层包括导电图案151和像素电极152，所述第二导电层包括栅极141和刻蚀阻挡保留图案142，导电图案151与栅极绝缘图案131在衬底基板11上的正投影重合，栅极141位于导电图案151上且与导电图案151电连接。
具体的，在包含绝缘薄膜13、第一导电薄膜15和第二导电薄膜14的衬底基板11上涂覆光刻胶30，如图8所示；接着进行曝光、显影，并采用湿法刻蚀工艺刻蚀第二导电薄膜14，形成第二导电层，所述第二导电层包括栅极141和刻蚀阻挡保留图案142，如图9所示；然后采用干法刻蚀工艺刻蚀绝缘薄膜13和第一导电薄膜15，以形成第一导电层和绝缘层，所述绝缘层包括栅极绝缘图案131和第一绝缘图案132，所述第一导电层包括导电图案151和像素电极152，如图10所示；最后剥离掉所述第二导电层上的光刻胶30，如图11所示。由于导电图案151与栅极绝缘图案131是通过干法刻蚀工艺刻蚀形成的，因而可以保证导电图案151与栅极绝缘图案131在衬底基板11上的正投影重合。
步骤307、形成覆盖第二导电层的层间介质层17，如图12所示；其中，层间介质层17也称为绝缘层，通常由绝缘材料构成。
步骤308、在层间介质层17上形成源极181和漏极182，如图12所示。其中漏极182与像素电极152通过刻蚀阻挡保留图案142电连接。
步骤309、形成覆盖源极181和漏极182的钝化层20。
具体的，在对钝化层20进行图形化时，首先涂覆光刻胶30，如图13所示；然后进行曝光和显影，接着利用干法刻蚀工艺对钝化层20进行刻蚀，如图14所示；然后利用湿法刻蚀工艺对漏极182和刻蚀阻挡保留图案142进行刻蚀，如图15所示，从而使得像素电极152暴露出来；最后剥离掉光刻胶30，如图16所示。
步骤310、在钝化层20上形成像素界定层21，如图17所示。
在本公开实施例中，由于导电图案151与栅极绝缘图案131是通过干法刻蚀工艺刻蚀形成的，因而可以保证导电图案151与栅极绝缘图案131在衬底基板11上的正投影重合，即栅极绝缘图案131上表面上各处位置均存在导电图案151，所述导电图案151弥补了相关技术中栅极绝缘图案边缘处的上方一小段距离无栅极的缺陷，使得整个栅极绝缘图案下面对应的有源层图案区域都可以被调控，这样增强了薄膜晶体管的电学特性，提高了显示装置的显示效果。
根据本公开实施例提供的薄膜晶体管及制作方法、显示基板及制作方法、显示装置中，所述薄膜晶体管包括衬底基板、设置在衬底基板上的有源层图案、设置在有源层图案上的栅极绝缘图案，以及设置在栅极绝缘图案上的栅极；栅极与栅极绝缘图案之间设置有导电图案，导电图案与栅极电连接；导电图案与栅极绝缘图案在衬底基板上的正投影重合。相较于相关技术，本公开实施例提供的薄膜晶体管通过在栅极和栅极绝缘图案之间设置导电图案，由于可以先通过湿刻工艺刻蚀形成栅极，然后通过干刻工艺刻蚀形成导电图案和栅极绝缘图案，因而可以保证导电图案与栅极绝缘图案在衬底基板上的正投影重合，即栅极绝缘图案上表面上各处位置均存在导电图案，所述导电图案弥补了相关技术中栅极绝缘图案边缘处的上方一小段距离无栅极的缺陷，使得整个栅极绝缘图案下面对应的有源层图案区域都可以被调控，这样增强了薄膜晶体管的电学特性，提高了显示装置的显示效果。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所附权利要求的保护范围为准。

Claims (19)

  1. 一种薄膜晶体管，包括设置在衬底基板上的有源层图案、设置在所述有源层图案上的栅极绝缘图案，以及设置在所述栅极绝缘图案上的栅极；其中，
    所述栅极与所述栅极绝缘图案之间设置有导电图案，所述导电图案与所述栅极电连接；所述导电图案与所述栅极绝缘图案在所述衬底基板上的正投影重合。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述栅极与所述导电图案在所述衬底基板上的正投影不完全重合。
  3. 根据权利要求1所述的薄膜晶体管，其中，所述导电图案包括非金属导电材料。
  4. 根据权利要求3所述的薄膜晶体管，其中，所述导电图案包括石墨烯材料或碳纳米管。
  5. 根据权利要求1所述的薄膜晶体管，其中，所述衬底基板和所述有源层图案之间还设置有缓冲层。
  6. 根据权利要求1所述的薄膜晶体管，其中，所述薄膜晶体管还包括覆盖所述栅极的层间介质层，以及设置在所述层间介质层上的源极和漏极，所述源极和所述漏极分别通过过孔与所述有源层图案电连接。
  7. 一种显示基板，包括权利要求1至6中任意一项所述的薄膜晶体管。
  8. 根据权利要求7所述的显示基板，其中，所述显示基板还包括像素电极，所述像素电极与所述导电图案同层同材料设置；
    所述像素电极与所述薄膜晶体管的漏极电连接。
  9. 根据权利要求8所述的显示基板，其中，所述显示基板还包括第一绝缘图案，所述第一绝缘图案与所述栅极绝缘图案同层设置。
  10. 根据权利要求9所述的显示基板，其中，所述显示基板还包括设置在第一绝缘图案与像素电极之间的彩膜。
  11. 根据权利要求8所述的显示基板，其中，所述显示基板还包括设置在所述像素电极的边缘位置上的刻蚀阻挡保留图案；
    所述刻蚀阻挡保留图案与所述栅极同层同材料设置。
  12. 根据权利要求11所述的显示基板，其中，所述显示基板还包括覆盖所述薄膜晶体管的钝化层，以及设置在所述钝化层上的像素界定层。
  13. 一种显示装置，包括权利要求7至12中任意一项所述的显示基板。
  14. 一种薄膜晶体管的制作方法，包括：
    在衬底基板上形成有源层图案；
    在所述衬底基板形成有所述有源层图案的一侧上形成依次层叠分布的栅极绝缘图案、导电图案和栅极，
    其中所述导电图案与所述栅极绝缘图案在所述衬底基板上的正投影重合；并且所述栅极位于所述导电图案上且与所述导电图案电连接。
  15. 根据权利要求14所述的制作方法，其中，所述形成依次层叠分布的栅极绝缘图案、导电图案和栅极包括：
    在所述衬底基板的形成有所述有源层图案的一侧上依次制作绝缘薄膜、第一导电薄膜和第二导电薄膜；
    采用湿法刻蚀工艺刻蚀所述第二导电薄膜以形成所述栅极；
    采用干法刻蚀工艺刻蚀所述绝缘薄膜和第一导电薄膜以形成所述栅极绝缘图案和所述导电图案。
  16. 根据权利要求14或15所述的制作方法，其中，在形成所述有源层图案之前，所述方法还包括：
    在所述衬底基板上形成缓冲层。
  17. 根据权利要求14或15所述的制作方法，其中，在形成所述栅极后，所述方法还包括：
    形成覆盖所述栅极的层间介质层；
    在所述层间介质层上形成源极和漏极，所述源极和所述漏极分别通过过孔与所述有源层图案电连接。
  18. 一种显示基板的制作方法，包括：
    在衬底基板上形成半导体层，所述半导体层包括有源层图案；
    在所述衬底基板形成有所述半导体层的一侧上形成依次层叠分布的绝缘层、第一导电层、第二导电层；其中，所述绝缘层包括栅极绝缘图案和第一绝缘图案，所述第一导电层包括导电图案和像素电极，所述第二导电层包括栅极和刻蚀阻挡保留图案，所述导电图案与 所述栅极绝缘图案在所述衬底基板上的正投影重合，并且所述栅极位于所述导电图案上且与所述导电图案电连接。
  19. 根据权利要求18所述的制作方法，其中，在形成所述第二导电层后，所述方法还包括：
    形成覆盖所述第二导电层的层间介质层；
    在所述层间介质层上形成源极和漏极；
    形成覆盖所述源极和所述漏极的钝化层；和
    在所述钝化层上形成像素界定层。
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