WO2018205587A1 - 显示基板及其制作方法、显示装置 - Google Patents

显示基板及其制作方法、显示装置 Download PDF

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Publication number
WO2018205587A1
WO2018205587A1 PCT/CN2017/115266 CN2017115266W WO2018205587A1 WO 2018205587 A1 WO2018205587 A1 WO 2018205587A1 CN 2017115266 W CN2017115266 W CN 2017115266W WO 2018205587 A1 WO2018205587 A1 WO 2018205587A1
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Prior art keywords
electrode
thin film
connection electrode
film transistor
display substrate
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PCT/CN2017/115266
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English (en)
French (fr)
Inventor
邹清华
何小祥
王玉
姚固
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP17893508.6A priority Critical patent/EP3624193A4/en
Priority to US16/075,042 priority patent/US20210210589A1/en
Publication of WO2018205587A1 publication Critical patent/WO2018205587A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/824—Cathodes combined with auxiliary electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80522—Cathodes combined with auxiliary electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/302—Details of OLEDs of OLED structures
    • H10K2102/3023—Direction of light emission
    • H10K2102/3026—Top emission
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/828—Transparent cathodes, e.g. comprising thin metal layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/85—Arrangements for extracting light from the devices
    • H10K50/856—Arrangements for extracting light from the devices comprising reflective means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • At least one embodiment of the present disclosure relates to a display substrate, a method of fabricating the same, and a display device.
  • the small-sized Organic Light Emitting Diode (OLED) panel is mainly a top-emitting OLED, and the cathode is mainly a semi-reflective and translucent cathode such as Mg/Ag, and the semi-reflective and translucent cathode has a higher resistance due to comparison. With the pronounced IR drop effect and higher power consumption, the semi-reflective translucent cathode cannot be implemented on large OLED panels.
  • At least one embodiment of the present disclosure provides a display substrate, including:
  • a light-emitting element located on the thin film transistor, including a first electrode and a second electrode, the first electrode and the second electrode being spaced apart from each other, the first electrode being electrically connected to the thin film transistor;
  • connection electrode between the substrate substrate and the light emitting element, the connection electrode and the thin film transistor being insulated from each other;
  • the conductive portion is configured to connect the second electrode in parallel with the connection electrode.
  • At least one embodiment of the present disclosure further provides a method of fabricating a display substrate, including:
  • the light emitting element including a first electrode and a second electrode, the first electrode and the second electrode being spaced apart from each other, the first electrode being electrically connected to the thin film transistor;
  • connection electrode Forming a connection electrode between the base substrate and the light emitting element, the connection electrode and the thin film transistor being insulated from each other;
  • a conductive portion is formed, the conductive portion being configured to connect the second electrode in parallel with the connection electrode.
  • At least one embodiment of the present disclosure also provides a display device including a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 1 is a schematic diagram of a display substrate and a display device including the display substrate according to an embodiment of the present disclosure
  • FIG. 2A is a schematic plan view showing a sub-pixel and a conductive portion in a display substrate according to an embodiment of the present disclosure
  • 2B is a schematic plan view showing a sub-pixel and a conductive portion in a display substrate according to another embodiment of the present disclosure
  • 3A is a schematic plan view showing a first electrode and a conductive portion in a display substrate according to an embodiment of the present disclosure
  • 3B is a schematic plan view showing a first electrode and a conductive portion in a display substrate according to another embodiment of the present disclosure
  • connection electrode 4 is a schematic plan view showing a connection electrode in a display substrate according to an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of a display substrate and a display device including the display substrate according to another embodiment of the present disclosure
  • 6A is a schematic plan view showing a connection electrode in a display substrate according to an embodiment of the present disclosure
  • 6B is a schematic plan view showing a connection electrode in a display substrate according to another embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a display substrate and a display device including the display substrate according to another embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a display substrate and a display device including the display substrate according to another embodiment of the present disclosure.
  • FIG. 9 is a schematic view showing a via hole formed in a method of fabricating a display substrate according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of forming a second sub-conductive portion in a via hole in a method of fabricating a display substrate according to an embodiment of the present disclosure
  • FIG. 11 is a schematic diagram of forming a first sub-conducting portion electrically connected to a second sub-conducting portion thereof in a method for fabricating a display substrate according to an embodiment of the present disclosure
  • FIG. 12 is a schematic diagram of forming a via hole in a method of fabricating a display substrate according to an embodiment of the present disclosure
  • FIG. 13 is a schematic diagram of forming a second sub-conductive portion in a via hole in a method of fabricating a display substrate according to an embodiment of the present disclosure
  • FIG. 14 is a schematic diagram of forming a first sub-conducting portion electrically connected thereto on a second sub-conducting portion in a method of fabricating a display substrate according to an embodiment of the present disclosure.
  • mainstream large-size organic light-emitting diode (OLED) panels use bottom-emitting OLEDs, but bottom-emitting OLEDs have a light-emitting surface on the side where a thin film transistor (TFT) is provided. It is bound to lead to a decrease in the aperture ratio. Meanwhile, TFTs of large-sized OLED panels generally employ an oxide semiconductor material such as IGZO. Since the oxide semiconductor material is very sensitive to light, the bottom-emitting OLED cannot avoid the influence of ambient light and light emitted from the OLED on the oxide semiconductor material.
  • a typical top emission mode display substrate includes a transparent or translucent electrode to facilitate light exit. When the transparent or translucent electrode has a high resistance, it may result in uneven brightness and high power consumption.
  • a display substrate 10 including:
  • the base substrate 101 for example, the base substrate 101 may include a glass substrate, but is not limited thereto;
  • TFT thin film transistor
  • the light emitting element 131 is disposed on the thin film transistor 121 and includes a first electrode 1121 and a second electrode 115.
  • the first electrode 1121 and the second electrode 115 are spaced apart from each other (for example, the first electrode 1121 and the second electrode 115 are in between
  • the light emitting function layer 114 is spaced apart, for example, the first electrode 1121 is closer to the base substrate 101 than the second electrode 115 (the first electrode 1121 is formed on the base substrate 101 before the second electrode 115), the first electrode 1121 and the thin film transistor 121 electrically connected; the second electrode 115 and the thin film transistor 121 are insulated from each other;
  • connection electrode 102 is located between the base substrate 101 and the light emitting element 131, and the connection electrode 102 and the thin film transistor 121 are insulated from each other;
  • the conduction portion 141 is disposed such that the second electrode 115 is connected in parallel with the connection electrode 102.
  • the conductive portion 141 is located between the second electrode 115 and the connection electrode 102.
  • the conductive portion 141 and the first electrode 1121 are insulated from each other, and the conductive portion 141 and the thin film transistor 121 are insulated from each other.
  • the top emission mode can be adopted, and the display panel of the top emission mode can have a large aperture ratio, which can significantly improve the brightness of the product.
  • the second electrode 115 and the connection electrode 102 are connected in parallel by the conduction portion 141, and the second electrode 115 is disposed in a different layer from the connection electrode 102, so that the connection electrode 102 electrically connected to the second electrode 115 can be different from the second electrode.
  • the material of 115 can make the second electrode 115 use a material with high transmittance to improve light extraction efficiency. Further, since the connection electrode 102 is provided, an electrical signal can be applied to the second electrode 115 through the connection electrode 102, so that the voltage drop can be reduced, so that the difference in electrical signals due to the voltage drop at different positions of the display substrate is reduced, and the display device is improved. Light uniformity and reduced power consumption.
  • spacing from each other includes being insulated from each other in the selected state.
  • spacing two components/components from each other means that the two components/components are insulated from one another when the thin film transistor and/or the light emitting component are in an inoperative state.
  • the non-operating state includes, for example, a state in which no voltage is applied or not, and includes, for example, a state in which the thin film transistor is not turned on and/or the light emitting element does not emit light.
  • the first electrode 1121 may be an anode
  • the second electrode 115 may be a cathode, but is not limited thereto.
  • the display substrate 10 provided by the embodiment of the present disclosure can be applied to a top emission display device, as shown in FIG. 1 , the light emitted from the light emitting unit 131 is from the display device.
  • the top surface of the connection electrode 102 can be opaque to have a function of reflecting ambient light, and light incident from the bottom surface of the display device can be reflected by the connected electrode 102.
  • the thin film transistor 121 may include a gate 104 , an active layer 106 , a drain 1081 , and a source 1082 .
  • the first electrode 1121 can be electrically connected to the drain 1081.
  • Source 1082 can be configured to apply an electrical signal.
  • the gate 104 can be configured to apply an electrical signal to control the turning on and off of the thin film transistor 121. Electrically connecting the first electrode 1121 to the thin film transistor 121 means, for example, that the first electrode 1121 is electrically connected to the drain 1081 or the source 1082 of the thin film transistor 121.
  • the source and the drain are opposite to each other.
  • the first electrode 1121 is electrically connected to the drain 1081 of the thin film transistor 121 as an example.
  • a TFT having a bottom gate structure will be described as an example. It should be noted that a TFT of a top gate structure may also be used to facilitate shielding of the light that is irradiated onto the active layer by the gate.
  • a display substrate 10 further includes a buffer layer 103 on a substrate substrate 101.
  • the gate electrode 104 is disposed on the buffer layer 103, and the gate electrode 104 is provided with a gate insulating layer.
  • the layer 105 is provided with an active layer 106 on the gate insulating layer 105, an etch stop layer 107 is disposed on the active layer 106, and a source/drain layer 108 is disposed on the etch stop layer 107.
  • the source drain layer 108 includes a drain 1081 and a source 1082 that are separated from each other and connected to the active layer 106, respectively.
  • a passivation layer 109 is disposed on the source drain layer 108, and a planarization layer 110 is disposed on the passivation layer 109.
  • the via hole 11101 penetrates through the buffer layer 103, the gate insulating layer 105, the etch barrier layer 107, the passivation layer 109, and the flat layer 110.
  • a second sub-conducting portion 111 is formed in the via hole 11101.
  • a first transparent conductive layer 112 is disposed on the flat layer 110.
  • the first transparent conductive layer 112 includes a first electrode 1121 and a first sub-conducting portion 1122. The first electrode 1121 and the first sub-conducting portion 1122 are insulated from each other.
  • the first sub-conducting portion 1122 and the second sub-conducting portion 111 constitute a conducting portion 141.
  • a pixel defining layer 113 is formed on the first transparent conductive layer 112
  • a light emitting function layer 114 is disposed on the pixel defining layer 113
  • a second electrode 115 is formed on the light emitting function layer 114.
  • the second electrode 115 is electrically connected to the connection electrode 102 through the conduction portion 141.
  • the light-emitting function layer 114 includes at least one light-emitting layer, and may further include at least one of a hole transport layer, a hole injection layer, an electron transport layer, an electron injection layer, and the like.
  • a hole transport layer e.g., a hole injection layer
  • an electron transport layer e.g., a hole injection layer
  • an electron injection layer e.g., a hole injection layer
  • other layer structures may also be included, and limited.
  • the material of any one of the buffer layer 103, the gate insulating layer 105, the etch barrier layer 107, and the passivation layer 109 may employ at least one of SiOx, SiNy, and SiNxOy
  • the planarization layer 110 may be a resin material.
  • the planar layer can have a substantially flat surface to facilitate fabrication of the first electrode.
  • the configuration of the display substrate provided by the embodiment of the present disclosure is not limited to that shown in FIG. 1 , and the embodiment of the present disclosure is described by taking the display substrate shown in FIG. 1 as an example.
  • a display substrate includes a plurality of sub-pixels 100 arranged in an array.
  • the sub-pixel 100 may be defined by the pixel defining layer 113.
  • the display substrate includes a non-pixel area 0100 in addition to the pixel area in which the sub-pixel 100 is located.
  • the conductive portion 141 may be located in the non-pixel region 0100.
  • the non-pixel region 010 includes an area between the sub-pixels 100.
  • each sub-pixel 100 may correspond to one light-emitting element 131.
  • the number of the light-emitting elements 131 is plural, and the first electrodes 1121 of the respective light-emitting elements 131 are insulated from each other.
  • the conductive portion 141 may be located in the non-pixel region 0100.
  • the conductive portion 141 may be located between the adjacent first electrodes 1121.
  • the conductive portion 141 is located between the adjacent two first electrodes 1121.
  • the conduction portion 141 is located between the adjacent four first electrodes 1121.
  • the second electrodes 115 of the respective light emitting elements 131 may be in communication with each other and configured to provide electrical signals to the plurality of light emitting elements 131. Due to the arrangement of the connection electrodes 102, the difference in electrical signals at different positions can be reduced, and the signal delay can be reduced, thereby improving the display effect.
  • the shape of the connection electrode 102 may include a planar shape.
  • the planar connection electrode 102 may be located between the base substrate 101 and the thin film transistor 121 (as shown in FIG. 1).
  • FIG. 4 is a schematic plan view showing a connection electrode in the display substrate shown in FIG. 1.
  • the planar connection electrode 102 facilitates reflection of the light that the light-emitting unit 131 is irradiated thereon, which is advantageous for improving the utilization of light.
  • the shape of the connection electrode 102 is not limited to a planar shape. Other shapes such as a grid shape can also be employed.
  • the planar connecting electrode 102 is more advantageous for reducing the pressure drop.
  • a square resistance of the connection electrode 102 is lower than a square resistance of the second electrode 115. That is, the connection electrode 102 may have a low square resistance.
  • the second electrode 115 can also provide only the electrical signals of adjacent sub-pixels, and a transparent electrode with a high transmittance can be prepared without a low square resistance to improve the light-emitting efficiency.
  • the first electrode 1121 and the second electrode 115 may be made of a metal (thin metal layer) or a transparent conductive oxide material.
  • the thin metal layer may be a Mg/Ag layer
  • the transparent conductive oxide may include indium zinc oxide (IZO).
  • a metal oxide transparent conductive material such as indium tin oxide (ITO) may also have a laminated structure such as ITO/Ag/ITO.
  • the material of the connection electrode 102 includes a metal
  • the material of the conduction portion 141 includes at least one of a metal, a transparent conductive oxide, for example, including ITO.
  • the connection electrode 102 of the metallic material may have a low square resistance and is opaque.
  • connection electrode 102 and the drain are disposed in the same layer, so that the conductive portion 141 is disposed in the same layer as the first electrode 1121.
  • the conductive portion 141 and the first electrode 1121 are insulated from each other. Therefore, the conductive portion 141 and the first electrode 1121 can be formed in the same layer, and the step of separately forming the conductive portion 141 can be omitted.
  • a schematic plan view of the conductive portion 141 and the first electrode 1121 can be referred to FIGS. 3A and 3B.
  • the connection electrode 102 includes a hollow portion 10201, and a plan view of the connection electrode 102 can be referred to FIGS. 6A and 6B.
  • connection electrode 102 and the source/drain layer 108 are disposed in the same layer, the source 1082 and the drain 1081 located in the hollow portion 10201 are omitted in FIGS. 6A and 6B, and in this case, the source 1082 and the drain 1081
  • the connection electrodes 102 are insulated from each other.
  • the shape of the connection electrode 102 includes a planar shape including the hollow structure 10201.
  • the hollow structure 10201 shape may include a circular shape, a rectangular shape, or the like.
  • connection electrode 102 may be located between the thin film transistor 121 and the light emitting element 131 , and the connection electrode 102 includes the hollow portion 10201 such that the connection electrode 102 and the first electrode 1121 Insulate each other.
  • the first electrode 1121 is electrically connected to the drain electrode 1081 through the via 112101 penetrating the flat layer 110 and the passivation layer 109.
  • the via 112101 In a direction perpendicular to the base substrate 101, the via 112101 is located within the range of the hollow structure 10201, and is displayed In the top view of the substrate, the size of the via 112101 is smaller than the size of the hollow structure 10201, so that the connection electrode 102 and the first electrode 1121 can be electrically insulated from being electrically connected.
  • connection electrode 102 may be disposed in the same layer as the gate 105 of the thin film transistor 121, and the connection electrode 102 includes a hollow portion 10201 to connect the electrode 102 and the thin film transistor 121.
  • the gate electrodes 105 are insulated from each other.
  • a plan view of the connection electrode 102 can be referred to FIGS. 6A and 6B.
  • At least one embodiment of the present disclosure further provides a method for fabricating a display substrate, as shown in FIGS. 1, 5, 7, and 8, including:
  • a light-emitting element 131 is formed on the thin film transistor 121.
  • the light-emitting element 131 includes a first electrode 1121 and a second electrode 115.
  • the first electrode 1121 and the second electrode 115 are insulated from each other, and the first electrode 1121 is closer to the base substrate than the second electrode 115. 101.
  • the first electrode 1121 is electrically connected to the thin film transistor 121.
  • connection electrode 102 is formed between the base substrate 101 and the light emitting element 131, and the connection electrode 102 and the thin film transistor 121 are insulated from each other;
  • the conductive portion 141 is formed, and the conductive portion 141 is disposed to electrically connect the second electrode 115 and the connection electrode 102.
  • the conductive portion 141 is located between the second electrode 115 and the connection electrode 102.
  • a square resistance of the connection electrode 102 is lower than a square resistance of the second electrode 115.
  • connection electrode 102 may be formed between the base substrate 101 and the thin film transistor 121.
  • the number of the light-emitting elements 131 is plural, and the first electrodes 1121 of the light-emitting elements 131 are insulated from each other.
  • the second electrodes 115 of the respective light emitting elements 131 are in communication with each other and are configured to provide electrical signals to the plurality of light emitting elements 131. Thereby, it is advantageous to reduce the voltage drop at the time of signal transmission.
  • the conductive portion 141 may be located between adjacent first electrodes 1121.
  • the thin film transistor 121 includes a gate electrode 105 and a drain electrode 1081, and the first electrode 1121 may be electrically connected to the drain electrode 1081.
  • the connection electrode 102 may be formed in the same layer as one of the gate electrode 105 or the drain electrode 1081 of the thin film transistor 121, and the connection electrode 102 includes a hollow portion to insulate the connection electrode 102 and the thin film transistor 121 from each other.
  • the conductive portion 141 and the first electrode 1121 may be formed in the same layer, and the conductive portion 141 and the first electrode 1121 are mutually connected to each other. insulation.
  • the drain electrode 1081 may be disposed in the same layer as the connection electrode 102. In order to help reduce the production process.
  • connection electrode 102 may also be disposed in the same layer as the gate electrode 104, and the connection electrode 102 includes a hollow portion 10201 to connect the electrode 102.
  • the gate electrodes 105 of the thin film transistor 121 are insulated from each other.
  • connection electrode 102 is located between the thin film transistor 121 and the light emitting element 131, and the connection electrode 102 includes the hollow portion 10201 such that the connection electrode 102 and the first The electrodes 1121 are insulated from each other.
  • the conductive portion 141 may be formed separately or in the same layer as the first electrode 1121, and the connection electrode 102 may be formed between the base substrate 101 and the thin film transistor 121. It may be formed between the thin film transistor 121 and the light emitting unit 131, and may be formed in the same layer as the gate electrode 104 or the source/drain layer 108 in the thin film transistor 121.
  • a display substrate as shown in FIG. 1 is formed.
  • the connection electrode 102 is formed between the base substrate 101 and the thin film transistor 121.
  • the through buffer layer 103, the gate insulating layer 105, the etch stop layer 107, and the passivation layer can be formed.
  • 109 and a via 11101 of the planar layer 110 can be formed.
  • the second sub-conducting portion 111 can be formed.
  • the second sub-conducting portion 111 is formed at a position corresponding to the via hole 11101.
  • the second sub-conducting portion 111 and the connecting electrode 102 are formed. Electrical connection. As shown in FIG.
  • the first transparent conductive layer 112 is further formed, and the first transparent conductive layer 112 includes a first sub-conducting portion 1122 insulated from the first electrode 1121.
  • the first sub-conducting portion 1122 is electrically connected to the second sub-conducting portion 111, and then performs a subsequent step of electrically connecting to the first sub-conducting portion 1122 during the subsequent formation of the second electrode 115.
  • the connection electrode 102 is formed between the thin film transistor 121 and the light emitting unit 131.
  • the via hole 1101 penetrating the flat layer 110 can be formed.
  • the second sub-conducting portion 111 can be formed.
  • the second sub-conducting portion 111 is formed at a position corresponding to the via hole 1101, and the second sub-conducting portion 111 and the connecting electrode are connected. 102 electrical connection.
  • a first transparent conductive layer 112 is further formed, and the first transparent conductive layer 112 includes a first sub-conducting portion 1122 insulated from the first electrode 1121.
  • the first sub-conducting portion 1122 is electrically connected to the second sub-conducting portion 111, and then performs a subsequent step of electrically connecting to the first sub-conducting portion 1122 during the subsequent formation of the second electrode 115.
  • connection electrode 102 is formed in the same layer as the drain electrode 1081 of the thin film transistor 121.
  • passivation layer 109 and the planarization layer 110 are formed on the source/drain layer 108, a corresponding connection electrode is formed.
  • the via holes of 102 and the drain 1081 form the conductive portion 141 and the first electrode 1121 which are insulated from each other in the same layer when the first transparent conductive layer 112 is formed.
  • a method for fabricating a display substrate may be performed by etching, for example, when a via is formed, the connection electrode 102 may be etched, and a portion of the connection electrode 102 may be exposed, or may be deposited or The conductive portion 141 or the second sub-conductive portion 111 is formed in the via hole by printing or the like.
  • a light-emitting functional layer can be prepared using a fine metal mask, and a second electrode 115 and a light extraction layer can be prepared by using an open mask. Packaging and other processes.
  • an RGB OLED device or a white light OELD device prepared by evaporation or printing may be used.
  • the organic light-emitting functional layer is prepared, the conductive portion 141 may be shielded, thereby making it possible to fabricate the second electrode 115.
  • the second electrode 115 is electrically connected to the conduction portion 141.
  • the method for fabricating the display substrate provided by at least one embodiment of the present disclosure and the display substrate provided by at least one embodiment of the present disclosure may be referred to each other or the like, and details are not described herein again.
  • At least one embodiment of the present disclosure provides a display device including any of the display substrates provided by the embodiments of the present disclosure.
  • the display device can also include an encapsulation layer 116.
  • the encapsulation layer 116 may employ a film or a substrate, for example, a glass substrate may be employed, but is not limited thereto.
  • “same layer” refers to a layer structure formed by forming a film layer for forming a specific pattern by the same film forming process, and then forming the pattern by one patterning process using the same mask.
  • a patterning process may include multiple exposure, development, or etching processes, and the particular pattern in the resulting layer structure may be continuous or discontinuous, and these particular patterns may also be at different heights. Or have different thicknesses.

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  • Manufacturing & Machinery (AREA)
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Abstract

一种显示基板及其制作方法、显示装置。显示基板，包括：衬底基板(101)、薄膜晶体管(121)、发光元件(131)、连接电极(102)和导通部(141)，薄膜晶体管(121)位于衬底基板(101)上，发光元件(131)位于薄膜晶体管(121)上，包括第一电极(1121)和第二电极(115)，第一电极(1121)和第二电极(115)彼此间隔，第一电极(1121)与薄膜晶体管(121)电连接；连接电极(102)位于衬底基板(101)和发光元件(131)之间，连接电极(102)与薄膜晶体管(121)彼此绝缘；导通部(141)被配置为使第二电极(115)与连接电极(102)并联。

Description

显示基板及其制作方法、显示装置
相关申请的交叉引用
本专利申请要求于2017年5月10日递交的中国专利申请第201710327057.6号的优先权，在此全文引用上述中国专利申请公开的内容以作为本公开的示例的一部分。
技术领域
本公开至少一实施例涉及一种显示基板及其制作方法、显示装置。
背景技术
小尺寸有机发光二极管(Organic Light Emitting Diode，OLED)面板主要是顶发射OLED，阴极主要是Mg/Ag等半反射半透明的阴极，而这种半反射半透明的阴极的电阻较高，由于较明显的压降(IR drop)效应和较高的功耗，半反射半透明的阴极无法在大尺寸OLED面板上实施。
发明内容
本公开的至少一实施例提供一种显示基板，包括：
衬底基板，
薄膜晶体管，位于所述衬底基板上，
发光元件，位于所述薄膜晶体管上，包括第一电极和第二电极，所述第一电极和所述第二电极彼此间隔，所述第一电极与所述薄膜晶体管电连接；
连接电极，位于所述衬底基板和所述发光元件之间，所述连接电极与所述薄膜晶体管彼此绝缘；
导通部，被配置为使所述第二电极与所述连接电极并联。
本公开的至少一实施例还提供一种显示基板的制作方法，包括：
在衬底基板上形成薄膜晶体管，
在所述薄膜晶体管上形成发光元件，所述发光元件包括第一电极和第二电极，所述第一电极和所述第二电极彼此间隔，所述第一电极与所述薄膜晶体管电连接；
在所述衬底基板和所述发光元件之间形成连接电极，所述连接电极与所述薄膜晶体管彼此绝缘；
形成导通部，所述导通部被配置为使所述第二电极与所述连接电极并联。
本公开的至少一实施例还提供一种显示装置，包括本公开的至少一实施例提供的显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开一实施例提供的显示基板及包含该显示基板的显示装置的示意图；
图2A为本公开一实施例提供的显示基板中子像素和导通部的平面示意图；
图2B为本公开另一实施例提供的显示基板中子像素和导通部的平面示意图；
图3A为本公开一实施例提供的显示基板中第一电极和导通部的平面示意图；
图3B为本公开另一实施例提供的显示基板中第一电极和导通部的平面示意图；
图4为本公开一实施例提供的显示基板中连接电极的平面示意图；
图5为本公开另一实施例提供的显示基板及包含该显示基板的显示装置的示意图；
图6A为本公开一实施例提供的显示基板中连接电极的平面示意图；
图6B为本公开另一实施例提供的显示基板中连接电极的平面示意图；
图7为本公开另一实施例提供的显示基板及包含该显示基板的显示装置的示意图；
图8为本公开另一实施例提供的显示基板及包含该显示基板的显示装置的示意图；
图9为本公开一实施例提供的显示基板的制作方法中形成过孔的示意 图；
图10为本公开一实施例提供的显示基板的制作方法中在过孔中形成第二子导通部的示意图；
图11为本公开一实施例提供的显示基板的制作方法中第二子导通部上形成与其电连接的第一子导通部的示意图；
图12为本公开一实施例提供的显示基板的制作方法中形成过孔的示意图；
图13为本公开一实施例提供的显示基板的制作方法中在过孔中形成第二子导通部的示意图；
图14为本公开一实施例提供的显示基板的制作方法中第二子导通部上形成与其电连接的第一子导通部的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在发明人所知的技术中，主流的大尺寸有机发光二极管(OLED)面板都是使用底发射OLED，但底发射OLED由于出光面在设有薄膜晶体管(Thin Film Transistor，TFT)的一侧，势必导致开口率的降低。同时，大尺寸OLED 面板的TFT通常采用例如IGZO的氧化物半导体材料，由于氧化物半导体材料对光非常敏感，底发射OLED无法避免环境光和OLED发出的光对氧化物半导体材料的影响。通常的顶发射模式的显示基板包括透明或者半透明电极以利于光出射。透明或者半透明电极具有较高电阻时，可导致亮度不均，且具有较高的功耗。
如图1所示，本公开至少一实施例提供一种显示基板10，包括：
衬底基板101，例如，衬底基板101可以包括玻璃基板，但不限于此；
薄膜晶体管(TFT)121，位于衬底基板101上，
发光元件131，位于薄膜晶体管121上，包括第一电极1121和第二电极115，第一电极1121和第二电极115彼此间隔(例如，第一电极1121和第二电极115以二者之间的发光功能层114间隔)，例如第一电极1121比第二电极115更靠近衬底基板101(第一电极1121先于第二电极115形成在衬底基板101上)，第一电极1121与薄膜晶体管121电连接；第二电极115与薄膜晶体管121彼此绝缘；
连接电极102，位于衬底基板101和发光元件131之间，连接电极102与薄膜晶体管121彼此绝缘；
导通部141，被配置为使第二电极115与连接电极102并联。
导通部141位于第二电极115与连接电极102之间。导通部141与第一电极1121彼此绝缘，导通部141与薄膜晶体管121彼此绝缘。
本公开至少一实施例提供的显示基板，至少部分地具有以下至少之一的
有益效果：
(1)可采用顶发射的模式，顶发射模式的显示面板可具有较大的开口率，可明显提升产品亮度。
(2)利于形成大尺寸显示基板/显示面板/显示装置。
(3)第二电极115与连接电极102通过导通部141并联，第二电极115与连接电极102不同层设置，可以使得与第二电极115电连接的连接电极102可以采用不同于第二电极115的材料，可以使得第二电极115采用高透过率的材料，提高出光效率。进而，因设置了连接电极102，可以通过连接电极102向第二电极115施加电信号，可以减少压降，使得显示基板不同位置处因压降带来的电信号的差异减小，提高显示装置出光均一性，并可以降低功 耗。
例如，本公开的实施例中，彼此间隔包括在所选择的状态下彼此绝缘。例如，两个部件/元件彼此间隔是指在薄膜晶体管和/或发光元件处于非工作状态时该两个部件/元件彼此绝缘。当处于工作状态时，该两个部件/元件可以电性相连。非工作状态例如包括不通电或不被施加电压的状态，例如包括薄膜晶体管不导通和/或发光元件不发光的状态。
根据本公开一实施例提供的显示基板，第一电极1121可以为阳极，第二电极115可以为阴极，但不限于此。
如图1所示，根据本公开一实施例提供的显示基板，本公开实施例提供的显示基板10可应用于顶发射的显示装置，如图1所示，发光单元131发出的光从显示装置的顶面出射，连接电极102可不透明，以具有反射外界环境光的功能，从显示装置底面入射的光线可因设置的连接电极102而被反射。
如图1所示，根据本公开一实施例提供的显示基板，薄膜晶体管121可包括栅极104、有源层106、漏极1081和源极1082。第一电极1121可与漏极1081电连接。源极1082可被配置来施加电信号。栅极104可被配置来施加电信号以控制薄膜晶体管121的开启和关闭。第一电极1121与薄膜晶体管121电连接例如是指第一电极1121与薄膜晶体管121的漏极1081或源极1082电连接。本公开的实施例中，源极和漏极相对而言，可相互替换。本公开的实施例中，以第一电极1121与薄膜晶体管121的漏极1081电连接为例进行说明。图1中以形成底栅结构的TFT为例进行说明。需要说明的是，也可以采用顶栅结构的TFT，以利于栅极遮挡照射到有源层的光线。
如图1所示，根据本公开一实施例提供的显示基板，显示基板10还包括位于衬底基板101上的缓冲层103，栅极104位于缓冲层103上，栅极104上设置栅极绝缘层105，栅极绝缘层105上设置有源层106，有源层106上设置刻蚀阻挡层107，刻蚀阻挡层107上设置源漏极层108。源漏极层108包括彼此分离且分别与有源层106相连的漏极1081和源极1082。源漏极层108上设置钝化层109，钝化层109上设置平坦层110。过孔11101贯穿缓冲层103、栅极绝缘层105、刻蚀阻挡层107、钝化层109和平坦层110。在过孔11101中形成有第二子导通部111。平坦层110上设置第一透明导电层112，第一透明导电层112包括第一电极1121和第一子导通部1122，第一电极1121 和第一子导通部1122彼此绝缘。第一子导通部1122和第二子导通部111构成导通部141。第一透明导电层112上形成像素限定层113，像素限定层113上设置发光功能层114，发光功能层114上形成第二电极115。第二电极115通过导通部141与连接电极102电连接。
例如，发光功能层114至少包括发光层，还可以包括空穴传输层、空穴注入层、电子传输层、电子注入层等至少之一，当然，还可以包括其他的层结构，在此不做限定。
例如，缓冲层103、栅极绝缘层105、刻蚀阻挡层107和钝化层109中任一个的材料可采用SiOx，SiNy和SiNxOy中的至少一个，平坦层110可采用树脂材料。平坦层可具有基本平坦的表面，以利于制作第一电极。
需要说明的是，本公开实施例提供的显示基板的构造不限于图1中所示，本公开的实施例以图1所示的显示基板为例进行说明。
如图2A所示，根据本公开一实施例提供的显示基板，包括多个子像素100，多个子像素100呈阵列排布。子像素100可通过像素限定层113来限定。显示基板除了子像素100所在的像素区外，还包括非像素区0100。如图2A和2B所示，导通部141可位于非像素区0100内。例如，非像素区010包括子像素100之间的区域。
如图3A和3B所示，根据本公开一实施例提供的显示基板，每个子像素100可对应一个发光元件131。发光元件131的数量为多个，各发光元件131的第一电极1121之间彼此绝缘。如图3A和3B所示，导通部141可位于非像素区0100内。导通部141可位于相邻的第一电极1121之间。例如，如图3A所示，导通部141位于相邻两个第一电极1121之间。例如，如图3B所示，导通部141位于相邻四个第一电极1121之间。
各发光元件131的第二电极115可彼此连通并被配置为给多个发光元件131提供电信号。因连接电极102的设置，可使得不同位置处的电信号差异减小，信号延迟减小，从而提高显示效果。
如图4所示，根据本公开一实施例提供的显示基板，连接电极102的形状可包括面状。面状的连接电极102可位于衬底基板101和薄膜晶体管121之间(如图1所示)。如图4示出了图1所示的显示基板中的连接电极的平面示意图。面状的连接电极102利于反射发光单元131照射到其上的光，利 于提高光的利用率。但连接电极102的形状并不限于面状。还可采用网格状等其他形状。面状的连接电极102更利于减小压降。
根据本公开一实施例提供的显示基板，连接电极102的方阻低于第二电极115的方阻。即，连接电极102可具有低方阻。例如，第二电极115也可只提供相邻子像素的电信号，无需很低的方阻，可以制备成很高穿透率的透明电极，以提高出光效率。
例如，第一电极1121和第二电极115可采用金属(薄金属层)或透明导电氧化物材料，例如，薄金属层可以是Mg/Ag层，透明导电氧化物包括氧化铟锌(IZO)、氧化铟锡(ITO)等金属氧化物透明导电材料，还可以为叠层结构，例如ITO/Ag/ITO。例如，连接电极102的材料包括金属，导通部141的材料包括金属，透明导电氧化物至少之一，透明导电氧化物例如包括ITO。金属材料的连接电极102可具有低方阻且不透明。
如图5所示，根据本公开一实施例提供的显示基板，为了节省制作工艺，连接电极102与漏极同层设置，可使得导通部141与第一电极1121同层设置。导通部141与第一电极1121彼此绝缘。从而，可以同层形成导通部141与第一电极1121，省去单独制作导通部141的步骤。同样，导通部141与第一电极1121的平面示意图可参照图3A和3B所示。如图5所示，连接电极102包括镂空部10201，连接电极102的平面图可参照图6A和6B。例如，当连接电极102和源漏极层108同层设置时，图6A和6B中省略了位于镂空部10201内的源极1082和漏极1081，且该情况下，源极1082和漏极1081与连接电极102彼此绝缘。
例如，如图6A所示，连接电极102的形状包括含有镂空结构10201的面状。
如图图6A和6B所示，镂空结构10201形状可包括圆形、矩形等形状。
如图7所示，根据本公开一实施例提供的显示基板，连接电极102可位于薄膜晶体管121和发光元件131之间，并且连接电极102包括镂空部10201以使得连接电极102和第一电极1121彼此绝缘。第一电极1121通过贯穿平坦层110和钝化层109的过孔112101与漏极1081电连接，在垂直于衬底基板101的方向上，过孔112101位于镂空结构10201的范围内，且在显示基板的俯视图上，过孔112101的尺寸小于镂空结构10201的尺寸，从而，可使得 连接电极102和第一电极1121电绝缘，避免两者电连接。
根据本公开一实施例提供的显示基板，如图8所示，连接电极102可与薄膜晶体管121的栅极105同层设置，并且连接电极102包括镂空部10201以使连接电极102和薄膜晶体管121的栅极105彼此绝缘。连接电极102的平面图可参照图6A和6B。
本公开至少一实施例还提供一种显示基板的制作方法，如图1、5、7和8所示，包括：
在衬底基板101上形成薄膜晶体管121，
在薄膜晶体管121上形成发光元件131，发光元件131包括第一电极1121和第二电极115，第一电极1121和第二电极115彼此绝缘，第一电极1121比第二电极115更靠近衬底基板101，第一电极1121与薄膜晶体管121电连接；
在衬底基板101和发光元件131之间形成连接电极102，连接电极102与薄膜晶体管121彼此绝缘；
形成导通部141，导通部141被配置为使第二电极115与连接电极102电连接。导通部141位于第二电极115与连接电极102之间。
根据本公开一实施例提供的显示基板的制作方法，连接电极102的方阻低于第二电极115的方阻。
根据本公开一实施例提供的显示基板的制作方法，如图1所示，可在衬底基板101和薄膜晶体管121之间形成连接电极102。
根据本公开一实施例提供的显示基板的制作方法，可如图2A、2B、3A和3B所示，发光元件131的数量为多个，各发光元件131的第一电极1121之间彼此绝缘，各发光元件131的第二电极115彼此连通并被配置为给多个发光元件131提供电信号。从而，可利于减少信号传输时的压降。
根据本公开一实施例提供的显示基板的制作方法，如图3A和3B所示，导通部141可位于相邻的第一电极1121之间。
根据本公开一实施例提供的显示基板的制作方法，如图5和8所示，薄膜晶体管121包括栅极105和漏极1081，第一电极1121可与漏极1081电连接。连接电极102可与薄膜晶体管121的栅极105或漏极1081之一同层形成，并且连接电极102包括镂空部以使连接电极102和薄膜晶体管121彼此绝缘。
根据本公开一实施例提供的显示基板的制作方法，为了减少制作工艺，可如图5所示，同层形成导通部141和第一电极1121，并且导通部141与第一电极1121彼此绝缘。此时，漏极1081可以与连接电极102同层设置。以利于减少制作工艺。
根据本公开一实施例提供的显示基板的制作方法，为了节省制作工艺，如图8所示，连接电极102还可与栅极104同层设置，连接电极102包括镂空部10201以使连接电极102和薄膜晶体管121的栅极105彼此绝缘。
根据本公开一实施例提供的显示基板的制作方法，如图7所示，连接电极102位于薄膜晶体管121和发光元件131之间，并且连接电极102包括镂空部10201以使得连接电极102和第一电极1121彼此绝缘。
根据本公开一实施例提供的显示基板的制作方法，导通部141可单独制作，也可以与第一电极1121同层形成，连接电极102可形成在衬底基板101和薄膜晶体管121之间，也可以形成在薄膜晶体管121和发光单元131之间，还可以和薄膜晶体管121中的栅极104或源漏极层108同层形成。
以形成如图1所示的显示基板为例。如图9所示，连接电极102形成在衬底基板101和薄膜晶体管121之间，形成平坦层110后，可形成贯穿缓冲层103、栅极绝缘层105、刻蚀阻挡层107、钝化层109和平坦层110的过孔11101。如图10所示，形成过孔11101后，可形成第二子导通部111，第二子导通部111形成在对应过孔11101的位置处，第二子导通部111与连接电极102电连接。如图11所示，再形成第一透明导电层112，第一透明导电层112包括与第一电极1121绝缘的第一子导通部1122。第一子导通部1122与第二子导通部111电连接，再进行后续步骤，在后续形成第二电极115的过程中，使其与第一子导通部1122电连接。
以形成如图7所示的显示基板为例，如图12所示，连接电极102形成在薄膜晶体管121和发光单元131之间，形成平坦层110后，可形成贯穿平坦层110的过孔1101，如图13所示，形成过孔1101后，可形成第二子导通部111，第二子导通部111形成在对应过孔1101的位置处，第二子导通部111与连接电极102电连接。如图14所示，再形成第一透明导电层112，第一透明导电层112包括与第一电极1121绝缘的第一子导通部1122。第一子导通部1122与第二子导通部111电连接，再进行后续步骤，在后续形成第二电极 115的过程中，使其与第一子导通部1122电连接。
以形成如图5所示的显示基板为例，连接电极102与薄膜晶体管121的漏极1081同层形成，在源漏极层108上形成钝化层109和平坦层110后，制作对应连接电极102和漏极1081的过孔，在形成第一透明导电层112时，同层形成彼此绝缘的导通部141和第一电极1121。该种制作方法可节省单独形成连接电极102和单独形成导通部141的步骤，利于工艺的节省。
根据本公开一实施例提供的显示基板的制作方法，过孔的形成可采用刻蚀的方法，例如，形成过孔时，可刻蚀到连接电极102，裸露一部分连接电极102，可通过沉积或者印刷等方式在过孔中形成导通部141或形成第二子导通部111。
根据本公开一实施例提供的显示基板的制作方法，可使用精细金属掩模(fine metal mask)制备发光功能层，再采用开口掩模板(open mask)制备第二电极115和光提取层，再进行封装等工艺。形成发光功能层114时，可以采用蒸镀或者打印制备的RGB OLED器件或者白光OELD器件，制备有机发光功能层时，可遮住导通部141，从而，在制作第二电极115时，可使得第二电极115与导通部141电连接。
本公开至少一实施例提供的显示基板的制作方法和本公开至少一实施例提供的显示基板相同或相似之处可互相参见，在此不再赘述。
本公开至少一实施例提供一种显示装置，包括本公开实施例提供的任一显示基板。
如图1、5、7和8所示，显示装置还可包括封装层116。例如，封装层116可采用薄膜或衬底基板，例如，可采用玻璃基板，但不限于此。
在本公开的实施例中，“同层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。
有以下几点需要说明：
(1)除非另作定义，本公开实施例以及附图中，同一附图标记代表同一含义。
(2)本公开实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(3)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
(4)在不冲突的情况下，本公开的同一实施例及不同实施例中的特征可以相互组合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种显示基板，包括：
    衬底基板，
    薄膜晶体管，位于所述衬底基板上，
    发光元件，位于所述薄膜晶体管上，包括第一电极和第二电极，所述第一电极和所述第二电极彼此间隔，所述第一电极与所述薄膜晶体管电连接；
    连接电极，位于所述衬底基板和所述发光元件之间，所述连接电极与所述薄膜晶体管彼此绝缘；
    导通部，被配置为使所述第二电极与所述连接电极并联。
  2. 根据权利要求1所述的显示基板，其中，所述连接电极的方阻低于所述第二电极的方阻。
  3. 根据权利要求1所述的显示基板，其中，所述导通部与所述第一电极同层设置，并且所述导通部与所述第一电极彼此绝缘。
  4. 根据权利要求1所述的显示基板，其中，所述连接电极位于所述衬底基板和所述薄膜晶体管之间。
  5. 根据权利要求4所述的显示基板，其中，所述连接电极的形状包括面状。
  6. 根据权利要求1所述的显示基板，其中，所述连接电极位于所述薄膜晶体管和所述发光元件之间，并且所述连接电极包括镂空部以使得所述连接电极和所述第一电极彼此绝缘。
  7. 根据权利要求1所述的显示基板，其中，所述薄膜晶体管包括栅极和漏极，所述第一电极与所述漏极电连接，所述连接电极与所述薄膜晶体管的栅极或漏极之一同层设置，并且所述连接电极包括镂空部以使所述连接电极和所述薄膜晶体管彼此绝缘。
  8. 根据权利要求6或7所述的显示基板，其中，所述连接电极的形状包括含有镂空结构的面状。
  9. 根据权利要求1-7任一项所述的显示基板，其中，所述发光元件的数量为多个，各发光元件的第一电极之间彼此绝缘，各发光元件的第二电极彼此连通并被配置为给所述多个发光元件提供电信号。
  10. 根据权利要求9所述的显示基板，其中，所述导通部位于相邻的第 一电极之间。
  11. 根据权利要求1-7任一项所述的显示基板，其中，所述第二电极的材料包括透明导电氧化物，所述连接电极的材料包括金属，所述导通部的材料包括金属和透明导电氧化物至少之一。
  12. 一种显示基板的制作方法，包括：
    在衬底基板上形成薄膜晶体管，
    在所述薄膜晶体管上形成发光元件，所述发光元件包括第一电极和第二电极，所述第一电极和所述第二电极彼此间隔，所述第一电极比所述第二电极更靠近衬底基板，所述第一电极与所述薄膜晶体管电连接；
    在所述衬底基板和所述发光元件之间形成连接电极，所述连接电极与所述薄膜晶体管彼此绝缘；
    形成导通部，所述导通部被配置为使所述第二电极与所述连接电极并联。
  13. 根据权利要求12所述的显示基板的制作方法，其中，所述连接电极的方阻低于所述第二电极的方阻。
  14. 根据权利要求12所述的显示基板的制作方法，其中，同层形成所述导通部和所述第一电极，并且所述导通部与所述第一电极彼此绝缘。
  15. 根据权利要求12所述的显示基板的制作方法，其中，在所述衬底基板和所述薄膜晶体管之间形成所述连接电极。
  16. 根据权利要求12所述的显示基板的制作方法，其中，所述连接电极位于所述薄膜晶体管和所述发光元件之间，并且所述连接电极包括镂空部以使得所述连接电极和所述第一电极彼此绝缘。
  17. 根据权利要求12-16任一项所述的显示基板的制作方法，其中，所述发光元件的数量为多个，各发光元件的第一电极之间彼此绝缘，各发光元件的第二电极彼此连通并被配置为给所述多个发光元件提供电信号。
  18. 根据权利要求17所述的显示基板的制作方法，其中，所述导通部位于相邻的第一电极之间。
  19. 根据权利要求12-16任一项所述的显示基板的制作方法，其中，所述薄膜晶体管包括栅极和漏极，所述第一电极与所述漏极电连接，所述连接电极与所述薄膜晶体管的栅极或漏极之一同层形成，并且所述连接电极包括镂空部以使所述连接电极和所述薄膜晶体管彼此绝缘。
  20. 一种显示装置，包括权利要求1-11任一项所述的显示基板。
PCT/CN2017/115266 2017-05-10 2017-12-08 显示基板及其制作方法、显示装置 WO2018205587A1 (zh)

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