WO2023280110A1 - 显示基板及其制备方法 - Google Patents

显示基板及其制备方法 Download PDF

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Publication number
WO2023280110A1
WO2023280110A1 PCT/CN2022/103659 CN2022103659W WO2023280110A1 WO 2023280110 A1 WO2023280110 A1 WO 2023280110A1 CN 2022103659 W CN2022103659 W CN 2022103659W WO 2023280110 A1 WO2023280110 A1 WO 2023280110A1
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Prior art keywords
layer
base substrate
via hole
display substrate
sub
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PCT/CN2022/103659
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English (en)
French (fr)
Inventor
张大成
李盼
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京东方科技集团股份有限公司
北京京东方技术开发有限公司
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Priority to US18/546,721 priority Critical patent/US20240172525A1/en
Publication of WO2023280110A1 publication Critical patent/WO2023280110A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80522—Cathodes combined with auxiliary electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/824—Cathodes combined with auxiliary electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass

Definitions

  • Embodiments of the present disclosure relate to a display substrate and a manufacturing method thereof.
  • OLED Organic Light Emitting Diode, organic light-emitting diode
  • OLED Organic Light Emitting Diode, organic light-emitting diode
  • An organic light-emitting diode as a light-emitting device in an OLED display device generally includes an anode, a cathode, and an organic functional layer, such as a light-emitting layer, located between the anode and the cathode.
  • an organic functional layer such as a light-emitting layer
  • At least one embodiment of the present disclosure provides a display substrate, which includes a base substrate, a first metal layer, a first insulating layer, a first electrode layer, a luminescent material layer, a carbon-containing structure layer, and a second electrode layer.
  • a metal layer is disposed on the base substrate, including at least one auxiliary electrode pattern, and a first insulating layer is disposed on a side of the first metal layer away from the base substrate, and includes an exposed portion of the at least one auxiliary electrode pattern.
  • the first electrode layer is arranged on the side of the first insulating layer away from the base substrate, and the luminescent material layer is arranged on the side of the first electrode layer away from the substrate One side of the substrate, wherein the first electrode layer and the luminescent material layer include at least one second via hole exposing part of the at least one auxiliary electrode pattern and penetrating the at least one first via hole, containing carbon
  • the structural layer is at least partially disposed in the at least one second via hole, and the second electrode layer is disposed on a side of the luminescent material layer and the carbon-containing structural layer away from the base substrate, wherein the first The second electrode layer is electrically connected to the at least one auxiliary electrode pattern through the carbon-containing structure layer, and the surface of the first metal layer close to the base substrate in the middle of the second via hole is connected to the second via hole.
  • the surface distance of the electrode layer away from the substrate is d1
  • the average carbon-to-oxygen ratio of the carbon-containing structure layer is c1
  • the first metal layer near the edge of the second via hole is close to the substrate
  • the distance between the surface of the substrate and the surface of the second electrode layer away from the base substrate is d2
  • the average carbon-oxygen ratio of the carbon-containing structure layer is c2
  • the average carbon-to-oxygen ratio of the carbon-containing structure layer is greater than 1.3:1 and less than 10:1.
  • the area of the orthographic projection of the carbon-containing structure layer on the base substrate is smaller than the area of the orthographic projection of the auxiliary electrode pattern on the base substrate .
  • the orthographic projection of the first via hole on the base substrate is located within the orthographic projection of the auxiliary electrode pattern on the base substrate
  • the The orthographic projection of the second via hole on the base substrate is located within the orthographic projection of the first via hole on the base substrate.
  • the carbon-containing structure layer includes a first portion in contact with the auxiliary electrode pattern and a second portion located on the sidewall of the second via hole, the first portion A part of the orthographic projection on the base substrate is located within the orthographic projection of the second via hole on the base substrate.
  • At least part of the edges of the second via holes are zigzag-shaped.
  • the contour of the orthographic projection of the first via hole on the auxiliary electrode pattern includes n inflection points, and the second via hole is on the auxiliary electrode pattern
  • the contour of the orthographic projection includes m inflection points, then: m>n>0.
  • the area of the orthographic projection of the carbon-containing structure layer on the base substrate is S1
  • the average carbon-to-oxygen ratio is Cs1
  • the first via hole does not include
  • the orthographic projection area of the luminescent material layer on the base substrate in the region of the carbon-containing structure layer is S2
  • the average carbon-oxygen ratio is Cs2
  • Carbon-oxygen matching coefficient k S2*Cs2/S1*Cs1, 0 ⁇ k ⁇ 2/3.
  • 0 ⁇ k ⁇ 0.2 In the display substrate provided by at least one embodiment of the present disclosure, 0 ⁇ k ⁇ 0.2.
  • the auxiliary electrode pattern includes a first protrusion protruding in a direction away from the base substrate, and the first protrusion is located on the base substrate.
  • the orthographic projection on is located within the orthographic projection of the second via hole on the base substrate.
  • the display substrate provided in at least one embodiment of the present disclosure further includes: a second insulating layer located between the first metal layer and the first insulating layer, wherein the second via hole penetrates through the second insulating layer , the first electrode layer is in contact with the second insulating layer through the first via hole of the first insulating layer.
  • the part of the auxiliary electrode pattern exposed by the second via hole is the first protrusion.
  • the thickness of the first raised portion is d3', and the auxiliary electrode pattern except The thickness of the part outside the first raised portion is d3, then: d3>d3'.
  • the display substrate provided in at least one embodiment of the present disclosure further includes: an interlayer insulating layer disposed between the base substrate and the first metal layer, wherein the interlayer insulating layer includes A second protruding portion protruding in the direction of the base substrate, the first protruding portion is disposed on a side of the second protruding portion away from the base substrate.
  • the portion of the interlayer insulating layer in contact with the first raised portion is the second raised portion;
  • the thickness of the second raised part is d4'
  • the thickness of the part of the interlayer insulating layer except the second raised part is d4, then: d4 ⁇ d4'.
  • a surface of the interlayer insulating layer close to the base substrate is a flat surface.
  • the auxiliary electrode pattern includes a first slope at the edge of the second via hole, and the interlayer insulating layer includes a slope at the edge of the second via hole.
  • the second slope, the length of the first slope is shorter than the length of the second slope.
  • the slope angle of the second slope portion is greater than the slope angle of the first slope portion.
  • the slope angle of the second slope portion is larger than the slope angle of the first insulating layer at the first via hole, and larger than the slope angle of the second insulating layer.
  • the slope angle at the second via is larger than the slope angle of the first insulating layer at the first via hole, and larger than the slope angle of the second insulating layer.
  • the display substrate provided in at least one embodiment of the present disclosure further includes a pixel driving circuit, wherein the pixel driving circuit includes a transistor and a storage capacitor, and the transistor includes an active layer disposed on the base substrate, disposed on The gate on the side of the active layer away from the base substrate and the source layer and drain layer arranged on the side of the gate away from the base substrate, the source layer and the drain layer They are respectively electrically connected to the active layer, the storage capacitor includes a first plate and a second plate, the source layer and the drain layer, and at least part of the second plate are arranged on the first In the metal layer, the second insulating layer is disposed on a side of the source layer and the drain layer away from the base substrate.
  • the pixel driving circuit includes a transistor and a storage capacitor
  • the transistor includes an active layer disposed on the base substrate, disposed on The gate on the side of the active layer away from the base substrate and the source layer and drain layer arranged on the side of the gate away from the base substrate, the source layer and the drain layer They
  • the first insulating layer further has a third via hole that exposes at least part of the second electrode plate, and is parallel to the surface of the base substrate. direction, the maximum width of the auxiliary electrode pattern is greater than the maximum width of the third via hole.
  • the perimeter of the contour of the orthographic projection of the second via hole on the auxiliary electrode pattern is larger than that of the third via hole on the second electrode plate.
  • the display substrate provided in at least one embodiment of the present disclosure further includes a light-shielding metal layer disposed between the base substrate and the active layer, and a gate metal pattern disposed on the same layer as the gate, wherein the The orthographic projection of the gate metal pattern on the base substrate at least partially overlaps with the orthographic projection of the light-shielding metal layer on the base substrate, and is at least partially overlapped with the source layer or the drain layer on the The orthographic projections on the base substrate are at least partially overlapped to form the storage capacitor.
  • the display substrate provided in at least one embodiment of the present disclosure further includes a buffer layer disposed between the light-shielding metal layer and the active layer, and the surface of the auxiliary electrode pattern far away from the base substrate and the The maximum distance of the surface of the buffer layer away from the base substrate is greater than the surface of the source layer and the drain layer far away from the base substrate and the surface of the buffer layer far away from the base substrate the maximum distance.
  • the second insulating layer has a first sub-via hole exposing the auxiliary electrode pattern and a second sub-via hole exposing the source layer or the drain layer. via holes, the second insulating layer has a third slope at the first sub-via, and a fourth slope at the second sub-via, and the slope angle of the third slope is greater than the Describe the slope angle of the fourth slope.
  • the luminescent material layer in the direction perpendicular to the board surface of the base substrate, has a first luminescent material portion overlapping with the third slope and a first luminescent material portion overlapping with the third slope.
  • the second luminescent material portion overlapping the fourth slope portion the thickness of the first luminescent material portion is smaller than the thickness of the second luminescent material portion.
  • the display substrate provided in at least one embodiment of the present disclosure further includes alternately arranged light-emitting pixel columns and transparent pixel columns, the light-emitting pixel columns include a plurality of light-emitting pixel units, and each of the plurality of light-emitting pixel units includes a plurality of light-emitting pixel units.
  • the transparent pixel column includes a plurality of transparent pixel units, the plurality of transparent pixel units are defined by grid lines and boundaries of the light-emitting pixel column, and each of the plurality of transparent pixel units includes a transparent pixel unit
  • the sub-pixels, the plurality of transparent pixel units and the plurality of light-emitting pixel units are arranged in a staggered manner along the column direction.
  • the plurality of light-emitting sub-pixels are basically arranged in a square shape, and the transparent sub-pixels are concave toward the direction of the light-emitting sub-pixels.
  • each of the plurality of light-emitting pixel units includes four sub-pixels, and the four sub-pixels include a red sub-pixel, a green sub-pixel, and a blue sub-pixel and a white sub-pixel, the red sub-pixel is in the same row as the blue sub-pixel, the green sub-pixel is in the same row as the white sub-pixel, the red sub-pixel is in the same row as the blue sub-pixel.
  • the sum of the areas of the light emitting regions is greater than the sum of the areas of the light emitting regions of the green sub-pixel and the white sub-pixel.
  • the red sub-pixel is located in the same column as the white sub-pixel
  • the green sub-pixel is located in the same column as the blue sub-pixel
  • the red sub-pixel The sum of the areas of the light-emitting regions of the white sub-pixel is greater than the sum of the areas of the light-emitting regions of the green sub-pixel and the blue sub-pixel.
  • the auxiliary electrode pattern is arranged in a row where the red sub-pixel and the blue sub-pixel are located.
  • each of the plurality of light-emitting sub-pixels includes a light-emitting device
  • the light-emitting device includes a first electrode located in the first electrode layer, a light-emitting device located in the light-emitting The light-emitting layer in the material layer and the second electrode located in the second electrode layer
  • the first electrode includes a first sub-electrode and a second sub-electrode
  • the first sub-electrode and the second sub-electrode pass through
  • the conductive structure is electrically connected, and the conductive structure is electrically connected to the source layer or the drain layer through the second sub-via hole, in a direction parallel to the board surface of the base substrate, so the second Two sub-vias are located between the first sub-electrode and the second sub-electrode.
  • the first sub-electrode in the direction parallel to the board surface of the base substrate, at least includes a first side, a second side, a The third side, the fourth side and the fifth side, at least one of the first side, the second side, the third side, the fourth side and the fifth side is a straight side.
  • the lengths of the first side, the second side, the third side, the fourth side and the fifth side are L1, L2, L3, L4 and L5 in sequence, but:
  • the second sub-electrode in a direction parallel to the board surface of the base substrate, includes at least a sixth side, a seventh side, a The eighth side, the ninth side and the tenth side, at least one of the sixth side, the seventh side, the eighth side, the ninth side and the tenth side is a straight side.
  • the lengths of the sixth side, the seventh side, the eighth side, the ninth side and the tenth side are L6, L7, L8, L9 and L10 in sequence, but:
  • At least one embodiment of the present disclosure provides a display substrate, which includes a base substrate, an interlayer insulating layer, a first metal layer, a first insulating layer, a first electrode layer, a luminescent material layer, a carbon-containing structure layer, and a second Two electrode layers, the interlayer insulating layer is disposed on the base substrate, the first metal layer is disposed on the side of the interlayer insulating layer away from the base substrate, and includes at least one auxiliary electrode pattern, the first insulating layer layer is disposed on the side of the first metal layer away from the base substrate, including at least one first via hole exposing part of the at least one auxiliary electrode pattern, and the first electrode layer is disposed on the first insulating layer The side of the first electrode layer away from the base substrate, the luminescent material layer is disposed on the side of the first electrode layer away from the base substrate, wherein the first electrode layer and the luminescent material layer include an exposed portion The at least one auxiliary electrode pattern and at least one second via hole penetrating the
  • the slope angle of the second slope portion is larger than the slope angle of the first slope portion, and larger than the slope angle of the first insulating layer at the first via hole.
  • the slope angle is larger than the slope angle of the second insulating layer at the second via hole.
  • the surface of the first metal layer close to the base substrate near the middle of the second via hole and the surface of the second electrode layer far away from the substrate The distance between the surface of the base substrate is d1, the average carbon-to-oxygen ratio of the carbon-containing structure layer is c1, and the surface of the first metal layer close to the edge of the second via hole is close to the surface of the base substrate and the first The surface distance of the two electrode layers away from the base substrate is d2, and the average carbon-oxygen ratio of the carbon-containing structure layer is c2, then:
  • the carbon-containing structure layer includes a first portion in contact with the auxiliary electrode pattern and a second portion located on the sidewall of the second via hole, the first portion A part of the orthographic projection on the base substrate is located within the orthographic projection of the second via hole on the base substrate.
  • At least part of the edges of the second via holes are zigzag-shaped.
  • the contour of the orthographic projection of the first via hole on the auxiliary electrode pattern includes n inflection points, and the second via hole is on the auxiliary electrode pattern
  • the contour of the orthographic projection includes m inflection points, then: m>n>0.
  • the area of the orthographic projection of the carbon-containing structure layer on the base substrate is S1
  • the average carbon-to-oxygen ratio is Cs1
  • the first via hole does not include
  • the orthographic projection area of the luminescent material layer on the base substrate in the region of the carbon-containing structure layer is S2
  • the average carbon-oxygen ratio is Cs2
  • Carbon-oxygen matching coefficient k S2*Cs2/S1*Cs1, 0 ⁇ k ⁇ 2/3.
  • At least one embodiment of the present disclosure provides a display substrate, including a base substrate, an interlayer insulating layer, a first metal layer, a first insulating layer, a first electrode layer, a luminescent material layer, and a second electrode layer; the first metal layer disposed on the base substrate, including at least one auxiliary electrode pattern, the first insulating layer is disposed on a side of the first metal layer away from the base substrate, and includes an exposed portion of the at least one auxiliary electrode pattern At least one first via hole, the first electrode layer is arranged on a side of the first insulating layer away from the base substrate, and the luminescent material layer is arranged on a side of the first electrode layer away from the base substrate side, wherein the first electrode layer and the luminescent material layer include at least one second via hole that exposes part of the at least one auxiliary electrode pattern and penetrates the at least one first via hole, and the second electrode layer is set On the side of the luminescent material layer away from the base substrate, wherein the second electrode layer is electrically
  • the display substrate provided in at least one embodiment of the present disclosure further includes: a second insulating layer located between the first metal layer and the first insulating layer, wherein the second via hole penetrates through the second insulating layer , the first electrode layer is in contact with the second insulating layer through the first via hole of the first insulating layer.
  • the part of the auxiliary electrode pattern exposed by the second via hole is the first protrusion.
  • the thickness of the first raised portion is d3', and the auxiliary electrode pattern except The thickness of the part outside the first raised portion is d3, then:
  • the display substrate provided in at least one embodiment of the present disclosure further includes: an interlayer insulating layer disposed between the base substrate and the first metal layer, wherein the interlayer insulating layer includes A second protruding portion protruding in the direction of the base substrate, the first protruding portion is disposed on a side of the second protruding portion away from the base substrate.
  • the portion of the interlayer insulating layer in contact with the first raised portion is the second raised portion;
  • the thickness of the second raised part is d4', and the thickness of the part of the interlayer insulating layer other than the second raised part is d4, then:
  • a surface of the interlayer insulating layer close to the base substrate is a flat surface.
  • At least one embodiment of the present disclosure provides a method for preparing a display substrate.
  • the preparation method includes: providing a base substrate, and forming a first metal layer on the base substrate, wherein the first metal layer includes at least one auxiliary An electrode pattern, forming a first insulating layer on a side of the first metal layer away from the base substrate, and forming at least one first insulating layer exposing a portion of the at least one auxiliary electrode pattern in the first insulating layer.
  • via holes forming a first electrode layer on the side of the first insulating layer away from the base substrate, forming a luminescent material layer on the side of the first electrode layer away from the base substrate, and At least one second via hole that exposes part of the at least one auxiliary electrode pattern and penetrates the at least one first via hole is formed in the first electrode layer and the luminescent material layer, and at least one second via hole is formed in the at least one second via hole
  • a carbon-containing structure layer is formed in the hole, and a second electrode layer is formed on the side of the luminescent material layer away from the base substrate, wherein the second electrode layer communicates with the at least one electrode layer through the carbon-containing structure layer.
  • the auxiliary electrode pattern is electrically connected, and the distance between the surface of the first metal layer close to the base substrate near the middle of the second via hole and the surface of the second electrode layer away from the base substrate is d1, so
  • the average carbon-to-oxygen ratio of the carbon-containing structure layer is c1
  • the surface of the first metal layer close to the base substrate near the edge of the second via hole and the surface of the second electrode layer far away from the base substrate The surface distance of is d2, and the average carbon-oxygen ratio of the carbon-containing structure layer is c2, then:
  • FIG. 1A is a circuit diagram of a pixel driving circuit of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 1B is a timing diagram of the pixel driving circuit in FIG. 1A;
  • FIG. 2 is a schematic partial cross-sectional view of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 3 is a schematic cross-sectional view of another part of the display substrate provided by at least one embodiment of the present disclosure
  • FIG. 4 is a schematic plan view of an auxiliary electrode pattern, a first via hole, and a second via hole of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 5 is a schematic cross-sectional view of another part of the display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 6 is a schematic partial cross-sectional view of a display substrate in a display area provided by at least one embodiment of the present disclosure
  • FIG. 7 is an enlarged schematic view of the display substrate in the dotted line frame position and its surroundings in FIG. 6;
  • FIG. 8 is a schematic plan view of a display substrate provided by at least one embodiment of the present disclosure.
  • Fig. 9 is a schematic plan view of a first electrode of a light emitting device of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 10A , FIG. 10B , FIG. 11A and FIG. 11B are schematic cross-sectional views of a display substrate in a manufacturing process provided by at least one embodiment of the present disclosure.
  • FIG. 1A shows a schematic diagram of a 3T1C pixel driving circuit
  • FIG. 1B is a timing diagram of the pixel driving circuit in FIG. 1A.
  • the pixel driving circuit includes structures such as a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor, and the storage capacitor includes a first plate ACT and a second plate SHL and SD, the pixel driving circuit is connected with signal lines such as data line DT, sensing line SN, high-level power supply line VDD and low-level power supply line Vss, and components such as digital-to-analog converter DAC and analog-to-digital converter ADC, and It has the connection relationship as shown in the figure.
  • the first control signal G1 and the second control signal G2 are turn-on signals and are input to the gates of the second transistor T2 and the third transistor T3 , the second transistor T2 and the third transistor T3 are turned on, the data signal dt is transmitted to the gate of the first transistor T1 through the second transistor T2, the first transistor T1 is turned on, and the sensing IC passes through the sensing line SN and the second transistor T2 writes the reset signal Vint to the first electrode (for example, the anode) of the light emitting device.
  • the first control signal G1 and the second control signal G2 are turn-on signals and are input to the gates of the second transistor T2 and the third transistor T3 , the second transistor T2 and the third transistor T3 are turned on, the data signal dt is transmitted to the gate of the first transistor T1 through the second transistor T2, the first transistor T1 is turned on, and the sensing IC passes through the sensing line SN and the second transistor T2 writes the reset signal Vint to the first electrode (for example, the an
  • the first control signal G1 and the second control signal G2 are off signals, the voltage across the storage capacitor remains constant, the first transistor T1 works in a saturated state with a constant current, and drives the light emitting device to emit light.
  • the pixel row where the light emitting device is located needs to be compensated, it enters into the sensing phase S, that is, the period t3-t6.
  • the first control signal G1 and the second control signal G2 are turn-on signals and are input to the gates of the second transistor T2 and the third transistor T3, the second transistor T2 and the third transistor T3 are turned on, and the data signal dt is passed through
  • the second transistor T2 transmits to the gate of the first transistor T1, the third transistor T3 is turned on, and the sensing IC writes the reset signal Vint to the first electrode (such as the anode) of the light emitting device through the sensing line SN and the second transistor T2 .
  • the sensing IC can obtain the potential of S to calculate the Vth of the third transistor, and the characteristic parameters such as the mobility of the third transistor can also be calculated according to the discharge curve at point S in the sensing stage.
  • the first transistor T1 is turned on, and the data line DT writes the data voltage to the gate of the third transistor T3. Due to the sensing phase, the pixel row where the light-emitting device is located does not emit light, which will cause a dark line to appear during display, so After the t4 stage ends, write a data voltage immediately to make the pixels in this row emit light, reducing the influence of dark lines on the display effect.
  • the first transistor T1 and the second transistor T2 are turned off, and the light emitting device emits light.
  • the above periods t5 and t6 are for the timing of increasing the power-on compensation, and these two stages are not needed in the power-off compensation.
  • the inventors of the present disclosure found that when using the above-mentioned pixel drive circuit to drive the light-emitting device to emit light, even if the same data voltage is input, the two ends of the light-emitting device (that is, the anode and the cathode) Different voltage differences cause an IR drop phenomenon, which causes differences in the display colors of different sub-pixels in the display substrate, which affects the uniformity of the display effect of the display panel.
  • the cathodes of the light-emitting devices are usually formed with thinner translucent metal materials, so that the cathodes of the light-emitting devices of different sub-pixels receive
  • the difference in the power supply voltage transmitted by the power line Vss is relatively large, which further aggravates the difference in the display colors of different sub-pixels in the display substrate and affects the uniformity of the display effect of the display panel.
  • the display substrate includes a base substrate, a first metal layer, a first insulating layer, a first electrode layer, a luminescent material layer, a carbon-containing structure layer, and a second Electrode layer; the first metal layer is disposed on the base substrate, including at least one auxiliary electrode pattern, and the first insulating layer is disposed on the side of the first metal layer away from the base substrate, and includes at least one exposed portion of at least one auxiliary electrode pattern A first via hole, the first electrode layer is arranged on the side of the first insulating layer away from the base substrate, the luminescent material layer is arranged on the side of the first electrode layer away from the base substrate, the first electrode layer and the luminescent material The layer includes at least one second via hole exposing part of at least one auxiliary electrode pattern and penetrating at least one first via hole, the carbon-containing structure layer is at least partially disposed in the at least one second via hole, and the second electrode layer is disposed
  • the transmission resistance of the second electrode layer can be reduced, and by setting the carbon-containing structure layer between the second electrode layer and the auxiliary electrode pattern , can reduce the contact resistance between the second electrode layer and the auxiliary electrode pattern, thereby further reducing the transmission resistance of the second electrode layer, by designing the average carbon oxygen of the carbon-containing structure layer at different positions of the second via hole and at different thicknesses of the structure In comparison, the adhesion between the auxiliary electrode pattern and the second electrode layer can be further ensured, the contact resistance between the second electrode layer and the auxiliary electrode pattern can be reduced, and the display uniformity of the display substrate can be improved.
  • the display substrate of the present disclosure and its preparation method will be described below through several specific examples.
  • FIG. 2 shows a partial cross-sectional view of the display substrate.
  • the display substrate includes a base substrate 10, a first metal layer M1, a first insulating layer 11.
  • the first electrode layer E1 the luminescent material layer EL, the carbon-containing structure layer C, and the second electrode layer E2.
  • the first metal layer M1 is disposed on the base substrate 10, including at least one auxiliary electrode pattern AE, for example, including a plurality of auxiliary electrode patterns AE arranged in an array, and one auxiliary electrode pattern AE is shown in FIG. 2 as an example.
  • the first insulating layer 11 is disposed on a side of the first metal layer M1 away from the base substrate 10 , and includes at least one first via hole V1 exposing the above-mentioned at least one auxiliary electrode pattern AE.
  • the first electrode layer E1 is arranged on the side of the first insulating layer 11 away from the base substrate 10, the luminescent material layer EL is arranged on the side of the first electrode layer E1 away from the base substrate 10, the first electrode layer E1 and the luminescent
  • the material layer EL includes at least one second via hole V2 exposing at least one auxiliary electrode pattern AE and passing through the at least one first via hole V1.
  • the carbon-containing structure layer C is disposed in at least one second via hole V2.
  • the carbon-containing structural layer C may be a material including carbon elements, such as activated carbon, graphene, carbon nanotubes, etc., and its square resistance may be between 0.01 ⁇ /sq and 500 ⁇ /sq.
  • the square resistance of the auxiliary electrode pattern AE is smaller than the square resistance of the second electrode layer E2.
  • the thickness of the auxiliary electrode layer AE is greater than the thickness of the second electrode layer E2 .
  • the second electrode layer E2 is disposed on the side of the luminescent material layer EL and the carbon-containing structural layer C away from the base substrate 10, so that the second electrode layer E2 is electrically connected to at least one auxiliary electrode pattern AE through the carbon-containing structural layer C, Thus, the second electrode layer E2 is connected in parallel with the carbon-containing structure layer C, which can reduce the transmission resistance of the second electrode layer E2 and reduce the voltage drop (IRdrop) phenomenon of the second electrode layer E2.
  • the carbon-containing structural layer C may be disposed in the middle of the second via hole V2; or, in other embodiments, as shown in FIG. 3, the carbon-containing structural layer C may also be disposed on the sidewall of the second via hole V2.
  • the carbon-containing structure layer C includes a first portion C1 in contact with the auxiliary electrode pattern AE and a second portion C2 located on the sidewall of the second via hole V2. The setting can increase the contact area between the carbon-containing structure layer C and the second electrode layer E2, so as to further reduce the transmission resistance of the second electrode layer E2.
  • the distance between the surface of the first metal layer M1 close to the base substrate 10 in the middle of the second via hole V2 and the surface of the second electrode layer E2 far away from the base substrate 10 is d1, where
  • the average carbon-oxygen ratio of the carbon-containing structure layer C is c1
  • the distance between the surface of the first metal layer M1 near the edge of the second via hole V2 close to the substrate 10 and the surface of the second electrode layer E2 far away from the substrate is d2
  • the average carbon-oxygen ratio of the carbon-containing structure layer C here is c2
  • the carbon-to-oxygen ratio of a structure refers to the ratio of the amount of carbon to oxygen contained in the material of the structure; the average carbon-to-oxygen ratio of a structure refers to the The average carbon-to-oxygen ratio of the average.
  • the lower the carbon-to-oxygen ratio the better the overlapping effect between the auxiliary electrode pattern AE and the second electrode layer E2 can be ensured, and the part of the carbon-containing structure layer C near the center of the second via hole V2 is closer to the second via hole V2.
  • the conductivity of the edge portion is high, which can effectively increase the conductivity of the second electrode layer E2 and reduce the voltage drop (IRdrop) of the second electrode layer E2.
  • c1*d1>c2*d2 further Ensure the adhesion between the auxiliary electrode pattern AE and the second electrode layer E2, reduce the contact resistance between the auxiliary electrode pattern AE and the second electrode layer E2, and improve the display uniformity of the display substrate, for example, effectively improve the display uniformity of the large-size display substrate .
  • the average carbon-to-oxygen ratio of the carbon-containing structural layer C is greater than 1.3:1 and less than 10:1, such as 2:1, 3:1, 5:1 or 8:1.
  • the carbon-containing structure layer C has higher conductivity, and can effectively reduce the contact resistance between the auxiliary electrode pattern AE and the second electrode layer E2.
  • the average carbon-to-oxygen ratio of the carbon-containing structure layer C near the center of the second via hole V2 may be 7:1, 8:1 or 9:1, etc., and the carbon-containing structure layer C is close to the second via hole V2.
  • the average carbon-to-oxygen ratio of the portion at the edge of the hole V2 can be 3:1, 4:1 or 5:1, etc.
  • the average carbon-oxygen ratio of the carbon-containing structural layer C is greater than 3:1 and less than 11:1; or, the average carbon-oxygen ratio of the carbon-containing structural layer C is greater than 4:1 and less than 12:1; or , the average carbon-oxygen ratio of the carbon-containing structural layer C is greater than 5:1 and less than 13:1; or, the average carbon-oxygen ratio of the carbon-containing structural layer C is greater than 6:1 and less than 15:1; or, the average carbon-oxygen ratio of the carbon-containing structural layer C is The carbon to oxygen ratio is greater than 7:1 and less than 20:1, etc.
  • FIG. 4 shows a schematic plan view of the auxiliary electrode pattern, the first via hole and the second via hole.
  • the orthographic projection of the first via hole V1 on the base substrate 10 is located within the orthographic projection of the auxiliary electrode pattern AE on the base substrate 10, and the orthographic projection of the second via hole V2 on the base substrate 10 Located within the orthographic projection of the first via hole V1 on the base substrate 10 .
  • the orthographic projection of the first portion C1 of the carbon-containing structural layer C on the base substrate 10 is located within the orthographic projection of the second via hole V2 on the base substrate 10 .
  • the area of the orthographic projection of the carbon-containing structure layer C on the base substrate 10 is smaller than the area of the orthographic projection of the auxiliary electrode pattern AE on the base substrate 10 . In this way, it is possible to reduce the adverse effects of particles generated during the manufacturing process of the carbon-containing structure layer on other regions of the display substrate.
  • edges of the second via hole V2 are in a zigzag shape, for example, in FIG. The edge) is zigzag.
  • one or all edges of the second via hole V2 may be zigzag, which is not specifically limited in the embodiments of the present disclosure.
  • At least part of the edge of the second via hole V2 is zigzag, which can increase the contact area between the second part C2 of the carbon-containing structure layer C and the second electrode layer E2, thereby further reducing the thickness of the second electrode layer E2. the transmission resistance.
  • the contour of the orthographic projection of the first via hole V1 on the auxiliary electrode pattern AE includes n inflection points, such as the part circled by the dotted circle in the figure, and the second via hole V2
  • the contour of the orthographic projection on the auxiliary electrode pattern AE includes m inflection points, such as the part circled by the dotted circle in the figure, then: m>n>0. Therefore, the second via hole V2 is more irregular than the first via hole V1 , so the contact area between the second via hole V2 and the second portion C2 of the carbon-containing structure layer C is larger.
  • the area of the orthographic projection of the carbon-containing structure layer C on the base substrate 10 is S1
  • the average carbon-to-oxygen ratio is Cs1
  • the first via hole V1 does not include a carbon-containing structure.
  • the area of the orthographic projection of the luminescent material layer EL on the base substrate 10 in the area of layer C is S2, and the average carbon-oxygen ratio is Cs2, then:
  • Carbon-oxygen matching coefficient k S2*Cs2/S1*Cs1, 0 ⁇ k ⁇ 2/3.
  • the space of the first via hole can be fully used to arrange the carbon-containing structure layer C, so as to reduce the transmission resistance of the second electrode layer E2, reduce the voltage drop of the second electrode layer E2, and improve the display uniformity of the display substrate.
  • FIG. 5 shows a schematic cross-sectional view of another part of the display substrate.
  • the auxiliary electrode pattern AE includes a first protrusion AE1 protruding away from the base substrate 10.
  • the positive orthographic projection of the protrusion AE1 on the base substrate 10 is located within the positive orthographic projection of the second via hole V2 on the base substrate 10 .
  • the portion of the auxiliary electrode pattern AE exposed by the second via hole V2 is the first protrusion AE1.
  • the thickness of the first raised portion AE1 is d3'
  • the auxiliary The thickness of the part of the electrode pattern AE except the first protrusion AE1 is d3, then: d3>d3'.
  • the display substrate may further include an interlayer insulating layer 13, and the interlayer insulating layer 13 is disposed between the base substrate 10 and the first metal layer M1, and the interlayer insulating layer 13 It includes a second protrusion 131 protruding away from the base substrate 10 , and the first protrusion AE1 is disposed on a side of the second protrusion 131 away from the base substrate 10 .
  • the portion of the interlayer insulating layer 13 in contact with the first raised portion AE1 is the second raised portion 131;
  • the thickness of the raised part 131 is d4', and the thickness of the part of the interlayer insulating layer 13 except the second raised part 131 is d4, then: d4 ⁇ d4'.
  • the auxiliary electrode pattern AE tends to have a concave structure, so that the auxiliary electrode pattern AE is likely to break at the second via hole V2,
  • the auxiliary electrode pattern AE By setting the interlayer insulating layer 13 in contact with the auxiliary electrode pattern AE as a raised structure at the second via hole V2, the auxiliary electrode pattern AE also has a raised structure correspondingly, thereby preventing the auxiliary electrode pattern AE from being broken, etc. adverse phenomena, and improve the contact effect between the auxiliary electrode pattern AE and the carbon-containing structure layer C.
  • the thickness d4 of the portion of the inter-insulating layer 13 other than the second protrusion 131 has the following relationship:
  • the overlapping effect between the auxiliary electrode pattern AE, the carbon-containing structure layer C and the second electrode layer E2 is better, so as to be more The transmission resistance of the second electrode layer E2 is greatly reduced.
  • the surface of the interlayer insulating layer 13 close to the base substrate 10 is a flat surface.
  • the auxiliary electrode pattern AE includes a first slope portion P1 at the edge of the second via hole V2, and the interlayer insulating layer 13 includes a second slope portion at the edge of the second via hole V2. P2, the length of the first slope P1 is smaller than the length of the second slope P2.
  • the length of the slope portion of a structure refers to the length of the curve presented in the cross-sectional view of the climbing part when the structure climbs from one plane to another, for example, as shown in Figure 5
  • the length of the first slope P1 is the length of the arc indicated by P1
  • the length of the second slope P2 is the length of the arc indicated by P2.
  • the slope angle a1 of the second slope portion P2 is greater than the slope angle a2 of the first slope portion P1, and at this time, the climbing of the first slope portion P1 is more gradual, so as to improve the relationship between the auxiliary electrode pattern AE and The overlapping effect of the carbon-containing structural layer C.
  • the display substrate may further include a second insulating layer 12, the second insulating layer 12 is located between the first metal layer M1 and the first insulating layer 11, and the second via hole V2 Through the second insulating layer 12 , the first electrode layer E1 is in contact with the second insulating layer 12 through the first via hole V1 of the first insulating layer 11 .
  • the slope angle a1 of the second slope portion P2 is also larger than the slope angle a3 of the first insulating layer 11 at the first via hole V1, and larger than the slope angle a3 of the second insulating layer 12 at the first via hole V1.
  • the slope angle a3 of the first insulating layer 11 at the first via hole V1 and the slope angle a4 of the second insulating layer 12 at the second via hole V2 are relatively gentle, so as to facilitate the formation of the carbon-containing structure layer C at the second via hole V2.
  • the side walls of the two via holes V2 are used to further improve the overlapping effect between the carbon-containing structure layer C and the second electrode layer E2.
  • the display area of the display substrate includes a plurality of light-emitting sub-pixels arranged in an array, and each light-emitting sub-pixel includes a light-emitting device and a pixel driving circuit for driving the light-emitting device.
  • the pixel driving circuit adopts a 3T1C pixel driver as shown in FIG. circuit.
  • FIG. 6 shows a partial cross-sectional schematic diagram of a pixel driving circuit of a light-emitting sub-pixel of the display substrate.
  • the pixel driving circuit includes a transistor T (such as a thin film transistor, implemented as the The third transistor T3) and the storage capacitor in the 3T1C pixel driving circuit, the transistor T includes an active layer AT disposed on the base substrate 10, a gate GT disposed on the side of the active layer AT away from the base substrate 10, and a set On the source layer S and the drain layer D on the side of the gate GT away from the base substrate 10 , the source layer S and the drain layer D are respectively electrically connected to the active layer AT.
  • the storage capacitor includes a first plate and a second plate.
  • the source layer S, the drain layer D, and the second electrode plate are disposed in the first metal layer M1, that is, disposed on the same layer as the auxiliary electrode pattern AE, and the second insulating layer 12 is disposed on the source layer S and the second electrode plate.
  • the side of the drain layer D away from the base substrate 10 can be reused as at least part of the second plate.
  • “set in the same layer” means that two functional layers or structural layers are formed on the same layer and with the same material in the hierarchical structure of the display substrate, that is, in the manufacturing process, the two functional layers or structural layers can be It is formed by the same material layer, and can form the required pattern and structure through the same patterning process.
  • the display substrate may further include a light-shielding metal layer SL disposed between the base substrate 10 and the active layer AT and a gate metal pattern GP disposed on the same layer as the gate GT.
  • the light-shielding metal layer SL can shield the active layer AT from light, so as to prevent the normal operation of the transistor T from being adversely affected by external light.
  • the orthographic projection of the gate metal pattern GP on the base substrate 10 at least partially overlaps the orthographic projection of the light-shielding metal layer SL on the base substrate 10, and overlaps with the source layer S or the drain layer D (shown as At least partially overlap with the orthographic projection of the drain layer D) on the base substrate 10 .
  • the drain layer D and the gate metal pattern GP constitute the first sub-capacitor Cst1
  • the light-shielding metal layer SL and the gate metal pattern GP constitute the second sub-capacitor Cst2 .
  • the gate metal pattern GP forms the first plate ACT of the storage capacitor in the 3T1C pixel driving circuit
  • the light-shielding metal layer SL and the drain layer D form the second plates SHL and SD of the storage capacitor, respectively.
  • the light-emitting device EM included in each light-emitting sub-pixel includes a first electrode E11 located in the first electrode layer E1, a light-emitting layer EL0 located in the light-emitting material layer EL, and a light-emitting layer located in the second electrode layer E2.
  • the first electrode E11 is electrically connected to the source layer S or the drain layer D of the transistor T (shown as being electrically connected to the drain layer in FIG. 6 ).
  • the second electrode E21 of the light-emitting device EM of each light-emitting sub-pixel is integrally connected, for example, the second electrode layer E2 is a whole-surface structure formed on the base substrate 10 .
  • the first electrode E11 may be an anode of the light emitting device EM
  • the second electrode E21 may be a cathode of the light emitting device EM.
  • the first insulating layer 11 also has a third via hole V3 exposing at least part of the second electrode plate (for example, part of the drain layer D).
  • the auxiliary electrode pattern AE The maximum width of is greater than the maximum width of the third via V3.
  • the perimeter of the orthographic projection of the second via hole V2 on the auxiliary electrode pattern AE is larger than the perimeter of the orthographic projection of the third via hole V3 on the second electrode plate.
  • the display substrate may further include a buffer layer 15 disposed between the light-shielding metal layer SL and the active layer AT, and the surface of the auxiliary electrode pattern AE far away from the base substrate 10 is connected to the buffer layer 15.
  • the maximum distance d5 away from the surface of the base substrate 10 is greater than the maximum distance d6 between the surfaces of the source layer S and the drain layer D away from the base substrate 10 and the surface of the buffer layer 15 away from the base substrate 10 .
  • the display substrate may further include a pixel defining layer 14, the pixel defining layer 14 has a sub-pixel opening 141 exposing the first electrode E11 of the light-emitting device EM, and the sub-pixel opening 141 defines the light-emitting device EM (or light-emitting device EM). sub-pixel) light-emitting area.
  • the display substrate may further include an encapsulation layer EN, and the encapsulation layer EN may include a first encapsulation sublayer EN1 , a second encapsulation sublayer EN2 and a third encapsulation sublayer EN3 to form a composite encapsulation layer.
  • the first encapsulation sublayer EN1 and the third encapsulation sublayer EN3 are inorganic encapsulation layers
  • the second encapsulation sublayer EN2 is an organic encapsulation layer to achieve better encapsulation effect.
  • FIG. 7 shows an enlarged schematic view of the display substrate in FIG. 6 in the dotted circle and its surrounding positions.
  • FIG. part of the via hole V2 and the second sub-via hole 121 exposing the source layer S or the drain layer D the situation shown in FIG. 6 , referring to FIG. 5 and FIG.
  • the second insulating layer 12 has a fourth slope P4 at the second sub-via 121, for example, the second sub-via
  • the hole 121 is surrounded by the fourth slope portion P4 , for example, the slope angle of the third slope portion P3 , that is, the slope angle a4 is greater than the slope angle a5 of the fourth slope portion P4 .
  • the fourth slope P4 is made gentler, that is, it is flatter than the third slope P3, which can ensure a better electrical connection effect between the first electrode E11 and the drain layer D.
  • the luminescent material layer EL in the direction perpendicular to the plate surface of the base substrate 10 , that is, in the vertical direction in the figure, the luminescent material layer EL has an overlap with the third slope portion P3
  • the first luminescent material part EL1 of the luminescent material layer EL that is, the part of the luminescent material layer EL close to the second via hole V2
  • the second luminescent material part EL2 overlapping with the fourth slope part P4
  • the thickness of the first luminescent material part EL1 is smaller than that of the second via hole V2.
  • the second light-emitting material portion EL2 at the fourth slope portion P4 is sandwiched between the first electrode E11 and the second electrode E21 for emitting light, by setting the second light-emitting material portion EL2 thicker, the light-emitting device can be ensured.
  • the EM has higher luminance at this position, which improves the lifespan of the light emitting device EM.
  • the display substrate includes rows of light-emitting pixels and rows of transparent pixels arranged alternately, thereby achieving a transparent display effect.
  • the auxiliary electrode patterns AE may be disposed in transparent pixel columns.
  • FIG. 8 shows a schematic plan view of a row of light-emitting pixels and a row of transparent pixels.
  • the luminous pixel column includes a plurality of luminous pixel units, and each luminous pixel unit includes a plurality of luminous sub-pixels.
  • the figure shows four luminous sub-pixels R/G/B/W as an example.
  • the transparent pixel column includes a plurality of transparent pixel units, the plurality of transparent pixel units are defined by the gate line GL and the boundary of the light-emitting pixel column, and each of the plurality of transparent pixel units includes a transparent sub-pixel O.
  • a plurality of transparent pixel units and a plurality of light-emitting pixel units are arranged in a staggered manner along the column direction.
  • the gate line GL has a recessed portion between adjacent luminous pixel columns, so that the plurality of transparent pixel units defined by the gate line GL are arranged in an offset arrangement with the plurality of luminous pixel units along the column direction. In this way, the influence of the diffraction effect of the metal line (eg, the grid line GL) on the display effect can be effectively reduced.
  • a column of transparent pixel units between every two adjacent columns of light-emitting pixel units
  • a plurality of light-emitting sub-pixels are basically arranged in a square shape, and the transparent sub-pixel O is concave toward the direction of the light-emitting sub-pixels, that is, the edges of the transparent sub-pixel O are non-linear and concave toward the direction of the light-emitting sub-pixels. In this way, the light transmittance of the display substrate can be effectively improved, and the transparent display effect of the display substrate can be further improved.
  • each light-emitting pixel unit includes four sub-pixels, namely a red sub-pixel R, a green sub-pixel G, a blue sub-pixel B and a white sub-pixel W.
  • the red sub-pixel E and the blue sub-pixel B are located in the same row
  • the green sub-pixel G and the white sub-pixel W are located in the same row.
  • the area of the light-emitting region of the pixel row with high brightness is smaller than the area of the light-emitting region of the pixel row with low brightness.
  • the brightness satisfies: the brightness of the green sub-pixel G>the brightness of the red sub-pixel R>the brightness of the blue sub-pixel B.
  • the sum of the areas of the light emitting region R1 of the red subpixel R and the light emitting region B1 of the blue subpixel B is greater than the area of the light emitting region G1 of the green subpixel G and the light emitting region W1 of the white subpixel W Sum.
  • the light-emitting areas of the above-mentioned light-emitting sub-pixels are limited by the sub-pixel openings 141 of the pixel defining layer 14.
  • the shape of the light-emitting area can also be a polygon such as pentagon, hexagon, or some irregular figures, etc., and the shapes of the light-emitting areas of each light-emitting sub-pixel can be the same or different.
  • the specific form is not limited.
  • the auxiliary electrode pattern AE is disposed in the row where the red sub-pixel R and the blue sub-pixel B are located.
  • the transmission resistance of the second electrode of the light-emitting sub-pixel in the row can be further reduced, the voltage drop can be reduced, and the display uniformity can be improved.
  • the red sub-pixel R and the white sub-pixel W are located in the same column
  • the green sub-pixel G is located in the same column as the blue sub-pixel B
  • the red sub-pixel R and the white sub-pixel W are located in the same column.
  • the sum of the areas of the light-emitting areas of the green sub-pixel G and the area of the blue sub-pixel B is greater than the sum of the areas of the light-emitting areas of the green sub-pixel G and the blue sub-pixel B.
  • the area of the light emitting region of the blue subpixel B>the area of the light emitting region of the red subpixel R>the area of the light emitting region of the green subpixel G, and the area of the light emitting region of the white subpixel W can be calculated according to A selection needs to be made, for example, the area of the light-emitting region of the white sub-pixel W>the area of the light-emitting region of the blue sub-pixel B.
  • FIG. 9 shows a schematic plan view of a first electrode of a light emitting device.
  • the first electrode E11 of at least part (for example, each) of the light emitting device EM may include a first sub-electrode ES1 and a second sub-electrode ES2, and the first sub-electrode ES1 and the second sub-electrode ES2 pass through the conductive structure ES3.
  • the conductive structure ES3 is electrically connected to the source layer S or the drain layer D through the second sub-via hole 121.
  • the second sub-via hole 121 is located in the first sub-via between the electrode ES1 and the second sub-electrode ES2.
  • the transparent display effect of the display substrate can be further improved by dividing one first electrode E11 into two electrically connected sub-electrodes.
  • the first sub-electrode ES1 at least includes a first side B1, a second side B2, a third side B3, a
  • the four sides B4 and the fifth side B5, at least one of the first side B1, the second side B2, the third side B3, the fourth side B4 and the fifth side B5 is a straight side, and the other part of the side can be a folded line side or a curve while waiting.
  • at least the adjacent first side B1 and the second side B2 are straight sides, and the other part of sides may be folded line sides or curved sides.
  • the lengths of the first side B1, the second side B2, the third side B3, the fourth side B4 and the fifth side B5 are L1, L2, L3, L4 and L5 in sequence, then:
  • the first side B1, the second side B2, the third side B3 and the fifth side B5 are straight sides, and the angle between two adjacent sides is 90 degrees
  • the fourth side B4 is a broken line side, and the included angle of the broken line part is also 90 degrees.
  • the second sub-electrode ES2 at least includes a sixth side B6, a seventh side B7, an eighth side B8, a At least one of the nine sides B9 and the tenth side B10, the sixth side B6, the seventh side B7, the eighth side B8, the ninth side B9 and the tenth side B10 is a straight side, and the other part of the side can be a folded line side or a curve while waiting.
  • at least the adjacent sixth side B6 and seventh side B7 are straight sides, and another part of sides may be folded line sides or curved sides.
  • the lengths of the sixth side B6, the seventh side B7, the eighth side B8, the ninth side B9 and the tenth side B10 are L6, L7, L8, L9 and L10, then:
  • the sixth side B6, the seventh side B7 and the ninth side B9 are straight sides
  • the eighth side B8 and the tenth side B10 are folded line sides
  • the adjacent two sides The included angle between them is 90 degrees
  • the included angle of the part of the folded line on the edge of the folded line is also 90 degrees.
  • the edges of the first sub-electrode ES1 and the second sub-electrode ES2 are more disordered, thereby reducing the influence of the diffraction effect of the metal structure on the display effect of the display substrate.
  • the display substrate may further include other structures, for details, reference may be made to related technologies, which will not be repeated here.
  • the base substrate 10 may include flexible insulating materials such as polyimide (PI) or rigid insulating materials such as glass substrates.
  • the base substrate 10 may be a stacked structure in which a plurality of flexible layers and a plurality of barrier layers are alternately arranged.
  • the flexible layer may include polyimide
  • the barrier layer may include inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.
  • the light-shielding metal layer SL may be made of metal materials such as copper, aluminum or molybdenum or alloy materials thereof.
  • the buffer layer 15 may use inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.
  • the active layer AT can be made of polysilicon and metal oxide (such as IGZO)
  • the gate insulating layer GI can be made of inorganic insulating materials such as silicon oxide, silicon nitride or silicon oxynitride
  • the gate GT can be made of copper, aluminum
  • Metal materials such as titanium and cobalt can be formed into a single-layer structure or a multi-layer structure, such as a multi-layer structure such as titanium/aluminum/titanium, molybdenum/aluminum/molybdenum
  • the first insulating layer 11 and the pixel defining layer 14 can be made of polyamide Organic insulating materials such as imide and resin
  • the second insulating layer 12 and the interlayer insulating layer 13 can use inorganic insulating materials such as silicon oxide, silicon nitride or silicon oxynitride
  • the source layer S and drain layer D and the auxiliary electrode pattern AE can use metal materials such as copper, aluminum, titanium, cobalt
  • the material of the luminescent material layer EL can be an organic luminescent material.
  • the material of the luminescent material layer EL can be selected from a luminescent material that can emit light of a certain color (such as red light, blue light or green light, etc.) according to requirements.
  • the second electrode layer E2 includes, for example, metals such as Mg, Ca, Li or Ag or alloys thereof, or metal oxides such as IZO and ZTO, or PEDOT/PSS (poly 3,4-ethylenedioxythiophene/polystyrenesulfonic acid Salt) and other organic materials with conductive properties.
  • the embodiments of the present disclosure do not specifically limit the material of each functional layer.
  • At least one embodiment of the present disclosure provides a method for preparing a display substrate, the preparation method comprising: providing a base substrate; forming a first metal layer on the base substrate, the first metal layer including at least one auxiliary electrode pattern; A first insulating layer is formed on the side of the metal layer away from the base substrate, and at least one first via hole exposing at least one auxiliary electrode pattern is formed in the first insulating layer; Form a first electrode layer on the side of the first electrode layer; form a light emitting material layer on the side of the first electrode layer away from the base substrate, and form at least one auxiliary electrode pattern exposed in the first electrode layer and the light emitting material layer and at least one first pass At least one second via hole through which the hole penetrates; a carbon-containing structure layer is formed in the at least one second via hole; a second electrode layer is formed on the side of the luminescent material layer away from the base substrate, and the second electrode layer passes through the carbon-containing structure
  • the layer is electrically connected with at least one auxiliary electrode pattern.
  • the distance between the surface of the first metal layer close to the substrate in the middle of the second via hole and the surface of the second electrode layer away from the substrate is d1, and the average carbon-oxygen ratio of the carbon-containing structure layer is c1.
  • the distance between the surface of the first metal layer on the edge of the via hole close to the substrate and the surface of the second electrode layer away from the substrate is d2, and the average carbon-oxygen ratio of the carbon-containing structure layer is c2, then:
  • the average carbon-to-oxygen ratio of the carbon-containing structural layer C is greater than 2:1 and less than 10:1, such as 3:1, 5:1 or 8:1.
  • a light-shielding metal material layer is deposited on the base substrate 10 , and then a patterning process is performed on the light-shielding metal material layer to form a light-shielding metal layer SL.
  • the light-shielding metal material layer may be copper, aluminum, molybdenum or other metal materials or their alloy materials, and the deposition thickness may be 200nm-600nm.
  • a patterning process may include photoresist formation, exposure, development, and etching processes.
  • the buffer layer 15 can be made of silicon oxide, silicon nitride or silicon oxynitride, and the deposition thickness can be 300nm-500nm.
  • an active material layer is deposited, and a patterning process is performed on the active material layer to form an active layer AT.
  • the active material layer can be made of materials such as polysilicon and metal oxide (such as IGZO), and the deposition thickness can be 30nm-50nm.
  • a gate insulating material layer and a gate metal layer are deposited, and the gate insulating material layer and the gate metal layer may be patterned by a self-alignment process to form a gate, a gate metal pattern and a gate insulating layer.
  • the same patterning process is performed on the gate insulating material layer and the gate metal layer to form the gate, the gate metal pattern and the gate insulating layer, so that the formed gate and the gate metal pattern have substantially the same pattern as the gate insulating layer.
  • the gate insulating layer GI may be made of inorganic insulating materials such as silicon oxide, silicon nitride or silicon oxynitride, and the deposition thickness may be 100nm-160nm.
  • the gate metal layer can be made of copper, aluminum, titanium, cobalt and other metal materials or their alloy materials. For example, it can be formed into a single-layer structure or a multi-layer structure, such as a molybdenum/aluminum double-layer structure. At this time, the deposition thickness of molybdenum is 30nm- 60nm, copper deposition thickness is 300nm-500nm.
  • an interlayer insulating material layer is deposited, and a patterning process is performed on the interlayer insulating material layer to form an interlayer insulating layer 13 having a plurality of via holes exposing the active layer AT.
  • the interlayer insulating layer 13 can be made of inorganic insulating materials such as silicon oxide, silicon nitride or silicon oxynitride, and the deposition thickness can be 400nm-600nm.
  • a first metal material layer is deposited, and the first metal material layer is patterned to form a first metal layer M1, the first metal layer M1 includes an auxiliary electrode pattern AE and a source layer S and a drain layer D, etc., the source Layer S and drain layer D are electrically connected to active layer AT through vias in interlayer insulating layer 13 .
  • the first metal material layer can adopt metal materials such as copper, aluminum, titanium, cobalt or alloy materials thereof, for example, can be formed as a single-layer structure or a multi-layer structure, such as forming a MoTi/Cu/MoTi three-layer structure, etc., at this time , the deposition thickness of MoTi alloy can be 30nm-60nm, and the deposition thickness of copper can be 300nm-600nm.
  • This three-layer structure can reduce the influence of the subsequent laser process on the auxiliary electrode pattern AE, which will be introduced later.
  • a second insulating material layer is deposited, and a patterning process is performed on the second insulating material layer to form a second insulating layer 12, and the second insulating layer 12 includes the first exposed auxiliary electrode pattern AE.
  • the second insulating layer 12 can be used as a passivation layer, and its material can be inorganic insulating materials such as silicon oxide, silicon nitride or silicon oxynitride, and the deposition thickness can be 300nm-5000nm.
  • a first insulating material layer is deposited, and a patterning process is performed on the first insulating material layer to form a first insulating layer 11 , and the first insulating layer 11 has a first via hole V1 exposing the auxiliary electrode pattern AE.
  • the first insulating layer 11 can be used as a flat layer, its material can be polyimide, resin and other organic insulating materials, and the deposition thickness can be 1000nm-3000nm.
  • the first electrode material layer is deposited, and the first electrode material layer is patterned to form the first electrode layer E1.
  • the first electrode layer E1 includes the first electrode E11 and other parts outside the first electrode E11. The other parts There are sub-vias exposing the auxiliary electrode patterns AE.
  • the first electrode material layer can be metal oxides such as ITO, IZO or metals such as Ag, Al, Mo or alloys thereof, and the deposition thickness can be 80nm-150nm.
  • a pixel defining material layer is deposited, and a patterning process is performed on the pixel defining material layer to form a pixel defining layer 14 having a plurality of sub-pixel openings exposing the first electrode E11 and sub via holes exposing the auxiliary electrode pattern AE.
  • organic insulating materials such as polyimide and resin may be used for the pixel defining material layer, and the deposition thickness may be 500nm-2000nm.
  • the organic luminescent material layer is evaporated, and the organic luminescent material layer is processed by a laser ablation process to form an organic luminescent layer EL.
  • the organic luminescent layer EL includes sub-via holes exposing the auxiliary electrode pattern AE.
  • the first sub-via hole of the interlayer insulating layer 13, the sub-via hole of the first electrode layer E1, the sub-via hole of the pixel defining layer, and the sub-via hole of the organic light-emitting layer EL penetrate each other to form a hole exposing the auxiliary electrode pattern AE.
  • the organic luminescent material layer can select a luminescent material that can emit light of a certain color (such as red light, blue light, or green light) according to requirements, and the evaporation thickness can be 200nm-500nm.
  • a carbon-containing structural layer C is prepared in the second via hole V2, and the carbon-containing structural layer C has a first portion C1 in contact with the auxiliary electrode pattern AE and a second portion C2 located on the sidewall of the second via hole V2.
  • the carbon-containing structure layer C may be formed to a thickness of 200nm-500nm.
  • the second electrode layer E2 is deposited, for example, the second electrode layer E2 may be deposited on the entire surface of the organic light-emitting layer EL.
  • the second electrode layer E2 can be made of metal materials such as Mg, Ca, Li or Ag or alloy materials thereof, and the deposition thickness is 30nm-150nm.
  • encapsulation layer EN may be deposited.
  • other functional layers such as the encapsulation layer EN may be deposited.

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Abstract

一种显示基板及其制备方法，该显示基板包括衬底基板(10)、第一金属层(M1)、第一绝缘层(11)、第一电极层(E1)、发光材料层(EL)、含碳结构层(C)以及第二电极层(E2)；第一金属层(M1)包括至少一个辅助电极图案(AE)，第一绝缘层(11)包括暴露部分至少一个辅助电极图案(AE)的至少一个第一过孔(V1)，第一电极层(E1)和发光材料层(EL)包括暴露部分至少一个辅助电极图案(AE)且与至少一个第一过孔(V1)贯通的至少一个第二过孔(V2)，含碳结构层(C)至少部分设置在至少一个第二过孔(V2)中，第二电极层(E2)通过含碳结构层(C)与至少一个辅助电极图案(AE)电连接，靠近第二过孔(V2)中部的第一金属层(M1)的靠近衬底基板(10)的表面与第二电极层(E2)的远离衬底基板(10)的表面距离为d1，含碳结构层(C)的平均碳氧比为c1，靠近第二过孔(V2)边缘的第一金属层(M1)的靠近衬底基板(10)的表面与第二电极层(E2)的远离衬底基板(10)的表面距离为d2，含碳结构层(C)的平均碳氧比为c2，则：d1＜d2，c1＞c2。该显示面板具有更好的显示效果。

Description

显示基板及其制备方法
本申请要求于2021年7月9日递交的中国专利申请第202110776580.3号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种显示基板及其制备方法。
背景技术
OLED(Organic Light Emitting Diode，有机发光二极管)显示装置具有自发光、对比度高、清晰度高、视角宽、功耗低、响应速度快、以及制造成本低等一系列优势，已经成为新一代显示装置的重点发展方向之一，因此受到越来越多的关注。
OLED显示装置中作为发光器件的有机发光二极管通常包括阳极、阴极以及位于阳极与阴极之间的有机功能层，例如发光层。当对有机发光二极管的阳极与阴极施加适当电压时，从阳极注入的空穴与从阴极注入的电子会在发光层中结合并激发产生光。
发明内容
本公开至少一实施例提供一种显示基板，该显示基板包括衬底基板、第一金属层、第一绝缘层、第一电极层、发光材料层、含碳结构层以及第二电极层，第一金属层设置在所述衬底基板上，包括至少一个辅助电极图案，第一绝缘层设置在所述第一金属层的远离所述衬底基板的一侧，包括暴露部分所述至少一个辅助电极图案的至少一个第一过孔，第一电极层设置在所述第一绝缘层的远离所述衬底基板的一侧，发光材料层设置在所述第一电极层的远离所述衬底基板的一侧，其中，所述第一电极层和所述发光材料层包括暴露部分所述至少一个辅助电极图案且与所述至少一个第一过孔贯通的至少一个第二过孔，含碳结构层至少部分设置在所述至少一个第二过孔中，第二电极层设置在所述发光材料层和所述含碳结构层的远离所述衬底基板的 一侧，其中，所述第二电极层通过所述含碳结构层与所述至少一个辅助电极图案电连接，靠近所述第二过孔中部的所述第一金属层的靠近所述衬底基板的表面与所述第二电极层的远离所述衬底基板的表面距离为d1，所述含碳结构层的平均碳氧比为c1，靠近所述第二过孔边缘的所述第一金属层的靠近所述衬底基板的表面与所述第二电极层的远离所述衬底基板的表面距离为d2，所述含碳结构层的平均碳氧比为c2，则：
d1＜d2，c1＞c2。
例如，本公开至少一实施例提供的显示基板中，c1*d1>c2*d2。
例如，本公开至少一实施例提供的显示基板中，20*c2*d2>c1*d1>3*c2*d2。
例如，本公开至少一实施例提供的显示基板中，所述含碳结构层的平均平均碳氧比大于1.3:1小于10:1。
例如，本公开至少一实施例提供的显示基板中，所述含碳结构层在所述衬底基板上的正投影的面积小于所述辅助电极图案在所述衬底基板上的正投影的面积。
例如，本公开至少一实施例提供的显示基板中，所述第一过孔在所述衬底基板上的正投影位于所述辅助电极图案在所述衬底基板上的正投影内，所述第二过孔在所述衬底基板上的正投影位于所述第一过孔在所述衬底基板上的正投影内。
例如，本公开至少一实施例提供的显示基板中，所述含碳结构层包括与所述辅助电极图案接触的第一部分以及位于所述第二过孔的侧壁的第二部分，所述第一部分在所述衬底基板上的正投影位于所述第二过孔在所述衬底基板上的正投影内。
例如，本公开至少一实施例提供的显示基板中，所述第二过孔的至少部分边缘呈锯齿形。
例如，本公开至少一实施例提供的显示基板中，所述第一过孔在所述辅助电极图案上的正投影的轮廓包括n个拐点，所述第二过孔在所述辅助电极图案上的正投影的轮廓包括m个拐点，则：m>n>0。
例如，本公开至少一实施例提供的显示基板中，所述含碳结构层在所述衬底基板上的正投影的面积为S1，平均碳氧比为Cs1，所述第一过孔不包括所述含碳结构层的区域的发光材料层在所述衬底基板上的正投影面积为S2， 平均碳氧比为Cs2，则：
碳氧匹配系数k＝S2*Cs2/S1*Cs1,0<k<2/3。
例如，本公开至少一实施例提供的显示基板中，0<k<0.2。
例如，本公开至少一实施例提供的显示基板中，所述辅助电极图案包括向远离所述衬底基板的方向突出的第一凸起部，所述第一凸起部在所述衬底基板上的正投影位于所述第二过孔在所述衬底基板上的正投影内。
例如，本公开至少一实施例提供的显示基板还包括：第二绝缘层，位于所述第一金属层和第一绝缘层之间，其中，所述第二过孔贯穿所述第二绝缘层，所述第一电极层通过所述第一绝缘层的所述第一过孔与所述第二绝缘层接触。
例如，本公开至少一实施例提供的显示基板中，所述辅助电极图案被所述第二过孔暴露的部分为所述第一凸起部。
例如，本公开至少一实施例提供的显示基板中，在垂直于所述衬底基板的板面的方向上，所述第一凸起部的厚度为d3’,所述辅助电极图案的除所述第一凸起部外的部分的厚度为d3，则：d3>d3’。
例如，本公开至少一实施例提供的显示基板还包括：层间绝缘层，设置在所述衬底基板与所述第一金属层之间，其中，所述层间绝缘层包括向远离所述衬底基板的方向突出的第二凸起部，所述第一凸起部设置在所述第二凸起部的远离所述衬底基板的一侧。
例如，本公开至少一实施例提供的显示基板中，所述层间绝缘层与所述第一凸起部接触的部分为所述第二凸起部；在垂直于所述衬底基板的板面的方向上，所述第二凸起部的厚度为d4’,所述层间绝缘层的除所述第二凸起部外的部分的厚度为d4，则：d4<d4’。
例如，本公开至少一实施例提供的显示基板中，
(d3-d3’)/d3>(d4’-d4)/d4；且
(d3+d4-(d3’+d4’))/(d3+d4)<0.02。
例如，本公开至少一实施例提供的显示基板中，所述层间绝缘层的靠近所述衬底基板的表面为平坦表面。
例如，本公开至少一实施例提供的显示基板中，所述辅助电极图案在所述第二过孔的边缘包括第一坡部，所述层间绝缘层在所述第二过孔的边缘包括第二坡部，所述第一坡部的长度小于第二坡部的长度。
例如，本公开至少一实施例提供的显示基板中，所述第二坡部的坡度角大于所述第一坡部的坡度角。
例如，本公开至少一实施例提供的显示基板中，所述第二坡部的坡度角大于所述第一绝缘层在所述第一过孔处的坡度角，且大于所述第二绝缘层在所述第二过孔处的坡度角。
例如，本公开至少一实施例提供的显示基板还包括像素驱动电路，其中，所述像素驱动电路包括晶体管和存储电容，所述晶体管包括设置在所述衬底基板上的有源层、设置在所述有源层远离所述衬底基板一侧的栅极以及设置在所述栅极的远离所述衬底基板一侧的源极层和漏极层，所述源极层和漏极层分别与所述有源层电连接，所述存储电容包括第一极板和第二极板，所述源极层和漏极层、所述第二极板的至少部分设置在所述第一金属层中，所述第二绝缘层设置在所述源极层和漏极层的远离所述衬底基板的一侧。
例如，本公开至少一实施例提供的显示基板中，所述第一绝缘层还具有暴露所述第二极板的至少部分的第三过孔，在平行于所述衬底基板的板面的方向上，所述辅助电极图案的最大宽度大于第三过孔的最大宽度。
例如，本公开至少一实施例提供的显示基板中，所述第二过孔在所述辅助电极图案上的正投影的轮廓的周长大于所述第三过孔在所述第二极板上的正投影的周长。
例如，本公开至少一实施例提供的显示基板还包括设置在所述衬底基板与所述有源层之间的遮光金属层以及与所述栅极同层设置的栅金属图案，其中，所述栅金属图案在所述衬底基板上的正投影与所述遮光金属层在所述衬底基板上的正投影至少部分重叠，且与所述源极层或所述漏极层在所述衬底基板上的正投影至少部分重叠，以构成所述存储电容。
例如，本公开至少一实施例提供的显示基板还包括设置在所述遮光金属层与所述有源层之间的缓冲层，所述辅助电极图案的远离所述衬底基板的表面与所述缓冲层的远离所述衬底基板的表面的最大距离，大于所述源极层和所述漏极层的远离所述衬底基板的表面与所述缓冲层的远离所述衬底基板的表面的最大距离。
例如，本公开至少一实施例提供的显示基板中，所述第二绝缘层具有暴露所述辅助电极图案的第一子过孔和暴露所述源极层或者所述漏极层的第二子过孔，所述第二绝缘层在所述第一子过孔处具有第三坡部，在所述第二 子过孔处具有第四坡部，所述第三坡部的坡度角大于所述第四坡部的坡度角。
例如，本公开至少一实施例提供的显示基板中，在垂直于所述衬底基板的板面的方向上，所述发光材料层具有与第三坡部重叠的第一发光材料部分以及与所述第四坡部重叠的第二发光材料部分，所述第一发光材料部分的厚度小于所述第二发光材料部分的厚度。
例如，本公开至少一实施例提供的显示基板还包括交替排布的发光像素列和透明像素列，所述发光像素列包括多个发光像素单元，所述多个发光像素单元的每个包括多个发光子像素，所述透明像素列包括多个透明像素单元，所述多个透明像素单元由栅线和所述发光像素列的边界限定，所述多个透明像素单元的每个包括一个透明子像素，所述多个透明像素单元和所述多个发光像素单元沿列方向错位排列。
例如，本公开至少一实施例提供的显示基板中，所述多个发光子像素基本呈方形排列，所述透明子像素向所述发光子像素的方向凹入。
例如，本公开至少一实施例提供的显示基板中，所述多个发光像素单元的每个包括四个子像素，所述四个子像素包括一个红色子像素、一个绿色子像素、一个蓝色子像素和一个白色子像素，所述红色子像素与所述蓝色子像素位于同一行，所述绿色子像素与所述白色子像素位于同一行，所述红色子像素与所述蓝色子像素的发光区域的面积之和大于所述绿色子像素与所述白色子像素的发光区域的面积之和。
例如，本公开至少一实施例提供的显示基板中，所述红色子像素与所述白色子像素位于同一列，所述绿色子像素与所述蓝色子像素位于同一列，所述红色子像素与所述白色子像素的发光区域的面积之和大于所述绿色子像素与所述蓝色子像素的发光区域的面积之和。
例如，本公开至少一实施例提供的显示基板中，所述辅助电极图案设置在所述红色子像素与所述蓝色子像素所在的行中。
例如，本公开至少一实施例提供的显示基板中，所述多个发光子像素的每个包括发光器件，所述发光器件包括位于所述第一电极层中的第一电极、位于所述发光材料层中的发光层以及位于所述第二电极层中的第二电极，所述第一电极包括第一子电极和第二子电极，所述第一子电极和所述第二子电极通过导电结构电连接，所述导电结构通过所述第二子过孔与所述源极层或 者所述漏极层电连接，在平行于所述衬底基板的板面的方向上，所,第二子过孔位于所述第一子电极和所述第二子电极之间。
例如，本公开至少一实施例提供的显示基板中，在平行于所述衬底基板的板面的方向上，所述第一子电极至少包括首尾依次相接的第一边、第二边、第三边、第四边和第五边，所述第一边、第二边、第三边、第四边和第五边中的至少一个为直边。
例如，本公开至少一实施例提供的显示基板中，所述第一边、第二边、第三边、第四边和第五边的边长依次为L1、L2、L3、L4和L5，则：
(L3+L4+L5) 2>(L1) 2+(L2) 2。
例如，本公开至少一实施例提供的显示基板中，在平行于所述衬底基板的板面的方向上，所述第二子电极至少包括首尾依次相接的第六边、第七边、第八边、第九边和第十边，所述第六边、第七边、第八边、第九边和第十边中的至少一个为直边。
例如，本公开至少一实施例提供的显示基板中，所述第六边、第七边、第八边、第九边和第十边的边长依次为L6、L7、L8、L9和L10，则：
(L8+L9+L10) 2>(L6) 2+(L7) 2。
本公开至少一实施例提供一种显示基板，该显示基板包括衬底基板、层间绝缘层、第一金属层、第一绝缘层、第一电极层、发光材料层、含碳结构层以及第二电极层，层间绝缘层设置在所述衬底基板上，第一金属层设置在所述层间绝缘层的远离所述衬底基板的一侧，包括至少一个辅助电极图案，第一绝缘层设置在所述第一金属层的远离所述衬底基板的一侧，包括暴露部分所述至少一个辅助电极图案的至少一个第一过孔，第一电极层设置在所述第一绝缘层的远离所述衬底基板的一侧，发光材料层设置在所述第一电极层的远离所述衬底基板的一侧，其中，所述第一电极层和所述发光材料层包括暴露部分所述至少一个辅助电极图案且与所述至少一个第一过孔贯通的至少一个第二过孔，含碳结构层至少部分设置在所述至少一个第二过孔中，第二电极层设置在所述发光材料层和所述含碳结构层的远离所述衬底基板的一侧，在垂直于所述衬底基板的板面的方向上，所述辅助电极层的厚度大于所述第二电极层的厚度；其中，所述第二电极层通过所述含碳结构层与所述至少一个辅助电极图案电连接，所述辅助电极图案在所述第二过孔的边缘包括第一坡部，所述层间绝缘层在所述第二过孔的边缘包括第二坡部，所述第 一坡部的长度小于第二坡部的长度。
例如，本公开至少一实施例提供的显示基板中，所述第二坡部的坡度角大于所述第一坡部的坡度角，大于所述第一绝缘层在所述第一过孔处的坡度角，且大于所述第二绝缘层在所述第二过孔处的坡度角。
例如，本公开至少一实施例提供的显示基板中，靠近所述第二过孔中部的所述第一金属层的靠近所述衬底基板的表面与所述第二电极层的远离所述衬底基板的表面距离为d1，所述含碳结构层的平均碳氧比为c1，靠近所述第二过孔边缘的所述第一金属层的靠近所述衬底基板的表面与所述第二电极层的远离所述衬底基板的表面距离为d2，所述含碳结构层的平均碳氧比为c2，则：
c1*d1>c2*d2。
例如，本公开至少一实施例提供的显示基板中，所述含碳结构层包括与所述辅助电极图案接触的第一部分以及位于所述第二过孔的侧壁的第二部分，所述第一部分在所述衬底基板上的正投影位于所述第二过孔在所述衬底基板上的正投影内。
例如，本公开至少一实施例提供的显示基板中，所述第二过孔的至少部分边缘呈锯齿形。
例如，本公开至少一实施例提供的显示基板中，所述第一过孔在所述辅助电极图案上的正投影的轮廓包括n个拐点，所述第二过孔在所述辅助电极图案上的正投影的轮廓包括m个拐点，则：m>n>0。
例如，本公开至少一实施例提供的显示基板中，所述含碳结构层在所述衬底基板上的正投影的面积为S1，平均碳氧比为Cs1，所述第一过孔不包括所述含碳结构层的区域的发光材料层在所述衬底基板上的正投影面积为S2，平均碳氧比为Cs2，则：
碳氧匹配系数k＝S2*Cs2/S1*Cs1,0<k<2/3。
本公开至少一实施例提供一种显示基板，包括衬底基板、层间绝缘层、第一金属层、第一绝缘层、第一电极层、发光材料层以及第二电极层；第一金属层设置在所述衬底基板上，包括至少一个辅助电极图案，第一绝缘层设置在所述第一金属层的远离所述衬底基板的一侧，包括暴露部分所述至少一个辅助电极图案的至少一个第一过孔，第一电极层设置在所述第一绝缘层的远离所述衬底基板的一侧，发光材料层设置在所述第一电极层的远离所述衬 底基板的一侧，其中，所述第一电极层和所述发光材料层包括暴露部分所述至少一个辅助电极图案且与所述至少一个第一过孔贯通的至少一个第二过孔，第二电极层设置在所述发光材料层的远离所述衬底基板的一侧，其中，所述第二电极层通过所述至少一个第二过孔与所述至少一个辅助电极图案电连接，所述辅助电极图案包括向远离所述衬底基板的方向突出的第一凸起部，所述第一凸起部在所述衬底基板上的正投影位于所述第二过孔在所述衬底基板上的正投影内。
例如，本公开至少一实施例提供的显示基板还包括：第二绝缘层，位于所述第一金属层和第一绝缘层之间，其中，所述第二过孔贯穿所述第二绝缘层，所述第一电极层通过所述第一绝缘层的所述第一过孔与所述第二绝缘层接触。
例如，本公开至少一实施例提供的显示基板中，所述辅助电极图案被所述第二过孔暴露的部分为所述第一凸起部。
例如，本公开至少一实施例提供的显示基板中，在垂直于所述衬底基板的板面的方向上，所述第一凸起部的厚度为d3’,所述辅助电极图案的除所述第一凸起部外的部分的厚度为d3，则：
d3>d3’。
例如，本公开至少一实施例提供的显示基板还包括：层间绝缘层，设置在所述衬底基板与所述第一金属层之间，其中，所述层间绝缘层包括向远离所述衬底基板的方向突出的第二凸起部，所述第一凸起部设置在所述第二凸起部的远离所述衬底基板的一侧。
例如，本公开至少一实施例提供的显示基板中，所述层间绝缘层与所述第一凸起部接触的部分为所述第二凸起部；在垂直于所述衬底基板的板面的方向上，所述第二凸起部的厚度为d4’,所述层间绝缘层的除所述第二凸起部外的部分的厚度为d4，则：
d4<d4’。
例如，本公开至少一实施例提供的显示基板中，
(d3-d3’)/d3>(d4’-d4)/d4；且
(d3+d4-(d3’+d4’))/(d3+d4)<0.02。
例如，本公开至少一实施例提供的显示基板中，所述层间绝缘层的靠近所述衬底基板的表面为平坦表面。
本公开至少一实施例提供一种显示基板的制备方法，该制备方法包括：提供衬底基板，在所述衬底基板上形成第一金属层，其中，所述第一金属层包括至少一个辅助电极图案，在所述第一金属层的远离所述衬底基板的一侧形成第一绝缘层，并在所述第一绝缘层中形成暴露部分所述至少一个辅助电极图案的至少一个第一过孔，在所述第一绝缘层的远离所述衬底基板的一侧形成第一电极层，在所述第一电极层的远离所述衬底基板的一侧形成发光材料层，并在所述第一电极层和所述发光材料层中形成暴露部分所述至少一个辅助电极图案且与所述至少一个第一过孔贯通的至少一个第二过孔，在所述至少一个第二过孔中形成含碳结构层，在所述发光材料层的远离所述衬底基板的一侧形成第二电极层，其中，所述第二电极层通过所述含碳结构层与所述至少一个辅助电极图案电连接，靠近所述第二过孔中部的所述第一金属层的靠近所述衬底基板的表面与所述第二电极层的远离所述衬基板的表面距离为d1，所述含碳结构层的平均碳氧比为c1，靠近所述第二过孔边缘的所述第一金属层的靠近所述衬底基板的表面与所述第二电极层的远离所述衬基板的表面距离为d2，所述含碳结构层的平均碳氧比为c2，则：
d1＜d2，c1＞c2。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为本公开至少一实施例提供的显示基板的像素驱动电路的电路图；
图1B为图1A中的像素驱动电路的时序图；
图2为本公开至少一实施例提供的显示基板的部分截面示意图；
图3为本公开至少一实施例提供的显示基板的另一部分截面示意图；
图4为本公开至少一实施例提供的显示基板的辅助电极图案、第一过孔以及第二过孔的平面示意图；
图5为本公开至少一实施例提供的显示基板的再一部分截面示意图；
图6为本公开至少一实施例提供的显示基板在显示区的部分截面示意图；
图7为图6中的显示基板在虚线框位置及其周边的放大示意图；
图8为本公开至少一实施例提供的显示基板的平面示意图；
图9为本公开至少一实施例提供的显示基板的发光器件的第一电极的平面示意图；以及
图10A、图10B、图11A和图11B为本公开至少一实施例提供的显示基板在制备过程中的截面示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
对于大尺寸OLED显示装置，例如可以采用3T1C像素驱动电路来驱动发光器件进行发光，图1A示出了一种3T1C像素驱动电路的示意图，图1B为图1A中的像素驱动电路的时序图。
例如，如图1A和图1B所示，该像素驱动电路包括第一晶体管T1、第二晶体管T2、第三晶体管T3以及存储电容等结构，存储电容包括第一极板ACT以及第二极板SHL和SD，该像素驱动电路连接有数据线DT、感测线SN、高电平电源线VDD和低电平电源线Vss等信号线以及数模转换器DAC以及模数转换器ADC等元件，并具有如图所示的连接关系。
在上述3T1C像素驱动电路的工作过程中，结合图1图2，在t1时段， 第一控制信号G1和第二控制信号G2为开启信号并输入至第二晶体管T2和第三晶体管T3的栅极，第二晶体管T2和第三晶体管T3导通，数据信号dt经第二晶体管T2传输至第一晶体管T1的栅极，第一晶体管T1导通，感测IC通过感测线SN及第二晶体管T2向发光器件的第一电极(例如阳极)写入复位信号Vint。
在t2时段，第一控制信号G1和第二控制信号G2为关闭信号，存储电容两端的电压保持不变，第一晶体管T1工作在饱和状态且电流不变，并驱动发光器件发光。
此时，如果该发光器件所在的像素行需要补偿时，则进入感测阶段S，即t3-t6时段。
在t3时段，第一控制信号G1和第二控制信号G2为开启信号并输入至第二晶体管T2和第三晶体管T3的栅极，第二晶体管T2和第三晶体管T3导通，数据信号dt经第二晶体管T2传输至第一晶体管T1的栅极，第三晶体管T3导通，感测IC通过感测线SN及第二晶体管T2向发光器件的第一电极(例如阳极)写入复位信号Vint。
在t4时段，第一晶体管T1关闭，第二晶体管T2和第三晶体管T3打开，通过S点向感测线SN的寄生电容放电，直到第三晶体管T3的Vgs＝Vth，第三晶体管T3关闭，此时感测IC获取到S的电位即可计算出第三晶体管的Vth，根据感测阶段S点的放电曲线还可以计算出第三晶体管的迁移率等特性参数。
在t5时段，第一晶体管T1打开，数据线DT向第三晶体管T3的栅极写入数据电压，由于感测阶段，该发光器件所在的像素行不发光，会导致显示时出现一条暗线，因此t4阶段结束后，立即写入一个数据电压，让该行像素发光，降低暗线对显示效果的影响。
在t6时段，第一晶体管T1和第二晶体管T2关闭，发光器件发光。
上述t5和t6时段是针对开机补偿增加的时序，关机补偿中不需要这两个阶段。
本公开的发明人发现，在利用上述像素驱动电路驱动发光器件发光时，即使输入同样的数据电压，在距离电源线Vss较近和较远的位置，发光器件两端(即阳极和阴极)的电压差不同，即产生压降(IRdrop)现象，因此使得显示基板中不同子像素的显示颜色存在差异，影响了显示面板显示效果的 均一性。
例如，对于顶发射型显示基板来说，其发光器件的阴极通常采用较薄的半透明金属材料形成，使得在距离电源线Vss较远和较近的位置，不同子像素的发光器件的阴极接收到的电源线Vss传输的电源电压的差异较大，进而加重了显示基板中不同子像素的显示颜色存在的差异，影响显示面板显示效果的均一性。
本公开至少一实施例提供一种显示基板及其制备方法，该显示基板包括衬底基板、第一金属层、第一绝缘层、第一电极层、发光材料层、含碳结构层以及第二电极层；第一金属层设置在衬底基板上，包括至少一个辅助电极图案，第一绝缘层设置在第一金属层的远离衬底基板的一侧，包括暴露部分至少一个辅助电极图案的至少一个第一过孔，第一电极层设置在第一绝缘层的远离衬底基板的一侧，发光材料层设置在第一电极层的远离衬底基板的一侧，第一电极层和发光材料层包括暴露部分至少一个辅助电极图案且与至少一个第一过孔贯通的至少一个第二过孔，含碳结构层至少部分设置在至少一个第二过孔中，第二电极层设置在发光材料层和含碳结构层的远离衬底基板的一侧，第二电极层通过含碳结构层与至少一个辅助电极图案电连接，靠近第二过孔中部的第一金属层的靠近衬底基板的表面与第二电极层的远离衬底基板的表面距离为d1，含碳结构层的平均碳氧比为c1，靠近第二过孔边缘的第一金属层的靠近衬底基板的表面与第二电极层的远离衬底基板的表面距离为d2，含碳结构层的平均碳氧比为c2，则：d1＜d2，c1＞c2。
本公开实施例提供的显示基板中，通过设置与第二电极层并联的辅助电极图案，可以降低第二电极层的传输电阻，通过设置第二电极层与辅助电极图案之间的含碳结构层，可以降低第二电极层与辅助电极图案的接触电阻，从而进一步降低第二电极层的传输电阻，通过设计在第二过孔不同位置处以及结构的不同厚度处含碳结构层的平均碳氧比，可以进一步保证辅助电极图案与第二电极层的粘附性，降低第二电极层与辅助电极图案的接触电阻，提高显示基板的显示均一性。
下面通过几个具体的实施例对本公开的显示基板及其制备方法进行说明。
本公开至少一实施例提供一种显示基板，图2示出了该显示基板的部分截面示意图，如图2所示，该显示基板包括衬底基板10、第一金属层M1、 第一绝缘层11、第一电极层E1、发光材料层EL、含碳结构层C以及第二电极层E2。
如图2所示，第一金属层M1设置在衬底基板10上，包括至少一个辅助电极图案AE，例如包括阵列排布的多个辅助电极图案AE，图2中示出一个辅助电极图案AE作为示例。第一绝缘层11设置在第一金属层M1的远离衬底基板10的一侧，包括暴露上述至少一个辅助电极图案AE的至少一个第一过孔V1。第一电极层E1设置在第一绝缘层11的远离衬底基板10的一侧，发光材料层EL设置在第一电极层E1的远离衬底基板10的一侧，第一电极层E1和发光材料层EL包括暴露至少一个辅助电极图案AE且与至少一个第一过孔V1贯通的至少一个第二过孔V2。
例如，含碳结构层C设置在至少一个第二过孔V2中。含碳结构层C可以为包括碳元素的材料，例如活性炭，石墨烯，碳纳米管等，其方阻可以在0.01Ω/sq到500Ω/sq之间。例如，辅助电极图案AE的方阻小于第二电极层E2的方阻。例如，在垂直于衬底基板10的板面的方向上，辅助电极层AE的厚度大于第二电极层E2的厚度。第二电极层E2设置在发光材料层EL和含碳结构层C的远离衬底基板10的一侧，以使得第二电极层E2通过含碳结构层C与至少一个辅助电极图案AE电连接，由此第二电极层E2与含碳结构层C并联，可以降低第二电极层E2的传输电阻，降低第二电极层E2的压降(IRdrop)现象。
例如，在一些实施例中，如图2所示，含碳结构层C可以设置在第二过孔V2的中间位置；或者，在另一些实施例中，如图3所示，含碳结构层C还可以设置在第二过孔V2的侧壁，此时，含碳结构层C包括与辅助电极图案AE接触的第一部分C1以及位于第二过孔V2的侧壁的第二部分C2，该设置可以增大含碳结构层C与第二电极层E2的接触面积，以进一步降低第二电极层E2的传输电阻。
例如，如图3所示，靠近第二过孔V2中部的第一金属层M1的靠近衬底基板10的表面与第二电极层E2的远离衬底基板10的表面距离为d1，此处的含碳结构层C的平均碳氧比为c1，靠近第二过孔V2边缘的第一金属层M1的靠近衬底基板10的表面与第二电极层E2的远离衬底基板的表面距离为d2，此处的含碳结构层C的平均碳氧比为c2，则：
d1＜d2，c1＞c2。
本公开的实施例中，一个结构的碳氧比指的是该结构的材料中所含的碳元素与氧元素的量的比值；一个结构的平均碳氧比指的是该结构在各个位置处的平均碳氧比的平均值。
例如，在一些实施例中，第一金属层M1的靠近衬底基板10的表面与第二电极层E2的远离衬底基板10的表面的距离越大，该处的含碳结构层C的平均碳氧比越低，由此可以保证辅助电极图案AE与第二电极层E2有较好的搭接效果，并且含碳结构层C靠近第二过孔V2中心的部分比靠近第二过孔V2边缘的部分的导电率高，可有效提高第二电极层E2的导电性，降低第二电极层E2的压降(IRdrop)。
例如，在一些实施例中，c1*d1>c2*d2。由于第一过孔V1的边缘存在较大的段差，此处存在膜层断裂的风险，因此需要对碳结构层C的碳氧比进行精细调控，通过使c1*d1>c2*d2，可以进一步保证辅助电极图案AE与第二电极层E2的粘附性，降低辅助电极图案AE与第二电极层E2的接触电阻，提高显示基板的显示均一性，例如有效提高大尺寸显示基板的显示均一性。
例如，在一些实施例中，20*c2*d2>c1*d1>3*c2*d2。例如，在一些示例中，10*c2*d2>c1*d1>5*c2*d2,在一些示例中，5*c2*d2>c1*d1>2*c2*d2。上述参数设计有助于进一步提高大尺寸显示基板的显示均一性。
例如，在一些实施例中，含碳结构层C的平均碳氧比大于1.3:1小于10:1，例如为2:1、3:1、5:1或者8:1等。此时，含碳结构层C具有较高的导电性，并可有效降低辅助电极图案AE与第二电极层E2的接触电阻。例如，在一些示例中，含碳结构层C靠近第二过孔V2中心的部分的平均碳氧比可以为7:1、8:1或者9:1等，含碳结构层C靠近第二过孔V2边缘的部分的平均碳氧比可以为3:1、4:1或者5:1等。
例如，在另一些实施例中，含碳结构层C的平均碳氧比大于3:1小于11:1；或者，含碳结构层C的平均碳氧比大于4:1小于12:1；或者，含碳结构层C的平均碳氧比大于5:1小于13:1；或者，含碳结构层C的平均碳氧比大于6:1小于15:1；或者，含碳结构层C的平均碳氧比大于7:1小于20:1等。这些参数设计均有助于降低辅助电极图案AE与第二电极层E2的接触电阻。
例如，图4示出了辅助电极图案、第一过孔与第二过孔的平面示意图。如图4所示，第一过孔V1在衬底基板10上的正投影位于辅助电极图案AE在衬底基板10上的正投影内，第二过孔V2在衬底基板10上的正投影位于 第一过孔V1在衬底基板10上的正投影内。例如，含碳结构层C的第一部分C1在衬底基板10上的正投影位于第二过孔V2在衬底基板10上的正投影内。
例如，如图4所示，含碳结构层C在衬底基板10上的正投影的面积小于辅助电极图案AE在衬底基板10上的正投影的面积。由此可减少含碳结构层在制作过程中产生的颗粒物对显示基板的其他区域产生不良影响。
例如，在一些实施例中，如图4所示，第二过孔V2的至少部分边缘呈锯齿形，例如在图4中示出为第二过孔V2的相对两个边缘(图中的左右边缘)呈锯齿形，在其他实施例中，也可以是第二过孔V2的一个边缘或者全部边缘呈锯齿形，本公开的实施例对此不做具体限定。
本公开的实施例中，第二过孔V2的至少部分边缘呈锯齿形可以增大含碳结构层C的第二部分C2与第二电极层E2的接触面积，从而进一步降低第二电极层E2的传输电阻。
例如，在一些实施例中，如图4所示，第一过孔V1在辅助电极图案AE上的正投影的轮廓包括n个拐点，例如图中虚线圈圈出的部分，第二过孔V2在辅助电极图案AE上的正投影的轮廓包括m个拐点，例如图中虚线圈圈出的部分，则：m>n>0。由此，第二过孔V2相对于第一过孔V1来说更不规则，因此第二过孔V2与含碳结构层C的第二部分C2的接触面积更大。
例如，在一些实施例中，如图4所示，含碳结构层C在衬底基板10上的正投影的面积为S1，平均碳氧比为Cs1，第一过孔V1不包括含碳结构层C的区域的发光材料层EL在衬底基板10上的正投影面积为S2，平均碳氧比为Cs2，则：
碳氧匹配系数k＝S2*Cs2/S1*Cs1,0<k<2/3。
例如，在一些示例中，0<k<0.2。例如，在一些示例中，k可以为0.05、0.1、0.2、0.3、0.4或者0.5等。由此，可以充分利用第一过孔的空间来设置含碳结构层C，以降低第二电极层E2的传输电阻，降低第二电极层E2的压降，提高显示基板的显示均一性。
例如，图5示出了显示基板的另一部分截面示意图，如图5所示，在一些实施例中，辅助电极图案AE包括向远离衬底基板10的方向突出的第一凸起部AE1，第一凸起部AE1在衬底基板10正的正投影位于第二过孔V2在衬底基板10正的正投影内。例如，在一些实施例中，辅助电极图案AE 被第二过孔V2暴露的部分为第一凸起部AE1。
例如，在一些实施例中，如图5所示，在垂直于衬底基板10的板面的方向上，即图中的竖直方向上，第一凸起部AE1的厚度为d3’,辅助电极图案AE的除第一凸起部AE1外的部分的厚度为d3，则：d3>d3’。
例如，在一些实施例中，如图5所示，显示基板还可以包括层间绝缘层13，层间绝缘层13设置在衬底基板10与第一金属层M1之间，层间绝缘层13包括向远离衬底基板10的方向突出的第二凸起部131，第一凸起部AE1设置在第二凸起部131的远离衬底基板10的一侧。
例如，层间绝缘层13与第一凸起部AE1接触的部分为第二凸起部131；在垂直于衬底基板10的板面的方向上，即图中的竖直方向上，第二凸起部131的厚度为d4’,层间绝缘层13的除第二凸起部131外的部分的厚度为d4，则：d4<d4’。
由于在显示基板的制备过程中，在形成暴露辅助电极图案AE的第二过孔V2时，辅助电极图案AE容易出现下凹结构，使得辅助电极图案AE容易在第二过孔V2处发生断裂，通过将与辅助电极图案AE接触的层间绝缘层13在第二过孔处V2设置为凸起结构，辅助电极图案AE也相应地具有凸起结构，由此可避免辅助电极图案AE发生断裂等不良现象，并提高辅助电极图案AE与含碳结构层C的接触效果。
例如，在一些实施例中，第一凸起部AE1的厚度d3’、辅助电极图案AE的除第一凸起部AE1外的部分的厚度d3、第二凸起部131的厚度d4’以及层间绝缘层13的除第二凸起部131外的部分的厚度d4存在如下关系：
(d3-d3’)/d3>(d4’-d4)/d4；且
(d3+d4-(d3’+d4’))/(d3+d4)<0.02。
当辅助电极图案AE和层间绝缘层13的凸起部的设置满足以上关系时，辅助电极图案AE、含碳结构层C以及第二电极层E2之间的搭接效果更佳，以在更大程度上降低第二电极层E2的传输电阻。
例如，在一些实施例中，如图5所示，层间绝缘层13的靠近衬底基板10的表面为平坦表面。
例如，在一些实施例中，如图5所示，辅助电极图案AE在第二过孔V2的边缘包括第一坡部P1，层间绝缘层13在第二过孔V2的边缘包括第二坡部P2，第一坡部P1的长度小于第二坡部P2的长度。
本公开的实施例中，一个结构的坡部的长度指的是该结构从一个平面爬坡到另一个平面时，爬坡部分在截面图中呈现的曲线的长度，例如在图5所示的截面图中，第一坡部P1的长度为P1所指的弧线的长度，第二坡部P2的长度为P2所指的弧线的长度。
例如，在一些实施例中，第二坡部P2的坡度角a1大于第一坡部P1的坡度角a2，此时，第一坡部P1的爬坡更缓，以利于提高辅助电极图案AE与含碳结构层C的搭接效果。
例如，在一些实施例中，如图5所示，显示基板还可以包括第二绝缘层12，第二绝缘层12位于第一金属层M1和第一绝缘层11之间，第二过孔V2贯穿第二绝缘层12，第一电极层E1通过第一绝缘层11的第一过孔V1与第二绝缘层12接触。
例如，在一些实施例中，如图5所示，第二坡部P2的坡度角a1还大于第一绝缘层11在第一过孔V1处的坡度角a3，且大于第二绝缘层12在第二过孔V2处的坡度角a4。此时，第一绝缘层11在第一过孔V1处的坡度角a3和第二绝缘层12在第二过孔V2处的坡度角a4均较缓，以利于含碳结构层C形成在第二过孔V2的侧壁，并进一步提高含碳结构层C与第二电极层E2之间的搭接效果。
例如，显示基板的显示区包括阵列排布的多个发光子像素，每个发光子像素包括发光器件以及驱动发光器件的像素驱动电路，该像素驱动电路例如采用如图1A所示的3T1C像素驱动电路。
例如，图6示出了该显示基板的一个发光子像素的像素驱动电路的部分截面示意图，如图6所示，该像素驱动电路包括晶体管T(例如为薄膜晶体管，实现为图1A所示的3T1C像素驱动电路中的第三晶体管T3)和存储电容，晶体管T包括设置在衬底基板10上的有源层AT、设置在有源层AT远离衬底基板10一侧的栅极GT以及设置在栅极GT的远离衬底基板10一侧的源极层S和漏极层D，源极层S和漏极层D分别与有源层AT电连接。存储电容包括第一极板和第二极板。例如，源极层S和漏极层D、第二极板的至少部分设置在第一金属层M1中，即与辅助电极图案AE同层设置，第二绝缘层12设置在源极层S和漏极层D的远离衬底基板10的一侧。例如，在图6所示的示例中，漏极层D可以复用为第二极板的至少部分。
在本公开的实施例中，“同层设置”为两个功能层或结构层在显示基板的 层级结构中同层且同材料形成，即在制备工艺中，该两个功能层或结构层可以由同一个材料层形成，且可以通过同一构图工艺形成所需要的图案和结构。
例如，在一些实施例中，如图6所示，显示基板还可以包括设置在衬底基板10与有源层AT之间的遮光金属层SL以及与栅极GT同层设置的栅金属图案GP，遮光金属层SL可以为有源层AT遮光，避免外界光对晶体管T的正常工作造成不良影响。例如，栅金属图案GP在衬底基板10上的正投影与遮光金属层SL在衬底基板10上的正投影至少部分重叠，且与源极层S或漏极层D(图中示出为与漏极层D)在衬底基板10上的正投影至少部分重叠。由此，漏极层D与栅金属图案GP构成第一子电容Cst1，遮光金属层SL与栅金属图案GP构成第二子电容Cst2。结合图1A，栅金属图案GP构成3T1C像素驱动电路中存储电容的第一极板ACT，遮光金属层SL和漏极层D分别构成存储电容的第二极板SHL和SD。
例如，如图6所示，每个发光子像素包括的发光器件EM包括位于第一电极层E1中的第一电极E11、位于发光材料层EL中的发光层EL0以及位于第二电极层E2中的第二电极E21。第一电极E11与晶体管T的源极层S或者漏极层D(图6中示为与漏极层电连接)电连接。例如，在一些实施例中，每个发光子像素的发光器件EM的第二电极E21为一体连接的结构，例如，第二电极层E2为在衬底基板10上形成的整面结构。例如，第一电极E11可以为发光器件EM的阳极，第二电极E21可以为发光器件EM的阴极。
例如，第一绝缘层11还具有暴露第二极板的至少部分(例如漏极层D部分)的第三过孔V3，在平行于衬底基板10的板面的方向上，辅助电极图案AE的最大宽度大于第三过孔V3的最大宽度。例如，第二过孔V2在辅助电极图案AE上的正投影的轮廓的周长大于第三过孔V3在第二极板上的正投影的周长。
例如，如图4和6所示，显示基板还可以包括设置在遮光金属层SL与有源层AT之间的缓冲层15，辅助电极图案AE的远离衬底基板10的表面与缓冲层15的远离衬底基板10的表面的最大距离d5，大于源极层S和漏极层D的远离衬底基板10的表面与缓冲层15的远离衬底基板10的表面的最大距离d6。
例如，如图6所示，显示基板还可以包括像素界定层14，像素界定层 14具有暴露发光器件EM的第一电极E11的子像素开口141，子像素开口141限定了发光器件EM(或者发光子像素)的发光区域。例如，显示基板还可以包括封装层EN，封装层EN可以包括第一封装子层EN1、第二封装子层EN2以及第三封装子层EN3，以构成复合封装层。例如，第一封装子层EN1和第三封装子层EN3为无机封装层，第二封装子层EN2为有机封装层，以实现更好的封装效果。
例如，图7示出了图6中的显示基板在虚线圈及其周边位置的放大示意图，如图7所示，第二绝缘层12具有暴露辅助电极图案的第一子过孔(即第二过孔V2的一部分)和暴露源极层S或者漏极层D(图6中示出的情况)的第二子过孔121，结合图5和图7，第二绝缘层12在第一子过孔处具有第三坡部P3，例如第一子过孔由第三坡部P3围绕形成，第二绝缘层12在第二子过孔121处具有第四坡部P4，例如第二子过孔121由第四坡部P4围绕形成，例如，第三坡部P3的坡度角，即坡度角a4大于第四坡部P4的坡度角a5。
本公开的实施例中，由于第一电极E11通过第四坡部P4形成的第二子过孔121与晶体管T的漏极层D电连接，由于在该第二子过孔121处，没有设置含碳结构层C，通过将第四坡部P4做得较缓，即比第三坡部P3更为平坦，可以保证第一电极E11与漏极层D有更好的电连接效果。
例如，在一些实施例中，结合图5和图7，在垂直于衬底基板10的板面的方向上，即图中的竖直方向上，发光材料层EL具有与第三坡部P3重叠的第一发光材料部分EL1(即发光材料层EL的靠近第二过孔V2的部分)以及与第四坡部P4重叠的第二发光材料部分EL2，第一发光材料部分EL1的厚度小于第二发光材料部分EL2的厚度。由于第四坡部P4处的第二发光材料部分EL2夹置在第一电极E11与第二电极E21之间，用于发光，通过将第二发光材料部分EL2设置的较厚，可以保证发光器件EM在该位置有更高的发光亮度，提高发光器件EM的寿命。
例如，在一些实施例中，显示基板包括交替排布的发光像素列和透明像素列，由此可以实现透明显示效果。例如，辅助电极图案AE可以设置在透明像素列中。例如，图8示出了发光像素列和透明像素列的平面示意图。如图8所示，发光像素列包括多个发光像素单元，每个发光像素单元包括多个发光子像素，图中示出四个发光子像素R/G/B/W作为示例。透明像素列包 括多个透明像素单元，多个透明像素单元由栅线GL和发光像素列的边界限定，多个透明像素单元的每个包括一个透明子像素O。
例如，如图8所示，多个透明像素单元和多个发光像素单元沿列方向错位排列。例如，栅线GL在相邻的发光像素列之间具有凹陷部，以使得由栅线GL限定的多个透明像素单元沿列方向与多个发光像素单元错位排列。由此可以有效降低金属线(例如栅线GL)衍射效应对显示效果的影响。
例如，在一些实施例中，每相邻的两列发光像素单元之间具有一列透明像素单元，每相邻的两列透明像素单元之间具有一列发光像素单元。例如，多个发光子像素基本呈方形排列，透明子像素O向发光子像素的方向凹入，即透明子像素O的边缘为非直线形，并向发光子像素的方向凹入。由此可以有效的提高显示基板的光透过率，进而提高显示基板的透明显示效果。
例如，在一些实施例中，如图8所示，每个发光像素单元包括四个子像素，即一个红色子像素R、一个绿色子像素G、一个蓝色子像素B和一个白色子像素W。例如，红色子像素E与蓝色子像素B位于同一行，绿色子像素G与白色子像素W位于同一行。例如，在发光像素单元发出的光达到白平衡时，亮度高的像素行的发光区域的面积小于亮度低的像素行的发光区域的面积。例如，在一些示例中，在发光像素单元发出的光达到白平衡时，亮度满足：绿色子像素G的亮度>红色子像素R的亮度>蓝色子像素B的亮度。
例如，在一些实施例中，红色子像素R的发光区域R1与蓝色子像素B的发光区域B1的面积之和大于绿色子像素G的发光区域G1与白色子像素W的发光区域W1的面积之和。
需要注意的是，上述各发光子像素的发光区域由像素界定层14的子像素开口141限定，图8中示出的各发光子像素的发光区域均为矩形，这只是示意性的，在一些实施例中，发光区域的形状还可以是五边形、六边形等多边形或者一些不规则图形等，各发光子像素的发光区域的形状可以相同也可以不同，本公开的实施例对发光区域的具体形式不做限定。
例如，在一些实施例中，辅助电极图案AE设置在红色子像素R与蓝色子像素B所在的行中。本公开的实施例中，通过将辅助电极图案设置在发光区域的面积更大的像素行中，可以进一步降低该行发光子像素的第二电极的传输电阻，降低压降，提高显示均一性。
例如，在一些实施例中，如图8所示，红色子像素R与白色子像素W 位于同一列，绿色子像素G与蓝色子像素B位于同一列，红色子像素R与白色子像素W的发光区域的面积之和大于绿色子像素G与蓝色子像素B的发光区域的面积之和。例如，在一些实施例中，蓝色子像素B的发光区域的面积>红色子像素R的发光区域的面积>绿色子像素G的发光区域的面积，白色子像素W的发光区域的面积可以根据需要进行选择，例如，白色子像素W的发光区域的面积＞蓝色子像素B的发光区域的面积。
例如，图9示出了发光器件的第一电极的平面示意图。如图9所示，至少部分(例如每个)发光器件EM的第一电极E11可以包括第一子电极ES1和第二子电极ES2，第一子电极ES1和第二子电极ES2通过导电结构ES3电连接，导电结构ES3通过第二子过孔121与源极层S或者漏极层D电连接，在平行于衬底基板10的板面的方向上，第二子过孔121位于第一子电极ES1和第二子电极ES2之间。
本公开的实施例中，通过将一个第一电极E11分为电连接的两个子电极可以进一步提高显示基板的透明显示效果。
例如，如图9所示，在平行于衬底基板10的板面的方向上，第一子电极ES1至少包括首尾依次相接的第一边B1、第二边B2、第三边B3、第四边B4和第五边B5，第一边B1、第二边B2、第三边B3、第四边B4和第五边B5中的至少一个为直边，另一部分边可以为折线边或者曲线边等。例如，在一些示例中，至少相邻的第一边B1和第二边B2为直边，另一部分边可以为折线边或者曲线边等。
例如，第一边B1、第二边B2、第三边B3、第四边B4和第五边B5的边长依次为L1、L2、L3、L4和L5，则：
(L3+L4+L5) 2>(L1) 2+(L2) 2。
例如，如图9所示，该示例中，第一边B1、第二边B2、第三边B3和第五边B5为直边，且相邻的两条边之间的夹角为90度，第四边B4为折线边，折线部分的夹角也为90度。
例如，如图9所示，在平行于衬底基板10的板面的方向上，第二子电极ES2至少包括首尾依次相接的第六边B6、第七边B7、第八边B8、第九边B9和第十边B10，第六边B6、第七边B7、第八边B8、第九边B9和第十边B10中的至少一个为直边，另一部分边可以为折线边或者曲线边等。例如，在一些示例中，至少相邻的第六边B6和第七边B7为直边，另一部分 边可以为折线边或者曲线边等。
例如，第六边B6、第七边B7、第八边B8、第九边B9和第十边B10的边长依次为L6、L7、L8、L9和L10，则：
(L8+L9+L10) 2>(L6) 2+(L7) 2。
例如，如图9所示，该示例中，第六边B6、第七边B7和第九边B9为直边，第八边B8和第十边B10为折线边，且相邻的两条边之间的夹角为90度，折线边的折线部分的夹角也为90度。
通过上述设置，第一子电极ES1和第二子电极ES2的边缘更无序化，由此可以降低金属结构衍射效应对显示基板的显示效果的影响。
本公开的实施例中，显示基板还可以包括其他结构，具体可以参考相关技术，这里不再赘述。
例如，本公开的实施例中，衬底基板10可以包括聚酰亚胺(PI)等柔性绝缘材料或者玻璃基板等刚性绝缘材料。例如，在一些示例中，衬底基板10可以为多个柔性层和多个阻挡层交替设置的叠层结构。此时，柔性层可以包括聚酰亚胺，阻挡层可以包括氧化硅、氮化硅或者氮氧化硅等无机绝缘材料。例如，遮光金属层SL可以采用铜、铝或者钼等金属材料或其合金材料。例如，缓冲层15可以采用氧化硅、氮化硅或者氮氧化硅等无机绝缘材料。
例如，有源层AT可以采用多晶硅和金属氧化物(例如IGZO)等材料，栅绝缘层GI可以采用氧化硅、氮化硅或者氮氧化硅等无机绝缘材料，栅极GT可以采用铜、铝、钛、钴等金属材料，例如可以形成为单层结构或者多层结构，例如钛/铝/钛、钼/铝/钼等多层结构，第一绝缘层11和像素界定层14可以采用聚酰亚胺、树脂等有机绝缘材料，第二绝缘层12和层间绝缘层13可以采用氧化硅、氮化硅或者氮氧化硅等无机绝缘材料，源极层S和漏极层D以及辅助电极图案AE可以采用铜、铝、钛、钴等金属材料，例如可以形成为单层结构或者多层结构，例如钛/铝/钛、钼/铝/钼等多层结构，第一电极层E1例如包括ITO、IZO等金属氧化物或者Ag、Al、Mo等金属或其合金。发光材料层EL的材料可以为有机发光材料，例如，发光材料层EL的材料可根据需求选择可发出某一颜色光(例如红光、蓝光或者绿光等)的发光材料。第二电极层E2例如包括Mg、Ca、Li或Ag等金属或其合金，或者IZO、ZTO 等金属氧化物，又或者PEDOT/PSS(聚3，4-乙烯二氧噻吩/聚苯乙烯磺酸盐)等具有导电性能有机材料。本公开的实施例对各个功能层的材料不做具体限定。
本公开至少一实施例提供一种显示基板的制备方法，该制备方法包括：提供衬底基板；在衬底基板上形成第一金属层，第一金属层包括至少一个辅助电极图案；在第一金属层的远离衬底基板的一侧形成第一绝缘层，并在第一绝缘层中形成暴露至少一个辅助电极图案的至少一个第一过孔；在第一绝缘层的远离衬底基板的一侧形成第一电极层；在第一电极层的远离衬底基板的一侧形成发光材料层，并在第一电极层和发光材料层中形成暴露至少一个辅助电极图案且与至少一个第一过孔贯通的至少一个第二过孔；在至少一个第二过孔中形成含碳结构层；在发光材料层的远离衬底基板的一侧形成第二电极层，第二电极层通过含碳结构层与至少一个辅助电极图案电连接。例如，靠近第二过孔中部的第一金属层的靠近衬底基板的表面与第二电极层的远离衬基板的表面距离为d1，含碳结构层的平均碳氧比为c1，靠近第二过孔边缘的第一金属层的靠近所述衬底基板的表面与第二电极层的远离衬基板的表面距离为d2，含碳结构层的平均碳氧比为c2，则：
d1＜d2，c1＞c2。
例如，在一些实施例中，c1*d1>c2*d2。例如，含碳结构层C的平均碳氧比大于2:1小于10:1，例如为3:1、5:1或者8:1等。对于含碳结构层C以及显示基板的更多结构和设置，可以参见上述实施例，在此不再赘述。
下面，结合图10A-图11B对本公开实施例提供的显示基板的制备方法进行详细说明。
如图10A和图10B所示，首先在衬底基板10上沉积遮光金属材料层，然后对遮光金属材料层进行构图工艺以形成遮光金属层SL。例如，遮光金属材料层可以采用铜、铝或者钼等金属材料或其合金材料，沉积厚度可以为200nm-600nm。
本公开的实施例中，一次构图工艺可以包括光刻胶的形成、曝光、显影以及刻蚀等工艺。
然后，沉积缓冲层15，缓冲层15可以采用氧化硅、氮化硅或者氮氧化硅等材料，沉积厚度可以为300nm-500nm。
之后，沉积有源材料层，并对有源材料层进行构图工艺以形成有源层 AT。例如，有源材料层可以采用多晶硅和金属氧化物(例如IGZO)等材料，沉积厚度可以为30nm-50nm。
之后，沉积栅绝缘材料层以及栅金属层，并可以采用自对准工艺对栅绝缘材料层以及栅金属层进行图案化以形成栅极、栅金属图案和栅极绝缘层。例如，对栅绝缘材料层以及栅金属层进行同一构图工艺以形成栅极、栅金属图案和栅极绝缘层，从而形成的栅极和栅金属图案与栅极绝缘层具有基本相同的图案。例如，栅绝缘层GI可以采用氧化硅、氮化硅或者氮氧化硅等无机绝缘材料，沉积厚度可以为100nm-160nm。栅金属层可以采用铜、铝、钛、钴等金属材料或其合金材料，例如可以形成为单层结构或者多层结构，例如钼/铝双层结构，此时，钼的沉积厚度为30nm-60nm，铜的沉积厚度为300nm-500nm。
之后，沉积层间绝缘材料层，并对层间绝缘材料层进行构图工艺以形成层间绝缘层13，层间绝缘层13具有暴露有源层AT的多个过孔。例如，层间绝缘层13可以采用氧化硅、氮化硅或者氮氧化硅等无机绝缘材料，沉积厚度可以为400nm-600nm。
之后，沉积第一金属材料层，并对第一金属材料层进行构图以形成第一金属层M1，第一金属层M1包括辅助电极图案AE以及源极层S和漏极层D等，源极层S和漏极层D通过层间绝缘层13中的过孔与有源层AT电连接。例如，第一金属材料层可以采用铜、铝、钛、钴等金属材料或其合金材料，例如可以形成为单层结构或者多层结构，例如形成MoTi/Cu/MoTi三层结构等，此时，MoTi合金的沉积厚度可以为30nm-60nm,，铜的沉积厚度可以为300nm-600nm，该三层结构可以减少后续激光工艺对辅助电极图案AE的影响，稍后介绍。
之后，如图11A和图11B所示，沉积第二绝缘材料层，并对第二绝缘材料层进行构图工艺以形成第二绝缘层12，第二绝缘层12包括暴露辅助电极图案AE的第一子过孔和暴露漏极层D的第二子过孔。第二绝缘层12可以作为钝化层，其材料可以采用氧化硅、氮化硅或者氮氧化硅等无机绝缘材料，沉积厚度可以为300nm-5000nm。
之后，沉积第一绝缘材料层，并对第一绝缘材料层进行构图工艺以形成第一绝缘层11，第一绝缘层11具有暴露辅助电极图案AE的第一过孔V1。第一绝缘层11可以作为平坦层，其材料可以采用聚酰亚胺、树脂等有机绝 缘材料，沉积厚度可以为1000nm-3000nm。
之后，沉积第一电极材料层，并对第一电极材料层进行构图工艺以形成第一电极层E1，第一电极层E1包括第一电极E11以及第一电极E11外的其他部分，该其他部分具有暴露辅助电极图案AE的子过孔。例如，第一电极材料层可以采用ITO、IZO等金属氧化物或者Ag、Al、Mo等金属或其合金，沉积厚度可以为80nm-150nm。
之后，沉积像素界定材料层，并对像素界定材料层进行构图工艺以形成像素界定层14，像素界定层14具有暴露第一电极E11的多个子像素开口以及暴露辅助电极图案AE的子过孔。例如，像素界定材料层可以采用聚酰亚胺、树脂等有机绝缘材料，沉积厚度可以为500nm-2000nm。
之后，蒸镀有机发光材料层，并采用激光烧蚀工艺对有机发光材料层进行处理，以形成有机发光层EL，有机发光层EL包括暴露出辅助电极图案AE的子过孔。
例如，层间绝缘层13的第一子过孔、第一电极层E1的子过孔、像素界定层的子过孔以及有机发光层EL的子过孔相互贯通以形成暴露辅助电极图案AE的第二过孔V2。例如，有机发光材料层可根据需求选择可发出某一颜色光(例如红光、蓝光或者绿光等)的发光材料，蒸镀厚度可以为200nm-500nm。
之后，在第二过孔V2中制备含碳结构层C，含碳结构层C具有与辅助电极图案AE接触的第一部分C1以及位于第二过孔V2侧壁的第二部分C2。例如，含碳结构层C的形成厚度可以为200nm-500nm。
之后，沉积第二电极层E2，例如，第二电极层E2可以整面沉积在有机发光层EL上。例如，第二电极层E2可以采用Mg、Ca、Li或Ag等金属材料或其合金材料，沉积厚度为30nm-150nm。
之后，可以沉积封装层EN等其他功能层，具体可以参考相关技术，本公开的实施例对此不再赘述。
还有以下几点需要说明：
(1)本公开实施例的附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当 诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以权利要求的保护范围为准。

Claims (55)

  1. 一种显示基板，包括：
    衬底基板，
    第一金属层，设置在所述衬底基板上，包括至少一个辅助电极图案，
    第一绝缘层，设置在所述第一金属层的远离所述衬底基板的一侧，包括暴露部分所述至少一个辅助电极图案的至少一个第一过孔，
    第一电极层，设置在所述第一绝缘层的远离所述衬底基板的一侧，
    发光材料层，设置在所述第一电极层的远离所述衬底基板的一侧，其中，所述第一电极层和所述发光材料层包括暴露部分所述至少一个辅助电极图案且与所述至少一个第一过孔贯通的至少一个第二过孔，
    含碳结构层，至少部分设置在所述至少一个第二过孔中，
    第二电极层，设置在所述发光材料层和所述含碳结构层的远离所述衬底基板的一侧，其中，所述第二电极层通过所述含碳结构层与所述至少一个辅助电极图案电连接，
    靠近所述第二过孔中部的所述第一金属层的靠近所述衬底基板的表面与所述第二电极层的远离所述衬底基板的表面距离为d1，所述含碳结构层的平均碳氧比为c1，
    靠近所述第二过孔边缘的所述第一金属层的靠近所述衬底基板的表面与所述第二电极层的远离所述衬底基板的表面距离为d2，所述含碳结构层的平均碳氧比为c2，则：
    d1＜d2，c1＞c2。
  2. 根据权利要求1所述的显示基板，其中，
    c1*d1>c2*d2。
  3. 根据权利要求2所述的显示基板，其中，
    20*c2*d2>c1*d1>3*c2*d2。
  4. 根据权利要求1-3任一所述的显示基板，其中，所述含碳结构层的平均碳氧比大于1.3:1小于10:1。
  5. 根据权利要求1-4任一所述的显示基板，其中，所述含碳结构层在所述衬底基板上的正投影的面积小于所述辅助电极图案在所述衬底基板上的正投影的面积。
  6. 根据权利要求1-5任一所述的显示基板，其中，所述第一过孔在所述衬底基板上的正投影位于所述辅助电极图案在所述衬底基板上的正投影内，所述第二过孔在所述衬底基板上的正投影位于所述第一过孔在所述衬底基板上的正投影内。
  7. 根据权利要求6所述的显示基板，其中，所述含碳结构层包括与所述辅助电极图案接触的第一部分以及位于所述第二过孔的侧壁的第二部分，
    所述第一部分在所述衬底基板上的正投影位于所述第二过孔在所述衬底基板上的正投影内。
  8. 根据权利要求7所述的显示基板，其中，所述第二过孔的至少部分边缘呈锯齿形。
  9. 根据权利要求7或8所述的显示基板，其中，所述第一过孔在所述辅助电极图案上的正投影的轮廓包括n个拐点，所述第二过孔在所述辅助电极图案上的正投影的轮廓包括m个拐点，则：
    m>n>0。
  10. 根据权利要求6-9任一所述的显示基板，其中，所述含碳结构层在所述衬底基板上的正投影的面积为S1，平均碳氧比为Cs1，所述第一过孔不包括所述含碳结构层的区域的发光材料层在所述衬底基板上的正投影面积为S2，平均碳氧比为Cs2，则：
    碳氧匹配系数k＝S2*Cs2/S1*Cs1,0<k<2/3。
  11. 根据权利要求10所述的显示基板，其中，
    0<k<0.2。
  12. 根据权利要求1-11任一所述的显示基板，其中，所述辅助电极图案包括向远离所述衬底基板的方向突出的第一凸起部，所述第一凸起部在所述衬底基板上的正投影位于所述第二过孔在所述衬底基板上的正投影内。
  13. 根据权利要求12所述的显示基板，还包括：
    第二绝缘层，位于所述第一金属层和第一绝缘层之间，
    其中，所述第二过孔贯穿所述第二绝缘层，所述第一电极层通过所述第一绝缘层的所述第一过孔与所述第二绝缘层接触。
  14. 根据权利要求13所述的显示基板，其中，所述辅助电极图案被所述第二过孔暴露的部分为所述第一凸起部。
  15. 根据权利要求14所述的显示基板，其中，在垂直于所述衬底基板 的板面的方向上，所述第一凸起部的厚度为d3’,所述辅助电极图案的除所述第一凸起部外的部分的厚度为d3，则：
    d3>d3’。
  16. 根据权利要求14或15所述的显示基板，还包括：
    层间绝缘层，设置在所述衬底基板与所述第一金属层之间，
    其中，所述层间绝缘层包括向远离所述衬底基板的方向突出的第二凸起部，所述第一凸起部设置在所述第二凸起部的远离所述衬底基板的一侧。
  17. 根据权利要求16所述的显示基板，其中，所述层间绝缘层与所述第一凸起部接触的部分为所述第二凸起部；
    在垂直于所述衬底基板的板面的方向上，所述第二凸起部的厚度为d4’,所述层间绝缘层的除所述第二凸起部外的部分的厚度为d4，则：
    d4<d4’。
  18. 根据权利要求16或17所述的显示基板，其中，
    (d3-d3’)/d3>(d4’-d4)/d4；且
    (d3+d4-(d3’+d4’))/(d3+d4)<0.02。
  19. 根据权利要求16-18任一所述的显示基板，其中，所述层间绝缘层的靠近所述衬底基板的表面为平坦表面。
  20. 根据权利要求1-19任一所述的显示基板，其中，所述辅助电极图案在所述第二过孔的边缘包括第一坡部，所述层间绝缘层在所述第二过孔的边缘包括第二坡部，
    所述第一坡部的长度小于第二坡部的长度。
  21. 根据权利要求20所述的显示基板，其中，所述第二坡部的坡度角大于所述第一坡部的坡度角。
  22. 根据权利要求21所述的显示基板，其中，所述第二坡部的坡度角大于所述第一绝缘层在所述第一过孔处的坡度角，且大于所述第二绝缘层在所述第二过孔处的坡度角。
  23. 根据权利要求21或22所述的显示基板，还包括像素驱动电路，其中，所述像素驱动电路包括晶体管和存储电容，所述晶体管包括设置在所述衬底基板上的有源层、设置在所述有源层远离所述衬底基板一侧的栅极以及设置在所述栅极的远离所述衬底基板一侧的源极层和漏极层，所述源极层和漏极层分别与所述有源层电连接，所述存储电容包括第一极板和第二极板，
    所述源极层和所述漏极层、所述第二极板的至少部分设置在所述第一金属层中，所述第二绝缘层设置在所述源极层和漏极层的远离所述衬底基板的一侧。
  24. 根据权利要求23所述的显示基板，所述第一绝缘层还具有暴露所述第二极板的至少部分的第三过孔，
    在平行于所述衬底基板的板面的方向上，所述辅助电极图案的最大宽度大于第三过孔的最大宽度。
  25. 根据权利要求24所述的显示基板，所述第二过孔在所述辅助电极图案上的正投影的轮廓的周长大于所述第三过孔在所述第二极板上的正投影的周长。
  26. 根据权利要求23-25任一所述的显示基板，还包括设置在所述衬底基板与所述有源层之间的遮光金属层以及与所述栅极同层设置的栅金属图案，
    其中，所述栅金属图案在所述衬底基板上的正投影与所述遮光金属层在所述衬底基板上的正投影至少部分重叠，且与所述源极层或所述漏极层在所述衬底基板上的正投影至少部分重叠，以构成所述存储电容。
  27. 根据权利要求26所述的显示基板，还包括设置在所述遮光金属层与所述有源层之间的缓冲层，
    所述辅助电极图案的远离所述衬底基板的表面与所述缓冲层的远离所述衬底基板的表面的最大距离，大于所述源极层和所述漏极层的远离所述衬底基板的表面与所述缓冲层的远离所述衬底基板的表面的最大距离。
  28. 根据权利要求23-27任一所述的显示基板，其中，所述第二绝缘层具有暴露所述辅助电极图案的第一子过孔和暴露所述源极层或者所述漏极层的第二子过孔，
    所述第二绝缘层在所述第一子过孔处具有第三坡部，在所述第二子过孔处具有第四坡部，所述第三坡部的坡度角大于所述第四坡部的坡度角。
  29. 根据权利要求28所述的显示基板，其中，在垂直于所述衬底基板的板面的方向上，所述发光材料层具有与第三坡部重叠的第一发光材料部分以及与所述第四坡部重叠的第二发光材料部分，
    所述第一发光材料部分的厚度小于所述第二发光材料部分的厚度。
  30. 根据权利要求28或29所述的显示基板，还包括交替排布的发光像 素列和透明像素列，
    所述发光像素列包括多个发光像素单元，所述多个发光像素单元的每个包括多个发光子像素，
    所述透明像素列包括多个透明像素单元，所述多个透明像素单元由栅线和所述发光像素列的边界限定，所述多个透明像素单元的每个包括一个透明子像素，
    所述多个透明像素单元和所述多个发光像素单元沿列方向错位排列。
  31. 根据权利要求30所述的显示基板，其中，所述多个发光子像素基本呈方形排列，所述透明子像素向所述发光子像素的方向凹入。
  32. 根据权利要求30或31所述的显示基板，其中，所述多个发光像素单元的每个包括四个子像素，所述四个子像素包括一个红色子像素、一个绿色子像素、一个蓝色子像素和一个白色子像素，所述红色子像素与所述蓝色子像素位于同一行，所述绿色子像素与所述白色子像素位于同一行，
    所述红色子像素与所述蓝色子像素的发光区域的面积之和大于所述绿色子像素与所述白色子像素的发光区域的面积之和。
  33. 根据权利要求32所述的显示基板，其中，所述红色子像素与所述白色子像素位于同一列，所述绿色子像素与所述蓝色子像素位于同一列，
    所述红色子像素与所述白色子像素的发光区域的面积之和大于所述绿色子像素与所述蓝色子像素的发光区域的面积之和。
  34. 根据权利要求32或33所述的显示基板，其中，所述辅助电极图案设置在所述红色子像素与所述蓝色子像素所在的行中。
  35. 根据权利要求30-34任一所述的显示基板，其中，所述多个发光子像素的每个包括发光器件，所述发光器件包括位于所述第一电极层中的第一电极、位于所述发光材料层中的发光层以及位于所述第二电极层中的第二电极，
    所述第一电极包括第一子电极和第二子电极，所述第一子电极和所述第二子电极通过导电结构电连接，
    所述导电结构通过所述第二子过孔与所述源极层或者所述漏极层电连接，在平行于所述衬底基板的板面的方向上，所述第二子过孔位于所述第一子电极和所述第二子电极之间。
  36. 根据权利要求35所述的显示基板，其中，在平行于所述衬底基板 的板面的方向上，所述第一子电极至少包括首尾依次相接的第一边、第二边、第三边、第四边和第五边，所述第一边、第二边、第三边、第四边和第五边中的至少一个为直边。
  37. 根据权利要求36所述的显示基板，其中，所述第一边、第二边、第三边、第四边和第五边的边长依次为L1、L2、L3、L4和L5，则：
    (L3+L4+L5) 2>(L1) 2+(L2) 2。
  38. 根据权利要求36或37所述的显示基板，其中，在平行于所述衬底基板的板面的方向上，所述第二子电极至少包括首尾依次相接的第六边、第七边、第八边、第九边和第十边，所述第六边、第七边、第八边、第九边和第十边中的至少一个为直边。
  39. 根据权利要求38所述的显示基板，其中，所述第六边、第七边、第八边、第九边和第十边的边长依次为L6、L7、L8、L9和L10，则：
    (L8+L9+L10) 2>(L6) 2+(L7) 2。
  40. 一种显示基板，包括：
    衬底基板，
    层间绝缘层，设置在所述衬底基板上，
    第一金属层，设置在所述层间绝缘层的远离所述衬底基板的一侧，包括至少一个辅助电极图案，
    第一绝缘层，设置在所述第一金属层的远离所述衬底基板的一侧，包括暴露部分所述至少一个辅助电极图案的至少一个第一过孔，
    第一电极层，设置在所述第一绝缘层的远离所述衬底基板的一侧，
    发光材料层，设置在所述第一电极层的远离所述衬底基板的一侧，其中，所述第一电极层和所述发光材料层包括暴露部分所述至少一个辅助电极图案且与所述至少一个第一过孔贯通的至少一个第二过孔，
    含碳结构层，至少部分设置在所述至少一个第二过孔中，
    第二电极层，设置在所述发光材料层和所述含碳结构层的远离所述衬底基板的一侧，在垂直于所述衬底基板的板面的方向上，所述辅助电极层的厚度大于所述第二电极层的厚度；
    其中，所述第二电极层通过所述含碳结构层与所述至少一个辅助电极图案电连接，所述辅助电极图案在所述第二过孔的边缘包括第一坡部，所述层间绝缘层在所述第二过孔的边缘包括第二坡部，所述第一坡部的长度小于第 二坡部的长度。
  41. 根据权利要求40所述的显示基板，其中，所述第二坡部的坡度角大于所述第一坡部的坡度角，大于所述第一绝缘层在所述第一过孔处的坡度角，且大于所述第二绝缘层在所述第二过孔处的坡度角。
  42. 根据权利要求40或41所述的显示基板，其中，靠近所述第二过孔中部的所述第一金属层的靠近所述衬底基板的表面与所述第二电极层的远离所述衬底基板的表面距离为d1，所述含碳结构层的平均碳氧比为c1，
    靠近所述第二过孔边缘的所述第一金属层的靠近所述衬底基板的表面与所述第二电极层的远离所述衬底基板的表面距离为d2，所述含碳结构层的平均碳氧比为c2，则：
    c1*d1>c2*d2。
  43. 根据权利要求40-42任一所述的显示基板，其中，所述含碳结构层包括与所述辅助电极图案接触的第一部分以及位于所述第二过孔的侧壁的第二部分，
    所述第一部分在所述衬底基板上的正投影位于所述第二过孔在所述衬底基板上的正投影内。
  44. 根据权利要求43所述的显示基板，其中，所述第二过孔的至少部分边缘呈锯齿形。
  45. 根据权利要求44所述的显示基板，其中，所述第一过孔在所述辅助电极图案上的正投影的轮廓包括n个拐点，所述第二过孔在所述辅助电极图案上的正投影的轮廓包括m个拐点，则：m>n>0。
  46. 根据权利要求40-45任一所述的显示基板，其中，所述含碳结构层在所述衬底基板上的正投影的面积为S1，平均碳氧比为Cs1，所述第一过孔不包括所述含碳结构层的区域的发光材料层在所述衬底基板上的正投影面积为S2，平均碳氧比为Cs2，则：
    碳氧匹配系数k＝S2*Cs2/S1*Cs1,0<k<2/3。
  47. 一种显示基板，包括：
    衬底基板，
    第一金属层，设置在所述衬底基板上，包括至少一个辅助电极图案，
    第一绝缘层，设置在所述第一金属层的远离所述衬底基板的一侧，包括暴露部分所述至少一个辅助电极图案的至少一个第一过孔，
    第一电极层，设置在所述第一绝缘层的远离所述衬底基板的一侧，
    发光材料层，设置在所述第一电极层的远离所述衬底基板的一侧，其中，所述第一电极层和所述发光材料层包括暴露部分所述至少一个辅助电极图案且与所述至少一个第一过孔贯通的至少一个第二过孔，
    第二电极层，设置在所述发光材料层的远离所述衬底基板的一侧，其中，所述第二电极层通过所述至少一个第二过孔与所述至少一个辅助电极图案电连接，
    所述辅助电极图案包括向远离所述衬底基板的方向突出的第一凸起部，所述第一凸起部在所述衬底基板上的正投影位于所述第二过孔在所述衬底基板上的正投影内。
  48. 根据权利要求47所述的显示基板，还包括：
    第二绝缘层，位于所述第一金属层和第一绝缘层之间，
    其中，所述第二过孔贯穿所述第二绝缘层，所述第一电极层通过所述第一绝缘层的所述第一过孔与所述第二绝缘层接触。
  49. 根据权利要求48所述的显示基板，其中，所述辅助电极图案被所述第二过孔暴露的部分为所述第一凸起部。
  50. 根据权利要求48或49所述的显示基板，其中，在垂直于所述衬底基板的板面的方向上，所述第一凸起部的厚度为d3’,所述辅助电极图案的除所述第一凸起部外的部分的厚度为d3，则：
    d3>d3’。
  51. 根据权利要求50所述的显示基板，还包括：
    层间绝缘层，设置在所述衬底基板与所述第一金属层之间，
    其中，所述层间绝缘层包括向远离所述衬底基板的方向突出的第二凸起部，所述第一凸起部设置在所述第二凸起部的远离所述衬底基板的一侧。
  52. 根据权利要求51所述的显示基板，其中，所述层间绝缘层与所述第一凸起部接触的部分为所述第二凸起部；
    在垂直于所述衬底基板的板面的方向上，所述第二凸起部的厚度为d4’,所述层间绝缘层的除所述第二凸起部外的部分的厚度为d4，则：
    d4<d4’。
  53. 根据权利要求52所述的显示基板，其中，
    (d3-d3’)/d3>(d4’-d4)/d4；且
    (d3+d4-(d3’+d4’))/(d3+d4)<0.02。
  54. 根据权利要求51-53任一所述的显示基板，其中，所述层间绝缘层的靠近所述衬底基板的表面为平坦表面。
  55. 一种显示基板的制备方法，包括：
    提供衬底基板，
    在所述衬底基板上形成第一金属层，其中，所述第一金属层包括至少一个辅助电极图案，
    在所述第一金属层的远离所述衬底基板的一侧形成第一绝缘层(平坦层)，并在所述第一绝缘层中形成暴露部分所述至少一个辅助电极图案的至少一个第一过孔，
    在所述第一绝缘层的远离所述衬底基板的一侧形成第一电极层，
    在所述第一电极层的远离所述衬底基板的一侧形成发光材料层，并在所述第一电极层和所述发光材料层中形成暴露部分所述至少一个辅助电极图案且与所述至少一个第一过孔贯通的至少一个第二过孔，
    在所述至少一个第二过孔中形成含碳结构层，
    在所述发光材料层的远离所述衬底基板的一侧形成第二电极层，其中，所述第二电极层通过所述含碳结构层与所述至少一个辅助电极图案电连接，
    靠近所述第二过孔中部的所述第一金属层的靠近所述衬底基板的表面与所述第二电极层的远离所述衬基板的表面距离为d1，所述含碳结构层的平均碳氧比为c1，
    靠近所述第二过孔边缘的所述第一金属层的靠近所述衬底基板的表面与所述第二电极层的远离所述衬基板的表面距离为d2，所述含碳结构层的平均碳氧比为c2，则：
    d1＜d2，c1＞c2。
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