WO2018214802A1 - Oled基板及其制备方法、显示装置及其制备方法 - Google Patents

Oled基板及其制备方法、显示装置及其制备方法 Download PDF

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WO2018214802A1
WO2018214802A1 PCT/CN2018/087301 CN2018087301W WO2018214802A1 WO 2018214802 A1 WO2018214802 A1 WO 2018214802A1 CN 2018087301 W CN2018087301 W CN 2018087301W WO 2018214802 A1 WO2018214802 A1 WO 2018214802A1
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pole
oled
pixel
substrate
defining layer
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PCT/CN2018/087301
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English (en)
French (fr)
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张锋
吕志军
刘文渠
董立文
张世政
党宁
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京东方科技集团股份有限公司
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Priority to US16/326,787 priority Critical patent/US10930518B2/en
Publication of WO2018214802A1 publication Critical patent/WO2018214802A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H10K50/818—Reflective anodes, e.g. ITO combined with thick metallic layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/85—Arrangements for extracting light from the devices
    • H10K50/856—Arrangements for extracting light from the devices comprising reflective means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80518—Reflective anodes, e.g. ITO combined with thick metallic layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/20—Changing the shape of the active layer in the devices, e.g. patterning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/20—Changing the shape of the active layer in the devices, e.g. patterning
    • H10K71/211—Changing the shape of the active layer in the devices, e.g. patterning by selective transformation of an existing layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/20—Changing the shape of the active layer in the devices, e.g. patterning
    • H10K71/231—Changing the shape of the active layer in the devices, e.g. patterning by etching of existing layers
    • H10K71/233—Changing the shape of the active layer in the devices, e.g. patterning by etching of existing layers by photolithographic etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present application belongs to the field of display technologies, and in particular, to an OLED substrate, a preparation method thereof, a display device, and a preparation method thereof.
  • LCDs liquid crystal display devices
  • OLEDs organic electroluminescent diodes
  • the present application provides a method for preparing an OLED substrate, including:
  • a patterning process Forming, by a patterning process, a pattern including a first pole of the OLED device and a pixel defining layer above the first pole over the substrate; wherein the pixel defining layer includes a plurality of pixel retaining walls spaced apart, Each of the pixel retaining walls defines a first pole of the OLED device.
  • the pattern of the first pole including the OLED device and the pixel defining layer above the layer where the first pole is located is formed over the substrate by one patterning process; wherein the pixel defining layer
  • the method includes a plurality of pixel retaining walls disposed at intervals, and each of the pixel retaining walls defining a first pole of the OLED device includes:
  • Pole material Developing and etching the exposed pixel region of the fully exposed region and the partially exposed region after exposure to remove the pixel defining layer material of the fully exposed region to expose a portion corresponding to the fully exposed region. Pole material
  • the remaining pixel defining layer material of the partially exposed area is removed to form the pixel retaining wall.
  • the method before the forming a pattern including a first pole of the OLED device and a pixel defining layer above the layer where the first pole is located over the substrate by one patterning process, the method further includes:
  • Layer layers of the thin film transistor and a planarization layer are sequentially formed on the substrate.
  • the thin film transistor is a low temperature polysilicon thin film transistor or an oxide thin film transistor.
  • the method further includes:
  • a spacer is formed between the substrate and between two adjacent OLED devices.
  • the method further includes: after the forming a pattern of the first pole including the OLED device and the pixel defining layer located above the layer where the first pole is located over the substrate by using a patterning process, the method further includes:
  • a light emitting layer and a second electrode above the first pole are sequentially formed.
  • the first pole is made of a conductive reflective material.
  • the electrically conductive reflective material comprises an ITO/Ag/ITO material.
  • the present application further provides an OLED substrate including a plurality of OLED devices, each of the OLED devices including a first pole and a pixel defining layer on the first pole, the pixel defining layer including a pixel retaining wall, the boundary of the orthographic projection of the pixel retaining wall on the substrate coincides with the boundary of the orthographic projection of the first pole of the OLED device on the substrate.
  • the first pole comprises a conductive reflective material.
  • the electrically conductive reflective material comprises an ITO/Ag/ITO material.
  • the pixel retaining wall includes two pixel sub-retaining walls.
  • the OLED device further includes a light emitting layer and a second electrode, wherein the light emitting layer is disposed on the first electrode, between two pixel sub-walls, and the second electrode is disposed on Two pixel sub-walls are connected to the light-emitting layer.
  • the present application further provides a display device including the above OLED substrate.
  • FIG. 1 is a schematic flow chart of a method for preparing an OLED substrate according to an embodiment of the present application
  • FIG. 2 is a schematic structural view of the method for fabricating an OLED substrate according to an embodiment of the present application after performing step S1;
  • FIG. 3 is another schematic structural diagram of the method for fabricating an OLED substrate according to an embodiment of the present application after performing step S1;
  • FIG. 4 is a schematic structural view of the method for fabricating an OLED substrate according to an embodiment of the present application after performing step S21;
  • FIG. 5 is a schematic structural diagram of the method for fabricating an OLED substrate according to an embodiment of the present application after performing step S23;
  • FIG. 6 is a schematic structural diagram of the method for fabricating an OLED substrate according to an embodiment of the present application after performing step S24;
  • FIG. 7 is a schematic structural diagram of the method for fabricating an OLED substrate according to an embodiment of the present application after performing step S25;
  • FIG. 8 is a schematic structural view of the method for fabricating an OLED substrate according to an embodiment of the present application after performing step S3;
  • FIG. 9 is a schematic structural diagram of the method for fabricating an OLED substrate according to an embodiment of the present application after step S4 is performed.
  • the OLED substrate generally includes, in order, a base substrate, a flat layer disposed over the base substrate, an anode, and a pixel defining layer.
  • the anode and the pixel defining layer are usually prepared by a two-step process after the formation of the flat layer, and when the pixel defining layer is prepared over the anode pattern after the anode is prepared, due to the large exposure amount, The light will be transmitted through the anode to the thin film transistor under the flat layer, causing the threshold voltage Vth of the thin film transistor to drift, which affects the stability of the OLED substrate.
  • the process of separately preparing the anode and the pixel defining layer may cause problems such as reduced productivity and increased cost. .
  • an embodiment of the present application provides a method for preparing an OLED substrate, including:
  • step S1 the layer structure of the thin film transistor and the planarization layer 8 are sequentially formed on the substrate 1.
  • the thin film transistor is a low temperature polysilicon thin film transistor or an oxide thin film transistor.
  • the type of the thin film transistor is not limited thereto, and will not be described herein.
  • the oxide thin film transistor includes a gate electrode 2, a gate insulating layer 3, and a metal oxide layer 4 (ie, an active layer) which are sequentially formed on the substrate 1. ), source 5, drain 6, and insulating layer 7.
  • a planarization layer 8 is formed on the insulating layer 7.
  • the low temperature polysilicon thin film transistor includes a low temperature polysilicon layer 9 (ie, active layer) sequentially formed on the substrate 1, a buffer layer 10, and a gate electrode. 2. Interlayer dielectric layer 11, source 5, drain 6, and insulating layer 7. A planarization layer 8 is formed on the insulating layer 7.
  • the thin film transistor of the bottom gate structure is described.
  • the present application is not limited thereto, and a top gate structure may also be used, and details are not described herein again.
  • a description will be made of a method for preparing an OLED substrate using an oxide thin film transistor.
  • a method for preparing an OLED substrate using a low-temperature polysilicon thin film transistor is the same, and details are not described herein again.
  • Step S2 forming, by a patterning process, a pattern including a first pole 14 of the OLED device and a pixel defining layer above the layer where the first pole 14 is located over the substrate 1; wherein the pixel defining layer includes a plurality of spaced apart layers A pixel retaining wall 15, each of the pixel retaining walls 15 defines a first pole 14 of an OLED device.
  • step S2 specifically includes:
  • step S21 the first pole material 12 and the pixel defining layer material 13 are sequentially deposited over the substrate 1.
  • the first pole material 12 is actually deposited on the planarization layer 8
  • the pixel defining layer material 13 is deposited on the first pole material 12.
  • step S22 the pixel defining layer material 13 is exposed with different precision to form a fully exposed area A, a partially exposed area B, and an unexposed area C.
  • the exposure of different precisions in this embodiment may be performed by using a gray scale mask or a halftone mask, but is not limited thereto.
  • the function of the pixel defining layer material 13 is equivalent to the photoresist layer in the prior art process, that is, the pixel defining layer material 13 can save the photoresist in addition to forming the pixel defining layer in the subsequent step. The role.
  • step S23 the pixel defining layer material 13 of the exposed fully exposed area A and the partially exposed area B is developed and etched to remove the pixel defining layer material 13 of the fully exposed area A to expose and completely. A portion of the first pole material 12 corresponding to the exposed area A.
  • the region where the first pole material 12 is completely exposed is the fully exposed region A, and the region where the thickness of the pixel defining layer material 13 is reduced is the partially exposed region, and the pixel is limited.
  • the region where the thickness of the layer material 13 does not change is the unexposed region C.
  • step S24 the exposed first pole material 12 is etched to form the first pole 14.
  • the first pole 14 is made of a conductive reflective material.
  • the reason for this is that the first pole 14 is formed by using a conductive reflective material, and the light irradiated onto the first pole 14 can be reflected, so that the ultraviolet light irradiated onto the first pole 14 is not irradiated.
  • the thin film transistor is located under the first pole 14 to effectively protect the influence of the ultraviolet light on the characteristics of the thin film transistor, thereby ensuring the stability of the OLED substrate.
  • the first pole 14 is made of an ITO/Ag/ITO material.
  • the reason for this is that the ITO/Ag/ITO material has high luminous efficiency and electron extraction rate.
  • the material used for preparing the first electrode 14 is not limited thereto, and other conductive materials may be used. No longer.
  • step S25 the remaining pixel defining layer material 13 of the partially exposed region B is removed to form the pixel retaining wall 15.
  • the remaining pixel-defining layer material 13 in the partially exposed region B may be removed by an ashing process, thereby forming the pixel retaining wall 15 (located in the unexposed region C) in the pixel defining layer.
  • the pixel defining layer material 13 in the partially exposed region B is removed, and the thickness of the pixel defining layer material 13 in the unexposed region C is reduced.
  • a pixel retaining wall 15 is formed on the first pole 14 of each OLED device, and each of the pixel retaining walls 15 includes two trapezoidal sub-retaining walls 15 on each of the first poles 14 in FIG. 1 and 15-2, the plurality of pixel retaining walls 15 together constitute a pixel defining layer, that is, in the embodiment, the pixel defining layer is not a whole layer structure, but includes a plurality of separate pixel retaining walls 15 Do not connect the structure.
  • step S3 a spacer 16 is formed between the substrate 1 and between two adjacent OLED devices.
  • a spacer 16 is formed on the planarization layer 8 and between adjacent two OLED devices, and the spacer 16 can be used for supporting the substrate or forming a color film.
  • Mask plate It will be understood that the height of the upper surface of the spacer 16 should be greater than the height of the upper surface of the pixel retaining wall 15.
  • step S4 the light-emitting layer 17 and the second electrode 18 are formed on the first pole 14.
  • one of the first pole 14 and the second pole 18 is an anode, and the other is a cathode.
  • the first pole 14 is an anode
  • the second pole 18 is a cathode.
  • the solution of the embodiment is not limited thereto, and the first pole 14 is a cathode, and the second pole 18 is an anode, and details are not described herein again.
  • the light-emitting layer 17 is formed in a partially exposed region to be connected to the first pole 14 and between the two pixel sub-walls.
  • the second pole 18 is located on the pixel retaining wall 15 and is connected to the light emitting layer 17.
  • the second pole 18 is also made of a conductive material.
  • the light-emitting layer 17 can be formed by an inkjet printing process, and the second electrode 18 is formed by an evaporation process.
  • the patterning process for forming the light-emitting layer 17 and the second electrode 18 is not limited thereto. Let me repeat.
  • the method for preparing an OLED substrate of the present embodiment includes: forming, by a patterning process, a first electrode 14 including an OLED device and a layer at the first electrode 14 over a substrate 1 on which a thin film transistor and a planarization layer are sequentially formed.
  • the upper pixel defines the pattern of the layer, that is, the first pole 14 and the pixel defining layer can be prepared by one patterning process, and the pixel defining layer can serve as an etch protection layer of the first pole 14 (ie, equivalent to the photoresist) ), the patterning process can be reduced, and the use of the photoresist can be reduced, thereby greatly reducing the cost and increasing the productivity of the OLED substrate.
  • the first pole 14 and the pixel defining layer are prepared by one patterning process, which can completely avoid the first The pattern deviation generated when the one pole 14 and the pixel defining layer are separately prepared, thereby increasing the aperture ratio of the OLED substrate; moreover, when the patterning process is performed, since the presence of the first pole 14 can reflect the light, the ultraviolet light is not irradiated
  • the thin film transistor is located below the first pole 14, so that the effect of the ultraviolet light on the characteristics of the thin film transistor can be effectively protected, thereby ensuring O The stability of the LED substrate.
  • An embodiment of the present application provides a method of fabricating a display device, including the steps of the method for fabricating the OLED substrate of Embodiment 1.
  • the method for preparing the display device of the present embodiment includes the method for preparing the OLED substrate of the first embodiment.
  • the method for preparing the OLED substrate of the first embodiment can be described in detail, and details are not described herein again.
  • the first electrode 14 and the pixel defining layer may be prepared by one patterning process, and the pixel defining layer may serve as an etch protection layer of the first electrode 14 (ie, equivalent to a photoresist). It can reduce the patterning process once and reduce the use of photoresist, thereby greatly reducing the cost and increasing the productivity of the OLED substrate.
  • the first pole 14 and the pixel defining layer are prepared by one patterning process, which can completely avoid the first pole.
  • the pixel 14 and the pixel defining layer are separated from each other to produce a pattern deviation, thereby increasing the aperture ratio of the OLED substrate; moreover, when the patterning process is performed, the presence of the first pole 14 can reflect the light, and the ultraviolet light is not irradiated to the first
  • the thin film transistor under one pole 14 can effectively protect the influence of ultraviolet light on the characteristics of the thin film transistor, thereby ensuring the stability of the OLED substrate.
  • an embodiment of the present application provides an OLED substrate including a plurality of OLED devices, each OLED device including a first pole 14 and a pixel defining layer on the first pole 14 , the pixel defining layer including a plurality of Pixel barrier 15, the boundary of the area defined by the orthographic projection of each pixel retaining wall 15 on the substrate 1 and the boundary defined by the orthographic projection of the first pole 14 of the OLED device on the substrate 1 coincide.
  • each of the pixel retaining walls 15 is completely located on the first pole 14, and therefore, the first pole 14 of each pixel retaining wall 15 on which the orthographic projection on the substrate 1 is completely below is on the substrate 1. Within the area defined by the orthographic projection.
  • the OLED substrate of the present embodiment is prepared by the method for preparing the OLED substrate of the first embodiment.
  • the OLED substrate of the present embodiment is prepared by the method for preparing the OLED substrate of the first embodiment.
  • the OLED substrate of the present embodiment is prepared by the method for preparing the OLED substrate of the first embodiment.
  • the OLED substrate of the present embodiment is prepared by the method for preparing the OLED substrate of the first embodiment, wherein the first electrode 14 and the pixel defining layer can be prepared by one patterning process, and the pixel defining layer can be used as the first electrode 14. Etching the protective layer (ie equivalent to photoresist) can reduce the patterning process once and reduce the use of photoresist, thereby greatly reducing the cost and increasing the productivity of the OLED substrate.
  • the first pole 14 and the pixel limit The layer is prepared by one patterning process, and the pattern deviation generated when the first pole 14 and the pixel defining layer are separately prepared can be completely avoided, thereby improving the aperture ratio of the OLED substrate; and, when the patterning process is performed, the first pole 14 can reflect The light does not illuminate the thin film transistor located below the first pole 14. Therefore, the influence of the ultraviolet light on the characteristics of the thin film transistor can be effectively protected, thereby ensuring the stability of the OLED substrate.
  • One embodiment of the present application provides a display device including the OLED substrate of Embodiment 3.
  • the display device can be: electronic paper, OLED panel, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator and the like with any display product or component.
  • the first electrode 14 and the pixel defining layer of the OLED substrate can be prepared by one patterning process, and the pixel defining layer can serve as an etch protection layer of the first electrode 14 (ie, corresponding to the photoresist) ), the patterning process can be reduced, and the use of the photoresist can be reduced, thereby greatly reducing the cost and increasing the productivity of the OLED substrate.
  • the first pole 14 and the pixel defining layer are prepared by one patterning process, which can completely avoid the first The pattern deviation generated when the one pole 14 and the pixel defining layer are separately prepared, thereby increasing the aperture ratio of the OLED substrate; moreover, when the patterning process is performed, since the presence of the first pole 14 can reflect the light, the ultraviolet light is not irradiated
  • the thin film transistor is located below the first pole 14 and thus can effectively protect the influence of the ultraviolet light on the characteristics of the thin film transistor, thereby ensuring the stability of the OLED substrate.

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Abstract

本申请提供一种OLED基板及其制备方法、显示装置及其制备方法，属于显示技术领域。本申请的OLED基板的制备方法，包括：通过一次构图工艺，在衬底的上方形成包括OLED器件的第一极和位于所述第一极上方的像素限定层的图形；其中，所述像素限定层包括间隔设置的多个像素挡墙，每一个所述像素挡墙限定一个所述OLED器件的第一极。

Description

OLED基板及其制备方法、显示装置及其制备方法
相关申请的交叉引用
本申请要求于2017年5月23日提交的中国专利申请No.201710368041.X的优先权，所公开的内容以引用的方式合并于此。
技术领域
本申请属于显示技术领域，具体涉及一种OLED基板及其制备方法、显示装置及其制备方法。
背景技术
随着科学技术的不断进步，视觉资讯在人们生活中的地位越来越重要，因此，承载视觉资讯信息的平板显示器件也在人们生活中占据着越来越重要的地位。这些常见的平板显示器件包括液晶显示器件(LCD)，有机电致发光二极管(OLED)等。
发明内容
本申请提供一种OLED基板的制备方法，包括：
通过一次构图工艺，在衬底的上方形成包括OLED器件的第一极和位于所述第一极上方的像素限定层的图形；其中，所述像素限定层包括间隔设置的多个像素挡墙，每一个所述像素挡墙限定一个所述OLED器件的第一极。
在一些实施例中，所述通过一次构图工艺，在衬底的上方形成包括OLED器件的第一极和位于所述第一极所在层上方的像素限定层的图形；其中，所述像素限定层包括间隔设置的多个像素挡墙，每一个所述像素挡墙限定一个所述OLED器件的第一极的步骤包括：
在所述衬底的上方依次沉积第一极材料和像素限定层材料；
对像素限定层材料进行不同精度的曝光，形成完全曝光区域、部分曝光区域和未曝光区域；
对曝光后的完全曝光区域和部分曝光区域的像素限定层材料进 行显影、刻蚀，去除所述完全曝光区域的像素限定层材料，以暴露出与所述完全曝光区域对应的部分所述第一极材料；
对暴露出的所述第一极材料进行刻蚀，以形成所述第一极；
去除所述部分曝光区域剩余的像素限定层材料，以形成所述像素挡墙。
在一些实施例中，在所述通过一次构图工艺，在衬底的上方形成包括OLED器件的第一极和位于所述第一极所在层上方的像素限定层的图形之前，还包括：
在所述衬底上依次形成薄膜晶体管的各层结构和平坦化层。
在一些实施例中，所述薄膜晶体管为低温多晶硅薄膜晶体管或氧化物薄膜晶体管。
在一些实施例中，在所述通过一次构图工艺，在衬底的上方形成包括OLED器件的第一极和位于所述第一极上方的像素限定层的图形之后，还包括：
在所述衬底的上方且相邻两个所述OLED器件之间形成隔垫物。
其中，在所述通过一次构图工艺，在衬底的上方形成包括OLED器件的第一极和位于所述第一极所在层上方的像素限定层的图形之后，还包括：
依次形成位于所述第一极上方的发光层和第二极。
在一些实施例中，所述第一极采用导电的反射材料制成。
在一些实施例中，所述导电的反射材料包括ITO/Ag/ITO材料。
作为另一技术方案，本申请还提供一种OLED基板，包括多个OLED器件，每个所述OLED器件包括第一极和位于所述第一极上的像素限定层，所述像素限定层包括像素挡墙，所述像素挡墙在衬底上的正投影的边界与所述OLED器件的第一极在衬底上的正投影的边界重合。
在一些实施例中，所述第一极包括导电的反射材料。
在一些实施例中，所述导电的反射材料包括ITO/Ag/ITO材料。
在一些实施例中，所述像素挡墙包括两个像素子挡墙。
在一些实施例中，所述OLED器件还包括发光层和第二电极， 其中，所述发光层设置在所述第一电极上、两个像素子挡墙之间，所述第二电极设置在两个像素子挡墙上且与所述发光层连接。
作为另一技术方案，本申请还提供一种显示装置，包括上述的OLED基板。
附图说明
图1为本申请的实施例的OLED基板的制备方法的流程示意图；
图2为本申请的实施例的OLED基板的制备方法中执行完步骤S1之后的一种结构示意图；
图3为本申请的实施例的OLED基板的制备方法中执行完步骤S1之后的另一种结构示意图；
图4为本申请的实施例的OLED基板的制备方法中执行完步骤S21之后的结构示意图；
图5为本申请的实施例的OLED基板的制备方法中执行完步骤S23之后的结构示意图；
图6为本申请的实施例的OLED基板的制备方法中执行完步骤S24之后的结构示意图；
图7为本申请的实施例的OLED基板的制备方法中执行完步骤S25之后的结构示意图；
图8为本申请的实施例的OLED基板的制备方法中执行完步骤S3之后的结构示意图；
图9为本申请的实施例的OLED基板的制备方法中执行完步骤S4之后的结构示意图。
具体实施方式
为使本领域技术人员更好地理解本申请的技术方案，下面结合附图和具体实施方式对本申请作进一步详细描述。
OLED基板中通常依次包括衬底基板、设置在衬底基板上方的平坦层、阳极和像素限定层。在现有OLED基板的制备过程中，通 常在平坦层形成之后通过两步工艺制备阳极和像素限定层，而在制备完成阳极之后，在阳极图案上方制备像素限定层时，由于曝光量较大，光线会透过阳极照射到平坦层下方的薄膜晶体管，导致薄膜晶体管的阈值电压Vth漂移，影响OLED基板的稳定性；另外，阳极和像素限定层分开制备的工艺会造成产能降低、成本增加等问题。
请参照图1至图9，本申请的一个实施例提供一种OLED基板的制备方法，包括：
步骤S1，在衬底1上依次形成薄膜晶体管的各层结构和平坦化层8。
其中，薄膜晶体管为低温多晶硅薄膜晶体管或氧化物薄膜晶体管。当然，薄膜晶体管的类型并不局限于此，在此不再赘述。
请参照图2，在薄膜晶体管为氧化物薄膜晶体管的情况下，该氧化物薄膜晶体管包括在衬底1上依次形成的栅极2、栅绝缘层3、金属氧化物层4(即有源层)、源极5、漏极6、绝缘层7。绝缘层7上形成有平坦化层8。
请参照图3，在薄膜晶体管为低温多晶硅薄膜晶体管的情况下，该低温多晶硅薄膜晶体管包括在衬底1上依次形成的低温多晶硅层9((即有源层))、缓冲层10、栅极2、层间介质层11、源极5、漏极6、绝缘层7。绝缘层7上形成有平坦化层8。
需要说明的是，本实施例中是以底栅结构的薄膜晶体管进行描述的，但本申请并不局限于此，还可以采用顶栅结构，在此不再赘述。在以下描述中，以采用氧化物薄膜晶体管的OLED基板的制备方法进行描述，当然，采用低温多晶硅薄膜晶体管的OLED基板的制备方法相同，在此不再赘述。
步骤S2，通过一次构图工艺，在衬底1的上方形成包括OLED器件的第一极14和位于第一极14所在层上方的像素限定层的图形；其中，像素限定层包括间隔设置的多个像素挡墙15，每一个像素挡墙15限定一个OLED器件的第一极14。
其中，步骤S2具体包括：
请参照图4，步骤S21，在衬底1的上方依次沉积第一极材料12和像素限定层材料13。从图4中可以看出，第一极材料12实际上是沉积在平坦化层8上的，像素限定层材料13沉积在第一极材料12上。
步骤S22，对像素限定层材料13进行不同精度的曝光，形成完全曝光区域A、部分曝光区域B和未曝光区域C。需要说明的是，本实施例中所说的不同精度的曝光可采用灰阶掩膜板或半色调掩膜板进行曝光，但不局限于此。此时，像素限定层材料13的作用相当于现有技术工艺中的光刻胶层，即像素限定层材料13除了在后续步骤中能够形成像素限定层之外，还可以起到节省光刻胶的作用。
请参照图5，步骤S23，对曝光后的完全曝光区域A和部分曝光区域B的像素限定层材料13进行显影、刻蚀，去除完全曝光区域A的像素限定层材料13，以暴露出与完全曝光区域A对应的部分第一极材料12。
从图5中可以看出，在进行不同精度的曝光之后，第一极材料12完全裸露出来的区域为完全曝光区域A，像素限定层材料13的厚度减小的区域为部分曝光区域，像素限定层材料13的厚度没有发生变化的区域为未曝光区域C。
请参照图6，步骤S24，对暴露出的第一极材料12进行刻蚀，以形成第一极14。
在一些实施例中，第一极14采用导电的反射材料制成。之所以如此设置，是由于采用导电的反射材料制成第一极14，能够对照射到第一极14上的光线进行反射，因此，不会使照射到第一极14上的紫外光照射到位于第一极14下方的薄膜晶体管上，从而能够有效的保护紫外光对薄膜晶体管的特性的影响，进而保证了OLED基板的稳定性。
在一些实施例中，第一极14采用ITO/Ag/ITO材料制成。之所以如此设置，是由于ITO/Ag/ITO材料具有较高的发光效率和电子取出率，当然，制备第一极14所采用的材料并不局限于此，还可以采用其他导电材料，在此不再赘述。
请参照图7，步骤S25，去除部分曝光区域B剩余的像素限定层材料13，以形成像素挡墙15。
在本实施例中，可采用灰化工艺去除部分曝光区域B中剩余的像素限定层材料13，从而形成像素限定层中的像素挡墙15(位于未曝光区域C中)。从图7中可以看出，在灰化工艺过程中，部分曝光区域B中的像素限定层材料13被去除，未曝光区域C中的像素限定层材料13的厚度被减小。
需要说明的是，每个OLED器件的第一极14上均形成有一个像素挡墙15，每个像素挡墙15包括图7中每个第一极14上的两个梯形子挡墙15-1和15-2，多个像素挡墙15共同组成像素限定层，也就是说，在本实施例中，像素限定层并不是一个整层结构，而是包括多个分开的像素挡墙15的不连接结构。
请参照图8，步骤S3，在衬底1的上方且相邻两个OLED器件之间形成隔垫物16。
从图8中可以看出，在平坦化层8上，且位于相邻两个OLED器件之间形成有隔垫物16，该隔垫物16能够用于支撑对盒基板或形成彩膜时所用的掩膜板。可以理解的是，隔垫物16的上表面的高度应大于像素挡墙15的上表面的高度。
请参照图9，步骤S4，形成位于第一极14之上的发光层17和第二极18。需要说明的是，第一极14和第二极18中的一者为阳极，另一者为阴极，在本实施例中，第一极14为阳极，第二极18为阴极，当然，本实施例的方案并不局限于此，也可第一极14为阴极，第二极18为阳极，在此不再赘述。
从图9中可以看出，发光层17形成在部分曝光区域中，以与第一极14连接，并且位于两个像素子挡墙之间。第二极18位于像素挡墙15上并与发光层17连接。需要说明的是，第二极18也采用导电材料制成。在本实施例中，可通过喷墨打印工艺形成发光层17，通过蒸镀工艺形成第二极18，当然，形成发光层17和第二极18的构图工艺并不局限于此，在此不再赘述。
本实施例的OLED基板的制备方法，包括：通过一次构图工艺， 在依次形成有薄膜晶体管和平坦化层的衬底1的上方形成包括OLED器件的第一极14和位于第一极14所在层上方的像素限定层的图形，也就是说，第一极14和像素限定层可以采用一次构图工艺制备，同时，像素限定层可以作为第一极14的刻蚀保护层(即相当于光刻胶)，既可以减少一次构图工艺，还可以减少光刻胶的使用，从而大幅度降低成本、提高OLED基板的产能；另外，第一极14和像素限定层通过一次构图工艺制备，能够完全避免第一极14和像素限定层分开制备时所产生的图案偏差，从而提高OLED基板的开口率；而且，在进行构图工艺时，由于第一极14的存在能够反射光线，不会使紫外光照射到位于第一极14下方的薄膜晶体管上，因此，能够有效的保护紫外光对薄膜晶体管的特性的影响，从而保证了OLED基板的稳定性。
本申请的一个实施例提供一种显示装置的制备方法，包括实施例1的OLED基板的制备方法的步骤。
本实施例的显示装置的制备方法，包括实施例1的OLED基板的制备方法，详细描述可参照实施例1的OLED基板的制备方法，在此不再赘述。
本实施例的显示装置的制备方法，第一极14和像素限定层可以采用一次构图工艺制备，同时，像素限定层可以作为第一极14的刻蚀保护层(即相当于光刻胶)，既可以减少一次构图工艺，还可以减少光刻胶的使用，从而大幅度降低成本、提高OLED基板的产能；另外，第一极14和像素限定层通过一次构图工艺制备，能够完全避免第一极14和像素限定层分开制备时所产生的图案偏差，从而提高OLED基板的开口率；而且，在进行构图工艺时，由于第一极14的存在能够反射光线，不会使紫外光照射到位于第一极14下方的薄膜晶体管上，因此，能够有效的保护紫外光对薄膜晶体管的特性的影响，从而保证了OLED基板的稳定性。
请参照图9，本申请的一个实施例提供一种OLED基板，包括 多个OLED器件，每个OLED器件包括第一极14和位于第一极14上的像素限定层，像素限定层包括多个像素挡墙15，每一个像素挡墙15在衬底1上的正投影所限定的区域的边界和其所在的OLED器件的第一极14在衬底1上的正投影所限定的区域的边界重合。
也就是说，每个像素挡墙15是完全位于第一极14上的，因此，每个像素挡墙15在衬底1上的正投影完全位于其下方的第一极14在衬底1上的正投影所限定的区域内。
本实施例的OLED基板，采用实施例1的OLED基板的制备方法制备而成，详细描述可参照实施例1的OLED基板的制备方法，在此不再赘述。
本实施例的OLED基板，采用实施例1的OLED基板的制备方法制备而成，其中，第一极14和像素限定层可以采用一次构图工艺制备，同时，像素限定层可以作为第一极14的刻蚀保护层(即相当于光刻胶)，既可以减少一次构图工艺，还可以减少光刻胶的使用，从而大幅度降低成本、提高OLED基板的产能；另外，第一极14和像素限定层通过一次构图工艺制备，能够完全避免第一极14和像素限定层分开制备时所产生的图案偏差，从而提高OLED基板的开口率；而且，在进行构图工艺时，由于第一极14能够反射光线，不会使紫外光照射到位于第一极14下方的薄膜晶体管上，因此，能够有效的保护紫外光对薄膜晶体管的特性的影响，从而保证了OLED基板的稳定性。
本申请的一个实施例提供了一种显示装置，包括实施例3的OLED基板。显示装置可以为：电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本实施例的显示装置，其中，OLED基板的第一极14和像素限定层可以采用一次构图工艺制备，同时，像素限定层可以作为第一极14的刻蚀保护层(即相当于光刻胶)，既可以减少一次构图工艺，还可以减少光刻胶的使用，从而大幅度降低成本、提高OLED基板 的产能；另外，第一极14和像素限定层通过一次构图工艺制备，能够完全避免第一极14和像素限定层分开制备时所产生的图案偏差，从而提高OLED基板的开口率；而且，在进行构图工艺时，由于第一极14的存在能够反射光线，不会使紫外光照射到位于第一极14下方的薄膜晶体管上，因此，能够有效的保护紫外光对薄膜晶体管的特性的影响，从而保证了OLED基板的稳定性。
可以理解的是，以上实施方式仅仅是为了说明本申请的原理而采用的示例性实施方式，然而本申请并不局限于此。对于本领域内的普通技术人员而言，在不脱离本申请的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本申请的保护范围。

Claims (14)

  1. 一种OLED基板的制备方法，包括：
    通过一次构图工艺，在衬底的上方形成包括OLED器件的第一极和位于所述第一极上方的像素限定层的图形；其中，所述像素限定层包括间隔设置的多个像素挡墙，每一个所述像素挡墙限定一个所述OLED器件的第一极。
  2. 根据权利要求1所述的OLED基板的制备方法，其中，所述通过一次构图工艺，在衬底的上方形成包括OLED器件的第一极和位于所述第一极上方的像素限定层的图形；其中，所述像素限定层包括间隔设置的多个像素挡墙，每一个所述像素挡墙限定一个所述OLED器件的第一极的步骤包括：
    在所述衬底的上方依次沉积第一极材料和像素限定层材料；
    对像素限定层材料进行不同精度的曝光，形成完全曝光区域、部分曝光区域和未曝光区域；
    对曝光后的完全曝光区域和部分曝光区域的像素限定层材料进行显影、刻蚀，去除所述完全曝光区域的像素限定层材料，以暴露出与所述完全曝光区域对应的部分所述第一极材料；
    对暴露出的所述第一极材料进行刻蚀，以形成所述第一极；
    去除所述部分曝光区域剩余的像素限定层材料，以形成所述像素挡墙。
  3. 根据权利要求1所述的OLED基板的制备方法，其中，在所述通过一次构图工艺，在衬底的上方形成包括OLED器件的第一极和位于所述第一极上方的像素限定层的图形之前，还包括：
    在所述衬底上依次形成薄膜晶体管的各层结构和平坦化层。
  4. 根据权利要求3所述的OLED基板的制备方法，其中，所述薄膜晶体管为低温多晶硅薄膜晶体管或氧化物薄膜晶体管。
  5. 根据权利要求1所述的OLED基板的制备方法，其中，在所述通过一次构图工艺，在衬底的上方形成包括OLED器件的第一极和位于所述第一极上方的像素限定层的图形之后，还包括：
    在所述衬底的上方且相邻两个所述OLED器件之间形成隔垫物。
  6. 根据权利要求1所述的OLED基板的制备方法，其中，在所述通过一次构图工艺，在衬底的上方形成包括OLED器件的第一极和位于所述第一极上方的像素限定层的图形之后，还包括：
    依次形成位于所述第一极上方的发光层和第二极。
  7. 根据权利要求1至6所述的OLED基板的制备方法，其中，所述第一极采用导电的反射材料制成。
  8. 根据权利要求7所述的OLED基板的制备方法，其中，所述导电的反射材料包括ITO/Ag/ITO材料。
  9. 一种OLED基板，其包括多个OLED器件，每个所述OLED器件包括第一极和位于所述第一极上的像素限定层，所述像素限定层包括像素挡墙，所述像素挡墙在衬底上的正投影的边界与所述OLED器件的第一极在衬底上的正投影的边界重合。
  10. 根据权利要求9所述的OLED基板，其中，所述第一极包括导电的反射材料。
  11. 根据权利要求10所述的OLED基板，其中，所述导电的反射材料包括ITO/Ag/ITO材料。
  12. 根据权利要求9所述的OLED基板，其中，所述像素挡墙包括两个像素子挡墙。
  13. 根据权利要求12所述的OLED基板，其中，所述OLED器件还包括发光层和第二电极，其中，所述发光层设置在所述第一电极上、两个像素子挡墙之间，所述第二电极设置在两个像素子挡墙上且与所述发光层连接。
  14. 一种显示装置，其包括权利要求9至13中任一项所述的OLED基板。
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