WO2020173102A1 - 阵列基板及其制造方法、显示面板及显示装置 - Google Patents

阵列基板及其制造方法、显示面板及显示装置 Download PDF

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Publication number
WO2020173102A1
WO2020173102A1 PCT/CN2019/111859 CN2019111859W WO2020173102A1 WO 2020173102 A1 WO2020173102 A1 WO 2020173102A1 CN 2019111859 W CN2019111859 W CN 2019111859W WO 2020173102 A1 WO2020173102 A1 WO 2020173102A1
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Prior art keywords
base substrate
pattern
source
flat pattern
drain
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PCT/CN2019/111859
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English (en)
French (fr)
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田宏伟
牛亚男
李栋
王纯阳
刘明
刘政
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京东方科技集团股份有限公司
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Priority to US16/766,905 priority Critical patent/US11139356B2/en
Publication of WO2020173102A1 publication Critical patent/WO2020173102A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/38—Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/20—Changing the shape of the active layer in the devices, e.g. patterning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/40—Thermal treatment, e.g. annealing in the presence of a solvent vapour

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate and a manufacturing method thereof, a display panel and a display device.
  • OLED Organic Light-Emitting Diode
  • OLED display panels generally use a circular polarizer to reduce external reflected light, that is, a circular polarizer is attached to the light-emitting surface of the OLED display panel.
  • the circular polarizer can reduce the ambient light entering the OLED display panel. The amount of light emitted from the light-emitting surface after the internal structure of the OLED display panel is reflected. The light-emitting effect of the OLED display panel still needs to be improved.
  • an array substrate with a display area including: a base substrate, and a thin film transistor structure located on the surface of the base substrate, wherein the thin film transistor structure is located in the display area;
  • the thin film transistor structure includes at least a source/drain pattern and a flat pattern, the source/drain pattern and the flat pattern are located on the side of the thin film transistor structure away from the base substrate; wherein the flat pattern is far away from the substrate.
  • the surface of the substrate and the surface of the source/drain pattern away from the base substrate are substantially in the same plane, the flat pattern has a first slot, and the source/drain pattern is accommodated in the first slot Inside.
  • the array substrate further includes: a non-display area adjacent to the display area; wherein the base substrate is a flexible base substrate, the non-display area includes a bending area, and the bending There is a second slot in the area, and an organic filler is arranged in the second slot; and the array substrate includes a wiring located in a non-display area, and the wiring is located in the organic filler away from the substrate One side of the substrate.
  • the flat pattern and the organic filler are formed by the same process.
  • the array substrate further includes a flat layer, and the flat layer is located on a side of the source and drain patterns away from the base substrate.
  • the thin film transistor structure further includes an active layer pattern, a passivation layer, and a gate pattern sequentially disposed on the base substrate, and the source and drain patterns pass through the passivation layer.
  • the hole is connected to the active layer pattern.
  • the thin film transistor structure further includes a gate pattern, an interlayer insulating layer, and an active layer pattern sequentially disposed on the base substrate, and the source and drain patterns are connected to the active layer pattern.
  • a display panel including: the array substrate according to any one of the first aspects.
  • the display panel further includes a first electrode, a light-emitting layer, a second electrode, and a filter stacked on a side of the flat pattern away from the base substrate.
  • the first electrode and the The second electrode is one of the cathode and the anode.
  • the display panel has two sets of parallel opposite sides, the display area has a plurality of pixels, and the arrangement direction of the plurality of pixels is not parallel to any side of the display panel.
  • a display device including: the display panel according to any one of the second aspects.
  • a method for manufacturing an array substrate includes: providing a base substrate; forming a thin film transistor structure on the base substrate, the thin film transistor structure being located In the display area, forming a thin film transistor structure on the base substrate at least includes: forming a flat pattern on the base substrate, the flat pattern having a first slot; forming in the first slot The source-drain pattern, wherein the surface of the flat pattern away from the base substrate and the surface of the source-drain pattern away from the base substrate are substantially in the same plane.
  • forming a flat pattern on the base substrate includes: coating an organic material on the base substrate to form an organic material layer in the display area, and the thickness of the organic material layer is greater than or equal to that of the source. The thickness of the drain pattern; the organic material layer located in the display area is exposed and developed to obtain the flat pattern.
  • the base substrate is a flexible base substrate
  • the non-display area includes a bending area
  • the method further includes: The inorganic film layer inside is etched to form a second slot; coating an organic material on the base substrate further includes: filling the second slot with the organic material to form a second slot An organic filler is formed in the tank.
  • the array substrate includes traces located in the bending area.
  • the method may further include: patterning in the organic The side of the filler away from the base substrate forms the wiring.
  • the thickness of the organic material layer is greater than the thickness of the source and drain patterns.
  • the method further includes: using a halftone mask to expose the flat pattern; The flat pattern after the exposure treatment is subjected to development processing, so that the thickness of the flat pattern after the development treatment is equal to the thickness of the source and drain patterns.
  • the thickness of the organic material layer is greater than the thickness of the source and drain patterns.
  • the method further includes: ashing the flat pattern by an ashing process to make The thickness of the flat pattern after the ashing treatment is equal to the thickness of the source and drain patterns.
  • FIG. 1 is a schematic structural diagram of an OLED display panel provided in the related art
  • FIG. 2 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic top view of a flat pattern provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of yet another array substrate provided by an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of still another array substrate provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of pixel distribution in a display panel provided by an embodiment of the present disclosure.
  • FIG. 9 is a flowchart of a manufacturing method of an array substrate provided by an embodiment of the present disclosure.
  • FIG. 10 is a flowchart of another method for manufacturing an array substrate provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of a process flow for forming a flat pattern on the side of the interlayer insulating layer away from the base substrate according to an embodiment of the present disclosure.
  • Color Filter on Encap, COE Color Filter on Encap
  • the filter is packaged on the light exit side of the OLED display panel. Since the filter can filter the light, it is also The amount of ambient light entering the OLED display panel from the light exit surface after being reflected by the internal structure of the OLED display panel can be reduced. In addition, compared with circular polarizers, filters have higher light transmittance and better flexibility. Therefore, COE technology has been developed.
  • the OLED display panel includes an array substrate and a light emitting device on the array substrate.
  • the thickness of the source and drain patterns of the thin film transistor (TFT) in the array substrate is getting larger and larger. Because the array substrate is a multilayer film layer stack structure, the thickness is larger.
  • the source-drain pattern will make its flatness poor, which easily leads to uneven surface of the bottom electrode in the light-emitting device. Therefore, in the existing COE technology, when the OLED display panel is in the off-screen state, when external light enters the inside of the OLED display panel and is reflected on the surface of the lower electrode, concentrated reflection in a certain direction is likely to occur, resulting in the reflected light being filtered. The color separation phenomenon occurs after the film, which causes the reflection image to be distorted. Therefore, the reliability of the OLED display panel in the related art is low.
  • FIG. 1 is a schematic structural diagram of an OLED display panel provided in the related art.
  • the OLED display panel includes an array substrate 10, a light emitting device 11 on the array substrate 10, and a light emitting device 11 on the light emitting side.
  • the array substrate 10 includes a base substrate 101, and an active layer 102, a passivation layer 103, a gate pattern 104, an interlayer insulating layer 105, a source/drain pattern 106, and an active layer 102 stacked on the base substrate 101.
  • the light emitting device 11 includes a first electrode 111, a light emitting layer 112 and a second electrode 113;
  • the filter 12 has a red filter region R, a green filter region G, and a blue filter region B.
  • the thickness of the source and drain patterns becomes larger and larger.
  • the flatness of the flat layer 107 formed on the side of the source and drain patterns 106 away from the base substrate 101 is poor, further resulting in a second layer formed on the flat layer 107.
  • the surface of an electrode 111 is uneven.
  • external light especially strong light
  • enters the inside of the OLED display panel and is reflected on the surface of the first electrode 111 since the surface of the first electrode 111 is uneven, concentrated reflection in a certain direction is likely to occur.
  • the reflected light exits through the R, G, and B on the filter, color separation will occur, which will cause distortion of the reflected image.
  • the reflected image refers to an image formed by reflecting external light when the OLED display panel is in the off-screen state.
  • the array substrate 20 has a display area A and a non-display area B located around the display area A.
  • the array substrate 20 includes:
  • the thin film transistor structure at least includes a source and drain pattern 205 and a flat pattern 204, and the source and drain pattern 205 and the flat pattern 204 are located on a side of the thin film transistor structure away from the base substrate 201.
  • the surface of the flat pattern 204 away from the base substrate 201 and the surface of the source/drain pattern 205 away from the base substrate 201 are substantially in the same plane, and the flat pattern 204 has The first slot H1, the source/drain pattern 205 is accommodated in the first slot H1.
  • substantially located in the same plane means that the step difference between the surface of the two film layers does not exceed 20% of the thickness of one of the film layers, such as not more than 15%, 10% of the thickness of one of the film layers, 5% etc.
  • the surface of the flat pattern 204 away from the base substrate 201 and the surface of the source/drain pattern 205 away from the base substrate 201 do not exceed 20% of the thickness of the flat pattern 204, specifically It can be no more than 15%, 10%, 5%, etc. of the thickness of the flat pattern 204; or no more than 20% of the thickness of the source/drain pattern 205, specifically can be no more than 15% of the thickness of the flat pattern 204 , 10%, 5%, etc.
  • the source-drain pattern 205 includes a source 205a and a drain 205b.
  • FIG. 3 is a schematic top view of the structure of a flat pattern provided by an embodiment of the present disclosure.
  • the flat pattern 204 has a first groove H1 that accommodates the source and drain patterns 205a, 205b.
  • the thickness of the flat pattern is equal to the thickness of the source and drain patterns.
  • the thickness of the flat pattern and the source/drain pattern ranges from 300 to 800 nanometers.
  • the thickness of the source/drain pattern refers to the thickness of the portion of the source/drain pattern located in the first groove of the flat pattern, excluding the thickness of the portion of the source/drain pattern located in the through hole.
  • the material of the gate pattern includes at least one of aluminum (Al), neodymium (Nd), and molybdenum (Mo); the material of the source and drain pattern includes at least one of aluminum, neodymium, and molybdenum; and the flat pattern
  • the materials used include polyimide (PI) and acrylic (polymethyl methacrylate (PMMA)) and other organic materials.
  • PI polyimide
  • PMMA polymethyl methacrylate
  • the thin film transistor structure in the embodiments of the present disclosure may be a top gate structure or a bottom gate structure.
  • the thin film transistor structure is a top gate structure, referring to FIG. 2, the thin film transistor structure further includes an active layer pattern 206, a passivation layer 207, and a gate pattern 202 sequentially disposed on the base substrate 201.
  • the source-drain pattern 205 is connected to the active layer pattern 206 via a through hole passing through the passivation layer 207.
  • 4 is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure.
  • the thin film transistor structure is a bottom gate structure, referring to FIG.
  • the thin film transistor structure further includes The gate pattern 202, the interlayer insulating layer 203 and the active layer pattern 206, and the source and drain patterns 205 are connected to the active layer pattern 206.
  • the following embodiments of the present disclosure take the thin film transistor structure as the top gate structure as an example for description.
  • the surface of the flat pattern away from the base substrate and the surface of the source/drain pattern away from the base substrate are substantially in the same plane, and the flat pattern has a pattern for accommodating the source/drain. That is, the source-drain pattern can be accommodated in the first groove of the flat pattern. Therefore, the problem of poor flatness of the array substrate due to the large thickness of the source and drain patterns can be alleviated, and the surface flatness of the array substrate can be improved. Further, the flatness of the film layer on the array substrate can be improved, and the phenomenon of concentrated reflection in a certain direction occurs when external light enters the interior of the display panel when reflection occurs on the surface of the film layer. Therefore, the color separation phenomenon can be improved and the product reliability can be improved.
  • the base substrate is a flexible base substrate, for example, the base substrate may be prepared from a polyethylene terephthalate (PET) plastic film or a PI plastic film.
  • FIG. 5 is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure. As shown in FIG. 5, the non-display area B includes a bending area, and the bending area has a second slot H2. An organic filler M is arranged in the second slot H2; the array substrate includes a wire 209 located in the bending area (that is, a wire 209 located in the non-display area B), and the wire 209 is located far away from the organic filler M One side of the base substrate 201.
  • PET polyethylene terephthalate
  • the thickness of the organic filler ranges from 0.5 to 1.5 microns.
  • the inorganic film layer (including the passivation layer and the interlayer insulating layer, etc.) has high rigidity and is prone to breakage when bent.
  • the fracture of the inorganic film layer may easily lead to the wiring breakage, which affects the normal display of the display panel.
  • the inorganic film layer in the bending area is usually etched to form a groove, and organic fillers are arranged in the groove. Since the organic filler has good flexibility, the possibility of breaking during bending is low, so the risk of wire breakage can be reduced and the reliability of the array substrate can be improved.
  • the flat pattern and the organic filler are formed by the same process. It should be noted that the flat pattern and the organic filler are prepared by the same process, without adding new process steps to prepare the flat pattern, that is, without adding additional process costs, and high achievability. Optionally, the flat pattern and the organic filler can also be prepared separately through different processes, which is not limited in the embodiment of the present disclosure.
  • the base substrate may also be a hard base substrate, for example, the base substrate may be prepared from materials such as glass, silicon wafer, and quartz.
  • the embodiment of the present disclosure does not limit the material of the base substrate.
  • FIG. 6 is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure. As shown in FIG. 6, the array substrate 20 further includes a flat layer 208, and the flat layer 208 is located on a side of the source and drain patterns 205 away from the base substrate 201. side.
  • the flatness of the array substrate can be further improved, and the flatness of the subsequently prepared film layer can be improved.
  • the surface of the flat pattern away from the base substrate and the surface of the source/drain pattern away from the base substrate are substantially in the same plane, and the flat pattern has a surface accommodating the source and drain electrodes.
  • the first groove of the pattern that is, the source-drain pattern can be accommodated in the first groove of the flat pattern. Therefore, the problem of poor flatness of the array substrate due to the large thickness of the source and drain patterns can be alleviated, and the surface flatness of the array substrate can be improved.
  • the flatness of the film layer on the array substrate can be improved, and the phenomenon of concentrated reflection in a certain direction occurs when external light enters the interior of the display panel when reflection occurs on the surface of the film layer. Therefore, the color separation phenomenon can be improved and the product reliability can be improved.
  • An embodiment of the present disclosure provides a display panel, which includes: an array substrate 20 as shown in any one of FIG. 2 and FIG. 4 to FIG. 6.
  • FIG. 7 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • the display panel includes an array substrate 20 as shown in FIG. 6, and the array substrate 20 further includes a flat layer 208.
  • the flat layer 208 is located on the side of the source and drain patterns 205 away from the base substrate 201.
  • the display panel further includes a first electrode 301, a light emitting layer 302, a second electrode 303, and a filter 40 stacked on the side of the flat layer 208 away from the base substrate 201.
  • the first electrode and the second electrode are respectively It is one of the cathode and anode.
  • the light-emitting layer includes a first carrier injection layer, a first carrier transport layer, a luminescent material layer, a second carrier transport layer, and a second carrier injection layer stacked in a direction away from the first electrode.
  • the first carrier and the second carrier are one of electrons and holes respectively.
  • the first carrier is the hole and the second carrier is the electron; when the first electrode is the cathode and the second electrode is the anode, the first carrier For electrons, the second carrier is holes.
  • the filter 40 has a red filter region R and a green sub-pixel.
  • the filter can filter the emitted light to improve the color purity of the emitted light; on the other hand, the filter can filter the external light, which can reduce the ambient light entering the display panel, thereby reducing The reflection of the ambient light by the display panel improves the user experience.
  • the structure composed of the first electrode, the light-emitting layer, and the second electrode that are stacked and arranged can also be called a light-emitting device.
  • the light-emitting device may be an OLED device or a Quantum Dot Light Emitting Diode (QLED) device or the like.
  • FIG. 8 is a schematic diagram of pixel distribution in a display panel provided by an embodiment of the present disclosure.
  • the display panel has two sets of parallel opposite sides, and the display area A has multiple pixels x.
  • the arrangement direction of the plurality of pixels x is not parallel to any side of the display panel.
  • each pixel x includes at least one color sub-pixel.
  • the arrangement direction of the plurality of pixels in the display area is not parallel to any side of the display panel, which can improve the color separation phenomenon of the display panel and improve the product reliability of the display panel.
  • the surface of the flat pattern away from the base substrate and the surface of the source/drain pattern away from the base substrate are substantially in the same plane, and the flat pattern has a pattern for accommodating the source/drain. That is, the source-drain pattern can be accommodated in the first groove of the flat pattern. Therefore, the problem of poor flatness of the array substrate due to the large thickness of the source and drain patterns can be alleviated, and the surface flatness of the array substrate can be improved. Further, the flatness of the film layer on the array substrate can be improved, and the phenomenon of concentrated reflection in a certain direction occurs when external light enters the interior of the display panel when reflection occurs on the surface of the film layer. Therefore, the color separation phenomenon can be improved and the product reliability can be improved.
  • An embodiment of the present disclosure provides a display device, including: a display panel as shown in FIG. 7.
  • the display device provided by the embodiment of the present disclosure may be any product or component with display function such as electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, or navigator.
  • FIG. 9 is a flowchart of a method for manufacturing an array substrate provided by an embodiment of the present disclosure.
  • the array substrate has a display area and a non-display area around the display area.
  • the method includes the following steps: S501: Provide a base substrate; S502: forming a thin film transistor structure on the base substrate, the thin film transistor structure is located in the display area, and forming the thin film transistor structure on the base substrate at least includes: S503: A flat pattern is formed on the base substrate, and the flat pattern has a first slot; S504: a source and drain pattern is formed in the first slot, wherein the flat pattern is away from the surface of the base substrate and the The surface of the source and drain patterns away from the base substrate is substantially in the same plane.
  • the array substrate as shown in FIG. 2 or FIG. 4 can be prepared.
  • the structure of the array substrate please refer to the embodiment on the structure side. Do not repeat it.
  • the manufacturing method of the array substrate provided by the embodiments of the present disclosure firstly forms a flat pattern on the base substrate, and then forms the source and drain patterns on the base substrate formed with the flat pattern.
  • the surface of the flat pattern away from the base substrate and the surface of the source/drain pattern away from the base substrate are substantially in the same plane, and the flat pattern has a first groove for accommodating the source/drain pattern, that is, the source/drain pattern can accommodate Place in the first slot of the flat pattern. Therefore, the problem of poor flatness of the array substrate due to the large thickness of the source and drain patterns can be alleviated, and the surface flatness of the array substrate can be improved.
  • the flatness of the film layer on the array substrate can be improved, and the phenomenon of concentrated reflection in a certain direction when the external light enters the inside of the display panel is prevented from being reflected on the surface of the film layer. Therefore, the color separation phenomenon can be improved and the product reliability can be improved.
  • the above method further includes: sequentially forming an active layer pattern, a passivation layer, a gate pattern, and an interlayer insulating layer on the base substrate.
  • the above method further includes: sequentially forming a gate pattern, an interlayer insulating layer, and an active layer on the base substrate.
  • the following embodiments of the present disclosure take the array substrate as the top gate structure as an example to describe the preparation process of the array substrate.
  • the manufacturing process of the array substrate of the bottom gate structure can refer to the manufacturing process of the array substrate of the top gate structure. Do not repeat it here.
  • FIG. 10 is a flowchart of another method for manufacturing an array substrate provided by an embodiment of the present disclosure.
  • the array substrate has a display area and a non-display area around the display area. As shown in FIG. 10, the method includes the following steps.
  • S601 Provide a base plate.
  • the base substrate is a flexible base substrate, for example, the base substrate may be prepared from a PET plastic film or a PI plastic film.
  • the base substrate may also be a hard base substrate, for example, the base substrate may be prepared from materials such as glass, silicon wafer, and quartz. The embodiment of the present disclosure does not limit the material of the base substrate.
  • the material of the active layer pattern includes indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO), single crystal silicon (a-Si), low temperature polysilicon (Low Temperature Poly-silicon, LTPS) or low temperature polycrystalline oxide At least one of Low Temperature Polycrystalline Oxide (LTPO).
  • the active layer pattern can be formed on the base substrate by deposition.
  • the material of the passivation layer includes at least one of silicon dioxide or silicon nitride.
  • the material of the gate pattern includes at least one of aluminum, neodymium, and molybdenum.
  • the gate layer can be formed by deposition, and then the gate pattern can be formed by a patterning process.
  • the patterning process includes: photoresist coating, exposure, development, etching, and photoresist stripping.
  • the gate pattern may be a two-layer structure, which is not limited in the embodiment of the present disclosure.
  • the material of the interlayer insulating layer includes at least one of silicon dioxide, silicon nitride, and aluminum oxide.
  • an interlayer insulating layer can be formed on the base substrate with the gate pattern formed by deposition.
  • a via hole may be formed on the interlayer insulating layer and the passivation layer through a patterning process, and the via hole is used to connect the active layer and the source and drain patterns.
  • the vias on the interlayer insulating layer and the passivation layer can be prepared by a patterning process, or can be prepared by a patterning process respectively, which is not limited in the embodiment of the present disclosure.
  • S606 Form a flat pattern on the side of the interlayer insulating layer away from the base substrate, the flat pattern having a first slot.
  • step S606 includes: coating an organic material on the side of the interlayer insulating layer away from the base substrate, thereby forming an organic material layer in the display area, and the thickness of the organic material layer is greater than or equal to that of the source and drain patterns. Thickness: The organic material layer is exposed and developed to obtain a flat pattern.
  • the material of the flat pattern may include organic materials such as PI and acrylic.
  • the above-mentioned via holes for connecting the active layer and the source and drain patterns can also be formed on the interlayer insulating layer and the passivation layer after the flat pattern is formed.
  • Those skilled in the art can make selection according to the specific process. This application does not limit this.
  • the base substrate is a flexible base substrate
  • the non-display area includes a bending area
  • the organic material is coated on the base substrate on which the interlayer insulating layer is formed
  • the inorganic The film layer is etched to form a second slot.
  • the above-mentioned coating of the organic material on the side of the interlayer insulating layer away from the base substrate may further include: filling the organic material in the second groove to form an organic filler in the second groove, that is, The organic filling in the bending area and the flat pattern in the display area are formed by the same process.
  • the rigidity of the inorganic film layer is high, and it is prone to breakage when bent.
  • the fracture of the inorganic film layer may easily lead to the wiring breakage, which affects the normal display of the display panel.
  • the inorganic film layer in the bending area is usually etched to form a groove, and organic fillers are arranged in the groove. Since the organic filler has good flexibility, the possibility of breaking during bending is low, so the risk of wire breakage can be reduced and the reliability of the array substrate can be improved.
  • the flat pattern and the organic filler are prepared through the same process, without adding new process steps to prepare the flat pattern, that is, without adding additional process costs, and high achievability.
  • the flat pattern and the organic filler can also be prepared separately, which is not limited in the embodiment of the present disclosure.
  • a certain error size is reserved in the first groove to improve the matching between the source and drain patterns and the flat pattern.
  • the gaps between the flat pattern and the source-drain pattern are not shown in FIGS. 2, 4, 5, 6, and 7, but the drawings are only schematic and do not represent a limitation of the present disclosure.
  • FIG. 11 is a schematic diagram of a process flow (both are top views) for forming a flat pattern on the side of the interlayer insulating layer away from the base substrate provided by an embodiment of the present disclosure. As shown in FIG. 11, it includes the following steps:
  • S1 Provide a base substrate on which an interlayer insulating layer 203 is formed, and a second slot H2 is formed in the bending area in the non-display area.
  • the depth of the second groove ranges from 0.5 to 1.5 microns.
  • the thickness of the organic filler formed in the second groove is in the range of 0.5 to 1.5 microns, that is, the thickness of the organic material layer is in the range of 0.5 to 1.5. Micrometers.
  • the thickness of the source and drain patterns is generally in the range of 300 to 800 nanometers.
  • a half-tone mask can be used to expose the flat pattern; the flat pattern after the exposure treatment is developed to undergo development processing
  • the thickness of the flat pattern is equal to the thickness of the source and drain patterns.
  • an ashing process may be used to perform an ashing process on the flat pattern, so that the thickness of the flat pattern after the ashing process is equal to the thickness of the source and drain patterns.
  • the thickness of the flat pattern is equal to the thickness of the source/drain pattern. After the source/drain pattern is accommodated in the first groove of the flat pattern, the source/drain pattern can be kept away from the surface of the base substrate. The surface of the flat pattern away from the base substrate is flush (that is, in the same plane), which further improves the flatness of the array substrate.
  • S607 forming a source-drain pattern on a base substrate with a flat pattern.
  • the surface of the flat pattern away from the base substrate and the source-drain pattern away from the base substrate are substantially in the same plane, and the source-drain pattern is accommodated in the first Inside a slot.
  • the material of the source and drain patterns includes at least one of aluminum, neodymium, and molybdenum, and the source and drain patterns may be formed on a base substrate with a flat pattern through a patterning process.
  • the preparation temperature of the source and drain metal is generally 200-250° C., or other low-temperature processes can be used to prepare the source and drain patterns.
  • the method may further include: The wiring is formed on the side of the organic filler away from the base substrate through a patterning process.
  • a flat layer is formed on the side of the source and drain patterns away from the base substrate by a deposition or coating process. It should be noted that by forming a flat layer on the side of the source and drain patterns away from the base substrate, the flatness of the array substrate can be further improved, thereby improving the reliability of subsequent film layer preparation.
  • the array substrate as shown in FIG. 6 can be prepared.
  • the structure of the array substrate please refer to the embodiment on the structure side. The embodiment of the present disclosure will not be repeated here. .
  • the manufacturing method of the array substrate provided by the embodiments of the present disclosure firstly forms a flat pattern on the base substrate, and then forms the source and drain patterns on the base substrate formed with the flat pattern.
  • the surface of the flat pattern away from the base substrate and the surface of the source/drain pattern away from the base substrate are substantially in the same plane, and the flat pattern has a first groove for accommodating the source/drain pattern, that is, the source/drain pattern can accommodate Place in the first slot of the flat pattern. Therefore, the problem of poor flatness of the array substrate due to the large thickness of the source and drain patterns can be alleviated, and the surface flatness of the array substrate can be improved.
  • the flatness of the film layer on the array substrate can be improved, and the phenomenon of concentrated reflection in a certain direction occurs when external light enters the interior of the display panel when reflection occurs on the surface of the film layer. Therefore, the color separation phenomenon can be improved and the product reliability can be improved.

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Abstract

一种具有显示区域（A）的阵列基板（20）及其制造方法、显示面板及显示装置。该具有显示区域（A）的阵列基板（20）包括：衬底基板（201），以及位于衬底基板（201）的表面的薄膜晶体管结构，其中，薄膜晶体管结构位于显示区域（A）中；薄膜晶体管结构至少包括源漏极图案（205）和平坦图案（204），源漏极图案（205）和平坦图案（204）位于所述薄膜晶体管结构远离衬底基板（201）的一侧；其中，平坦图案（204）远离衬底基板（201）的表面与源漏极图案（205）远离衬底基板（201）的表面基本上位于同一平面中，平坦图案（204）具有第一开槽（H1），源漏极图案（205）容置于所述第一开槽（H1）内。

Description

阵列基板及其制造方法、显示面板及显示装置
相关申请
本公开要求2019年2月26日提交的申请号为201910140616.1的中国专利申请的优先权，该专利申请的所有内容通过引用合并于此。
技术领域
本公开涉及显示技术领域，特别涉及一种阵列基板及其制造方法、显示面板及显示装置。
背景技术
有机发光二极管(Organic Light-Emitting Diode，OLED)作为一种电流型发光器件，因其所具有的低功耗、自发光、高色饱和度、快速响应、宽视角和能够实现柔性化等特点而越来越多地被应用于高性能显示领域当中。目前的OLED显示面板普遍采用圆偏光片(Circular Polarizer)来减少外部的反射光线，即在OLED显示面板的出光面贴附圆偏光片，该圆偏光片能够减少进入OLED显示面板内的环境光被OLED显示面板的内部结构反射后从出光面的出射量。OLED显示面板的出光效果仍需改善。
发明内容
第一方面，提供了一种具有显示区域的阵列基板，包括：衬底基板，以及位于所述衬底基板的表面的薄膜晶体管结构，其中，所述薄膜晶体管结构位于所述显示区域中；所述薄膜晶体管结构至少包括源漏极图案和平坦图案，所述源漏极图案和平坦图案位于所述薄膜晶体管结构远离所述衬底基板的一侧；其中，所述平坦图案远离所述衬底基板的表面与所述源漏极图案远离所述衬底基板的表面基本上位于同一平面中，所述平坦图案具有第一开槽，所述源漏极图案容置于所述第一开槽内。
可选地，所述阵列基板还包括：与所述显示区域相邻的非显示区域；其中，所述衬底基板为柔性衬底基板，所述非显示区域包括弯折区，所述弯折区内具有第二开槽，所述第二开槽内设置有有机填充物； 并且所述阵列基板包括位于非显示区域的走线，所述走线位于所述有机填充物远离所述衬底基板的一侧。
可选地，所述平坦图案与所述有机填充物由同一工艺形成。
可选地，所述阵列基板还包括平坦层，所述平坦层位于所述源漏极图案远离所述衬底基板的一侧。
可选地，所述薄膜晶体管结构还包括依次设置在所述衬底基板上的有源层图案、钝化层和栅极图案，所述源漏极图案经由穿过所述钝化层的通孔与所述有源层图案连接。
可选地，所述薄膜晶体管结构还包括依次设置在所述衬底基板上的栅极图案、层间绝缘层和有源层图案，所述源漏极图案与所述有源层图案连接。
第二方面，提供了一种显示面板，包括：如第一方面任一所述的阵列基板。
可选地，所述显示面板还包括位于所述平坦图案远离所述衬底基板的一侧层叠设置的第一电极、发光层、第二电极和滤光片，所述第一电极和所述第二电极分别为阴极和阳极中的一极。
可选地，所述显示面板具有两组平行的对边，所述显示区域内具有多个像素，所述多个像素的排布方向与所述显示面板的任一边不平行。
第三方面，提供了一种显示装置，包括：如第二方面任一所述的显示面板。
第四方面，提供了一种阵列基板的制造方法，所述阵列基板具有显示区域，所述方法包括：提供衬底基板；在所述衬底基板上形成薄膜晶体管结构，所述薄膜晶体管结构位于所述显示区域中，在所述衬底基板上形成薄膜晶体管结构至少包括：在所述衬底基板上形成平坦图案，所述平坦图案具有第一开槽；在所述第一开槽内形成源漏极图案，其中，所述平坦图案远离所述衬底基板的表面与所述源漏极图案远离所述衬底基板的表面基本上位于同一平面中。
可选地，在所述衬底基板上形成平坦图案包括：在所述衬底基板上涂覆有机材料，从而在显示区域形成有机材料层，所述有机材料层的厚度大于或等于所述源漏极图案的厚度；对位于所述显示区域内的有机材料层进行曝光显影处理，得到所述平坦图案。
可选地，所述衬底基板为柔性衬底基板，所述非显示区域包括弯折区，在所述衬底基板上涂覆有机材料之前，所述方法还包括：对所述弯折区内的无机膜层进行蚀刻处理，形成第二开槽；在所述衬底基板上涂覆有机材料还包括：在所述第二开槽内填充所述有机材料，以在所述第二开槽内形成有机填充物。
可选地，所述阵列基板包括位于所述弯折区内的走线，与在第一开槽内形成所述源漏极图案同时，所述方法还可以包括：通过构图工艺在所述有机填充物远离所述衬底基板的一侧形成所述走线。
可选地，所述有机材料层的厚度大于所述源漏极图案的厚度，在得到所述平坦图案之后，所述方法还包括：采用半色调掩模板对所述平坦图案进行曝光处理；对经过所述曝光处理后的平坦图案进行显影处理，使经过所述显影处理后的平坦图案的厚度等于所述源漏极图案的厚度。
可选地，所述有机材料层的厚度大于所述源漏极图案的厚度，在得到所述平坦图案之后，所述方法还包括：采用灰化工艺对所述平坦图案进行灰化处理，使经过所述灰化处理后的平坦图案的厚度等于所述源漏极图案的厚度。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是相关技术中提供的一种OLED显示面板的结构示意图；
图2是本公开实施例提供的一种阵列基板的结构示意图；
图3是本公开实施例提供的平坦图案的俯视结构示意图；
图4是本公开实施例提供的另一种阵列基板的结构示意图；
图5是本公开实施例提供的又一种阵列基板的结构示意图；
图6是本公开实施例提供的再一种阵列基板的结构示意图；
图7是本公开实施例提供的一种显示面板的结构示意图；
图8是本公开实施例提供的一种显示面板中的像素分布示意图；
图9是本公开实施例提供的一种阵列基板的制造方法的流程图；
图10是本公开实施例提供的另一种阵列基板的制造方法流程图；以及
图11是本公开实施例提供的一种在层间绝缘层远离衬底基板的一侧形成平坦图案的工艺流程示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
相关技术中提供了一种封装上的彩色滤光片(Color Filter on Encap，COE)技术，在OLED显示面板的出光侧封装滤光片，由于滤光片能够对光线起到过滤作用，因此也可以减少进入OLED显示面板内的环境光被OLED显示面板的内部结构反射后从出光面的出射量。另外，滤光片与圆偏光片相比，其光透过率更高且柔性效果更好，因此COE技术得到了发展。
OLED显示面板包括阵列基板以及位于阵列基板上的发光器件。随着OLED显示面板的分辨率的提高，阵列基板中薄膜晶体管(Thin Film Transistor，TFT)的源漏极图案的厚度越来越大，由于阵列基板为多层膜层堆叠结构，厚度较大的源漏极图案会使其平坦度较差，易导致发光器件中的下电极表面不平整。因此在现有的COE技术中，当该OLED显示面板处于熄屏状态，外界光线进入OLED显示面板内部在下电极表面发生反射时，易出现某个方向上的集中反射现象，导致反射光线经过滤光片后出现色分离现象，进而导致反射图像失真，因此相关技术中OLED显示面板的信赖性较低。
图1是相关技术中提供的一种OLED显示面板的结构示意图，如图1所示，该OLED显示面板包括阵列基板10，位于阵列基板10上的发光器件11，以及位于发光器件11出光侧的滤光片12。参见图1，阵列基板10包括衬底基板101，以及层叠设置在衬底基板101上的有源层102、钝化层103、栅极图案104、层间绝缘层105、源漏极图案106 和平坦层107；发光器件11包括第一电极111、发光层112和第二电极113；滤光片12具有红色滤光区R、绿色滤光区G和蓝色滤光区B。
随着OLED显示面板的分辨率的提高，源漏极图案的厚度越来越大。参见图1，由于源漏极图案106的厚度较大，在源漏极图案106远离衬底基板101的一侧形成的平坦层107的平坦度较差，进一步导致在平坦层107上形成的第一电极111的表面不平整。当外界光线(尤其是强光)进入OLED显示面板内部，在第一电极111的表面发生反射时，由于第一电极111的表面不平整，易出现某个方向上的集中反射现象。反射光线经过滤光片上的R、G和B出射后会出现色分离现象，进而导致反射图像失真。其中，反射图像指OLED显示面板处于熄屏状态下，通过反射外界光线形成的图像。
图2是本公开实施例提供的一种阵列基板的结构示意图，如图2所示，该阵列基板20具有显示区域A和位于显示区域A周围的非显示区域B，该阵列基板20包括：
衬底基板201，以及位于所述衬底基板201的表面的薄膜晶体管结构，其中，所述薄膜晶体管结构位于所述显示区域中。所述薄膜晶体管结构至少包括源漏极图案205和平坦图案204，所述源漏极图案205和平坦图案204位于所述薄膜晶体管结构远离所述衬底基板201的一侧。如图2所示，所述平坦图案204远离所述衬底基板201的表面与所述源漏极图案205远离所述衬底基板201的表面基本上位于同一平面中，所述平坦图案204具有第一开槽H1，所述源漏极图案205容置于所述第一开槽H1内。需要说明的是“基本上位于同一平面中”指的是两个膜层表面之间的段差不超过其中一个膜层厚度的20％，如不超过其中一个膜层厚度的15％，10％，5％等。本公开内容中可以是所述平坦图案204远离所述衬底基板201的表面与所述源漏极图案205远离所述衬底基板201的表面不超过所述平坦图案204厚度的20％，具体可以是不超过所述平坦图案204厚度的15％，10％，5％等；或者不超过所述源漏极图案205厚度的20％，具体可以是不超过所述平坦图案204厚度的15％，10％，5％等。
其中，源漏极图案205包括源极205a和漏极205b。
图3是本公开实施例提供的平坦图案的俯视结构示意图，如图3所示，平坦图案204具有容置源漏极图案205a、205b的第一开槽H1。
可选地，平坦图案的厚度与源漏极图案的厚度相等。平坦图案和源漏极图案的厚度范围为300至800纳米。
需要说明的是，源漏极图案的厚度指的是源漏极图案位于平坦图案的第一开槽中的部分的厚度，不包括源漏极图案位于通孔中的部分的厚度。
可选地，栅极图案的材料包括铝(Al)、钕(Nd)和钼(Mo)中的至少一种；源漏极图案的材料包括铝、钕和钼中的至少一种；平坦图案的材料包括聚酰亚胺(polyimide，PI)和亚克力(聚甲基丙烯酸甲酯(polymethyl methacrylate，PMMA))等有机材料。本公开实施例对各个膜层的材料不做限定。
本公开实施例中的薄膜晶体管结构可以是顶栅结构，也可以是底栅结构。当该薄膜晶体管结构为顶栅结构时，参见图2，该薄膜晶体管结构还包括依次设置在所述衬底基板201上的有源层图案206、钝化层207和栅极图案202，所述源漏极图案205经由穿过所述钝化层207的通孔与所述有源层图案206连接。图4是本公开实施例提供的另一种阵列基板的结构示意图，当该薄膜晶体管结构为底栅结构时，参见图4，该薄膜晶体管结构还包括依次设置在所述衬底基板201上的栅极图案202、层间绝缘层203和有源层图案206，所述源漏极图案205与所述有源层图案206连接。本公开以下实施例以薄膜晶体管结构为顶栅结构为例进行说明。
综上所述，本公开实施例提供的阵列基板，平坦图案远离衬底基板的表面与源漏极图案远离衬底基板的表面基本上在同一平面中，且平坦图案具有容置源漏极图案的第一开槽，即该源漏极图案能够容置于平坦图案的第一开槽内。因此，可以减轻由于源漏极图案的厚度较大导致阵列基板的平坦度较差的问题，提高了阵列基板的表面平整性。进一步的，可以提高位于阵列基板上的膜层的平整性，避免外界光线进入显示面板内部后，在膜层表面发生反射时出现某个方向上的集中反射现象。因此，可以改善色分离现象，提高产品信赖度。
可选地，衬底基板为柔性衬底基板，例如该衬底基板可以由聚对苯二甲酸(polyethylene terephthalate，PET)塑料薄膜或PI塑料薄膜制备得到。图5是本公开实施例提供的又一种阵列基板的结构示意图，如图5所示，非显示区域B包括弯折(Bending)区，该弯折区内具有 第二开槽H2，该第二开槽H2内设置有有机填充物M；所述阵列基板包括位于弯折区内的走线209(即位于非显示区域B内的走线209)，该走线209位于有机填充物M远离衬底基板201的一侧。
可选地，有机填充物的厚度范围为0.5至1.5微米。
需要说明的是，无机膜层(包括钝化层和层间绝缘层等)的刚性强度较大，弯折时易发生断裂。当弯折区内的走线形成在无机膜层上时，无机膜层断裂易导致走线断裂，影响显示面板的正常显示。目前，通常对弯折区内的无机膜层进行蚀刻处理形成开槽，并在开槽内设置有机填充物。由于有机填充物的柔韧性较好，弯折时发生断裂的可能性较低，因此可以减小走线断裂的风险，提高阵列基板的可靠性。
可选地，平坦图案与有机填充物由同一工艺形成。需要说明的是，通过同一工艺制备平坦图案与有机填充物，无需增加新的工艺步骤来制备平坦图案，即无需增加额外的工艺成本，可实现性高。可选地，平坦图案与有机填充物也可以通过不同工艺分别制备，本公开实施例对此不做限定。
可选地，衬底基板也可以为硬质衬底基板，例如该衬底基板可以由玻璃、硅片和石英等材料制备得到。本公开实施例对衬底基板的材质不做限定。
图6是本公开实施例提供的再一种阵列基板的结构示意图，如图6所示，该阵列基板20还包括平坦层208，平坦层208位于源漏极图案205远离衬底基板201的一侧。
需要说明的是，通过在源漏极图案远离衬底基板的一侧设置平坦层，可以进一步提高阵列基板的平坦度，进而提高后续制备的膜层的平坦度。
综上所述，本公开实施例提供的阵列基板，平坦图案远离衬底基板的表面与源漏极图案远离衬底基板的表面基本上在同一平面中，且平坦图案具有容置位于源漏极图案的第一开槽，即该源漏极图案能够容置于平坦图案的第一开槽内。因此，可以减轻由于源漏极图案的厚度较大导致阵列基板的平坦度较差的问题，提高了阵列基板的表面平整性。进一步的，可以提高位于阵列基板上的膜层的平整性，避免外界光线进入显示面板内部后，在膜层表面发生反射时出现某个方向上的集中反射现象。因此，可以改善色分离现象，提高产品信赖度。
本公开实施例提供了一种显示面板，该显示面板包括：如图2以及图4至图6任一所示的阵列基板20。
可选地，图7是本公开实施例提供的一种显示面板的结构示意图，如图7所示，该显示面板包括如图6所示的阵列基板20，该阵列基板20还包括平坦层208，平坦层208位于源漏极图案205远离衬底基板201的一侧。
参见图7，显示面板还包括位于平坦层208远离衬底基板201的一侧层叠设置的第一电极301、发光层302、第二电极303和滤光片40，第一电极和第二电极分别为阴极和阳极中的一极。其中，发光层包括沿远离第一电极的方向层叠设置的第一载流子注入层、第一载流子传输层、发光材料层、第二载流子传输层和第二载流子注入层，第一载流子和第二载流子分别为电子和空穴中的一种。当第一电极为阳极，第二电极为阴极时，第一载流子为空穴，第二载流子为电子；当第一电极为阴极，第二电极为阳极时，第一载流子为电子，第二载流子为空穴。
可选地，显示面板的显示区域内具有多个像素，当每个像素包括红色子像素、绿色子像素和蓝色子像素时，参见图7，滤光片40具有红色滤光区R、绿色滤光区G和蓝色滤光区B。一方面，滤光片能够对出射的光线进行过滤处理，提高出射光线的色纯度；另一方面，滤光片能够对外界光线起到过滤作用，可以减少进入显示面板内的环境光，进而减少显示面板对环境光的反射，提高用户体验。
需要说明的是，层叠设置的第一电极、发光层和第二电极组成的结构也可称为发光器件。在本公开实施例中，该发光器件可以是OLED器件或量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)器件等。
可选地，图8是本公开实施例提供的一种显示面板中的像素分布示意图，如图8所示，显示面板具有两组平行的对边，显示区域A内具有多个像素x，该多个像素x的排布方向与显示面板的任一边不平行。其中，每个像素x包括至少一种颜色的子像素。
需要说明的是，显示区域中的多个像素的排布方向与显示面板的任一边不平行，可以改善显示面板的色分离现象，提高显示面板的产品信赖性。
综上所述，本公开实施例提供的阵列基板，平坦图案远离衬底基板的表面与源漏极图案远离衬底基板的表面基本上在同一平面中，且平坦图案具有容置源漏极图案的第一开槽，即该源漏极图案能够容置于平坦图案的第一开槽内。因此，可以减轻由于源漏极图案的厚度较大导致阵列基板的平坦度较差的问题，提高了阵列基板的表面平整性。进一步的，可以提高位于阵列基板上的膜层的平整性，避免外界光线进入显示面板内部后，在膜层表面发生反射时出现某个方向上的集中反射现象。因此，可以改善色分离现象，提高产品信赖度。
本公开实施例提供了一种显示装置，包括：如图7所示的显示面板。
可选地，本公开实施例提供的显示装置可以为电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。
图9是本公开实施例提供的一种阵列基板的制造方法的流程图，该阵列基板具有显示区域和位于显示区域周围的非显示区域，如图9所示，该方法包括下列步骤：S501：提供衬底基板；S502：在所述衬底基板上形成薄膜晶体管结构，所述薄膜晶体管结构位于所述显示区域中，在所述衬底基板上形成薄膜晶体管结构至少包括：S503：在所述衬底基板上形成平坦图案，所述平坦图案具有第一开槽；S504：在所述第一开槽内形成源漏极图案，其中，所述平坦图案远离所述衬底基板的表面与所述源漏极图案远离所述衬底基板的表面基本上位于同一平面中。
可选地，采用如图9所示的阵列基板的制造方法，可以制备得到如图2或图4所示的阵列基板，该阵列基板的结构可以参考结构侧实施例，本公开实施例在此不做赘述。
综上所述，本公开实施例提供的阵列基板的制造方法，先在衬底基板上形成平坦图案，再在形成有平坦图案的衬底基板上形成源漏极图案。平坦图案远离衬底基板的表面与源漏极图案远离衬底基板的表面基本上在同一平面中，且平坦图案具有容置源漏极图案的第一开槽，即该源漏极图案能够容置于平坦图案的第一开槽内。因此，可以减轻由于源漏极图案的厚度较大导致阵列基板的平坦度较差的问题，提高了阵列基板的表面平整性。进一步的，可以提高位于阵列基板上的膜 层的平整性，避免外界光线进入显示面板内部后，在膜层表面发生反射时出现某个方向上的集中反射现象。因此，可以改善色分离现象，提高产品信赖度。
可选地，当阵列基板为顶栅结构，在S503执行之前，上述方法还包括：在衬底基板上依次形成有源层图案、钝化层、栅极图案和层间绝缘层。当阵列基板为底栅结构，在S503执行之前，上述方法还包括：在衬底基板上依次栅极图案、层间绝缘层和有源层。本公开以下实施例以阵列基板为顶栅结构为例，对阵列基板的制备过程进行说明，底栅结构的阵列基板的制造过程可参考顶栅结构的阵列基板的制造过程，本公开实施例在此不做赘述。
图10是本公开实施例提供的另一种阵列基板的制造方法流程图，该阵列基板具有显示区域和位于显示区域周围的非显示区域，如图10所示，该方法包括下列步骤。
S601：提供衬底基板。
可选地，衬底基板为柔性衬底基板，例如该衬底基板可以由PET塑料薄膜或PI塑料薄膜制备得到。或者，衬底基板也可以为硬质衬底基板，例如该衬底基板可以由玻璃、硅片和石英等材料制备得到。本公开实施例对衬底基板的材质不做限定。
S602：在衬底基板上形成有源层图案。
可选地，有源层图案的材料包括铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)、单晶硅(a-Si)、低温多晶硅(Low Temperature Poly-silicon，LTPS)或低温多晶氧化物(Low Temperature Polycrystalline Oxide，LTPO)中的至少一种。例如可以采用沉积的方式在衬底基板上形成有源层图案。
S603：在形成有有源层图案的衬底基板上形成钝化层。
可选地，钝化层的材料包括二氧化硅或氮化硅中的至少一种。
S604：在形成有钝化层的衬底基板上形成栅极图案。
可选地，栅极图案的材料包括铝、钕和钼中的至少一种。可以采用沉积的方式形成栅极层，再通过构图工艺形成栅极图案。在本公开实施例中，构图工艺包括：光刻胶涂覆、曝光、显影、刻蚀和光刻胶剥离。其中，栅极图案可以是两层结构，本公开实施例对此不做限定。
S605：在形成有栅极图案的衬底基板上形成层间绝缘层。
可选地，层间绝缘层的材料包括二氧化硅、氮化硅和氧化铝中的至少一种。例如可以采用沉积的方式在形成有栅极图案的衬底基板上形成层间绝缘层。
可选地，可以通过构图工艺在层间绝缘层和钝化层上形成过孔，该过孔用于连通有源层和源漏极图案。其中，层间绝缘层和钝化层上的过孔可以通过一次构图工艺制备得到，也可以分别通过构图工艺制备得到，本公开实施例对此不做限定。
S606：在层间绝缘层远离衬底基板的一侧形成平坦图案，该平坦图案具有第一开槽。
可选地，步骤S606的实现过程包括：在层间绝缘层远离衬底基板的一侧涂覆有机材料，从而在显示区域形成有机材料层，有机材料层的厚度大于或等于源漏极图案的厚度；对该有机材料层进行曝光显影处理，得到平坦图案。平坦图案的材料可以包括PI和亚克力等有机材料。
可选地，也可以在形成平坦图案之后再在层间绝缘层和钝化层上形成上述用于连通有源层和源漏极图案的过孔，本领域技术人员可以根据具体工艺进行选择，本申请对此不做限定。
可选地，当衬底基板为柔性衬底基板，非显示区域包括弯折区，在形成有所述层间绝缘层的衬底基板上涂覆有机材料之前，需要对弯折区内的无机膜层(包括钝化层和层间绝缘层等)进行蚀刻处理，形成第二开槽。
可选地，上述在层间绝缘层远离衬底基板的一侧涂覆有机材料还可以包括：在第二开槽内填充有机材料，以在第二开槽内形成有机填充物，也即是弯折区内的有机填充物与显示区域内的平坦图案由同一工艺形成。
需要说明的是，无机膜层的刚性强度较大，弯折时易发生断裂。当弯折区内的走线形成在无机膜层上时，无机膜层断裂易导致走线断裂，影响显示面板的正常显示。目前，通常对弯折区内的无机膜层进行蚀刻处理形成开槽，并在开槽内设置有机填充物。由于有机填充物的柔韧性较好，弯折时发生断裂的可能性较低，因此可以减小走线断裂的风险，提高阵列基板的可靠性。并且，通过同一工艺制备平坦图案与有机填充物，无需增加新的工艺步骤来制备平坦图案，即无需增 加额外的工艺成本，可实现性高。
可选地，平坦图案与有机填充物也可以分别制备得到，本公开实施例对此不做限定。
可选地，由于存在工艺误差，因此通常在形成平坦图案上的第一开槽时，在第一开槽中预留一定的误差尺寸，以提高源漏极图案与平坦图案的匹配性。也就是说，实际形成的平坦图案与源漏极图案之间可能存在一定的间隙。图2、4、5、6、7中未示出平坦图案与源漏极图案之间的间隙，但附图仅是示意性的，不代表对本公开的限定。
示例地，图11是本公开实施例提供的一种在层间绝缘层远离衬底基板的一侧形成平坦图案的工艺流程示意图(均为俯视图)，如图11所示，包括以下步骤：
S1：提供衬底基板，该衬底基板上形成有层间绝缘层203，且非显示区域内的弯折区内形成有第二开槽H2。
可选地，第二开槽的深度范围为0.5至1.5微米。
S2：在层间绝缘层远离衬底基板的一侧整层涂覆有机材料，在显示区域A内形成有机材料层L，并在第二开槽H2内形成有机填充物M。
可选地，由于第二开槽的深度范围为0.5至1.5微米，因此在第二开槽内形成的有机填充物的厚度范围为0.5至1.5微米，即有机材料层的厚度范围为0.5至1.5微米。
S3：对显示区域A内的有机材料层L进行曝光显影处理，得到平坦图案204。
可选地，源漏极图案的厚度范围一般为300至800纳米。当有机材料层的厚度大于源漏极图案的厚度时，在得到平坦图案之后，可以采用半色调掩模板对平坦图案进行曝光处理；对经过曝光处理后的平坦图案进行显影处理，使经过显影处理后的平坦图案的厚度等于源漏极图案的厚度。或者，可以采用灰化(ashing)工艺对平坦图案进行灰化处理，使经过灰化处理后的平坦图案的厚度等于源漏极图案的厚度。
需要说明的是，设置平坦图案的厚度与源漏极图案的厚度相等，可以在源漏极图案容置于平坦图案的第一开槽内后，使源漏极图案远离衬底基板的表面与平坦图案远离衬底基板的表面平齐(即位于同一平面内)，进一步提高阵列基板的平坦度。
S607：在形成有平坦图案的衬底基板上形成源漏极图案，平坦图 案远离衬底基板的表面与源漏极图案远离衬底基板基本上在同一平面中，源漏极图案容置于第一开槽内。
可选地，源漏极图案的材料包括铝、钕和钼中的至少一种，可以通过构图工艺在形成有平坦图案的衬底基板上形成源漏极图案。源漏极金属的制备温度一般在200～250℃，或者，可以采用其他低温工艺制备源漏极图案。
参考步骤S606，当衬底基板为柔性衬底基板时，阵列基板包括位于弯折区内的走线，与在第一开槽内形成所述源漏极图案同时，所述方法还可以包括：通过构图工艺在所述有机填充物远离所述衬底基板的一侧形成所述走线。
S608：在源漏极图案远离衬底基板的一侧形成平坦层。
可选地，通过沉积或涂覆工艺在源漏极图案远离衬底基板的一侧形成平坦层。需要说明的是，通过在源漏极图案远离衬底基板的一侧形成平坦层，可以进一步提高阵列基板的平坦度，进而提高后续膜层的制备可靠性。
可选地，采用如图10所示的阵列基板的制造方法，可以制备得到如图6所示的阵列基板，该阵列基板的结构可以参考结构侧实施例，本公开实施例在此不做赘述。
需要说明的是，本公开实施例提供的阵列基板的制造方法步骤的先后顺序可以进行适当调整，步骤也可以根据情况进行相应增减，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化的方法，都应涵盖在本公开的保护范围之内，因此不再赘述。
综上所述，本公开实施例提供的阵列基板的制造方法，先在衬底基板上形成平坦图案，再在形成有平坦图案的衬底基板上形成源漏极图案。平坦图案远离衬底基板的表面与源漏极图案远离衬底基板的表面基本上在同一平面中，且平坦图案具有容置源漏极图案的第一开槽，即该源漏极图案能够容置于平坦图案的第一开槽内。因此，可以减轻由于源漏极图案的厚度较大导致阵列基板的平坦度较差的问题，提高了阵列基板的表面平整性。进一步的，可以提高位于阵列基板上的膜层的平整性，避免外界光线进入显示面板内部后，在膜层表面发生反射时出现某个方向上的集中反射现象。因此，可以改善色分离现象，提高产品信赖度。
以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (16)

  1. 一种具有显示区域的阵列基板，包括：
    衬底基板，以及位于所述衬底基板的表面的薄膜晶体管结构，
    其中，所述薄膜晶体管结构位于所述显示区域中；所述薄膜晶体管结构至少包括源漏极图案和平坦图案，所述源漏极图案和平坦图案位于所述薄膜晶体管结构远离所述衬底基板的一侧；
    其中，所述平坦图案远离所述衬底基板的表面与所述源漏极图案远离所述衬底基板的表面基本上位于同一平面中，所述平坦图案具有第一开槽，所述源漏极图案容置于所述第一开槽内。
  2. 根据权利要求1所述的阵列基板，还包括：与所述显示区域相邻的非显示区域；
    其中，所述衬底基板为柔性衬底基板，所述非显示区域包括弯折区，所述弯折区内具有第二开槽，所述第二开槽内设置有有机填充物；并且
    所述阵列基板包括位于非显示区域的走线，所述走线位于所述有机填充物远离所述衬底基板的一侧。
  3. 根据权利要求2所述的阵列基板，其中，
    所述平坦图案与所述有机填充物由同一工艺形成。
  4. 根据权利要求1所述的阵列基板，还包括平坦层，所述平坦层位于所述源漏极图案远离所述衬底基板的一侧。
  5. 根据权利要求1至4任一所述的阵列基板，其中，所述薄膜晶体管结构还包括依次设置在所述衬底基板上的有源层图案、钝化层和栅极图案，所述源漏极图案经由穿过所述钝化层的通孔与所述有源层图案连接。
  6. 根据权利要求1至4任一所述的阵列基板，其中，所述薄膜晶体管结构还包括依次设置在所述衬底基板上的栅极图案、层间绝缘层和有源层图案，所述源漏极图案与所述有源层图案连接。
  7. 一种显示面板，包括如权利要求1至6任一所述的阵列基板。
  8. 根据权利要求7所述的显示面板，还包括位于所述平坦图案远离所述衬底基板的一侧层叠设置的第一电极、发光层、第二电极和滤光片，所述第一电极和所述第二电极分别为阴极和阳极中的一极。
  9. 根据权利要求7或8所述的显示面板，其中，所述显示面板具有两组平行的对边，所述显示区域内具有多个像素，所述多个像素的排布方向与所述显示面板的任一边不平行。
  10. 一种显示装置，包括如权利要求7至9任一所述的显示面板。
  11. 一种阵列基板的制造方法，所述阵列基板具有显示区域，所述方法包括：
    提供衬底基板；
    在所述衬底基板上形成薄膜晶体管结构，所述薄膜晶体管结构位于所述显示区域中，
    在所述衬底基板上形成薄膜晶体管结构至少包括：
    在所述衬底基板上形成平坦图案，所述平坦图案具有第一开槽；
    在所述第一开槽内形成源漏极图案，
    其中，所述平坦图案远离所述衬底基板的表面与所述源漏极图案远离所述衬底基板的表面基本上位于同一平面中。
  12. 根据权利要求11所述的方法，其中，在所述衬底基板上形成平坦图案包括：
    在所述衬底基板上涂覆有机材料，从而在显示区域形成有机材料层，所述有机材料层的厚度大于或等于所述源漏极图案的厚度；
    对位于所述显示区域内的有机材料层进行曝光显影处理，得到所述平坦图案。
  13. 根据权利要求12所述的方法，其中，所述衬底基板为柔性衬底基板，所述非显示区域包括弯折区，在所述衬底基板上涂覆有机材料之前，所述方法还包括：
    对所述弯折区内的无机膜层进行蚀刻处理，形成第二开槽；
    在所述衬底基板上涂覆有机材料还包括：
    在所述第二开槽内填充所述有机材料，以在所述第二开槽内形成有机填充物。
  14. 根据权利要求13所述的方法，其中，所述阵列基板包括位于所述弯折区内的走线，与在第一开槽内形成所述源漏极图案同时，所述方法还可以包括：
    通过构图工艺在所述有机填充物远离所述衬底基板的一侧形成所述走线。
  15. 根据权利要求12所述的方法，其中，所述有机材料层的厚度大于所述源漏极图案的厚度；在得到所述平坦图案之后，所述方法还包括：
    采用半色调掩模板对所述平坦图案进行曝光处理；
    对经过所述曝光处理后的平坦图案进行显影处理，使经过所述显影处理后的平坦图案的厚度等于所述源漏极图案的厚度。
  16. 根据权利要求12所述的方法，其中，所述有机材料层的厚度大于所述源漏极图案的厚度，在得到所述平坦图案之后，所述方法还包括：
    采用灰化工艺对所述平坦图案进行灰化处理，使经过所述灰化处理后的平坦图案的厚度等于所述源漏极图案的厚度。
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