WO2020143433A1 - 阵列基板、其制备方法及相关装置 - Google Patents

阵列基板、其制备方法及相关装置 Download PDF

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Publication number
WO2020143433A1
WO2020143433A1 PCT/CN2019/127229 CN2019127229W WO2020143433A1 WO 2020143433 A1 WO2020143433 A1 WO 2020143433A1 CN 2019127229 W CN2019127229 W CN 2019127229W WO 2020143433 A1 WO2020143433 A1 WO 2020143433A1
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Prior art keywords
storage capacitor
photosensitive
pixel
electrode
optical compensation
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PCT/CN2019/127229
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English (en)
French (fr)
Inventor
王国英
宋振
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京东方科技集团股份有限公司
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Priority to US16/767,377 priority Critical patent/US11271049B2/en
Publication of WO2020143433A1 publication Critical patent/WO2020143433A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to an array substrate, a preparation method thereof, and related devices.
  • OLED display devices are widely used due to their own characteristics.
  • OLED display screen brightness and uniformity compensation are mainly based on electrical compensation, including internal compensation and external compensation, or a combination of two compensation schemes.
  • electrical compensation can only compensate for the display Mura due to changes in the threshold voltage and mobility of the driving TFT, and cannot compensate for the problem of uneven display due to changes in the luminous efficiency of the OLED device itself.
  • the current optical compensation scheme is to perform an optical compensation on the entire panel when the panel leaves the factory, but it cannot solve the Mura caused by the EL efficiency attenuation, that is, it cannot achieve real-time compensation similar to electrical compensation.
  • the pixel storage capacitor of the pixel driving TFT occupies most of the layout design area, making the pixel aperture ratio lower.
  • An embodiment of the present disclosure provides an array substrate including a plurality of sub-pixel regions, each of the sub-pixel regions includes a pixel driving circuit and an optical compensation circuit on a base substrate, the pixel driving circuit includes a coupling with a driving transistor A pixel storage capacitor, the optical compensation circuit includes a photosensitive storage capacitor coupled to a photosensitive device; the pixel storage capacitor and the photosensitive storage capacitor are stacked, and the pixel storage capacitor and the photosensitive storage capacitor share the same electrode board.
  • the photosensitive device in the optical compensation circuit is located between the photosensitive storage capacitor and the base substrate; the pixel storage capacitor Located on the side of the photosensitive storage capacitor facing away from the base substrate;
  • a light-shielding metal layer is provided between the photosensitive device and the base substrate, and an orthographic projection of the light-shielding metal layer on the base substrate covers an orthographic projection of the photosensitive device on the base substrate.
  • the photosensitive storage capacitor includes a first electrode, an insulating dielectric layer, and a second electrode that are sequentially stacked on the photosensitive device
  • the pixel storage capacitor includes the second electrode, the insulating buffer layer, and the third electrode that are sequentially stacked.
  • the optical compensation circuit further includes an optical compensation control transistor on the insulating buffer layer; a source of the optical compensation control transistor Or the drain is electrically coupled to the light-shielding metal layer and electrically coupled to the second electrode.
  • the optical compensation control transistor is a top-gate transistor; the orthographic projection of the light-shielding metal layer on the base substrate covers the location The orthographic projection of the active layer of the optical compensation control transistor on the base substrate.
  • the third electrode and the active layer of the optical compensation control transistor are disposed in the same layer.
  • the pixel driving circuit further includes a driving thin film transistor, and a gate of the driving thin film transistor is electrically coupled to the third electrode.
  • the embodiment of the present disclosure also provides a bottom emission type OLED display panel, including the above-mentioned array substrate provided by the embodiment of the present disclosure.
  • an embodiment of the present disclosure also provides a display device, including the above-mentioned bottom emission type OLED display panel provided by the embodiment of the present disclosure.
  • the embodiments of the present disclosure also provide a method for preparing an array substrate, including:
  • the photosensitive storage capacitor includes a first electrode, an insulating dielectric layer, and a second electrode that are sequentially stacked;
  • the gate and the source and drain of the optical compensation control transistor are formed in this order.
  • FIG. 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of the array substrate shown in FIG. 1;
  • FIG. 3 is a schematic structural diagram of a photosensitive device provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of an equivalent circuit of a photosensitive device, a photosensitive storage capacitor, and an optical compensation control transistor provided by an embodiment of the present disclosure
  • FIG. 5 is a schematic flowchart of a method for preparing an array substrate provided by an embodiment of the present disclosure
  • 6A to 6F are schematic structural views of the array substrate shown in FIG. 1 after performing each step;
  • FIG. 7 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • An array substrate provided by an embodiment of the present disclosure includes a plurality of sub-pixel regions, and each sub-pixel region includes a pixel driving circuit (not shown in FIG. 1) and an optical compensation circuit on a base substrate 1 2.
  • the pixel driving circuit includes a pixel storage capacitor 20 coupled to a driving transistor (not shown in FIG. 1), and the optical compensation circuit 2 includes a photosensitive device. 21 is coupled to the photosensitive storage capacitor 22; the pixel storage capacitor 20 and the photosensitive storage capacitor 22 are stacked, and the pixel storage capacitor 20 and the photosensitive storage capacitor 22 share the same electrode plate.
  • An array substrate provided by an embodiment of the present disclosure includes a plurality of sub-pixel regions, and each sub-pixel region includes a pixel driving circuit and an optical compensation circuit on a base substrate, the pixel driving circuit includes a pixel storage capacitor coupled to a driving transistor, and an optical compensation circuit It includes a photosensitive storage capacitor coupled to the photosensitive device; a pixel storage capacitor and a photosensitive storage capacitor are stacked, and the pixel storage capacitor and the photosensitive storage capacitor share the same electrode plate.
  • the photosensitive device, the photosensitive storage capacitor, and the pixel storage capacitor are sequentially stacked in a direction away from the base substrate, that is, the front projection of the photosensitive device, the photosensitive storage capacitor, and the pixel storage capacitor on the base substrate have overlap Area, the area occupied by the pixel storage capacitor in the sub-pixel area is reduced, and accordingly the area of the light-emitting area can be increased, thereby increasing the aperture ratio of the sub-pixel area.
  • the photosensitive device 21 in the optical compensation circuit 2 is located between the photosensitive storage capacitor 22 and the base substrate 1; pixels The storage capacitor 20 is located on the side of the photosensitive storage capacitor 22 facing away from the base substrate 1;
  • a light-shielding metal layer 3 is provided between the photosensitive device 21 and the base substrate 1.
  • the orthographic projection of the light-shielding metal layer 3 on the base substrate 1 covers the orthographic projection of the photosensitive device 21 on the base substrate 1.
  • the photosensitive device 21 is prepared on the light-shielding metal layer 3, and the light-shielding metal layer 3 can play a certain protective role on the photosensitive device 21 to prevent the ambient light emitted from the non-sub-pixel area from affecting the photosensitive device 21.
  • the photosensitive accuracy of the photosensitive device 21 is improved, thereby improving the light compensation accuracy.
  • the material of the light-shielding metal layer may be common metal materials such as Mo, Al, Ti, Au, Cu, Hf, Ta, or alloy materials such as AlNd and MoNb.
  • the photosensitive storage capacitor 22 includes a first electrode 01 and an insulating medium that are sequentially stacked on the photosensitive device 21 Layer 02 and second electrode 03;
  • the pixel storage capacitor 20 includes a second electrode 03, an insulating buffer layer 04 and a third electrode 05 which are sequentially stacked.
  • the materials of the first electrode 01, the second electrode 03, and the third electrode 05 are all transparent conductive materials.
  • the materials of the first electrode 01, the second electrode 03, and the third electrode 05 may all be indium tin oxide (ITO) or indium-doped zinc oxide (IZO).
  • the material of the insulating dielectric layer may be silicon oxide, silicon nitride, silicon oxynitride, or other insulating materials.
  • the material of the insulating buffer layer may be an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or the like.
  • the photosensitive device 21 may include an N-type semiconductor layer 001 stacked on the side facing away from the base substrate 1 and the present invention. ⁇ Semiconductor layer 002 and P-type semiconductor layer 003.
  • the N-type semiconductor layer 001 is electrically coupled to the drain of the optical compensation control transistor 23, the P-type semiconductor layer 003 is electrically coupled to the first electrode 01, and the first electrode 01 is connected to the signal line 11.
  • the equivalent circuit diagrams of the photosensitive device 21, the photosensitive storage capacitor 22, and the optical compensation control transistor 23 are shown in FIG.
  • the N-type semiconductor layer may be a semiconductor doped with phosphorus or arsenic
  • the P-type semiconductor layer may be a boron-doped semiconductor.
  • the above-mentioned array substrate provided by an embodiment of the present disclosure, as shown in FIG. 1, it further includes a signal line 11 electrically coupled to the first electrode 01.
  • the signal line 11 passes through the insulating buffer layer 04 and the interlayer
  • the via hole of the dielectric layer 4 is electrically coupled to the first electrode 01, and the signal line 11 may provide a low voltage, for example, the provided low voltage may be -5V.
  • the optical compensation circuit 2 further includes an optical compensation control transistor 23 located on the insulating buffer layer 04; an optical compensation control transistor The source electrode 06 or the drain electrode 23 of 23 is electrically coupled to the light-shielding metal layer 3 and electrically coupled to the second electrode 03.
  • the embodiments of the present disclosure are all described by taking the example of the electrical coupling of the drain 07 of the optical compensation control transistor 23 and the light-shielding metal layer 3 as an example.
  • the drain electrode 07 and the second electrode electrode 03 are electrically coupled through the first coupling portion 12 filled in the via penetrating the insulating buffer layer 04 and the interlayer dielectric layer 4.
  • the optical compensation control transistor 23 is a top-gate transistor; the light-shielding metal layer 3 is on the base substrate 1
  • the projection covers the orthographic projection of the active layer 08 of the optical compensation control transistor 23 on the base substrate 1.
  • the light-shielding metal layer 3 can block light from irradiating to the active layer 08 of the optical compensation control transistor 23, which can play a certain protective role on the active layer 08 of the optical compensation control transistor 23 and prevent light from affecting the optical compensation control transistor 23
  • the source layer 08 has an influence, so that the stability of the optical compensation control transistor 23 can be improved.
  • the material of the active layer 08 may include various materials such as a-IGZO, ZnON, IZTO, a-Si, p-Si, hexathiophene, polythiophene, and the like.
  • the third electrode 05 is provided in the same layer as the active layer 08 of the optical compensation control transistor 23 .
  • the material of the third electrode 05 may be a metal oxide material, such as IGZO material.
  • the pixel driving circuit further includes a driving thin film transistor (not shown in FIG. 1) and a gate of the driving thin film transistor
  • the second coupling portion 13 filled in the via hole penetrating the interlayer dielectric layer 4 is electrically coupled to the third electrode 05.
  • the photosensitive device 21 is prepared on the light-shielding metal layer 3, and the light-shielding metal layer 3 can play a certain protective role on the photosensitive device 21 to avoid ambient light on the photosensitive device 21 causes an impact, which can improve the photosensitive accuracy of the photosensitive device 21, thereby improving the optical compensation accuracy, and then prepare the photosensitive storage capacitor 22 on the photosensitive device 21, the insulating buffer layer 04 on the photosensitive storage capacitor 22, and the insulating buffer layer 04 An optical compensation control transistor 23, a third electrode 05, and a signal line 11 are prepared.
  • the drain 07 of the optical compensation control transistor 23 is electrically coupled to the light-shielding metal layer 3, because the photosensitive device 21 is disposed on the light-shielding metal layer 3, that is, optical compensation control
  • the drain 07 of the transistor 23 is electrically coupled to the photosensitive device 21, and the N-type semiconductor layer of the photosensitive device 21 is formed on the light-shielding metal layer 3, and the light-shielding metal layer 3 is connected to the drain 07 of the optical compensation control transistor 23 to shield the metal
  • the layer 3 may be connected to the optical compensation control transistor 23 as the N terminal electrode of the photosensitive device 21.
  • the P-type semiconductor layer of the photosensitive device 21 is the P terminal electrode of the photosensitive device 21 and is coupled to the signal line 11.
  • FIG. 2 is a schematic top view of the array substrate shown in FIG. 1. It can be seen that since the photosensitive storage capacitor 22 and the pixel storage capacitor 20 are stacked, the area occupied by the pixel storage capacitor 20 can be reduced. Thereby increasing the aperture ratio of the pixel.
  • the above array substrate provided by the embodiments of the present disclosure is provided with an optical compensation circuit in each sub-pixel area.
  • the optical compensation circuit includes an optical compensation control transistor, a photosensitive storage capacitor and a photosensitive device.
  • the overall structure of the photosensitive storage capacitor and the photosensitive device is called It is an optical detection device, which is electrically coupled to the source or drain in the optical compensation control transistor.
  • the optical detection device can detect the brightness of the light emitted from the sub-pixel area, and the detection result of the light brightness is compensated optically
  • the output of the transistor is controlled, and then the brightness of the sub-pixel area can be compensated according to the detection result of the light brightness.
  • the optical compensation control transistor is prepared after the insulating buffer layer is formed on the photosensitive storage capacitor, the photosensitive device and the photosensitive storage capacitor are protected by an insulating buffer layer, and the etching process in the subsequent preparation of the optical compensation control transistor will not affect the photosensitive
  • the side walls of the device cause damage, and because the insulating buffer layer isolates the photosensitive device from the optical compensation control transistor, when the optical compensation control transistor is prepared, the influence of hydrogen introduced during the preparation of the photosensitive device on the optical compensation control transistor can be avoided. Improve the reliability of the array substrate.
  • the optical compensation control transistor 23 further includes a gate insulating layer 10 and a gate 09.
  • the material can be insulating materials such as silicon oxide, silicon nitride, silicon oxynitride; the material of the gate 09 can be common metal materials such as Mo, Al, Ti, Au, Cu, Hf, Ta, or MoNd/Cu/MoNd Alloy materials.
  • the above-mentioned array substrate provided by an embodiment of the present disclosure further includes a passivation layer 5, a planarization 6, an anode layer 7, and a pixel defining layer 8.
  • a passivation layer 5 for a planarization of a planarization of a planarization of a planarization of a planarization of a planarization of a planarization of a planarization of a planarization of a planarization 6, an anode layer 7, and a pixel defining layer 8.
  • These membrane layers have the same functions and structures as in the prior art, and will not be described in detail here.
  • an embodiment of the present disclosure also provides a method for manufacturing an array substrate, as shown in FIG. 5, including:
  • the photosensitive storage capacitor includes a first electrode, an insulating dielectric layer, and a second electrode that are sequentially stacked;
  • an active layer and a third electrode of the optical compensation control transistor are simultaneously formed on the insulating buffer layer; the second electrode, the insulating buffer layer and the third electrode constitute a pixel storage capacitor;
  • the present disclosure is to sequentially arrange the photosensitive device, the photosensitive storage capacitor and the pixel storage capacitor in a direction away from the base substrate, that is, the photosensitive device, the photosensitive storage capacitor and the pixel storage
  • the orthographic projection of the three capacitors on the base substrate has an overlapping area, which reduces the occupied area of the pixel storage capacitor in the sub-pixel area, and accordingly can increase the area of the light-emitting area, thereby improving the aperture ratio of the sub-pixel area;
  • the photosensitive device and the photosensitive storage capacitor are prepared before the compensation control transistor, and an insulating buffer layer is formed on the photosensitive storage capacitor.
  • the etching process during the subsequent preparation of the optical compensation control transistor will not cause damage to the sidewall of the photosensitive device, and due to the insulation
  • the buffer layer isolates the photosensitive device from the optical compensation control transistor.
  • the preparation method of the array substrate shown in FIG. 1 provided by an embodiment of the present disclosure is described in detail below through specific examples. As shown in FIGS. 6A to 6F, the preparation method specifically includes the following steps:
  • a light-shielding metal layer 3 is formed on the base substrate 1, as shown in FIG. 6A;
  • a photosensitive device 21 is formed on the light-shielding metal layer 3, and the orthographic projection of the light-shielding metal layer 3 on the base substrate 1 covers the orthographic projection of the photosensitive device 21 on the base substrate 1, as shown in FIG. 6B;
  • a photosensitive storage capacitor 22 is formed on the photosensitive device 21; the photosensitive storage capacitor 22 includes a first electrode 01, an insulating dielectric layer 02, and a second electrode 03 that are sequentially stacked, as shown in FIG. 6C;
  • An insulating buffer layer 04 is formed on the photosensitive storage capacitor 22, as shown in FIG. 6D;
  • the active layer 08 and the third electrode 05 of the optical compensation control transistor 23 are simultaneously formed on the insulating buffer layer 04; the second electrode 03, the insulating buffer layer 04 and the third electrode 05 constitute the pixel storage capacitor 20, as shown in FIG. 6E Shown
  • the gate 09, the source 06, the drain 07 of the optical compensation control transistor 23, the first coupling portion 12 in the via hole penetrating the insulating buffer layer 04 and the interlayer dielectric layer 4, and the penetrating interlayer dielectric are formed in this order
  • the second coupling portion 13 and the signal line 11 in the via of the layer 4, the drain 07 are electrically coupled with the light-shielding metal layer 3, the first coupling portion 12, the second coupling portion 13 and the gate of the driving transistor
  • the signal line 11 is electrically coupled to the first electrode 01 through a via penetrating the interlayer dielectric layer 4 and the insulating buffer layer 04, as shown in FIG. 6F;
  • the passivation layer 5, the planarization layer 6, the anode layer 7, and the pixel defining layer 8 are sequentially formed, as shown in FIG.
  • step (7) further includes preparing a driving circuit, a color filter layer, an organic light emitting layer and a cathode, the anode layer is coupled to the driving circuit, and the driving circuit drives the organic light emitting layer to emit light toward the side of the base substrate.
  • a driving circuit preparing a driving circuit, a color filter layer, an organic light emitting layer and a cathode
  • the anode layer is coupled to the driving circuit
  • the driving circuit drives the organic light emitting layer to emit light toward the side of the base substrate.
  • the patterning process may only include a photolithography process, or may include a photolithography process and an etching step, and may also include printing, inkjet, etc.
  • the process of forming a predetermined pattern; the photolithography process refers to the process of forming a pattern using photoresist, mask, exposure machine, etc., including film forming, exposure, development and other processes.
  • the corresponding patterning process can be selected according to the structure formed in the present disclosure.
  • an embodiment of the present disclosure also provides a bottom emission type OLED display panel, including the above-mentioned array base provided by the embodiment of the present disclosure, the array substrate is a back plate of the bottom emission type OLED display panel, and further includes The cover corresponds to a cover plate provided, and the cover plate may be a glass cover plate.
  • an embodiment of the present disclosure also provides a display device, including the bottom emission type OLED display panel in the above embodiments. Since the principle of the display device to solve the problem is similar to that of the aforementioned array substrate, the implementation of the display device can refer to the implementation of the aforementioned array substrate, and the repetition is not repeated here.
  • the above-mentioned display device provided by the embodiment of the present disclosure may be a full-screen display device, or may also be a flexible display device, etc., which is not limited herein.
  • the above display device provided by an embodiment of the present disclosure may be a full-screen mobile phone as shown in FIG. 7.
  • the above display device provided by the embodiments of the present disclosure may also be any product or component with a display function such as a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the other indispensable components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should it be used as a limitation to the present disclosure.
  • the array substrate includes a plurality of sub-pixel regions, and each sub-pixel region includes a pixel driving circuit and an optical compensation circuit on the base substrate.
  • the pixel driving circuit includes For the pixel storage capacitor coupled with the transistor, the optical compensation circuit includes a photosensitive storage capacitor coupled to the photosensitive device; the pixel storage capacitor and the photosensitive storage capacitor are stacked, and the pixel storage capacitor and the photosensitive storage capacitor share the same electrode plate.
  • the photosensitive device, the photosensitive storage capacitor, and the pixel storage capacitor are sequentially stacked in a direction away from the base substrate, that is, the front projection of the photosensitive device, the photosensitive storage capacitor, and the pixel storage capacitor on the base substrate have overlap Area, the area occupied by the pixel storage capacitor in the sub-pixel area is reduced, and accordingly the area of the light-emitting area can be increased, thereby increasing the aperture ratio of the sub-pixel area.

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Abstract

一种阵列基板、其制备方法及相关装置，该阵列基板包括多个子像素区域，各子像素区域包括位于衬底基板（1）上的像素驱动电路和光学补偿电路（2），像素驱动电路包括与驱动晶体管耦接的像素存储电容（20），光学补偿电路（2）包括与感光器件（21）耦接的感光存储电容（22）；像素存储电容（20）和感光存储电容（22）叠层设置，且像素存储电容（20）和感光存储电容（22）共用同一电极板。通过将感光器件（21）、感光存储电容（22）和像素存储电容（20）沿背离衬底基板（1）的方向上依次叠层设置，即感光器件（21）、感光存储电容（22）和像素存储电容（20）三者在衬底基板（1）上的正投影具有重叠区域，减小了子像素区域像素存储电容（20）的占用面积，相应地可以增加发光区的面积，从而提高子像素区域的开口率。

Description

阵列基板、其制备方法及相关装置
相关申请的交叉引用
本公开要求在2019年01月08日提交中国专利局、申请号为201910014900.4、申请名称为“一种阵列基板、其制备方法及相关装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，特别是涉及一种阵列基板、其制备方法及相关装置。
背景技术
OLED显示器件由于自身的特性，被广泛应用，目前OLED的显示画面亮度及均匀性补偿主要以电学补偿为主，包括内部补偿和外部补偿两种方式，也可以采用两种补偿方案相结合的方式，但是电学补偿只能对由于驱动TFT阈值电压和迁移率变化造成的显示Mura进行补偿，无法补偿由于OLED器件本身发光效率变化造成的显示不均的问题。现行的光学补偿方案是在panel出厂时对panel整体进行一次光学补偿，但无法解决伴随EL效率衰减造成的Mura，即无法实现与电学补偿类似的实时补偿。除此之外像素驱动TFT的像素存储电容占用版图设计的大部分面积，使得像素开口率较低。
发明内容
本公开实施例提供了一种阵列基板，包括多个子像素区域，各所述子像素区域包括位于衬底基板上的像素驱动电路和光学补偿电路，所述像素驱动电路包括与驱动晶体管耦接的像素存储电容，所述光学补偿电路包括与感光器件耦接的感光存储电容；所述像素存储电容和所述感光存储电容叠层设置，且所述像素存储电容和所述感光存储电容共用同一电极板。
可选地，在具体实施时，在本公开实施例提供的上述阵列基板中，所述光学补偿电路中的感光器件位于所述感光存储电容与所述衬底基板之间；所述像素存储电容位于所述感光存储电容背离所述衬底基板的一侧；
在所述感光器件与所述衬底基板之间具有遮光金属层，所述遮光金属层在所述衬底基板上的正投影覆盖所述感光器件在所述衬底基板上的正投影。
可选地，在具体实施时，在本公开实施例提供的上述阵列基板中，所述感光存储电容包括位于所述感光器件之上依次叠层设置的第一电极、绝缘介质层、第二电极；所述像素存储电容包括依次叠层设置的所述第二电极、绝缘缓冲层和第三电极。
可选地，在具体实施时，在本公开实施例提供的上述阵列基板中，所述光学补偿电路还包括位于所述绝缘缓冲层上的光学补偿控制晶体管；所述光学补偿控制晶体管的源极或漏极与所述遮光金属层电耦接、且与所述第二电极电耦接。
可选地，在具体实施时，在本公开实施例提供的上述阵列基板中，所述光学补偿控制晶体管为顶栅型晶体管；所述遮光金属层在所述衬底基板上的正投影覆盖所述光学补偿控制晶体管的有源层在所述衬底基板上的正投影。
可选地，在具体实施时，在本公开实施例提供的上述阵列基板中，所述第三电极与所述光学补偿控制晶体管的有源层同层设置。
可选地，在具体实施时，在本公开实施例提供的上述阵列基板中，所述像素驱动电路还包括驱动薄膜晶体管，所述驱动薄膜晶体管的栅极与所述第三电极电耦接。
相应地，本公开实施例还提供了一种底发射型OLED显示面板，包括本公开实施例提供的上述阵列基板。
相应地，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述底发射型OLED显示面板。
相应地，本公开实施例还提供了一种阵列基板的制备方法，包括：
在衬底基板上形成遮光金属层；
在所述遮光金属层上形成感光器件；
在所述感光器件上形成感光存储电容；所述感光存储电容包括依次叠层设置的第一电极、绝缘介质层、第二电极；
在所述感光存储电容上形成绝缘缓冲层；
在所述绝缘缓冲层上同时形成光学补偿控制晶体管的有源层和第三电极；所述第二电极、所述绝缘缓冲层和所述第三电极构成像素存储电容；
依次形成所述光学补偿控制晶体管的栅极和源漏极。
附图说明
图1为本公开实施例提供的阵列基板的结构示意图；
图2为图1所示的阵列基板的结构示意图；
图3为本公开实施例提供的感光器件的结构示意图；
图4为本公开实施例提供的感光器件、感光存储电容和光学补偿控制晶体管的等效电路示意图；
图5为本公开实施例提供的阵列基板的制备方法的流程示意图；
图6A至图6F分别为图1所示的阵列基板在执行各步骤后的结构示意图；
图7为本公开实施例提供的显示装置的结构示意图。
具体实施方式
为了使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开作进一步地详细描述，显然，所描述的实施例仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本公开保护的范围。
附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
本公开实施例提供的一种阵列基板，如图1所示，包括多个子像素区域，各子像素区域包括位于衬底基板1上的像素驱动电路(图1中未示出)和光 学补偿电路2，本公开的图1中以其中一个子像素区域为例进行说明，像素驱动电路包括与驱动晶体管(图1中未示出)耦接的像素存储电容20，光学补偿电路2包括与感光器件21耦接的感光存储电容22；像素存储电容20和感光存储电容22叠层设置，且像素存储电容20和感光存储电容22共用同一电极板。
本公开实施例提供的阵列基板包括多个子像素区域，各子像素区域包括位于衬底基板上的像素驱动电路和光学补偿电路，像素驱动电路包括与驱动晶体管耦接的像素存储电容，光学补偿电路包括与感光器件耦接的感光存储电容；像素存储电容和感光存储电容叠层设置，且像素存储电容和感光存储电容共用同一电极板。本公开通过将感光器件、感光存储电容和像素存储电容沿背离衬底基板的方向上依次叠层设置，即感光器件、感光存储电容和像素存储电容三者在衬底基板上的正投影具有重叠区域，减小了子像素区域像素存储电容的占用面积，相应地可以增加发光区的面积，从而提高子像素区域的开口率。
可选地，在具体实施时，在本公开实施例提供的上述阵列基板中，如图1所示，光学补偿电路2中的感光器件21位于感光存储电容22与衬底基板1之间；像素存储电容20位于感光存储电容22背离衬底基板1的一侧；
在感光器件21与衬底基板1之间具有遮光金属层3，遮光金属层3在衬底基板1上的正投影覆盖感光器件21在衬底基板1上的正投影。本公开实施例通过将感光器件21制备在遮光金属层3上，遮光金属层3可以对感光器件21起到一定的保护作用，避免非子像素区域发出的环境光对感光器件21造成影响，可以提高感光器件21的感光准确度，进而提高光补偿精度。
在本公开实施例提供的上述阵列基板中，遮光金属层的材料可以为Mo、Al、Ti、Au、Cu、Hf、Ta等常用金属材料，也可以为AlNd、MoNb等合金材料。
可选地，在具体实施时，在本公开实施例提供的上述阵列基板中，如图1所示，感光存储电容22包括位于感光器件21之上依次叠层设置的第一电极 01、绝缘介质层02、第二电极03；像素存储电容20包括依次叠层设置的第二电极03、绝缘缓冲层04和第三电极05。
在本公开实施例提供的上述阵列基板中，如图1所示，由于感光器件21是用于亮度检测的，为了避免第一电极01、第二电极03和第三电极05影响感光器件21进行亮度检测的准确性，第一电极01、第二电极03和第三电极05的材料均为透明导电材料。例如，第一电极01、第二电极03和第三电极05的材料均可以为氧化铟锡(ITO)或掺铟氧化锌(IZO)等。
可选地，绝缘介质层的材料可以为氧化硅、氮化硅、氮氧化硅等绝缘材料。
可选地，绝缘缓冲层的材料可以为氧化硅、氮化硅、氮氧化硅等绝缘材料。
可选地，在具体实施时，在本公开实施例提供的上述阵列基板中，如图3所示，感光器件21可以包括背离衬底基板1一侧叠层设置的N型半导体层001、本征半导体层002和P型半导体层003。N型半导体层001与光学补偿控制晶体管23的漏极电耦接，P型半导体层003与第一电极01电耦接，第一电极01与信号线11相连。感光器件21、感光存储电容22和光学补偿控制晶体管23的等效电路图如图4所示。具体地，N型半导体层可以磷或砷掺杂半导体，P型半导体层可以为硼掺杂半导体。
在具体实施时，在本公开实施例提供的上述阵列基板中，如图1所示，还包括与第一电极01电耦接的信号线11，信号线11通过贯穿绝缘缓冲层04和层间介质层4的过孔与第一电极01电耦接，信号线11可以提供低电压，例如提供的低电压可以是-5V。
可选地，在具体实施时，在本公开实施例提供的上述阵列基板中，如图1所示，光学补偿电路2还包括位于绝缘缓冲层04上的光学补偿控制晶体管23；光学补偿控制晶体管23的源极06或漏极07与遮光金属层3电耦接、且与第二电极电03耦接。需要说明的是，本公开实施例均是以光学补偿控制晶体管23的漏极07与遮光金属层3电耦接为例进行示意性说明的。具体地，漏极 07与第二电极电03通过填充在贯穿绝缘缓冲层04和层间介质层4的过孔内的第一耦接部12电耦接。
可选地，在具体实施时，在本公开实施例提供的上述阵列基板中，如图1所示，光学补偿控制晶体管23为顶栅型晶体管；遮光金属层3在衬底基板1上的正投影覆盖光学补偿控制晶体管23的有源层08在衬底基板1上的正投影。遮光金属层3可以遮挡光照射到光学补偿控制晶体管23的有源层08，这样可以对光学补偿控制晶体管23的有源层08起到一定的保护作用，避免光线对光学补偿控制晶体管23的有源层08造成影响，从而可以提高光学补偿控制晶体管23的稳定性。
可选地，有源层08的材料可以包括a-IGZO，ZnON，IZTO，a-Si，p-Si，六噻吩，聚噻吩等各种材料。
可选地，在具体实施时，为了减少制作工艺，在本公开实施例提供的上述阵列基板中，如图1所示，第三电极05与光学补偿控制晶体管23的有源层08同层设置。第三电极05的材料可以为金属氧化物材料，如IGZO材料。
可选地，在具体实施时，在本公开实施例提供的上述阵列基板中，如图1所示，像素驱动电路还包括驱动薄膜晶体管(图1中未示出)，驱动薄膜晶体管的栅极通过填充在贯穿层间介质层4的过孔内的第二耦接部13与第三电极05电耦接。
在具体实施时，如图1所示，本公开实施例通过将感光器件21制备在遮光金属层3上，遮光金属层3可以对感光器件21起到一定的保护作用，避免环境光对感光器件21造成影响，可以提高感光器件21的感光准确度，进而提高光学补偿精度，然后在感光器件21上制备感光存储电容22，在感光存储电容22上制备绝缘缓冲层04，在绝缘缓冲层04上制备光学补偿控制晶体管23、第三电极05和信号线11，光学补偿控制晶体管23的漏极07与遮光金属层3电耦接，由于感光器件21设置于遮光金属层3上，即光学补偿控制晶体管23的漏极07与感光器件21电耦接，且感光器件21的N型半导体层形成于遮光金属层3上，遮光金属层3与光学补偿控制晶体管23的漏极07相连， 则遮光金属层3可以作为感光器件21的N端电极与光学补偿控制晶体管23相连，感光器件21的P型半导体层为感光器件21的P端电极与信号线11耦接。
如图2所示，图2为图1所示的阵列基板的俯视示意图，可以看出由于感光存储电容22和像素存储电容20采用叠层设置，因此可以减小像素存储电容20占用的面积，从而提高像素的开口率。
综上所述，本公开实施例提供的上述阵列基板在每个子像素区域设置了光学补偿电路，光学补偿电路包括光学补偿控制晶体管、感光存储电容和感光器件，感光存储电容和感光器件整体结构称为光学检测器件，该光学检测器件与光学补偿控制晶体管中的源极或漏极电耦接，通过光学检测器件可以检测子像素区域发出的光的亮度，并将光亮度的检测结果通过光学补偿控制晶体管输出，之后就可以根据该光亮度的检测结果对子像素区域的亮度进行补偿。从而能够实现在该阵列基板所在的OLED显示面板出厂后，对子像素进行实时亮度补偿，有效缓解了OLED显示面板亮度变化造成的显示不良，并且由于本公开实施例中先制备感光器件和感光存储电容，在感光存储电容上形成绝缘缓冲层之后再制备光学补偿控制晶体管，则感光器件和感光存储电容上有绝缘缓冲层保护，在后续制备光学补偿控制晶体管过程中的刻蚀工艺不会对感光器件的侧壁造成损伤，且由于绝缘缓冲层将感光器件和光学补偿控制晶体管隔离开，在制备光学补偿控制晶体管时，可以避免在制备感光器件过程中引入的氢对光学补偿控制晶体管造成影响，提高阵列基板的信赖性。
可选地，在具体实施时，在本公开实施例提供的上述阵列基板中，如图1所示，光学补偿控制晶体管23还包括栅极绝缘层10和栅极09，栅极绝缘层10的材料可以为氧化硅、氮化硅、氮氧化硅等绝缘材料；栅极09的材料可以为Mo、Al、Ti、Au、Cu、Hf、Ta等常用金属材料，也可以为MoNd/Cu/MoNd合金材料。
可选地，在具体实施时，在本公开实施例提供的上述阵列基板中，如图1 所示，还包括钝化层5、平坦化6、阳极层7和像素界定层8。这些膜层与现有技术中的功能及结构相同，在此不做详述。
基于同一发明构思，本公开实施例还提供了一种阵列基板的制备方法，如图5所示，包括：
S501、在衬底基板上形成遮光金属层；
S502、在遮光金属层上形成感光器件；
S503、在感光器件上形成感光存储电容；感光存储电容包括依次叠层设置的第一电极、绝缘介质层、第二电极；
S504、在感光存储电容上形成绝缘缓冲层；
S505、在绝缘缓冲层上同时形成光学补偿控制晶体管的有源层和第三电极；第二电极、绝缘缓冲层和第三电极构成像素存储电容；
S506、依次形成光学补偿控制晶体管的栅极和源漏极。
本公开实施例提供的上述阵列基板的制备方法，本公开通过将感光器件、感光存储电容和像素存储电容沿背离衬底基板的方向上依次叠层设置，即感光器件、感光存储电容和像素存储电容三者在衬底基板上的正投影具有重叠区域，减小了子像素区域像素存储电容的占用面积，相应地可以增加发光区的面积，从而提高子像素区域的开口率；并在制备光学补偿控制晶体管之前制备感光器件和感光存储电容，并在感光存储电容上形成绝缘缓冲层，在后续制备光学补偿控制晶体管过程中的刻蚀工艺不会对感光器件的侧壁造成损伤，且由于绝缘缓冲层将感光器件和光学补偿控制晶体管隔离开，在制备光学补偿控制晶体管时，可以避免在制备感光器件过程中引入的氢对光学补偿控制晶体管造成影响，从而可以提高阵列基板的信赖性。
下面通过具体的实例对本公开实施例提供的图1所示的阵列基板的制备方法进行详细说明，如图6A至6F所示，该制备方法具体包括以下步骤：
(1)在衬底基板1上形成遮光金属层3，如图6A所示；
(2)在遮光金属层3上形成感光器件21，遮光金属层3在衬底基板1上的正投影覆盖感光器件21在衬底基板1上的正投影，如图6B所示；
(3)在感光器件21上形成感光存储电容22；感光存储电容22包括依次叠层设置的第一电极01、绝缘介质层02、第二电极03，如图6C所示；
(4)在感光存储电容22上形成绝缘缓冲层04，如图6D所示；
(5)在绝缘缓冲层04上同时形成光学补偿控制晶体管23的有源层08和第三电极05；第二电极03、绝缘缓冲层04和第三电极05构成像素存储电容20，如图6E所示；
(6)依次形成光学补偿控制晶体管23的栅极09、源极06、漏极07、贯穿绝缘缓冲层04和层间介质层4的过孔内的第一耦接部12、贯穿层间介质层4的过孔内的第二耦接部13和信号线11，漏极07与遮光金属层3、第一耦接部12电耦接，第二耦接部13和驱动晶体管的栅极电耦接，信号线11通过贯穿层间介质层4和绝缘缓冲层04的过孔与第一电极01电耦接，如图6F所示；
(7)依次形成钝化层5、平坦化层6、阳极层7和像素界定层8，如图1所示。
通过上述步骤(1)-(7)即可以得到本公开实施例图1所示的阵列基板。
需要说明的是，上述步骤(1)-(7)中各膜层的材料参见本公开实施例提供的阵列基板中提供的各膜层的材料，在上述制备方法中不一一举例。
在具体实施时，在步骤(7)之后还包括制备驱动电路，滤色层、有机发光层和阴极，阳极层与驱动电路耦接，驱动电路驱动有机发光层向衬底基板所在侧发光。这些膜层的结构及功能均与现有技术中相同的膜层结构及功能相同，在此不做详述。
需要说明的是，在本公开实施例提供的上述制备方法中，构图工艺可只包括光刻工艺，或，可以包括光刻工艺以及刻蚀步骤，同时还可以包括打印、喷墨等其他用于形成预定图形的工艺；光刻工艺是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。在具体实施时，可根据本公开中所形成的结构选择相应的构图工艺。
基于同一发明构思，本公开实施例还提供了一种底发射型OLED显示面板，包括本公开实施例提供的上述阵列基，该阵列基板为底发射型OLED显 示面板的背板，还包括与背板对应设置的盖板，该盖板可以为玻璃盖板。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括上述实施例中的底发射型OLED显示面板。由于该显示装置解决问题的原理与前述一种阵列基板相似，因此该显示装置的实施可以参见前述阵列基板的实施，重复之处不再赘述。
在具体实施时，本公开实施例提供的上述显示装置可以为全面屏显示装置，或者也可以为柔性显示装置等，在此不作限定。
在具体实施时，本公开实施例提供的上述显示装置可以为如图7所示的全面屏的手机。当然，本公开实施例提供的上述显示装置也可以为平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
本公开实施例提供的阵列基板、其制备方法及相关装置，该阵列基板包括多个子像素区域，各子像素区域包括位于衬底基板上的像素驱动电路和光学补偿电路，像素驱动电路包括与驱动晶体管耦接的像素存储电容，光学补偿电路包括与感光器件耦接的感光存储电容；像素存储电容和感光存储电容叠层设置，且像素存储电容和感光存储电容共用同一电极板。本公开通过将感光器件、感光存储电容和像素存储电容沿背离衬底基板的方向上依次叠层设置，即感光器件、感光存储电容和像素存储电容三者在衬底基板上的正投影具有重叠区域，减小了子像素区域像素存储电容的占用面积，相应地可以增加发光区的面积，从而提高子像素区域的开口率。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (10)

  1. 一种阵列基板，其中，包括多个子像素区域，各所述子像素区域包括位于衬底基板上的像素驱动电路和光学补偿电路，所述像素驱动电路包括与驱动晶体管耦接的像素存储电容，所述光学补偿电路包括与感光器件耦接的感光存储电容；所述像素存储电容和所述感光存储电容叠层设置，且所述像素存储电容和所述感光存储电容共用同一电极板。
  2. 如权利要求1所述的阵列基板，其中，所述光学补偿电路中的感光器件位于所述感光存储电容与所述衬底基板之间；所述像素存储电容位于所述感光存储电容背离所述衬底基板的一侧；
    在所述感光器件与所述衬底基板之间具有遮光金属层，所述遮光金属层在所述衬底基板上的正投影覆盖所述感光器件在所述衬底基板上的正投影。
  3. 如权利要求2所述的阵列基板，其中，所述感光存储电容包括位于所述感光器件之上依次叠层设置的第一电极、绝缘介质层、第二电极；所述像素存储电容包括依次叠层设置的所述第二电极、绝缘缓冲层和第三电极。
  4. 如权利要求3所述的阵列基板，其中，所述光学补偿电路还包括位于所述绝缘缓冲层上的光学补偿控制晶体管；所述光学补偿控制晶体管的源极或漏极与所述遮光金属层电耦接、且与所述第二电极电耦接。
  5. 如权利要求4所述的阵列基板，其中，所述光学补偿控制晶体管为顶栅型晶体管；所述遮光金属层在所述衬底基板上的正投影覆盖所述光学补偿控制晶体管的有源层在所述衬底基板上的正投影。
  6. 如权利要求5所述的阵列基板，其中，所述第三电极与所述光学补偿控制晶体管的有源层同层设置。
  7. 如权利要求3所述的阵列基板，其中，所述像素驱动电路还包括驱动薄膜晶体管，所述驱动薄膜晶体管的栅极与所述第三电极电耦接。
  8. 一种底发射型OLED显示面板，其中，包括如权利要求1-7任一项所述的阵列基板。
  9. 一种显示装置，其中，包括如权利要求8所述的底发射型OLED显示面板。
  10. 一种如权利要求1-7任一项所述的阵列基板的制备方法，其中，包括：
    在衬底基板上形成遮光金属层；
    在所述遮光金属层上形成感光器件；
    在所述感光器件上形成感光存储电容；所述感光存储电容包括依次叠层设置的第一电极、绝缘介质层、第二电极；
    在所述感光存储电容上形成绝缘缓冲层；
    在所述绝缘缓冲层上同时形成光学补偿控制晶体管的有源层和第三电极；所述第二电极、所述绝缘缓冲层和所述第三电极构成像素存储电容；
    依次形成所述光学补偿控制晶体管的栅极和源漏极。
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