WO2021097995A1 - 一种阵列基板及其制备方法 - Google Patents

一种阵列基板及其制备方法 Download PDF

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Publication number
WO2021097995A1
WO2021097995A1 PCT/CN2019/126907 CN2019126907W WO2021097995A1 WO 2021097995 A1 WO2021097995 A1 WO 2021097995A1 CN 2019126907 W CN2019126907 W CN 2019126907W WO 2021097995 A1 WO2021097995 A1 WO 2021097995A1
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Prior art keywords
electrode
layer
gate
array substrate
base substrate
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PCT/CN2019/126907
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English (en)
French (fr)
Inventor
林振国
周星宇
徐源竣
吕伯彦
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深圳市华星光电半导体显示技术有限公司
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Priority to US16/627,784 priority Critical patent/US11233074B2/en
Publication of WO2021097995A1 publication Critical patent/WO2021097995A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Definitions

  • This application relates to the field of display technology, and in particular to an array substrate and a preparation method thereof.
  • One of the main problems of existing large-size and high-resolution display panels is to solve the problem of aperture ratio, that is, thin film transistors (TFT) and capacitors occupy as little as possible to increase the area of the pixel's light-transmitting area, thereby increasing the pixel aperture ratio .
  • TFT thin film transistors
  • capacitors and TFTs require a certain size to ensure good functions. Therefore, the size of the capacitors and TFTs of the existing display panel is limited in size reduction, which still occupies a certain pixel area, thereby affecting the aperture ratio of the display panel.
  • the present application provides an array substrate and a preparation method thereof, which can increase the aperture ratio of pixels, improve the resolution of the display panel, and have a simple preparation method and save manufacturing cost.
  • the application provides an array substrate, including:
  • Thin film transistors are arranged on the base substrate;
  • the storage capacitor is arranged on the base substrate;
  • the storage capacitor includes a first electrode and a second electrode isolated by a dielectric layer, and both the first electrode and the second electrode are transparent electrodes.
  • the thin film transistor includes a gate electrode, an active layer, and source/drain electrodes
  • the gate is disposed on the first electrode and located at one end of the first electrode;
  • the active layer is provided on the gate in an insulated manner
  • the source/drain electrodes are respectively arranged at two ends of the active layer and are electrically connected to the active layer.
  • the second electrode and the active layer are arranged in the same layer and spaced apart, and the second electrode corresponds to the part of the first electrode that corresponds to the part other than the gate, There is a gap between the second electrode and the source/drain.
  • the orthographic projection of the gate on the base substrate falls within the range of the orthographic projection of the first electrode on the base substrate.
  • the orthographic projection of the second electrode on the base substrate falls within the range of the orthographic projection of the first electrode on the base substrate.
  • a passivation layer and a pixel electrode are stacked on the thin film transistor and the storage capacitor, and the passivation layer is provided at a position corresponding to the drain electrode and the second electrode. Via holes, the pixel electrode is electrically connected to the drain electrode and the second electrode through the via holes, respectively.
  • the material of the second electrode includes one or more of indium gallium zinc oxide, indium tin zinc oxide, and indium gallium zinc tin oxide.
  • the active layer and the second electrode are made of the same material, and the second electrode is formed through conductorization.
  • the present application also provides a method for manufacturing an array substrate.
  • the method includes the following steps:
  • Step S10 sequentially forming a first electrode layer and a gate layer on the base substrate
  • step S20 the first electrode layer and the gate layer are exposed and developed using a first halftone mask process, and a first electrode and a gate located on the first electrode are formed at the same time, wherein, The gate is formed at one end of the first electrode;
  • Step S30 a dielectric layer, a patterned oxide semiconductor layer, and a source-drain metal layer are sequentially formed on the gate and the first electrode.
  • the oxide semiconductor layer includes an active layer and an oxide semiconductor pattern. ;
  • Step S40 using a second half-tone mask process to expose and develop the source and drain metal layers to expose the oxide semiconductor pattern, and conduct the conductorization of the oxide semiconductor pattern to form a second electrode , And then form the source/drain;
  • the first electrode and the second electrode are both transparent electrodes.
  • the application also provides an array substrate, including:
  • Thin film transistors are arranged on the base substrate;
  • the storage capacitor is arranged on the base substrate;
  • the storage capacitor includes a first electrode and a second electrode isolated by a dielectric layer, the first electrode and the second electrode are both transparent electrodes, and the material of the first electrode includes indium zinc oxide, aluminum zinc One or more of oxide and indium aluminum zinc oxide.
  • the thin film transistor includes a gate electrode, an active layer, and source/drain electrodes
  • the gate is disposed on the first electrode and located at one end of the first electrode;
  • the active layer is provided on the gate in an insulated manner
  • the source/drain electrodes are respectively arranged at two ends of the active layer and are electrically connected to the active layer.
  • the second electrode and the active layer are arranged in the same layer and spaced apart, and the second electrode corresponds to the part of the first electrode that corresponds to the part other than the gate, There is a gap between the second electrode and the source/drain.
  • the orthographic projection of the gate on the base substrate falls within the range of the orthographic projection of the first electrode on the base substrate.
  • the orthographic projection of the second electrode on the base substrate falls within the range of the orthographic projection of the first electrode on the base substrate.
  • a passivation layer and a pixel electrode are stacked on the thin film transistor and the storage capacitor, and the passivation layer is provided at a position corresponding to the drain electrode and the second electrode. Via holes, the pixel electrode is electrically connected to the drain electrode and the second electrode through the via holes, respectively.
  • the material of the second electrode includes one or more of indium gallium zinc oxide, indium tin zinc oxide, and indium gallium zinc tin oxide.
  • the active layer and the second electrode are made of the same material, and the second electrode is formed through conductorization.
  • the beneficial effect of the present application is that compared with the existing array substrate, the array substrate and the preparation method thereof provided in the present application are formed of transparent materials because the first electrode and the second electrode of the storage capacitor are transparent.
  • the light can be placed under the light-emitting layer, thereby increasing the aperture ratio of the pixel area and increasing the resolution.
  • the first electrode and the gate of the storage capacitor are formed at the same time by using a half-tone mask process, and when the source and drain are formed, the second electrode is simultaneously realized. Therefore, the process does not increase the number of new photomasks, saves manufacturing costs, and can avoid the generation of etching residues.
  • FIG. 1 is a flow chart of a manufacturing method of an array substrate provided by an embodiment of the application.
  • FIGS. 2A to 2H are schematic diagrams of the manufacturing method of the array substrate provided by the embodiment of the application.
  • FIG. 3 is a schematic structural diagram of an array substrate provided by an embodiment of the application.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features.
  • features defined with “first” and “second” may explicitly or implicitly include one or more of the features.
  • “/” means or, and “plurality” means two or more, unless otherwise specifically defined.
  • the present application is directed to the technical problem of the existing array substrate, because the capacitor and the TFT occupy a certain pixel area, thereby affecting the aperture ratio of the display panel. This embodiment can solve the defect.
  • the present application provides a method for manufacturing an array substrate, the method includes the following steps:
  • step S10 a first electrode layer and a gate layer are sequentially formed on the base substrate.
  • the base substrate 10 is cleaned first, and the base substrate 10 may be a glass substrate. Then, a first electrode layer 11 and a gate layer 12 are formed on the base substrate 10 successively.
  • the material of the first electrode layer 11 includes but is not limited to one or one of indium zinc oxide (InZnO, IZO), aluminum zinc oxide (AlZnO, AZO), and indium aluminum zinc oxide (InAlZnO, IAZO) Above, the film thickness is 300 A ⁇ 2000A.
  • the material of the gate layer 12 includes but is not limited to one or more of Mo, Al, Cu, and Ti, and the thickness of the film layer is 500A -10000A.
  • step S20 the first electrode layer and the gate layer are exposed and developed using a first halftone mask process, and a first electrode and a gate located on the first electrode are formed at the same time, wherein, The gate is correspondingly formed at one end of the first electrode.
  • step S20 includes the following steps:
  • Step S201 as shown in FIG. 2B, a first photoresist layer 13 is formed on the gate layer 12, and the first photoresist layer 13 includes a completely opaque area 130 corresponding to the gate to be formed and corresponding
  • the first half-tone mask (not labeled) is used to perform the first half-tone masking process for the completely light-transmitting area 132 and the remaining part of the light-transmitting area 131 other than the first electrode to be formed.
  • the part of the first halftone mask plate corresponding to the completely opaque region 130 is opaque, and the part corresponding to the partially transparent region 131 is partially transparent, corresponding to the completely transparent region 131.
  • the area 132 is completely transparent.
  • step S202 as shown in FIG. 2C, the gate layer 12 is etched for the first time to remove the gate layer 12 corresponding to the completely transparent region 132.
  • the first photoresist layer 13 and the gate layer 12 corresponding to the fully transparent region 132 are removed, so that the gate layer 12 forms an intermediate pattern.
  • step S203 as shown in FIG. 2D, the first electrode layer 11 is etched to remove the first electrode layer 11 corresponding to the completely transparent region 132, and the first electrode 110 is formed.
  • the first electrode layer 11 is etched using oxalic acid for wet etching. After that, the first photoresist layer 13 in the partially transparent region 131 is removed.
  • Step S204 remove the first photoresist layer 13 of the partial light-transmitting area 131, and perform a second etching on the gate layer 12 to remove the corresponding partial light-transmitting area
  • the gate electrode layer 12 of 131 forms the gate electrode 120, and then the remaining first photoresist layer 13 is removed.
  • Step S30 a dielectric layer, a patterned oxide semiconductor layer, and a source-drain metal layer are sequentially formed on the gate and the first electrode.
  • the oxide semiconductor layer includes an active layer and an oxide semiconductor pattern. .
  • step S30 includes the following steps:
  • Step S301 as shown in FIG. 2F, a second photoresist layer 17 is formed on the source/drain metal layer 16.
  • the second photoresist layer 17 includes completely opaque regions corresponding to the source/drain electrodes to be formed 170. Correspond to the partially transparent region 171 between the source/drain and the remaining fully transparent region 172.
  • a dielectric layer 14 is formed on the gate 120, a patterned oxide semiconductor layer 15 is formed on the dielectric layer 14, and a source-drain metal layer 16 is formed on the oxide semiconductor layer 15.
  • a second photoresist layer 17 is formed on the source and drain metal layer 16, and a second half-tone mask (not labeled) is used to perform a second half-tone mask process.
  • the material of the dielectric layer 14 includes but is not limited to SiOx or SiNx, etc., and its thickness is 1000A -5000A.
  • the material of the oxide semiconductor layer 15 includes but is not limited to IGZO, IZTO, IGZTO, etc., and the thickness thereof is 100A-1000A.
  • the material of the source and drain metal layer 16 includes, but is not limited to, one or more of Mo, Al, Cu, and Ti, and the thickness thereof is 2000A to 10000A.
  • the patterned oxide semiconductor layer 15 includes an active layer 151 and an oxide semiconductor pattern 152 arranged at intervals.
  • Step S40 using a second half-tone mask process to expose and develop the source and drain metal layers to expose the oxide semiconductor pattern, and conduct the conductorization of the oxide semiconductor pattern to form a second electrode , And then form the source/drain.
  • step S40 includes the following steps:
  • step S401 as shown in FIG. 2G, the source-drain metal layer 16 is etched for the first time to remove the source-drain metal layer 16 corresponding to the fully transparent region 172, and the oxide semiconductor pattern 152 is exposed. , And conduct the conductorization of the oxide semiconductor pattern 152 to form the second electrode 152'.
  • the second photoresist layer 17 and the source-drain metal layer 16 corresponding to the completely transparent region 172 are removed, and the exposed oxide semiconductor pattern 152 is conductive.
  • the source layer 151 is blocked by the source-drain metal layer 16 and still maintains semiconductor characteristics.
  • the oxide semiconductor pattern 152 is not protected by the source/drain metal layer 16, its resistance is significantly reduced after processing, and an N+ conductor layer is formed, that is, the oxide semiconductor pattern 152 above the first electrode 110 undergoes After the conductive process, the second electrode 152' of the storage capacitor is formed.
  • Step S402 remove the second photoresist layer 17 of the partially transparent region 171, and perform a second etching on the source and drain metal layer 16 to remove the corresponding partially transparent region.
  • the source/drain metal layer 16 in the region 171 forms the source/drain 160 electrically connected to the active layer 151.
  • the method further includes forming a passivation layer on the source/drain 160 and defining a passivation layer via; then forming a patterned pixel electrode on the passivation layer, and the pixel electrode passes through the passivation layer.
  • the via holes of the chemical layer are in electrical contact with the source/drain 160 and the second electrode 152' respectively.
  • the storage capacitor formed by the first electrode 110 and the second electrode 152' is made of transparent material, and the storage capacitor and the thin film transistor are partially overlapped, that is, the gate of the thin film transistor
  • the orthographic projection of the electrode 120 and the active layer 151 on the base substrate 10 all fall within the range of the orthographic projection of the first electrode 110 on the base substrate 10.
  • the first electrode 110 and the gate 120 are formed at the same time by using a half-tone mask process.
  • the second electrode 152' is simultaneously formed as a conductor. Therefore, the process does not increase the number of new masks, saves manufacturing costs, and can avoid etching residues (the traditional ITO material will have etching residues after wet etching after crystallization).
  • the present application also provides an array substrate prepared by the above method, as shown in FIG. 3 and in conjunction with FIGS. 2A to 2H.
  • the array substrate includes: a base substrate 10, which may be a glass substrate or a flexible Substrate; thin film transistors 20 are arranged on the base substrate 10 at intervals; storage capacitors 30 are arranged on the base substrate 10.
  • the storage capacitor 30 includes a first electrode 110 and a second electrode 152' isolated by a dielectric layer 14.
  • the first electrode 110 and the second electrode 152' are both transparent electrodes.
  • the thin film transistor 20 includes a gate 120, an active layer 151, and a source/drain 160.
  • the gate 120 is disposed on the first electrode 110 and located at one end of the first electrode 110.
  • the orthographic projection of the gate 120 on the base substrate 10 falls within the range of the orthographic projection of the first electrode 110 on the base substrate 10.
  • the orthographic projection of the active layer 151 on the base substrate 10 may also fall within the orthographic projection range of the first electrode 110 on the base substrate 10.
  • the thin film transistor 20 and the storage capacitor 30 partially overlap, thereby increasing the pixel aperture ratio.
  • the active layer 151 is disposed on the gate 120 in an insulated manner. Specifically, the active layer 151 is disposed directly opposite to the gate 120 through the dielectric layer 14.
  • the source/drain electrodes 160 are respectively disposed at two ends of the active layer 151 and are electrically connected to the active layer 151.
  • the second electrode 152' and the active layer 151 are arranged in the same layer and spaced apart, and the second electrode 152' corresponds to the part of the first electrode 110 outside of the gate 120, so There is a gap between the second electrode 152' and the source/drain 160, and the two are not in direct contact.
  • the orthographic projection of the second electrode 152' on the base substrate 10 and the orthographic projection of the first electrode 110 on the base substrate 10 partially overlap, that is, the The second electrode 152 ′ may extend to a side away from the source/drain 160 to correspond to the first electrode 110.
  • the orthographic projection of the second electrode 152' on the base substrate 10 completely falls within the range of the orthographic projection of the first electrode 110 on the base substrate 10.
  • a passivation layer 18 and a pixel electrode 19 are stacked on the thin film transistor 20 and the storage capacitor 30, and the passivation layer 18 is provided at a position corresponding to the drain 160 and the second electrode 152'. There are via holes, and the pixel electrode 19 is electrically connected to the drain 160 and the second electrode 152' through the via holes, respectively.
  • the material of the first electrode 110 is a transparent material, including but not limited to one or more of indium zinc oxide, aluminum zinc oxide, and indium aluminum zinc oxide.
  • the material of the second electrode 152' is also a transparent material, including but not limited to one or more of indium gallium zinc oxide, indium tin zinc oxide, and indium gallium zinc tin oxide.
  • the active layer 151 and the second electrode 152' are made of the same material, and the second electrode 152' is formed through a conductive process, which will not be repeated here.
  • the array substrate also includes other conventional film layers that are not shown in the figure, which will not be repeated here.
  • the storage capacitor itself can transmit light and can be placed under the light-emitting layer. Increase the aperture ratio of the pixel area and increase the resolution.
  • the first electrode and the gate of the storage capacitor are formed at the same time by using a half-tone mask process, and the second electrode is simultaneously realized when the source/drain are formed. Therefore, the process does not increase the number of new photomasks, saves manufacturing costs, and can avoid the generation of etching residues.

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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

一种阵列基板及其制备方法，该阵列基板包括：制备于衬底基板（10）上的薄膜晶体管（20）以及存储电容（30）；薄膜晶体管（20）包括栅极（120）、有源层（151）、以及源/漏极（160）；存储电容（30）包括第一电极（110）以及通过介电层（14）隔绝的第二电极（152'）；栅极（120）设置于第一电极（110）之上且位于第一电极（110）的一端；第二电极（152'）与第一电极（110）对应栅极（120）之外的部分相对应。

Description

一种阵列基板及其制备方法
本申请要求于2019年11月19日提交中国专利局、申请号为201911131998.8、发明名称为“一种阵列基板及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及其制备方法。
 背景技术
现有大尺寸高分辨率的显示面板，主要问题之一是解决开口率的问题，即薄膜晶体管（TFT）以及电容尽量占比少，以增加像素透光区域的面积，从而增大像素开口率。但是电容和TFT需要一定的尺寸才能保证良好的功能，所以现有显示面板的电容和TFT尺寸减小的幅度有限，依然会占用一定的像素区域，从而影响显示面板的开口率。
因此，现有技术存在缺陷，急需改进。
 技术问题
本申请提供一种阵列基板及其制备方法，能够增加像素的开口率，提高显示面板的分辨率，并且制备方法简单、节约制造成本。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请提供一种阵列基板，包括：
衬底基板；
薄膜晶体管，设置于所述衬底基板上；
存储电容，设置于所述衬底基板上；
所述存储电容包括第一电极以及通过介电层隔绝的第二电极，所述第一电极与所述第二电极均为透明电极。
在本申请的阵列基板中，所述薄膜晶体管包括栅极、有源层、以及源/漏极；
所述栅极设置于所述第一电极之上，并且位于所述第一电极的一端；
所述有源层绝缘的设置于所述栅极之上；
所述源/漏极分别设置于所述有源层的两端，并且与所述有源层电性连接。
在本申请的阵列基板中，所述第二电极与所述有源层同层且间隔设置，并且，所述第二电极与所述第一电极对应所述栅极之外的部分相对应，所述第二电极与所述源/漏极之间存在间隙。
在本申请的阵列基板中，所述栅极在所述衬底基板上的正投影落入所述第一电极在所述衬底基板上的正投影范围内。
在本申请的阵列基板中，所述第二电极在所述衬底基板上的正投影落入所述第一电极在所述衬底基板上的正投影范围内。
在本申请的阵列基板中，所述薄膜晶体管以及所述存储电容上还层叠设置有钝化层和像素电极，所述钝化层在对应所述漏极以及所述第二电极的位置设有过孔，所述像素电极通过所述过孔分别与所述漏极以及所述第二电极电连接。
在本申请的阵列基板中，所述第二电极的材料包括铟镓锌氧化物、铟锡锌氧化物、铟镓锌锡氧化物中的一种或一种以上。
在本申请的阵列基板中，所述有源层与所述第二电极所用材料相同，所述第二电极是经由导体化形成的。
本申请还提供一种阵列基板的制备方法，所述方法包括以下步骤：
步骤S10，在衬底基板上依次形成第一电极层和栅极层；
步骤S20，采用第一道半色调掩膜工艺对所述第一电极层和所述栅极层进行曝光、显影，同时形成第一电极和位于所述第一电极之上的栅极，其中，所述栅极对应形成于所述第一电极的一端；
步骤S30，在所述栅极以及所述第一电极上依次形成介电层、图案化的氧化物半导体层以及源漏金属层，所述氧化物半导体层包括有源层和氧化物半导体图块；
步骤S40，采用第二道半色调掩膜工艺对所述源漏金属层进行曝光、显影，露出所述氧化物半导体图块，并对所述氧化物半导体图块进行导体化，形成第二电极，之后形成源/漏极；
其中，所述第一电极和所述第二电极均为透明电极。
本申请还提供一种阵列基板，包括：
衬底基板；
薄膜晶体管，设置于所述衬底基板上；
存储电容，设置于所述衬底基板上；
所述存储电容包括第一电极以及通过介电层隔绝的第二电极，所述第一电极与所述第二电极均为透明电极，所述第一电极的材料包括铟锌氧化物、铝锌氧化物、铟铝锌氧化物中的一种或一种以上。
在本申请的阵列基板中，所述薄膜晶体管包括栅极、有源层、以及源/漏极；
所述栅极设置于所述第一电极之上，并且位于所述第一电极的一端；
所述有源层绝缘的设置于所述栅极之上；
所述源/漏极分别设置于所述有源层的两端，并且与所述有源层电性连接。
在本申请的阵列基板中，所述第二电极与所述有源层同层且间隔设置，并且，所述第二电极与所述第一电极对应所述栅极之外的部分相对应，所述第二电极与所述源/漏极之间存在间隙。
在本申请的阵列基板中，所述栅极在所述衬底基板上的正投影落入所述第一电极在所述衬底基板上的正投影范围内。
在本申请的阵列基板中，所述第二电极在所述衬底基板上的正投影落入所述第一电极在所述衬底基板上的正投影范围内。
在本申请的阵列基板中，所述薄膜晶体管以及所述存储电容上还层叠设置有钝化层和像素电极，所述钝化层在对应所述漏极以及所述第二电极的位置设有过孔，所述像素电极通过所述过孔分别与所述漏极以及所述第二电极电连接。
在本申请的阵列基板中，所述第二电极的材料包括铟镓锌氧化物、铟锡锌氧化物、铟镓锌锡氧化物中的一种或一种以上。
在本申请的阵列基板中，所述有源层与所述第二电极所用材料相同，所述第二电极是经由导体化形成的。
 有益效果
本申请的有益效果为：相较于现有的阵列基板，本申请提供的阵列基板及其制备方法，由于存储电容的第一电极与第二电极均采用透明材料形成，存储电容本身就可以透光，可置于发光层的下方，从而增加像素区域的开口率，增加分辨率。另外，存储电容的第一电极与栅极采用半色调掩模工艺同时形成，在形成源漏极时，同时实现对第二电极的导体化。因此，该制程并未增加新的光罩数，节约制造成本，并且能够避免产生蚀刻残留。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为本申请实施例提供的阵列基板的制备方法流程图。
图2A~2H为本申请实施例提供的阵列基板的制备方法示意图。
图3为本申请实施例提供的阵列基板的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“/”表示或者的意思，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
本申请针对现有的阵列基板，由于电容和TFT占用一定的像素区域，从而影响显示面板开口率的技术问题，本实施例能够解决该缺陷。
参照图1以及图2A~2H，本申请提供一种阵列基板的制备方法，所述方法包括以下步骤：
步骤S10，在衬底基板上依次形成第一电极层和栅极层。
如图2A所示，首先清洗衬底基板10，所述衬底基板10可以为玻璃基板。然后先后在所述衬底基板10上形成第一电极层11和栅极层12。
所述第一电极层11的材料包括但不限于铟锌氧化物（InZnO，IZO）、铝锌氧化物（AlZnO，AZO）、铟铝锌氧化物（InAlZnO，IAZO）中的一种或一种以上，膜层厚度为300 A ~2000A。所述栅极层12的材料包括但不限于Mo、Al、Cu、Ti中的一种或一种以上，膜层厚度为500A -10000A。
步骤S20，采用第一道半色调掩膜工艺对所述第一电极层和所述栅极层进行曝光、显影，同时形成第一电极和位于所述第一电极之上的栅极，其中，所述栅极对应形成于所述第一电极的一端。
具体地，所述步骤S20包括以下步骤：
步骤S201，如图2B所示，在所述栅极层12上形成第一光刻胶层13，所述第一光刻胶层13包括对应待形成栅极的完全不透光区130、对应待形成第一电极之外的完全透光区132以及剩余的部分透光区131，采用第一半色调掩膜板（未标示）进行第一道半色调掩膜工艺。
可以理解的是，所述第一半色调掩膜板对应所述完全不透光区130 的部位不透光，对应所述部分透光区131的部位为部分透光，对应所述完全透光区132的部位为完全透光。
步骤S202，如图2C所示，对所述栅极层12进行第一次蚀刻，去除对应所述完全透光区132的所述栅极层12。
其中，曝光显影后，去除对应所述完全透光区132的所述第一光刻胶层13以及所述栅极层12，使所述栅极层12形成中间图案。
步骤S203，如图2D所示，对所述第一电极层11进行蚀刻，去除对应所述完全透光区132的所述第一电极层11，形成所述第一电极110。
其中，所述第一电极层11刻蚀采用草酸进行湿法刻蚀。之后，去除所述部分透光区131的所述第一光刻胶层13。
步骤S204，如图2E所示，去除所述部分透光区131的所述第一光刻胶层13，并对所述栅极层12进行第二次蚀刻，去除对应所述部分透光区131的所述栅极层12，形成所述栅极120，之后去除剩余所述第一光刻胶层13。
步骤S30，在所述栅极以及所述第一电极上依次形成介电层、图案化的氧化物半导体层以及源漏金属层，所述氧化物半导体层包括有源层和氧化物半导体图块。
具体地，所述步骤S30包括以下步骤：
步骤S301，如图2F所示，在所述源漏金属层16上形成第二光刻胶层17，所述第二光刻胶层17包括对应待形成源/漏极的完全不透光区170、对应所述源/漏极之间的部分透光区171以及剩余的完全透光区172。
具体地，在所述栅极120上形成介电层14，在所述介电层14上形成图案化的氧化物半导体层15，在所述氧化物半导体层15上形成源漏金属层16，在所述源漏金属层16上形成第二光刻胶层17，采用第二半色调掩膜板（未标示）进行第二道半色调掩膜工艺。
所述介电层14的材料包括但不限于SiOx或是SiNx等，其厚度为1000A -5000A。
所述氧化物半导体层15的材料包括但不限于IGZO、IZTO、IGZTO等，其厚度为100A -1000A。
所述源漏金属层16的材料包括但不限于 Mo、Al、Cu、Ti中的一种或一种以上，其厚度为2000A -10000A。
其中，所述图案化的氧化物半导体层15包括间隔设置的有源层151和氧化物半导体图块152。
步骤S40，采用第二道半色调掩膜工艺对所述源漏金属层进行曝光、显影，露出所述氧化物半导体图块，并对所述氧化物半导体图块进行导体化，形成第二电极，之后形成源/漏极。
具体地，所述步骤S40包括以下步骤：
步骤S401，如图2G所示，对所述源漏金属层16进行第一次蚀刻，去除对应所述完全透光区172的所述源漏金属层16，露出所述氧化物半导体图块152，并对所述氧化物半导体图块152进行导体化，形成所述第二电极152’。
具体地，去除对应所述完全透光区172的所述第二光刻胶层17以及所述源漏金属层16，并对露出所述氧化物半导体图块152进行导体化，由于所述有源层151被所述源漏金属层16遮挡，仍然保持半导体特性。而所述氧化物半导体图块152未被所述源漏金属层16保护，其处理以后电阻明显降低，形成N+导体层，即所述第一电极110上方的所述氧化物半导体图块152经导体化处理后形成存储电容的第二电极152’。
步骤S402，如图2H所示，去除所述部分透光区171的所述第二光刻胶层17，并对所述源漏金属层16进行第二次蚀刻，去除对应所述部分透光区171的所述源漏金属层16，形成与所述有源层151电连接的所述源/漏极160。
之后，去除剩余所述第二光刻胶层17。
所述方法还包括在所述源/漏极160上制作钝化层，并定义钝化层过孔；然后在所述钝化层上制作图案化的像素电极，所述像素电极通过所述钝化层的过孔分别与所述源/漏极160以及所述第二电极152’电性接触。
在本实施例中，由所述第一电极110和所述第二电极152’形成的存储电容为透明材质，并且所述存储电容与所述薄膜晶体管形成部分重叠，即所述薄膜晶体管的栅极120以及所述有源层151在所述衬底基板10上的正投影均落入所述第一电极110在所述衬底基板10上正投影的范围内。从而增加像素区域的开口率，增加分辨率。另外，所述第一电极110与所述栅极120采用半色调掩模工艺同时形成，在形成所述源/漏极160时，同时实现对所述第二电极152’的导体化。因此，该制程并未增加新的光罩数，节约制造成本，并且能够避免产生蚀刻残留（传统的ITO材料结晶后湿刻会有刻蚀残留）。
本申请还提供一种采用上述方法制备的阵列基板，如图3所示，并结合图2A~2H，所述阵列基板包括：衬底基板10，所述衬底基板10可以为玻璃基板或柔性基板；薄膜晶体管20，间隔的设置于所述衬底基板10上；存储电容30，设置于所述衬底基板10上。
其中，所述存储电容30包括第一电极110以及通过介电层14隔绝的第二电极152’，所述第一电极110与所述第二电极152’均为透明电极。
具体地，所述薄膜晶体管20包括栅极120、有源层151、以及源/漏极160。所述栅极120设置于所述第一电极110之上，并且位于所述第一电极110的一端。
在一种实施例中，所述栅极120在所述衬底基板10上的正投影落入所述第一电极110在所述衬底基板10上的正投影范围内。所述有源层151在所述衬底基板10上的正投影也可落入所述第一电极110在所述衬底基板10上的正投影范围内。从而使所述薄膜晶体管20与所述存储电容30形成部分重叠，进而增大像素开口率。
所述有源层151绝缘的设置于所述栅极120之上，具体地，所述有源层151通过所述介电层14与所述栅极120正对设置。
所述源/漏极160分别设置于所述有源层151的两端，并且与所述有源层151电性连接。
所述第二电极152’与所述有源层151同层且间隔设置，并且，所述第二电极152’与所述第一电极110对应所述栅极120之外的部分相对应，所述第二电极152’与所述源/漏极160之间存在间隙，两者不直接接触。
在一种实施例中，所述第二电极152’在所述衬底基板10上的正投影与所述第一电极110在所述衬底基板10上的正投影形成部分重叠，即所述第二电极152’可向远离所述源/漏极160一侧延伸至对应所述第一电极110外。
在一种实施例中，所述第二电极152’在所述衬底基板10上的正投影完全落入所述第一电极110在所述衬底基板10上的正投影范围内。
在所述薄膜晶体管20以及所述存储电容30上还层叠设置有钝化层18和像素电极19，所述钝化层18在对应所述漏极160以及所述第二电极152’的位置设有过孔，所述像素电极19通过所述过孔分别与所述漏极160以及所述第二电极152’电连接。
其中，所述第一电极110的材料为透明材料，包括但不限于铟锌氧化物、铝锌氧化物、铟铝锌氧化物中的一种或一种以上。所述第二电极152’的材料也为透明材料，包括但不限于铟镓锌氧化物、铟锡锌氧化物、铟镓锌锡氧化物中的一种或一种以上。
另外，所述有源层151与所述第二电极152’所用材料相同，所述第二电极152’是经由导体化制程形成的，此处不再赘述。
可以理解的是，所述阵列基板还包括图中未示意的其他常规膜层，此处不再赘述。
综上所述，本申请提供的阵列基板及其制备方法，由于存储电容的第一电极与第二电极均采用透明材料形成，存储电容本身就可以透光，可置于发光层的下方，从而增加像素区域的开口率，增加分辨率。另外，存储电容的第一电极与栅极采用半色调掩模工艺同时形成，在形成源/漏极时，同时实现对第二电极的导体化。因此，该制程并未增加新的光罩数，节约制造成本，并且能够避免产生蚀刻残留。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (17)

  1. 一种阵列基板，其包括：
    衬底基板；
    薄膜晶体管，设置于所述衬底基板上；
    存储电容，设置于所述衬底基板上；
    所述存储电容包括第一电极以及通过介电层隔绝的第二电极，所述第一电极与所述第二电极均为透明电极。
  2. 根据权利要求1所述的阵列基板，其中，所述薄膜晶体管包括栅极、有源层、以及源/漏极；
    所述栅极设置于所述第一电极之上，并且位于所述第一电极的一端；
    所述有源层绝缘的设置于所述栅极之上；
    所述源/漏极分别设置于所述有源层的两端，并且与所述有源层电性连接。
  3. 根据权利要求2所述的阵列基板，其中，所述第二电极与所述有源层同层且间隔设置，并且，所述第二电极与所述第一电极对应所述栅极之外的部分相对应，所述第二电极与所述源/漏极之间存在间隙。
  4. 根据权利要求2所述的阵列基板，其中，所述栅极在所述衬底基板上的正投影落入所述第一电极在所述衬底基板上的正投影范围内。
  5. 根据权利要求3所述的阵列基板，其中，所述第二电极在所述衬底基板上的正投影落入所述第一电极在所述衬底基板上的正投影范围内。
  6. 根据权利要求1所述的阵列基板，其中，所述薄膜晶体管以及所述存储电容上还层叠设置有钝化层和像素电极，所述钝化层在对应所述漏极以及所述第二电极的位置设有过孔，所述像素电极通过所述过孔分别与所述漏极以及所述第二电极电连接。
  7. 根据权利要求2所述的阵列基板，其中，所述第二电极的材料包括铟镓锌氧化物、铟锡锌氧化物、铟镓锌锡氧化物中的一种或一种以上。
  8. 根据权利要求7所述的阵列基板，其中，所述有源层与所述第二电极所用材料相同，所述第二电极是经由导体化形成的。
  9. 一种阵列基板的制备方法，其中，所述方法包括以下步骤：
    步骤S10，在衬底基板上依次形成第一电极层和栅极层；
    步骤S20，采用第一道半色调掩膜工艺对所述第一电极层和所述栅极层进行曝光、显影，同时形成第一电极和位于所述第一电极之上的栅极，其中，所述栅极对应形成于所述第一电极的一端；
    步骤S30，在所述栅极以及所述第一电极上依次形成介电层、图案化的氧化物半导体层以及源漏金属层，所述氧化物半导体层包括有源层和氧化物半导体图块；
    步骤S40，采用第二道半色调掩膜工艺对所述源漏金属层进行曝光、显影，露出所述氧化物半导体图块，并对所述氧化物半导体图块进行导体化，形成第二电极，之后形成源/漏极；
    其中，所述第一电极和所述第二电极均为透明电极。
  10. 一种阵列基板，其包括：
    衬底基板；
    薄膜晶体管，设置于所述衬底基板上；
    存储电容，设置于所述衬底基板上；
    所述存储电容包括第一电极以及通过介电层隔绝的第二电极，所述第一电极与所述第二电极均为透明电极，所述第一电极的材料包括铟锌氧化物、铝锌氧化物、铟铝锌氧化物中的一种或一种以上。
  11. 根据权利要求10所述的阵列基板，其中，所述薄膜晶体管包括栅极、有源层、以及源/漏极；
    所述栅极设置于所述第一电极之上，并且位于所述第一电极的一端；
    所述有源层绝缘的设置于所述栅极之上；
    所述源/漏极分别设置于所述有源层的两端，并且与所述有源层电性连接。
  12. 根据权利要求11所述的阵列基板，其中，所述第二电极与所述有源层同层且间隔设置，并且，所述第二电极与所述第一电极对应所述栅极之外的部分相对应，所述第二电极与所述源/漏极之间存在间隙。
  13. 根据权利要求11所述的阵列基板，其中，所述栅极在所述衬底基板上的正投影落入所述第一电极在所述衬底基板上的正投影范围内。
  14. 根据权利要求12所述的阵列基板，其中，所述第二电极在所述衬底基板上的正投影落入所述第一电极在所述衬底基板上的正投影范围内。
  15. 根据权利要求10所述的阵列基板，其中，所述薄膜晶体管以及所述存储电容上还层叠设置有钝化层和像素电极，所述钝化层在对应所述漏极以及所述第二电极的位置设有过孔，所述像素电极通过所述过孔分别与所述漏极以及所述第二电极电连接。
  16. 根据权利要求11所述的阵列基板，其中，所述第二电极的材料包括铟镓锌氧化物、铟锡锌氧化物、铟镓锌锡氧化物中的一种或一种以上。
  17. 根据权利要求16所述的阵列基板，其中，所述有源层与所述第二电极所用材料相同，所述第二电极是经由导体化形成的。
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