WO2017041447A1 - 一种阵列基板及其制作方法、显示装置 - Google Patents

一种阵列基板及其制作方法、显示装置 Download PDF

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Publication number
WO2017041447A1
WO2017041447A1 PCT/CN2016/074427 CN2016074427W WO2017041447A1 WO 2017041447 A1 WO2017041447 A1 WO 2017041447A1 CN 2016074427 W CN2016074427 W CN 2016074427W WO 2017041447 A1 WO2017041447 A1 WO 2017041447A1
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Prior art keywords
electrode
photoresist
layer
forming
source
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PCT/CN2016/074427
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English (en)
French (fr)
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李正亮
姚琪
张斌
曹占锋
张伟
孙雪菲
周斌
高锦成
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京东方科技集团股份有限公司
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Priority to EP16784366.3A priority Critical patent/EP3349242B1/en
Priority to US15/306,550 priority patent/US10181482B2/en
Publication of WO2017041447A1 publication Critical patent/WO2017041447A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G02F1/136236—Active matrix addressed cells for reducing the number of lithographic steps using a grey or half tone lithographic process
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates

Definitions

  • the present disclosure relates to the field of display panel systems, and in particular, to an array substrate, a method for fabricating the same, and a display device.
  • TFT Thin Film Transistor
  • HADS backplane manufacturing process usually requires 9-13 patterning processes, a large number of patterning processes, and high production costs.
  • the number of patterning processes of the array substrate in the prior art is large, which results in low production efficiency of the array substrate, wastes cost, and reduces equipment utilization.
  • the embodiment of the present disclosure provides an array substrate, a manufacturing method thereof, and a display device, which are used to reduce the number of patterning processes of the array substrate, thereby reducing the production cost of the array substrate, and improving production efficiency and equipment utilization.
  • an embodiment of the present disclosure provides an array substrate
  • the manufacturing method comprises the following steps:
  • the gate electrode, the source electrode, the drain electrode, and the first transparent electrode are formed by one patterning process.
  • a first transparent conductive layer is sequentially formed on the substrate, then a metal layer is formed on the first transparent conductive layer, and finally a gate electrode is formed by one patterning process.
  • the source electrode, the drain electrode and the first transparent electrode form a gate electrode, a source electrode, a drain electrode and a first transparent electrode in one patterning process, thereby reducing the number of patterning processes in the array substrate, thereby reducing the production of the array substrate Cost, increase production efficiency and equipment utilization.
  • the step of forming the gate electrode, the source electrode, the drain electrode, and the first transparent electrode by using one patterning process comprising:
  • the photoresist in the completely remaining region of the photoresist is removed to form a gate electrode, a source electrode, a drain electrode, and a first transparent electrode.
  • the common electrode line is formed while forming the gate electrode, the source electrode, the drain electrode, and the first transparent electrode by one patterning process.
  • the method before the forming the first transparent conductive layer and the metal layer on the substrate substrate, the method further includes:
  • An active layer and a gate insulating layer are sequentially formed on the base substrate.
  • the method further includes:
  • the active layer includes a doped region, and a source electrode and a leakage current are respectively formed at positions corresponding to the active layer doped region, the source electrode, and the drain electrode on the protective layer Each via of the pole and active layer doped regions;
  • Forming a second transparent conductive layer Forming a second transparent conductive layer, forming a second transparent electrode, a first connection electrode for connecting the source electrode and the doped region of the active layer, and a doping for the drain electrode and the active layer by a patterning process a second connection electrode of the region, wherein the first connection electrode and the second connection electrode are located in the respective via holes.
  • the active layer is low temperature polysilicon, and the doped region is N-type doped.
  • the second transparent electrode is a slit electrode.
  • the first transparent electrode and/or the second transparent electrode comprise one or a combination of the following materials: indium zinc oxide IZO, indium tin oxide ITO, indium gallium zinc oxide IGZO, indium tin zinc oxide ITZO, tin zinc oxide TZO, gallium zinc oxide GZO, indium gallium oxide IGO.
  • the gate electrode, the source electrode, the drain electrode, and the metal layer on the first transparent conductive layer for forming the first transparent electrode are simultaneously exposed to form a gate electrode, a source electrode, a drain electrode, and a first transparent electrode.
  • the photoresist in the completely remaining region of the photoresist is removed, first, the photoresist covering the metal layer for forming the drain electrode and the source electrode is removed, and the drain layer and the source layer are exposed first. Forming a drain electrode and a source electrode; secondly, removing the photoresist for forming the gate electrode metal layer, exposing the gate layer to form a gate electrode; and finally, removing the photoresist for forming the first transparent electrode, All of the metal in the fully retained region of the photoresist is exposed to form a first transparent electrode.
  • the photoresist in the completely remaining region of the photoresist first, removing the photoresist for forming the gate electrode metal layer, exposing the gate layer to form a gate electrode; secondly, removing for Forming a photoresist on the source and drain electrode metal layers, exposing the drain layer and the source layer to form a drain electrode and a source electrode; and finally, removing the photoresist for forming the first transparent electrode to enable photolithography All of the metal in the fully retained area of the glue is exposed to form a first transparent electrode.
  • the photoresist for forming the first transparent electrode is removed to form a first transparent electrode; secondly, the source electrode and the drain are removed for formation. a photoresist on the electrode metal layer, exposing the drain layer and the source layer to form a drain electrode and a source electrode; and finally, removing the photoresist for forming the gate electrode metal layer to expose the gate layer to form Gate electrode.
  • the material of the metal layer comprises one or a combination of the following materials: molybdenum Mo, chromium Cr, Titanium Ti, tantalum Ta, copper Cu, gold Au, aluminum Al, silver Ag, tungsten W.
  • an embodiment of the present disclosure provides an array substrate formed using the method of fabricating the array substrate provided by the present disclosure.
  • an embodiment of the present disclosure provides a display device including the array substrate provided by the present disclosure.
  • the number of patterning processes of the array substrate can be reduced, and the production cost of the array substrate can be reduced, thereby improving production efficiency and equipment utilization.
  • FIG. 1 is a schematic flow chart of a method for fabricating an array substrate according to an embodiment of the present disclosure
  • FIG. 2 is a first schematic structural diagram of a method for fabricating an array substrate according to an embodiment of the present disclosure
  • FIG. 3 is a second schematic structural diagram of a method for fabricating an array substrate according to an embodiment of the present disclosure
  • FIG. 4 is a third schematic structural diagram of a method for fabricating an array substrate according to an embodiment of the present disclosure
  • FIG. 5 is a fourth schematic structural diagram of a method for fabricating an array substrate according to an embodiment of the present disclosure.
  • FIG. 6 is a fifth schematic structural diagram of a method for fabricating an array substrate according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram showing a sixth structure of a method for fabricating an array substrate according to an embodiment of the present disclosure Figure
  • FIG. 8 is a seventh structural schematic diagram of a method for fabricating an array substrate according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram showing an eighth structure of a method for fabricating an array substrate according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram showing a ninth structure of a method for fabricating an array substrate according to an embodiment of the present disclosure.
  • the embodiment of the present disclosure provides an array substrate, a manufacturing method thereof, and a display device, which are used to reduce the number of patterning processes of the array substrate, thereby reducing the production cost of the array substrate, and improving production efficiency and equipment utilization.
  • each film layer in the drawings do not reflect the true proportions of the components of the array substrate, and the purpose is only to schematically illustrate the contents of the present disclosure.
  • a method for fabricating an array substrate according to an embodiment of the present disclosure includes the following steps:
  • the first transparent electrode is a common electrode.
  • the patterning process in the embodiments of the present disclosure includes the steps of exposure, development.
  • step S101 before the first transparent conductive layer and the metal layer are sequentially formed on the substrate, the method further includes:
  • An active layer and a gate insulating layer are sequentially formed on the base substrate.
  • the active layer, the gate insulating layer, the first transparent conductive layer, and the metal layer are sequentially formed on the base substrate.
  • the step of forming the gate electrode, the source electrode, the drain electrode, and the first transparent electrode by using one patterning process specifically includes:
  • the photoresist of the completely remaining region is removed to form a gate electrode, a source electrode, a drain electrode, and a first transparent electrode.
  • the method further includes the following steps:
  • a second transparent conductive layer TCO Forming a second transparent conductive layer TCO, forming a second transparent electrode by a patterning process, a first connection electrode for connecting the source electrode and the active layer doped region, and a first electrode for connecting the drain electrode and the active layer doped region Two connecting electrodes.
  • the first connection electrode and the second connection electrode are located in the via hole.
  • a first via hole exposing an active layer doped region at a corresponding position of the active layer doped region is formed on the protective layer, and a second via hole exposing the source electrode at a position corresponding to the source electrode is formed.
  • a third via hole exposing the drain electrode at a position corresponding to the drain electrode is formed.
  • a first connection electrode for connecting the source electrode and the active layer doped region is formed at a position corresponding to the first via and the second via in the second transparent conductive layer.
  • a second connection electrode for connecting the drain electrode and the active layer doping region is formed at a position corresponding to the first via hole and the third via hole. Therefore, the active layer doped region is connected to the source through the first connection electrode, and is connected to the drain through the second connection electrode.
  • the active layer is a low temperature polysilicon P-si and the doped region is N-type doped.
  • the second transparent electrode is a slit electrode.
  • the step of removing the photoresist in the completely remaining region to form the gate electrode, the source electrode, the drain electrode, and the first transparent electrode comprises:
  • the photoresist for forming the source electrode and the drain electrode metal layer is removed, and the drain layer and the source layer are exposed to form a drain electrode and a source electrode;
  • the photoresist for forming the gate electrode metal layer is removed to expose the gate layer to form a gate electrode
  • the photoresist for forming the first transparent electrode is removed, and all the metals in the completely remaining region of the photoresist are exposed to form a first transparent electrode;
  • the photolithography for forming the gate electrode metal layer is removed.
  • the photoresist for forming the first transparent electrode is removed, and all the metals in the completely remaining region of the photoresist are exposed to form a first transparent electrode;
  • the photoresist used to form the gate electrode metal layer is removed to expose the gate layer to form a gate electrode.
  • the photoresist covering the metal layer for forming the drain electrode and the source electrode is first removed, and the drain layer and the source layer are exposed first.
  • a layer of photoresist exposes the metal layer.
  • the gate electrode, the source electrode, the drain electrode, and the metal layer on the first transparent conductive layer for forming the first transparent electrode may be simultaneously exposed according to the process requirements.
  • the first transparent electrode and/or the second transparent electrode comprise one or a combination of the following materials: indium zinc oxide IZO, indium tin oxide ITO, indium gallium zinc oxide IGZO, indium tin zinc oxide ITZO, tin zinc oxidation TZO, gallium zinc oxide GZO, indium gallium oxide IGO.
  • first transparent electrode and the second transparent electrode provided by the embodiments of the present disclosure may be one of the above oxides or a mixture of any of the above oxides.
  • the embodiments of the present disclosure are not specifically limited.
  • the material of the metal layer in the embodiments of the present disclosure includes one or a combination of the following materials: molybdenum Mo, chromium Cr, titanium Ti, tantalum Ta, copper Cu, gold Au, aluminum Al, silver Ag, tungsten W.
  • the metal material provided in the embodiments of the present disclosure may be one of the above materials, or a mixture of several of them, and the embodiment of the present disclosure does not specifically limit set.
  • the photoresist on the metal layer covering the gate electrode, the source electrode, the drain electrode, and the first transparent conductive layer may be formed by a two-tone mask or a three-tone mask, and a process of coating, exposure, development, or the like.
  • the method for fabricating the array substrate includes:
  • Step 1 referring to FIG. 2, a buffer layer 22 is deposited on the base substrate 21 and the light shielding layer 211 of the base substrate, and an active layer 23 is deposited on the buffer layer 22 on the active layer 23.
  • a gate insulating layer 24 is deposited.
  • Step 2 referring to FIG. 3, a first transparent conductive layer TCO 25 is deposited on the gate insulating layer 24 shown in FIG. 2, wherein the first transparent conductive layer 25 includes: a transparent region located on the substrate substrate 21 and used for A transparent conductive layer of the common electrode layer 251 is formed.
  • Step 3 referring to FIG. 4, a metal layer 26 is deposited on the first transparent conductive layer 25 shown in FIG.
  • Step 4 referring to FIG. 5, a photoresist layer 27 is formed on the metal layer 26 shown in FIG. 4, and the photoresist layer is subjected to an exposure process to form a photoresist non-retained region 271 and a photoresist partially reserved region. 272 and the photoresist completely retain region 273.
  • Step 5 referring to FIG. 6, the photoresist of the photoresist non-retained region 271 is removed, and the metal layer under the photoresist and the first transparent conductive layer of the photoresist non-retained region 271 are simultaneously heavily doped active.
  • Layer 23 forms doped regions 231.
  • Step 6 the photoresist of the photoresist partial retention region 272 is removed by an ashing process, and the metal layer of the photoresist portion retention region 272 is removed.
  • Step 7 referring to FIG. 8, the photoresist of the photoresist completely remaining region 273 is removed, and the gate electrode 261, the source electrode 262, the drain electrode 263, and the first transparent electrode 251 are formed.
  • Step 8 referring to FIG. 9, a protective layer 28 is formed, while a via hole 281 for connecting the active layer doping region 231 and the source electrode 262 is formed, and a connection for connecting the active layer doping region 231 and the drain electrode 263 is formed.
  • the via 281 includes a second via 2811 over the source electrode 262 and a first via 2812 over the active layer doped region 231.
  • the via 282 includes a third via 2821 over the drain electrode 263 and a fourth pass over the active layer doped region 231. Hole 2822.
  • Step 9 referring to FIG. 10, forming a second transparent conductive layer, forming a second transparent electrode 291, a first connection electrode 292 for connecting the source electrode and the active layer doping region 231, and a drain electrode for connecting the drain electrode by a patterning process
  • the second connection electrode 293 is doped with the active layer doping region 231.
  • the first patterning process is: forming an active layer and a gate insulating layer.
  • the second patterning process is: forming a first transparent conductive layer TCO on the gate insulating layer.
  • a metal layer is then formed on the first transparent conductive layer.
  • a photoresist layer is formed on the metal layer.
  • the photoresist layer is then subjected to an exposure process to form a photoresist non-retained region, a photoresist portion remaining region, and a photoresist completely remaining region.
  • the gate electrode, the source electrode, the drain electrode, and the first transparent electrode are formed by engraving, thereby forming a gate electrode, a source electrode, a drain electrode, and a common electrode layer in one patterning process.
  • the third patterning process is: forming a protective layer on the basis of the second patterning process.
  • the fourth patterning process is: forming a second transparent electrode and a connection electrode on the basis of the third patterning process. Therefore, the array substrate provided by the embodiment of the present disclosure has a four-layer patterning process, thereby reducing the number of patterning processes of the array substrate, reducing the production cost of the array substrate, improving the production efficiency, and the device utilization rate.
  • This embodiment further provides an array substrate formed by the method for fabricating the array substrate provided by the embodiments of the present disclosure.
  • the embodiment further provides a display device comprising the array substrate provided by the embodiments of the present disclosure.
  • a first transparent conductive layer TCO is formed on the gate insulating layer.
  • a metal layer is then formed on the first transparent conductive layer.
  • a photoresist layer is formed on the metal layer.
  • the photoresist layer is then subjected to an exposure process to form a photoresist non-retained region, a photoresist portion remaining region, and a photoresist completely remaining region.
  • the photoresist, the metal layer and the first transparent conductive layer of the photoresist non-retained region are removed.
  • the photoresist and metal layer of the remaining portion of the photoresist are removed by an ashing process.
  • the photoresist in the completely remaining area of the photoresist is removed.
  • a gate electrode, a source electrode, a drain electrode, and a first transparent electrode are formed.
  • the gate electrode, the source electrode, the drain electrode, and the first transparent electrode are formed in one patterning process. Therefore, the method for fabricating the array substrate provided by the embodiments of the present disclosure reduces the number of patterning processes of the array substrate, reduces the production cost of the array substrate, improves the production efficiency, and improves the utilization rate of the device.

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Abstract

一种阵列基板及其制作方法、显示装置，用以减少阵列基板的构图工艺数量，从而降低阵列基板的生产成本，提高生产效率和设备利用率。阵列基板的制作方法包括：在衬底基板（21）上依次形成第一透明导电层（25）和金属层（26）；采用一次构图工艺形成栅电极（261）、源电极（262）、漏电极（263）和第一透明电极（251）。

Description

一种阵列基板及其制作方法、显示装置
相关申请的交叉参考
本申请主张在2015年9月7日在中国提交的中国专利申请号No.201510564851.3的优先权，其全部内容通过引用包含于此。
技术领域
本公开文本涉及显示面板系统领域，尤其涉及一种阵列基板及其制作方法、显示装置。
背景技术
平板显示器(Flat Panel Display，FPD)或薄膜太阳能电池等近年来所制造的电气产品都在基板上配置有薄膜晶体管。薄膜晶体管(Thin Film Transistor，TFT)是液晶显示器的关键器件，对显示器件的工作性能具有十分重要的作用。液晶显示器上的每一液晶像素点都是由集成在其后的TFT来驱动，从而可以做到高速度、高亮度、高对比度显示屏幕信息。
近年来，低温多晶硅液晶显示技术因多晶硅迁移率高、TFT尺寸可以做小以提高开口率、可驱动集成等优势，被广泛应用。但是，HADS背板制造工艺通常需要9-13道构图工艺，构图工艺数量多，生产成本高。
综上所述，现有技术中的阵列基板的构图工艺数量较多，造成阵列基板的生产效率低，且浪费成本，降低了设备利用率。
发明内容
(一)要解决的技术问题
本公开文本实施例提供了一种阵列基板及其制作方法、显示装置，用以减少阵列基板的构图工艺数量，从而降低阵列基板的生产成本，提高生产效率和设备利用率。
(二)技术方案
根据本公开文本的第一方面，本公开文本实施例提供了一种阵列基板的 制作方法，该方法包括如下步骤：
在所述阵列基板的衬底基板上依次形成第一透明导电层TCO和金属层；
采用一次构图工艺形成栅电极、源电极、漏电极和第一透明电极。
通过本公开文本实施例提供的阵列基板的制作方法，首先在衬底基板上依次形成第一透明导电层，然后在所述第一透明导电层上形成金属层，最后采用一次构图工艺形成栅电极、源电极、漏电极和第一透明电极，使得在一次构图工艺中形成栅电极，源电极、漏电极和第一透明电极，因此减少了阵列基板中的构图工艺数量，从而降低阵列基板的生产成本，提高生产效率和设备利用率。
可选地，所述采用一次构图工艺形成栅电极、源电极、漏电极和第一透明电极的步骤，包括：
在所述金属层上形成光刻胶层；
对所述光刻胶进行曝光工艺，形成光刻胶不保留区域、光刻胶部分保留区域和光刻胶完全保留区域；
去除光刻胶不保留区域中的光刻胶、金属层和第一透明导电层；
采用灰化工艺去除光刻胶部分保留区域中的光刻胶；
去除光刻胶部分保留区域中的金属层；以及
去除光刻胶完全保留区域中的光刻胶，以便形成栅电极、源电极、漏电极和第一透明电极。
可选地，采用一次构图工艺形成栅电极、源电极、漏电极和第一透明电极的同时，还形成了公共电极线。
可选地，所述在衬底基板上依次形成第一透明导电层和金属层之前，该方法还包括：
在衬底基板上依次形成有源层和栅绝缘层。
可选地，所述在形成栅电极、源电极、漏电极和第一透明电极之后，该方法还包括：
形成保护层，其中，所述有源层包括掺杂区域，在所述保护层上与所述有源层掺杂区域、源电极和漏电极对应的位置处分别形成露出源电极、漏电 极和有源层掺杂区域的各个过孔；
形成第二透明导电层，采用构图工艺形成第二透明电极、用于连接源电极与所述有源层掺杂区域的第一连接电极、和用于连接漏电极与所述有源层掺杂区域的第二连接电极，其中，所述第一连接电极和第二连接电极位于所述各个过孔中。
可选地，所述有源层为低温多晶硅，所述掺杂区域为N型掺杂。
可选地，所述第二透明电极为狭缝状电极。
可选地，所述第一透明电极和/或所述第二透明电极包含如下材料之一或组合：铟锌氧化物IZO、铟锡氧化物ITO、铟镓锌氧化物IGZO、铟锡锌氧化物ITZO、锡锌氧化物TZO、镓锌氧化物GZO、铟镓氧化物IGO。
可选地，将栅电极、源电极、漏电极、以及用于形成第一透明电极的第一透明导电层上的金属层同时露出，以便形成栅电极、源电极、漏电极和第一透明电极。
可选地，在去除光刻胶完全保留区域中的光刻胶时，首先，去除覆盖用于形成漏电极和源电极的金属层上的光刻胶，使漏极层和源极层先露出，形成漏电极和源电极；其次，去除用于形成栅电极金属层上的光刻胶，使栅极层露出，形成栅电极；以及最后，去除用于形成第一透明电极的光刻胶，使光刻胶完全保留区域中的所有金属均露出，形成第一透明电极。
可选地，在去除光刻胶完全保留区域中的光刻胶时，首先，去除用于形成栅电极金属层上的光刻胶，使栅极层露出，形成栅电极；其次，去除用于形成源电极和漏电极金属层上的光刻胶，使漏极层、源极层露出，形成漏电极和源电极；以及最后，去除用于形成第一透明电极的光刻胶，使光刻胶完全保留区域中的所有金属均露出，形成第一透明电极。
可选地，在去除光刻胶完全保留区域中的光刻胶时，首先，去除用于形成第一透明电极的光刻胶，形成第一透明电极；其次，去除用于形成源电极和漏电极金属层上的光刻胶，使漏极层、源极层露出，形成漏电极和源电极；以及最后，去除用于形成栅电极金属层上的光刻胶，使栅极层露出，形成栅电极。
可选地，所述金属层的材料包含如下材料之一或组合：钼Mo、铬Cr、 钛Ti、钽Ta、铜Cu、金Au、铝Al、银Ag、钨W。
根据本公开文本的第二方面，本公开文本实施例提供了一种阵列基板，采用本公开文本提供的阵列基板的制作方法形成。
根据本公开文本的第三方面，本公开文本实施例提供了一种显示装置，包括本公开文本提供的阵列基板。
(三)有益效果
本公开文本实施例至少具有如下有益效果：
根据本公开文本实施例所提供的阵列基板及其制作方法、显示装置，能够减少阵列基板的构图工艺数量，并且降低阵列基板的生产成本，从而提高生产效率，以及设备利用率。
附图说明
为了更清楚地说明本公开文本实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开文本的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开文本实施例提供的阵列基板的制作方法的流程示意图；
图2为本公开文本实施例提供的阵列基板的制作方法的第一结构示意图；
图3为本公开文本实施例提供的阵列基板的制作方法的第二结构示意图；
图4为本公开文本实施例提供的阵列基板的制作方法的第三结构示意图；
图5为本公开文本实施例提供的阵列基板的制作方法的第四结构示意图；
图6为本公开文本实施例提供的阵列基板的制作方法的第五结构示意图；
图7为本公开文本实施例提供的阵列基板的制作方法的第六结构示意 图；
图8为本公开文本实施例提供的阵列基板的制作方法的第七结构示意图；
图9为本公开文本实施例提供的阵列基板的制作方法的第八结构示意图；以及
图10为本公开文本实施例提供的阵列基板的制作方法的第九结构示意图。
具体实施方式
下面结合附图和实施例，对本公开文本的具体实施方式做进一步描述。以下实施例仅用于说明本公开文本，但不用来限制本公开文本的范围。
为使本公开文本实施例的目的、技术方案和优点更加清楚，下面将结合本公开文本实施例的附图，对本公开文本实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开文本的一部分实施例，而不是全部的实施例。基于所描述的本公开文本的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开文本保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开文本所属领域内具有一般技能的人士所理解的通常意义。本公开文本专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也相应地改变。
为了使本公开文本的目的、技术方案和优点更加清楚，下面将结合附图对本公开文本作进一步地详细描述，显然，所描述的实施例仅仅是本公开文本一部分实施例，而不是全部的实施例。基于本公开文本中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都 属于本公开文本保护的范围。
本公开文本实施例提供了一种阵列基板及其制作方法、显示装置，用以减少阵列基板的构图工艺数量，从而降低阵列基板的生产成本，提高生产效率和设备利用率。
下面结合附图，对本公开文本实施例提供的阵列基板及其制作方法、显示装置的具体实施方式进行详细地说明。
附图中各膜层的厚度和区域的大小形状不反映阵列基板各部件的真实比例，目的只是示意性地说明本公开文本的内容。
实施例1
参见图1，本公开文本实施例提供的一种阵列基板的制作方法，该方法包括如下步骤：
S101，在衬底基板上依次形成第一透明导电层TCO和金属层；以及
S102，采用一次构图工艺形成栅电极、源电极、漏电极和第一透明电极。
需要说明的是第一透明电极为公共电极。本公开文本实施例中的构图工艺包括步骤：曝光、显影。
可选地，在步骤S101中，在衬底基板上依次形成第一透明导电层和金属层之前，该方法还包括：
在衬底基板上依次形成有源层和栅绝缘层。
也就是说，在衬底基板上依次形成有源层、栅绝缘层、第一透明导电层和金属层。
可选地，在步骤S102中，采用一次构图工艺形成栅电极、源电极、漏电极和第一透明电极的步骤，具体包括：
在金属层上形成光刻胶层；
对该光刻胶层进行曝光工艺，形成光刻胶不保留区域、光刻胶部分保留区域和光刻胶完全保留区域；
去除不保留区域的光刻胶、金属层和第一透明导电层；
采用灰化工艺去除部分保留区域的光刻胶；
去除部分保留区域的金属层；以及
去除完全保留区域的光刻胶，形成栅电极、源电极、漏电极和第一透明电极。
可选地，在形成栅电极、源电极、漏电极和第一透明电极之后，该方法还包括如下步骤：
形成保护层，其中有源层包括掺杂区域，在保护层上与有源层掺杂区域、源电极和漏电极对应的位置分别形成露出有源层掺杂区域、源电极和漏电极过孔；以及
形成第二透明导电层TCO，采用构图工艺形成第二透明电极、用于连接源电极与有源层掺杂区域的第一连接电极、和用于连接漏电极与有源层掺杂区域的第二连接电极。第一连接电极和第二连接电极位于过孔中。
需要说明的是，在保护层上分别形成在有源层掺杂区域对应位置处露出有源层掺杂区域的第一过孔，形成在源电极对应的位置处露出源电极的第二过孔，同时形成在漏电极对应的位置处露出漏电极的第三过孔。在第二透明导电层中通过第一过孔和第二过孔对应的位置处形成用于连接源电极与有源层掺杂区域的第一连接电极。另一方面，通过第一过孔和第三过孔对应的位置处形成用于连接漏电极与有源层掺杂区域的第二连接电极。所以，有源层掺杂区域通过第一连接电极与源极相连接，并通过第二连接电极与漏极相连接。
可选地，有源层为低温多晶硅P-si，掺杂区域为N型掺杂。
可选地，第二透明电极为狭缝状电极。
可选地，去除完全保留区域的光刻胶，形成栅电极、源电极、漏电极和第一透明电极的步骤，具体包括：
在光刻胶完全保留区域中，首先，去除用于形成源电极和漏电极金属层上的光刻胶，使漏极层、源极层露出，形成漏电极和源电极；
其次，去除用于形成栅电极金属层上的光刻胶，使栅极层露出，形成栅电极；以及
最后，去除用于形成第一透明电极的光刻胶，使光刻胶完全保留区域中的所有金属均露出，形成第一透明电极；或者，
在光刻胶完全保留区域中，首先，去除用于形成栅电极金属层上的光刻 胶，使栅极层露出，形成栅电极；
其次，去除用于形成源电极和漏电极金属层上的光刻胶，使漏极层、源极层露出，形成漏电极和源电极；以及
最后，去除用于形成第一透明电极的光刻胶，使光刻胶完全保留区域中的所有金属均露出，形成第一透明电极；或者，
在光刻胶完全保留区域中，首先，去除用于形成第一透明电极的光刻胶，形成第一透明电极；
其次，去除用于形成源电极和漏电极金属层上的光刻胶，使漏极层、源极层露出，形成漏电极和源电极；以及
最后，去除用于形成栅电极金属层上的光刻胶，使栅极层露出，形成栅电极。
需要说明的是，在去除光刻胶完全保留区域中的光刻胶时，首先去除覆盖用于形成漏电极和源电极的金属层上的光刻胶，使漏极层和源极层先露出；或者，首先去除覆盖在用于形成栅电极的金属层上的光刻胶，使栅极层先露出；或者，首先去除覆盖在用于形成第一透明电极的第一透明导电层上的金属层的光刻胶，使金属层露出。从而形成栅电极、漏电极、源电极和第一透明电极。因此降低了阵列基板的生产成本，提高了生产效率。
需要强调的是，若根据工艺需要，也可以将栅电极、源电极、漏电极、以及用于形成第一透明电极的第一透明导电层上的金属层同时露出。
其中，第一透明电极和/或第二透明电极包含如下材料之一或组合：铟锌氧化物IZO、铟锡氧化物ITO、铟镓锌氧化物IGZO、铟锡锌氧化物ITZO、锡锌氧化物TZO、镓锌氧化物GZO、铟镓氧化物IGO。
需要说明的是，本公开文本实施例提供的第一透明电极和第二透明电极，可以为上述氧化物中的一种，或者为上述氧化物中的任意几种的混合物。本公开文本实施例不做具体限定。本公开文本实施例中的金属层的材料包含如下材料之一或组合：钼Mo、铬Cr、钛Ti、钽Ta、铜Cu、金Au、铝Al、银Ag、钨W。
需要说明的是，本公开文本实施例中提供的金属材料可以为上述材料中的一种，或者为由其中的几种组成的混合物，本公开文本实施例不做具体限 定。
其中，可以通过双色调掩膜或三色调掩膜，以及涂布、曝光、显影等工艺来制作覆盖栅电极、源电极、漏电极以及第一透明导电层的金属层上的光刻胶。
为了更加清楚明了地介绍该阵列基板的制作方法，可以结合附图进行详细说明。
具体的，本公开文本实施例提供的阵列基板的制作方法，包括：
步骤一，参见图2，在衬底基板21以及该衬底基板的遮光层211上沉积一层缓冲层22，且在该缓冲层22上沉积一层有源层23，在有源层23上沉积一层栅绝缘层24。
步骤二，参见图3，在图2所示的栅绝缘层24上沉积一层第一透明导电层TCO 25，其中该第一透明导电层25包括：位于衬底基板21的透明区域且用于形成公共电极层251的透明导电层。
步骤三，参见图4，在图3所示的第一透明导电层25上沉积金属层26。
步骤四，参见图5，在图4所示的金属层26上形成光刻胶层27，并对该光刻胶层进行曝光工艺，形成光刻胶不保留区域271、光刻胶部分保留区域272和光刻胶完全保留区域273。
步骤五，参见图6，去除光刻胶不保留区域271的光刻胶，和该光刻胶不保留区域271的光刻胶下面的金属层和第一透明导电层，同时重掺杂有源层23形成掺杂区域231。
步骤六，参见图7，采用灰化工艺去除光刻胶部分保留区域272的光刻胶，以及该光刻胶部分保留区域272的金属层。
步骤七，参见图8，去除光刻胶完全保留区域273的光刻胶，形成栅电极261、源电极262、漏电极263和第一透明电极251。
步骤八，参见图9，形成保护层28，同时形成用于连接有源层掺杂区域231与源电极262的过孔281，以及形成用于连接有源层掺杂区域231与漏电极263的过孔282。其中，过孔281包括位于源电极262上方的第二过孔2811，和位于有源层掺杂区域231上方的第一过孔2812。过孔282包括位于漏电极263上方的第三过孔2821，和位于有源层掺杂区域231上方的第四过 孔2822。
步骤九，参见图10，形成第二透明导电层，采用构图工艺形成第二透明电极291、用于连接源电极与有源层掺杂区域231的第一连接电极292、和用于连接漏电极与有源层掺杂区域231的第二连接电极293。
综上，通过本公开文本实施例提供的阵列基板的制作方法，首先第一构图工艺为：形成有源层和栅绝缘层。第二构图工艺为：在栅绝缘层上形成一层第一透明导电层TCO。然后在该第一透明导电层上形成金属层。在该金属层上形成光刻胶层。然后对该光刻胶层进行曝光工艺，形成光刻胶不保留区域、光刻胶部分保留区域和光刻胶完全保留区域。去除光刻胶不保留区域的光刻胶、金属层和第一透明导电层；采用灰化工艺去除光刻胶部分保留区域的光刻胶和金属层，其次去除光刻胶完全保留区域的光刻胶，形成栅电极、源电极、漏电极和第一透明电极，从而在一次构图工艺中形成了栅电极、源电极、漏电极和公共电极层。第三构图工艺为：在该第二构图工艺的基础上形成保护层。第四构图工艺为：在该第三构图工艺的基础上形成第二透明电极和连接电极。从而使得本公开文本实施例提供的阵列基板共有四层构图工艺，从而减少了阵列基板的构图工艺数量，并且降低了阵列基板的生产成本，提高了生产效率，以及设备利用率。
实施例2
本实施例还提供了一种阵列基板，采用本公开文本实施例提供的阵列基板的制作方法形成。
实施例3
本实施例还提供了一种显示装置，其包括本公开文本实施例提供的阵列基板。
综上所述，根据本公开文本实施例提供的阵列基板的制作方法，在栅绝缘层上形成一层第一透明导电层TCO。然后在该第一透明导电层上形成金属层。在该金属层上形成光刻胶层。然后对该光刻胶层进行曝光工艺，形成光刻胶不保留区域、光刻胶部分保留区域和光刻胶完全保留区域。去除光刻胶不保留区域的光刻胶、金属层和第一透明导电层。采用灰化工艺去除光刻胶部分保留区域的光刻胶和金属层。其次去除光刻胶完全保留区域的光刻胶， 形成栅电极、源电极、漏电极和第一透明电极。从而使得在一次构图工艺中形成了栅电极、源电极、漏电极和第一透明电极。因此，通过本公开文本实施例提供的阵列基板的制作方法，减少了阵列基板的构图工艺数量，降低了阵列基板的生产成本，提高了生产效率，以及设备利用率。
显然，本领域的技术人员可以对本公开文本进行各种改动和变型而不脱离本公开文本的精神和范围。这样，倘若本公开文本的这些修改和变型属于本公开文本权利要求及其等同技术的范围之内，则本公开文本也意图包含这些改动和变型在内。

Claims (15)

  1. 一种阵列基板的制作方法，包括如下步骤：
    在所述阵列基板的衬底基板上依次形成第一透明导电层TCO和金属层；以及
    采用一次构图工艺形成栅电极、源电极、漏电极和第一透明电极。
  2. 根据权利要求1所述的制作方法，其中，所述采用一次构图工艺形成栅电极、源电极、漏电极和第一透明电极的步骤包括：
    在所述金属层上形成光刻胶层；
    对所述光刻胶层进行曝光工艺，形成光刻胶不保留区域、光刻胶部分保留区域和光刻胶完全保留区域；
    去除光刻胶不保留区域中的光刻胶、金属层和第一透明导电层；
    采用灰化工艺去除光刻胶部分保留区域的光刻胶；
    去除光刻胶部分保留区域中的金属层；以及
    去除光刻胶完全保留区域中的光刻胶，以便形成栅电极、源电极、漏电极和第一透明电极。
  3. 根据权利要求1或2所述的制作方法，其中，在采用一次构图工艺形成栅电极、源电极、漏电极和第一透明电极的同时，还形成了公共电极线。
  4. 根据权利要求1至3中任一项所述的制作方法，其中，所述在衬底基板上依次形成第一透明导电层和金属层之前，该方法还包括：
    在衬底基板上依次形成有源层和栅绝缘层。
  5. 根据权利要求4所述的制作方法，其中，所述在形成栅电极、源电极、漏电极和第一透明电极之后，该方法还包括：
    形成保护层，其中，所述有源层包括掺杂区域，在所述保护层上与所述有源层掺杂区域、源电极和漏电极对应的位置处分别形成露出有源层掺杂区域、源电极和漏电极的各个过孔；以及
    形成第二透明导电层，采用构图工艺形成第二透明电极、用于连接源电极与所述有源层掺杂区域的第一连接电极、和用于连接漏电极与所述有源层掺杂区域的第二连接电极，其中，所述第一连接电极和第二连接电极位于所 述各个过孔中。
  6. 根据权利要求5所述的制作方法，其中，所述有源层为低温多晶硅，所述有源层掺杂区域为N型掺杂。
  7. 根据权利要求5所述的制作方法，其中，所述第二透明电极为狭缝状电极。
  8. 根据权利要求5所述的制作方法，其中，所述第一透明电极和/或所述第二透明电极包含如下材料之一或组合：铟锌氧化物IZO、铟锡氧化物ITO、铟镓锌氧化物IGZO、铟锡锌氧化物ITZO、锡锌氧化物TZO、镓锌氧化物GZO、铟镓氧化物IGO。
  9. 根据权利要求2所述的制作方法，其中，将栅电极、源电极、漏电极、以及用于形成第一透明电极的第一透明导电层上的金属层同时露出，以便形成栅电极、源电极、漏电极和第一透明电极。
  10. 根据权利要求2所述的制作方法，其中，在去除光刻胶完全保留区域中的光刻胶时，首先，去除覆盖用于形成漏电极和源电极的金属层上的光刻胶，使漏极层和源极层先露出，形成漏电极和源电极；
    其次，去除用于形成栅电极金属层上的光刻胶，使栅极层露出，形成栅电极；以及
    最后，去除用于形成第一透明电极的光刻胶，使光刻胶完全保留区域中的所有金属均露出，形成第一透明电极。
  11. 根据权利要求2所述的制作方法，其中，在去除光刻胶完全保留区域中的光刻胶时，首先，去除用于形成栅电极金属层上的光刻胶，使栅极层露出，形成栅电极；
    其次，去除用于形成源电极和漏电极金属层上的光刻胶，使漏极层、源极层露出，形成漏电极和源电极；以及
    最后，去除用于形成第一透明电极的光刻胶，使光刻胶完全保留区域中的所有金属均露出，形成第一透明电极。
  12. 根据权利要求2所述的制作方法，其中，在去除光刻胶完全保留区域中的光刻胶时，首先，去除用于形成第一透明电极的光刻胶，形成第一透明电极；
    其次，去除用于形成源电极和漏电极金属层上的光刻胶，使漏极层、源极层露出，形成漏电极和源电极；以及
    最后，去除用于形成栅电极金属层上的光刻胶，使栅极层露出，形成栅电极。
  13. 根据权利要求1至12中任一项所述的制作方法，其中，所述金属层的材料包含如下材料之一或组合：钼Mo、铬Cr、钛Ti、钽Ta、铜Cu、金Au、铝Al、银Ag、钨W。
  14. 一种阵列基板，采用权利要求1至13中任一项所述的制作方法形成。
  15. 一种显示装置，包括权利要求14所述的阵列基板。
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