WO2016192471A1 - 一种阵列基板及其制备方法、显示装置及其制备方法 - Google Patents

一种阵列基板及其制备方法、显示装置及其制备方法 Download PDF

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WO2016192471A1
WO2016192471A1 PCT/CN2016/079359 CN2016079359W WO2016192471A1 WO 2016192471 A1 WO2016192471 A1 WO 2016192471A1 CN 2016079359 W CN2016079359 W CN 2016079359W WO 2016192471 A1 WO2016192471 A1 WO 2016192471A1
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layer
metal layer
storage pattern
source
pattern
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PCT/CN2016/079359
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English (en)
French (fr)
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孔祥永
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京东方科技集团股份有限公司
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Priority to US15/547,410 priority Critical patent/US20180011356A1/en
Publication of WO2016192471A1 publication Critical patent/WO2016192471A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate, a preparation method thereof, a display device, and a preparation method thereof.
  • TFT Thin Film Transistor
  • LCD liquid crystal display
  • OLED Organic Light-Emitting Diode
  • the thin film transistors located in the same row are simultaneously turned on by controlling the input signals of the gate lines. After a certain time, the thin film transistors of the next row are simultaneously turned on, and so on.
  • the opening time of each row of thin film transistors is relatively short, it is difficult to achieve the response time of the liquid crystal, which causes the liquid crystal display to flicker. Therefore, in order to avoid such a problem, the phenomenon that the liquid crystal display screen flickers is generally avoided by the storage capacitor.
  • the storage capacitor can be used to maintain the voltage of the pixel electrode for a certain period of time after the thin film transistor is turned off, thereby providing time for the liquid crystal response.
  • the size of the pixel is made smaller and smaller, which causes a decrease in the storage capacitance, so that the response time of the liquid crystal is insufficient, thereby causing the occurrence of flicker phenomenon, which seriously affects the display. effect.
  • the storage capacitor is increased, the storage capacitor with a large area will affect the aperture ratio of the pixel.
  • the present disclosure provides an array substrate, a method of fabricating the same, a display device, and a method of fabricating the same.
  • the technical solution of the present disclosure effectively reduces the occupied area of the storage capacitor and increases the aperture ratio of the pixel by parallel storage capacitors.
  • the present disclosure provides an array substrate, including: a substrate, a gate metal layer, an active layer, a source/drain metal layer, and a pixel electrode layer, wherein the array substrate has a storage capacitor region;
  • the gate metal layer includes a gate metal layer storage pattern
  • the active layer includes an active layer storage pattern
  • the source/drain metal layer includes a source/drain metal layer storage pattern
  • the pixel electrode layer Include a pixel electrode layer storage pattern
  • the gate metal layer storage pattern, the active layer storage pattern, the source/drain metal layer storage pattern, and the projection of the pixel electrode layer storage pattern on the substrate at least partially coincide, and the pixel An electrode layer storage pattern is electrically connected to the gate metal layer storage pattern to constitute a first electrode of a storage capacitor, and the active layer storage pattern is electrically connected to the source/drain metal layer storage pattern to constitute a second of the storage capacitor electrode.
  • the active layer is disposed on the gate metal layer
  • the source/drain metal layer is disposed on the active layer
  • the pixel electrode layer is disposed on the source/drain metal layer
  • the array substrate further comprises: a gate insulating layer disposed between the gate metal layer and the active layer, and etching disposed between the active layer and the source/drain metal layer a barrier layer, and a passivation layer disposed between the source/drain metal layer and the pixel electrode layer.
  • the pixel electrode layer storage pattern is electrically connected to the gate metal layer storage pattern through a first via hole in the passivation layer, the etch barrier layer, and the gate insulating layer ;
  • the source/drain metal layer storage pattern is electrically connected to the active layer storage pattern through a second via in the etch barrier layer.
  • the active layer storage pattern in the storage capacitor region is an active layer storage pattern after plasma processing or ion implantation.
  • the gate insulating layer, the etch stop layer, and the passivation layer are Included at least one of an oxide of silicon, a nitride of silicon, an oxide of cerium, an oxynitride of silicon, and an oxide of aluminum;
  • the substrate comprising at least at least a glass substrate, a quartz substrate, and an organic resin substrate One type;
  • the gate metal layer includes at least one of molybdenum, molybdenum-niobium alloy, aluminum, aluminum-niobium alloy, titanium, and copper;
  • the active layer includes a transparent metal oxide semiconductor
  • the source/drain metal layer includes at least one of molybdenum, molybdenum-niobium alloy, aluminum, aluminum-niobium alloy, titanium, and copper;
  • the pixel electrode layer includes a transparent conductive metal oxide.
  • the present disclosure further provides a method for fabricating an array substrate, comprising: forming a gate metal layer, an active layer, a source/drain metal layer, and a pixel electrode layer on a substrate, wherein the array substrate has a storage capacitor region;
  • the gate metal layer comprises a gate metal layer storage pattern
  • the active layer comprises an active layer storage pattern
  • the source/drain metal layer comprises a source/drain metal layer storage pattern
  • the pixel The electrode layer includes a pixel electrode layer storage pattern
  • the gate metal layer storage pattern, the active layer storage pattern, the source/drain metal layer storage pattern, and the projection of the pixel electrode layer storage pattern on the substrate at least partially coincide, and
  • the pixel electrode layer storage pattern is electrically connected to the gate metal layer storage pattern to constitute a first electrode of the storage capacitor, and the active layer storage pattern is electrically connected to the source/drain metal layer storage pattern to constitute the storage capacitor Two electrodes.
  • the method further includes: disposing the active layer on the gate metal layer, disposing the source/drain metal layer on the active layer, and setting the source/drain metal layer a pixel electrode layer, and wherein the method further comprises:
  • the active layer storage pattern pre-formed in the storage capacitor region is subjected to plasma processing or ion implantation processing.
  • the gate insulating layer, the etch stop layer, and the passivation layer respectively comprise an oxide of silicon, a nitride of silicon, an oxide of germanium, an oxynitride of silicon, and aluminum. At least one of oxides;
  • the substrate includes at least one of a glass substrate, a quartz substrate, and an organic resin substrate;
  • the gate metal layer includes at least one of molybdenum, molybdenum-niobium alloy, aluminum, aluminum-niobium alloy, titanium, and copper;
  • the active layer includes a transparent metal oxide semiconductor
  • the source/drain metal layer includes at least one of molybdenum, molybdenum-niobium alloy, aluminum, aluminum-niobium alloy, titanium, and copper;
  • the pixel electrode layer includes a transparent conductive metal oxide.
  • the present disclosure also provides a display device including the above array substrate.
  • the present disclosure further provides a method of fabricating a display device, including the method of fabricating the above array substrate.
  • an array substrate, a preparation method thereof, a display device and a preparation method thereof are provided in the present disclosure.
  • the storage capacitor in the array substrate adopts two storage capacitors in parallel, and two storage capacitors are lined.
  • the projections on the bottom coincide, which reduces the footprint of the two parallel storage capacitors and increases the aperture ratio of the pixels.
  • FIG. 1 to FIG. 9 are schematic diagrams showing processes for preparing an array substrate according to an embodiment of the present disclosure
  • the array substrate includes: a substrate 1, a gate metal layer 2, an active layer 4, a source/drain metal layer 9, a pixel electrode layer 11, and a storage capacitor region. ;
  • the gate metal layer 2 includes a gate metal layer memory pattern 22
  • the active layer 4 includes an active layer memory pattern 42
  • the source and drain metal layer 9 includes a source/drain metal layer memory pattern 93
  • the pixel electrode layer 11 includes pixels. Electrode layer storage pattern 112;
  • the projections of the gate metal layer storage pattern 22, the active layer storage pattern 42, the source/drain metal layer storage pattern 93, and the pixel electrode layer storage pattern 112 on the substrate 1 at least partially overlap, and the pixel electrode layer stores the pattern 112 and the gate.
  • the metal layer storage pattern 22 electrically connects the first electricity constituting the storage capacitor
  • the active layer storage pattern 42 and the source/drain metal layer storage pattern 93 are electrically connected to a second electrode constituting a storage capacitor.
  • the storage capacitors in the array substrate are connected in parallel by two storage capacitors, wherein the gate metal layer storage pattern 22 and the active layer storage pattern 42 form a storage capacitor, and the source/drain metal layer storage pattern 93 and the pixel electrode layer storage pattern 112 constitute a capacitor.
  • the other storage capacitor, and the two storage capacitors are connected in parallel in the same storage capacitor region, and the projection on the substrate coincides, thereby reducing the occupied area of the two parallel storage capacitors and increasing the aperture ratio of the pixel.
  • the array substrate further includes: a gate insulating layer 3 disposed between the gate metal layer 2 and the active layer 4, disposed between the active layer 4 and the source/drain metal layer 9.
  • the etch stop layer 8 and the passivation layer 10 disposed between the source/drain metal layer 9 and the pixel electrode layer 11.
  • the gate insulating layer 3, the etch stop layer 8 and the passivation layer 10 are all insulated, and the material thereof may be silicon oxide (SiO x ), silicon nitride (SiN x ), germanium.
  • the two-layer structure of the passivation layer 10 may be a SiN x /SiO x layer structure, or may be a SiN x /SiON/SiO x layer structure, and the total thickness of the film layer may be controlled to be about 100 to 600 nm. The thickness of each film layer can be adjusted according to the actual situation.
  • the gate insulating layer 3 and the etch stop layer 8 described above are similar to the passivation layer 10, and will not be described in detail in this embodiment.
  • the pixel electrode layer storage pattern 111 passes through the first pass through the passivation layer 10, the etch barrier layer 8 and the gate insulating layer 3.
  • the hole 12 is electrically connected to the gate metal layer storage pattern 22;
  • the source/drain metal layer storage pattern 93 is electrically connected to the active layer storage pattern 42 through the second via 13 penetrating the etch barrier layer 8.
  • the active layer storage pattern 42 can be used as an electrode of the storage capacitor. It is understood that the pattern is stored as an active layer of the conductor by plasma treatment or post-ion implantation.
  • the embodiment of the present disclosure further provides a method for preparing an array substrate, the method comprising: Forming a gate metal layer 2, an active layer 4, a source/drain metal layer 9, a pixel electrode layer 11, and a storage capacitor region on the substrate 1;
  • the gate metal layer 2 includes a gate metal layer memory pattern 22, the active layer 4 includes an active layer memory pattern 42, the source/drain metal layer 9 includes a source/drain metal layer storage pattern 93, and the pixel electrode layer 11 includes The pixel electrode layer storage pattern 112; the projections of the gate metal layer storage pattern 22, the active layer storage pattern 42, the source/drain metal layer storage pattern 93, and the pixel electrode layer storage pattern 112 on the substrate 1 at least partially coincide, and the pixel electrode layer
  • the memory pattern 112 is electrically connected to the gate metal layer storage pattern 22 to constitute a first electrode of the storage capacitor
  • the active layer storage pattern 42 is electrically connected to the source/drain metal layer storage pattern 93 to constitute a second electrode of the storage capacitor.
  • the storage capacitor is formed in the storage capacitor region by using two storage capacitors in parallel, wherein the gate metal layer storage pattern 22 and the active layer storage pattern 42 form a storage capacitor, and the source/drain metal layer storage pattern 93 and the pixel electrode layer are stored.
  • the pattern 112 constitutes another storage capacitor, and the two storage capacitors are in the same storage capacitor region, and the projections on the substrate coincide, thereby reducing the occupied area of the two parallel storage capacitors and increasing the aperture ratio of the pixels.
  • the process of the method for preparing the array substrate described above is described in detail by using a specific embodiment.
  • the process of the method for preparing the array substrate may include the following steps:
  • Step S1 a gate metal layer 2 is formed on the substrate 1, as shown in FIG.
  • the substrate 1 may be a glass substrate, a quartz substrate or an organic resin substrate;
  • the material of the gate metal layer 2 may be molybdenum (Mo), molybdenum-niobium alloy (MoNb), aluminum (Al), or aluminum-bismuth alloy (A single-layer or multi-layer composite laminate formed of one or more materials of AlNd), titanium (Ti) and copper (Cu), preferably a single layer or multiple layers composed of Mo, Al or an alloy containing Mo or Al Composite film.
  • the thickness is from 100 nm to 500 nm.
  • the gate metal layer 2 described above may deposit a gate metal layer on the substrate 1 by sputtering or thermal evaporation.
  • Step S2 the gate pattern 21 and the gate metal layer storage pattern 22 are formed by one patterning process, as shown in FIG.
  • the above patterning process can be understood as that a photoresist is coated on the gate metal layer 2 deposited in the above step S1, and the coated photoresist is exposed and developed by a mask, and then mixed.
  • the acid liquid removes the gate metal layer 2 of the photoresist-free region, and finally the photoresist is peeled off to form the gate pattern 21 and the gate metal layer memory pattern 22 as shown in FIG.
  • Step S3 depositing a gate insulating layer 3 on the gate pattern 21 and the gate metal layer memory pattern 22, and the substrate 1, as shown in FIG.
  • the material of the gate insulating layer 3 may be made of silicon oxide (SiO x), silicon nitride (SiN x), hafnium oxide (HfO x), silicon oxynitride (SiON), A multilayer composite film composed of one or two of AlO x or the like.
  • the gate insulating layer 3 is formed by plasma enhanced chemical vapor deposition (PECVD), that is, Plasma Enhanced Chemical Vapor Deposition, and the hydrogen content of the film layer needs to be controlled at a low level during the fabrication process.
  • PECVD plasma enhanced chemical vapor deposition
  • the gate insulating layer second-generation structure may be a SiN x /SiO x stacked structure, or may be a SiN x /SiON/SiO x stacked structure.
  • the total thickness of the film layer can be controlled to be about 100 to 600 nm, and the thickness of each film layer can be adjusted according to actual conditions.
  • Step S4 depositing the active layer 4 on the gate insulating layer 3, and forming a layer of photoresist on the active layer 4.
  • the material of the active layer may be Indium Gallium Zinc Oxide (IGZO), Indium Tin Zinc Oxide (ITZO), Indium Oxide (In 2 O 3 ), and oxidation.
  • IGZO Indium Gallium Zinc Oxide
  • ITZO Indium Tin Zinc Oxide
  • ITZO Indium Tin Zinc Oxide
  • In 2 O 3 Indium Oxide
  • ZnO transparent metal oxide semiconductor materials
  • Step S5 using a gray-scale mask to form a fully exposed area, an unexposed area, and a gray-scale exposed area by exposure and development processes, removing the photoresist of the fully exposed area (the photoresist completely removed area 6), and gray scale exposure a portion of the photoresist (resistive semi-reserved region 7) of the region, as shown in FIG. 4;
  • the gray scale mask comprises a fully opaque portion, a translucent portion and a fully transparent portion. That is, the gray-scale mask refers to forming a light-shielding metal layer that is opaque in some areas on the transparent substrate material, and a light-shielding metal layer that is semi-transmissive in other areas, and does not form any light-shielding metal layer in other areas. Wherein, the thickness of the semi-transmissive light-shielding metal layer is smaller than the thickness of the light-shielding metal layer which is completely opaque. In addition, the transmittance of the semi-transmissive light-shielding metal layer to ultraviolet light can also be changed by adjusting the thickness of the semi-transmissive light-shielding metal layer.
  • the working principle of the gray-scale mask is as follows: by controlling the thickness of the light-shielding metal layer at different regions on the upper and lower surfaces of the gray-scale mask, the intensity of the transmitted light in different regions is different, thereby enabling photolithography. After the selective exposure development of the glue, an unexposed area, a gray scale exposed area, and a fully exposed area corresponding to the completely opaque portion, the translucent portion, and the completely transparent portion of the gray scale mask, respectively, are formed.
  • the photoresists referred to in this embodiment are all positive photoresists, and may be a light-sensitive mixed liquid composed of three main components of a photosensitive resin, a sensitizer and a solvent. After the photosensitive resin is irradiated, a photocuring reaction can be quickly performed in the exposed region, and the cured photosensitive resin can be washed away by a specific solution.
  • Step S6 etching the active layer 4 corresponding to the fully exposed region, as shown in FIG.
  • Step S7 peeling off the photoresist of the gray-scale exposed region, and processing the semiconductor of the exposed pre-formed active layer storage pattern by plasma processing (H-plasma processing) or ion implantation to process the active layer storage pattern 42 of the conductor. ,As shown in Figure 6.
  • the photoresist for stripping the gradation exposure region may be again exposed and developed by the ash mask by etching, and the photoresist in the gradation exposure region is peeled off, and the embodiment is not specifically implemented.
  • the method is limited.
  • Step S8 removing the photoresist of the unexposed region (the photoresist completely remaining region 5), forming the active layer pattern 41, and forming an etch stop layer 8 on the active layer pattern 41 and the active layer storage pattern 42,
  • the second via 13, the third via 14, and the fourth via 15 are formed by one patterning process as shown in FIG.
  • step S2 it can be understood that the above-mentioned patterning process is similar to step S2, and this embodiment will not be described in detail.
  • the second via 13 can be understood as a via that pre-forms one electrode of the storage capacitor.
  • the third via 14 and the fourth via 15 can be understood to be formed at opposite positions of the active layer pattern 41.
  • Step S9 depositing a source/drain metal layer 9 on the etch barrier layer 8, and forming a source pattern 91, a drain pattern 92, and a source/drain metal layer storage pattern 93 by one patterning process, as shown in FIG.
  • the material of the source/drain metal layer 9 may be molybdenum (Mo), molybdenum-niobium alloy (MoNb), aluminum (Al), Single or multi-layer composite laminate formed of one or more materials of aluminum-niobium alloy (AlNd), titanium (Ti) and copper (Cu), preferably composed of Mo, Al or alloys containing Mo and Al Layer or multilayer composite film.
  • the patterning process of forming the source pattern 91, the drain pattern 92, and the source/drain metal layer storage pattern 93 may be similar to step S2, and will not be described in detail in this embodiment.
  • the positions of the source pattern 91 and the drain pattern 92 are also interchangeable, and the positions are different depending on the flow direction of the current.
  • Step S10 depositing a passivation layer 10, and after forming the passivation layer 10, forming a first via 12 penetrating the passivation layer 10, the etch barrier layer 8 and the gate insulating layer 3, for making pixels of the storage capacitor region
  • the electrode layer storage pattern 112 is electrically connected to the gate metal layer storage pattern 22.
  • the passivation layer 10 may be made of silicon oxide (SiO x), silicon nitride (SiN x), hafnium oxide (HfO x), silicon oxynitride (SiON), AlO x and the like in a Composition of a multilayer composite film of two or two compositions.
  • the passivation layer 10 is fabricated by plasma enhanced chemical vapor deposition (PECVD), that is, Plasma Enhanced Chemical Vapor Deposition, and the hydrogen content of the film layer is controlled to be at a low level during the fabrication process.
  • PECVD plasma enhanced chemical vapor deposition
  • the two-layer structure of the passivation layer 10 may be a SiN x /SiO x layer structure, or may be a SiN x /SiON/SiO x layer structure, and the total thickness of the film layer may be controlled to be about 100 to 600 nm. The thickness of the film can be adjusted according to the actual situation.
  • Step S11 the pixel electrode layer 11 is formed, and the pixel electrode pattern 111 and the pixel electrode layer storage pattern 112 are formed by one patterning process, as shown in FIG.
  • the pixel electrode layer 11 may be a transparent conductive metal oxide such as ITO, IZO, or the like, which may be deposited by sputtering, and may have a deposition thickness of 40 to 200 nm.
  • the patterning process of forming the pixel electrode pattern 111 and the pixel electrode layer storage pattern 112 may be similar to step S2, and will not be described in detail in this embodiment.
  • each layer such as the gate metal layer 2, the gate insulating layer 3, the active layer 4, the etch stop layer 8, the source/drain metal layer 9, the passivation layer 10, and the pixel electrode layer 11 or the like can be formed by vacuum deposition or magnetron sputtering, and this embodiment will not be described in detail.
  • the pixel electrode layer 11 can be understood to include the gate pattern 21 and The gate metal layer stores the pattern 22 or a layer pre-formed with the gate pattern 21 and the gate metal layer storage pattern 22;
  • the active layer 4 may be understood to include the active layer pattern 41 and the active layer storage pattern 42 or the pre-formed active layer pattern 41 and a layer of the active layer storage pattern 42;
  • the source/drain metal layer includes a source pattern 91, a drain pattern 92, and a source/drain metal layer storage pattern 93 or a pre-formed source pattern 91, a drain pattern 92, and a source/drain metal
  • the pixel electrode layer is a layer including the pixel electrode pattern 111 and the pixel electrode layer storage pattern 112 or the pre-formed pixel electrode pattern 111 and the pixel electrode layer storage pattern 112.
  • This embodiment also provides a display device comprising the array substrate as described above.
  • the display device in this embodiment may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种阵列基板及其制备方法、显示装置及其制备方法，该阵列基板包括：衬底（1）、栅金属层（2）、有源层（4）、源漏金属层（9）、像素电极层（11），其中所述阵列基板具有存储电容区域；在存储电容区域，栅金属层（2）包括栅金属层存储图案（22）、有源层（4）包括有源层存储图案（42）、源漏金属层（9）包括源漏金属层存储图案（93）、像素电极层（11）包括像素电极层存储图案（112）；其中，所述栅金属层存储图案（22）、所述有源层存储图案（42）、所述源漏金属层存储图案（93）和所述像素电极层存储图案（112）在衬底（1）上的投影至少部分重合，且像素电极层存储图案（112）与栅金属层存储图案（22）电连接以构成存储电容的第一电极，有源层存储图案（42）与源漏金属层存储图案（93）电连接以构成存储电容的第二电极。

Description

一种阵列基板及其制备方法、显示装置及其制备方法
相关申请的交叉引用
本申请要求于2015年06月04日递交的中国专利申请第201510303519.1号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开文本涉及显示技术领域，具体涉及一种阵列基板及其制备方法、显示装置及其制备方法。
背景技术
近年来，显示技术得到快速的发展，如薄膜晶体管(Thin Film Transistor，简称TFT)技术由原来的非晶硅薄膜晶体管发展到现在的低温多晶硅薄膜晶体管、金属氧化物半导体薄膜晶体管等。而发光技术也由原来的液晶显示(Liquid Crystal Display，简称LCD)技术发展为现在的有机发光二极管显示(Organic Light-Emitting Diode，简称OLED)技术。
根据液晶显示器的原理，通过控制栅线的输入信号，位于同一行的薄膜晶体管被同时打开。在一定时间后，下一行的薄膜晶体管被同时打开，依次类推。然而，由于每一行薄膜晶体管打开的时间比较短，很难达到液晶的响应时间，从而会使液晶显示器出现闪烁现象。因此，为了避免这样的问题，目前一般通过存储电容避免液晶显示屏出现闪烁的现象。这样，在薄膜晶体管关闭之后的一定时间内，该存储电容便可以用于维持像素电极的电压，从而为液晶响应提供时间。
目前，为了满足液晶显示面板的高分辨率的需求，像素的尺寸做的越来越小，这样会引起存储电容的减小，使得液晶的响应时间不够，从而导致闪烁现象的发生，严重影响显示效果。然而如果增大存储电容，则占用面积较大的存储电容会影响像素的开口率。
发明内容
针对现有技术中的缺陷，本公开文本提供了一种阵列基板及其制备方法、显示装置及其制造方法。本公开文本的技术方案通过并联存储电容，有效减少了存储电容的占用面积，提高像素的开口率。
第一方面，本公开文本提供一种阵列基板，包括：衬底、栅金属层、有源层、源漏金属层、像素电极层，其中所述阵列基板具有存储电容区域；
在所述存储电容区域，所述栅金属层包括栅金属层存储图案、所述有源层包括有源层存储图案、所述源漏金属层包括源漏金属层存储图案、所述像素电极层包括像素电极层存储图案；
其中，所述栅金属层存储图案、所述有源层存储图案、所述源漏金属层存储图案和所述像素电极层存储图案在所述衬底上的投影至少部分重合，且所述像素电极层存储图案与所述栅金属层存储图案电连接以构成存储电容的第一电极，所述有源层存储图案与所述源漏金属层存储图案电连接以构成所述存储电容的第二电极。
可选的，所述有源层被设置在所述栅金属层上，所述源漏金属层被设置在所述有源层上，所述像素电极层被设置在所述源漏金属层上，并且其中，所述阵列基板还包括：设置在所述栅金属层和所述有源层之间的栅绝缘层，设置在所述有源层和所述源漏金属层之间的刻蚀阻挡层，以及设置在所述源漏金属层和所述像素电极层之间的钝化层。
可选的，在所述存储电容区域，所述像素电极层存储图案通过在所述钝化层、刻蚀阻挡层和栅绝缘层中的第一过孔与所述栅金属层存储图案电连接；
所述源漏金属层存储图案通过在所述刻蚀阻挡层中的第二过孔与所述有源层存储图案电连接。
可选的，所述存储电容区域中的有源层存储图案为通过等离子处理或离子注入后的有源层存储图案。
在一种实施方案中，所述栅绝缘层、所述刻蚀阻挡层和所述钝化层分 别包括硅的氧化物、硅的氮化物、铪的氧化物、硅的氮氧化物和铝的氧化物中的至少一种；所述衬底包括玻璃基板、石英基板和有机树脂基板中的至少一种；
所述栅金属层包括钼、钼铌合金、铝、铝钕合金、钛和铜中的至少一种；
所述有源层包括透明金属氧化物半导体；
所述源漏金属层包括钼、钼铌合金、铝、铝钕合金、钛和铜中的至少一种；
所述像素电极层包括透明导电金属氧化物。
第二方面，本公开文本还提供了一种阵列基板的制备方法，包括：在衬底上形成栅金属层、有源层、源漏金属层、像素电极层其中，所述阵列基板具有存储电容区域；
其中，在所述存储电容区域，所述栅金属层包括栅金属层存储图案、所述有源层包括有源层存储图案、所述源漏金属层包括源漏金属层存储图案、所述像素电极层包括像素电极层存储图案，
并且其中，所述栅金属层存储图案、所述有源层存储图案、所述源漏金属层存储图案和所述像素电极层存储图案在所述衬底上的投影至少部分重合，且所述像素电极层存储图案与所述栅金属层存储图案电连接以构成存储电容的第一电极，所述有源层存储图案与所述源漏金属层存储图案电连接以构成所述存储电容的第二电极。
可选的，所述方法进一步包括，在所述栅金属层上设置所述有源层，在所述有源层上设置所述源漏金属层，在所述源漏金属层上设置所述像素电极层，并且其中，所述方法还包括：
在所述栅金属层和所述有源层之间形成栅绝缘层，在所述有源层和所述源漏金属层之间形成刻蚀阻挡层，以及在所述源漏金属层和所述像素电极层之间形成钝化层。
可选的，在形成所述刻蚀阻挡层之前，对预形成在所述存储电容区域中的有源层存储图案进行等离子处理或离子注入处理。
可选的，在形成所述钝化层之后，形成在所述钝化层、刻蚀阻挡层和栅绝缘层中的第一过孔，用于使所述存储电容区域的像素电极层存储图案与栅金属层存储图案电连接。
可选的，在形成所述刻蚀阻挡层之后，在所述刻蚀阻挡层中形成第二过孔，用于使所述存储电容区域的源漏金属层存储图案与所述有源层存储图案电连接。
在一种实施方式中，所述栅绝缘层、所述刻蚀阻挡层和所述钝化层分别包括硅的氧化物、硅的氮化物、铪的氧化物、硅的氮氧化物和铝的氧化物中的至少一种；
所述衬底包括玻璃基板、石英基板和有机树脂基板中的至少一种；
所述栅金属层包括钼、钼铌合金、铝、铝钕合金、钛和铜中的至少一种；
所述有源层包括透明金属氧化物半导体；
所述源漏金属层包括钼、钼铌合金、铝、铝钕合金、钛和铜中的至少一种；
所述像素电极层包括透明导电金属氧化物。
第三方面，本公开文本还提供了一种显示装置，包括上述的阵列基板。
第四方面，本公开文本还提供了一种显示装置的制备方法，包括上述的阵列基板的制备方法。
由上述技术方案可知，本公开文本提供的一种阵列基板及其制备方法、显示装置及其制备方案，该阵列基板中的存储电容采用两个存储电容并联的方式，且两个存储电容在衬底上的投影重合，进而减少了两个并联存储电容的占用面积，提高了像素的开口率。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1至图9为本公开文本一实施例提供的制备阵列基板的过程示意图；
其中附图标记说明：
1、衬底；2、栅金属层；3、栅绝缘层；4、有源层；5、光刻胶完全保留区域；6、光刻胶完全去除区域；7、光刻胶半保留区域；8、刻蚀阻挡层；9、源漏金属层；10、钝化层；11、像素电极层；12、第一过孔；13、第二过孔；14、第三过孔；15、第四过孔；16、第五过孔；21、栅极图案；22、栅金属层存储图案；41、有源层图案；42、有源层存储图案；91、源极图案；92、漏极图案；93、源漏金属层存储图案；111、像素电极图案；112、像素电极层存储图案。
具体实施方式
除非上下文中另外明确地指出，否则在本文和所附权利要求中所使用的词语的单数形式包括复数，反之亦然。因而，当提及单数时，通常包括相应术语的复数。相似地，措辞“包含”和“包括”将解释为包含在内而不是独占性地。同样地，术语“包括”和“或”应当解释为包括在内的，除非本文中明确禁止这样的解释。在本文中使用术语“实例”之处，特别是当其位于一组术语之后时，所述“实例”仅仅是示例性的和阐述性的，且不应当被认为是独占性的或广泛性的。
本公开文本提供了一种阵列基板，参见图9所示，该阵列基板包括：衬底1、栅金属层2、有源层4、源漏金属层9、像素电极层11、以及存储电容区域；
在存储电容区域，上述栅金属层2包括栅金属层存储图案22、有源层4包括有源层存储图案42、源漏金属层9包括源漏金属层存储图案93、像素电极层11包括像素电极层存储图案112；
其中，栅金属层存储图案22、有源层存储图案42、源漏金属层存储图案93和像素电极层存储图案112在衬底1上的投影至少部分重合，且像素电极层存储图案112与栅金属层存储图案22电连接构成存储电容的第一电 极，有源层存储图案42与源漏金属层存储图案93电连接构成存储电容的第二电极。
上述阵列基板中的存储电容采用两个存储电容并联的方式，其中栅金属层存储图案22与有源层存储图案42构成一个存储电容，源漏金属层存储图案93与像素电极层存储图案112构成另外一个存储电容，且两个存储电容在同一存储电容区域并联，在衬底上的投影重合，进而减少了两个并联存储电容的占用面积，提高了像素的开口率。
为了形成上述两个存储电容，故上述阵列基板还包括：设置在栅金属层2和有源层4之间的栅绝缘层3，设置在有源层4和源漏金属层9之间的刻蚀阻挡层8，以及设置在源漏金属层9和像素电极层11之间的钝化层10。
可理解的是，上述栅绝缘层3、刻蚀阻挡层8和钝化层10均为绝缘的，其材质可以为由硅的氧化物(SiOx)、硅的氮化物(SiNx)、铪的氧化物(HfOx)、硅的氮氧化物(SiON)、AlOx等中的一种或两种组成的多层复合膜组成。例如钝化层10的两层结构可以为SiNx/SiOx的叠层结构，也可以为SiNx/SiON/SiOx的叠层结构，膜层的总厚度可以控制在100～600nm左右，至于各膜层厚度可依照实际情况做调整。上述的栅绝缘层3和刻蚀阻挡层8与钝化层10类似，本实施例不进行详细说明。
在形成存储电容的第一电极和第二电极时，例如可以通过在存储电容区域，像素电极层存储图案111通过贯穿钝化层10、刻蚀阻挡层8和栅绝缘层3上的第一过孔12与栅金属层存储图案22电连接；
源漏金属层存储图案93通过贯穿刻蚀阻挡层8上的第二过孔13与有源层存储图案42电连接。
需要说明的是，由于上述有源层4的材质为氧化物半导体，故为了使该有源层4形成的有源层存储图案42能够作为存储电容的一个电极，该有源层存储图案42可以理解为通过等离子处理或离子注入后处理为导体的有源层存储图案。
本公开文本实施例还提供了一种阵列基板的制备方法，该方法包括： 在衬底1上形成栅金属层2、有源层4、源漏金属层9、像素电极层11、以及存储电容区域；
其中，在存储电容区域，栅金属层2包括栅金属层存储图案22、有源层4包括有源层存储图案42、源漏金属层9包括源漏金属层存储图案93、像素电极层11包括像素电极层存储图案112；栅金属层存储图案22、有源层存储图案42、源漏金属层存储图案93和像素电极层存储图案112在衬底1上的投影至少部分重合，且像素电极层存储图案112与栅金属层存储图案22电连接构成存储电容的第一电极，有源层存储图案42与源漏金属层存储图案93电连接构成所述存储电容的第二电极。
上述方法中在存储电容区域形成存储电容采用两个存储电容并联的方式，其中栅金属层存储图案22与有源层存储图案42构成一个存储电容，源漏金属层存储图案93与像素电极层存储图案112构成另外一个存储电容，且两个存储电容在同一存储电容区域，在衬底上的投影重合，进而减少了两个并联存储电容的占用面积，提高了像素的开口率。
下面通过具体的实施例对上述阵列基板的制备方法的过程进行详细说明，该阵列基板的制备方法的流程可以包括以下步骤：
步骤S1、在衬底1上形成栅金属层2，如图1所示。
举例来说，上述的衬底1可以为玻璃基板、石英基板或有机树脂基板；栅金属层2的材质可以为钼(Mo)、钼铌合金(MoNb)、铝(Al)、铝钕合金(AlNd)、钛(Ti)和铜(Cu)中的一种或多种材料形成的单层或多层复合叠层，优先为Mo、Al或含Mo、Al的合金组成的单层或多层复合膜。在一种实施方式中，厚度为100nm～500nm。
上述栅金属层2可以利用溅射或热蒸发的方式在衬底1上沉积一层栅金属层。
步骤S2、通过一次构图工艺形成栅极图案21和栅金属层存储图案22，如图2所示。
上述构图工艺可以理解为，在上述步骤S1沉积的栅金属层2上涂覆一层光刻胶，利用掩膜板对涂覆的光刻胶进行曝光和显影处理，然后混合 酸液去除无光刻胶区域的栅金属层2，最后将光刻胶剥离，形成如图2所示的栅极图案21和栅金属层存储图案22。
步骤S3、在栅极图案21和栅金属层存储图案22、以及衬底1上沉积栅绝缘层3，如图3所示。
在本实施例中，栅绝缘层3的材质可以由硅的氧化物(SiOx)、硅的氮化物(SiNx)、铪的氧化物(HfOx)、硅的氮氧化物(SiON)、AlOx等中的一种或两种组成的多层复合膜组成。栅绝缘层3用等离子体增强化学气相沉积法PECVD，即Plasma Enhanced Chemical Vapor Deposition制作，且在制作过程中，需控制膜层的氢含量在较低的水平。例如栅绝缘层二代结构可以为SiNx/SiOx的叠层结构，也可以为SiNx/SiON/SiOx的叠层结构。膜层的总厚度可以控制在100～600nm左右，至于各膜层厚度可依照实际情况做调整。
步骤S4、在栅绝缘层3上沉积有源层4，以及在有源层4上形成一层光刻胶。
上述有源层的材质可以为采用铟镓锌氧化物(Indium Gallium Zinc Oxide，简称IGZO)、铟锡锌氧化物(Indium Tin Zinc Oxide，简称ITZO)、氧化铟(In2O3)、以及氧化锌(ZnO)等透明金属氧化物半导体材料中的至少一种，厚度可以控制在10-150nm。
步骤S5、利用灰阶掩膜板通过曝光显影工艺后形成完全曝光区域、未曝光区域以及灰度曝光区域，去掉完全曝光区域的光刻胶(光刻胶完全去除区域6)，以及灰度曝光区域的部分光刻胶(光刻胶半保留区域7)，如图4所示；
可理解的是，灰阶掩膜板包括完全不透明部分、半透明部分和完全透明部分。即灰阶掩膜板是指在透明衬底材料上在某些区域形成不透光的遮光金属层，在另外一些区域形成半透光的遮光金属层，其他区域不形成任何遮光金属层。其中，半透光的遮光金属层的厚度小于完全不透光的遮光金属层的厚度。此外，还可以通过调节半透光的遮光金属层的厚度来改变半透光的遮光金属层对紫外光的透过率。
基于此，灰阶掩膜板的工作原理说明如下：通过控制灰阶掩膜板上下不同区域处遮光金属层的厚度，使曝光在不同区域的透过光的强度有所不同，从而使光刻胶进行有选择性的曝光显影后，形成与灰阶掩膜板的完全不透明部分、半透明部分以及完全透明部分分别对应的未曝光区域、灰度曝光区域和完全曝光区域。
本实施例中所指的光刻胶均为正性光刻胶，可以为由感光树脂、增感剂和溶剂三种主要成分组成的对光敏感的混合液体。感光树脂经过光照后，在曝光区域能很快地发生光固化反应，后续通过特定的溶液可以将固化的感光树脂清洗掉。
步骤S6、刻蚀完全曝光区域对应的有源层4，如图5所示。
步骤S7、剥离灰度曝光区域的光刻胶，并对露出的预形成的有源层存储图案的半导体通过等离子处理(H-plasma处理)或离子注入后处理为导体的有源层存储图案42，如图6所示。
上述剥离灰度曝光区域的光刻胶可以通过刻蚀的方法也可以再次通过上述灰阶掩膜板再一次曝光显影，将灰度曝光区域的光刻胶剥离，本实施例不对其具体的实施方式进行限定。
步骤S8、去掉未曝光区域的光刻胶(光刻胶完全保留区域5)，形成有源层图案41，并在有源层图案41以及有源层存储图案42上形成刻蚀阻挡层8，通过一次构图工艺形成第二过孔13、第三过孔14和第四过孔15，如图7所示。
可理解的是，上述构图工艺与步骤S2类似，本实施例不再进行详细说明。
另外，上述第二过孔13可以理解为预形成存储电容一个电极的过孔，上述第三过孔14和第四过孔15可以理解为形成在有源层图案41的相对位置上，预将有源层图案41与源极图案91和漏极图案92电连接的过孔。
步骤S9、在刻蚀阻挡层8上沉积源漏金属层9，并通过一次构图工艺形成源极图案91、漏极图案92和源漏金属层存储图案93，如图8所示。
上述源漏金属层9的材质可以为钼(Mo)、钼铌合金(MoNb)、铝(Al)、 铝钕合金(AlNd)、钛(Ti)和铜(Cu)中的一种或多种材料形成的单层或多层复合叠层，优先为Mo、Al或含Mo、Al的合金组成的单层或多层复合膜。
其中，形成源极图案91、漏极图案92和源漏金属层存储图案93的构图工艺可以与步骤S2类似，本实施例不进行详细说明。
可理解的是，上述源极图案91和漏极图案92的位置也可以互换，根据电流的流向不同，该位置也不同。
步骤S10、沉积钝化层10，并在形成钝化层10之后，形成贯穿钝化层10、刻蚀阻挡层8和栅绝缘层3的第一过孔12，用于使存储电容区域的像素电极层存储图案112与栅金属层存储图案22电连接。
钝化层10的材质可以由硅的氧化物(SiOx)、硅的氮化物(SiNx)、铪的氧化物(HfOx)、硅的氮氧化物(SiON)、AlOx等中的一种或两种组成的多层复合膜组成。该钝化层10用等离子体增强化学气相沉积法PECVD，即Plasma Enhanced Chemical Vapor Deposition制作，且在制作过程中，需控制膜层的氢含量在较低的水平。例如钝化层10两层结构可以为SiNx/SiOx的叠层结构，也可以为SiNx/SiON/SiOx的叠层结构，膜层的总厚度可以控制在100～600nm左右，至于各膜层厚度可依照实际情况做调整。
步骤S11、形成像素电极层11，并通过一次构图工艺形成像素电极图案111和像素电极层存储图案112，如图9所示。
像素电极层11可以为透明的导电金属氧化物，如ITO、IZO等，可以通过溅射的方式进行沉积，沉积厚度可以为40-200nm。
形成像素电极图案111和像素电极层存储图案112的构图工艺可以与步骤S2类似，本实施例不进行详细说明。
可理解的是，上述阵列基板制备过程中，各层比如栅金属层2、栅绝缘层3、有源层4、刻蚀阻挡层8、源漏金属层9、钝化层10、像素电极层11等可以通过真空沉积或磁控溅射的方式形成，本实施例不再进行详细说明。
另外，需要说明的是，像素电极层11可以理解为包括栅极图案21和 栅金属层存储图案22或预形成栅极图案21和栅金属层存储图案22的层；有源层4可以理解为包括有源层图案41和有源层存储图案42或预形成有源层图案41和有源层存储图案42的层；源漏金属层为包括源极图案91、漏极图案92和源漏金属层存储图案93或预形成源极图案91、漏极图案92和源漏金属层存储图案93的层；像素电极层为包括像素电极图案111和像素电极层存储图案112或预形成像素电极图案111和像素电极层存储图案112的层。
本实施例还提供了一种显示装置，包括如上述的阵列基板。
本实施例中的显示装置可以为：手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开文本的说明书中，说明了大量具体细节。然而，能够理解，本公开文本的实施例可以在没有这些具体细节的情况下实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
本公开使用的技术术语或者科学术语应当为本公开文本所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
最后应说明的是：以上各实施例仅用以说明本公开文本的技术方案，而非对其限制；尽管参照前述各实施例对本公开文本进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这 些修改或者替换，并不使相应技术方案的本质脱离本公开文本各实施例技术方案的范围，其均应涵盖在本公开文本的权利要求和说明书的范围当中。

Claims (13)

  1. 一种阵列基板，包括：衬底、栅金属层、有源层、源漏金属层、像素电极层，其中所述阵列基板具有存储电容区域；
    在所述存储电容区域，所述栅金属层包括栅金属层存储图案、所述有源层包括有源层存储图案、所述源漏金属层包括源漏金属层存储图案、所述像素电极层包括像素电极层存储图案；
    其中，所述栅金属层存储图案、所述有源层存储图案、所述源漏金属层存储图案和所述像素电极层存储图案在所述衬底上的投影至少部分重合，且所述像素电极层存储图案与所述栅金属层存储图案电连接以构成存储电容的第一电极，所述有源层存储图案与所述源漏金属层存储图案电连接构成以所述存储电容的第二电极。
  2. 根据权利要求1所述的阵列基板，其中，所述有源层被设置在所述栅金属层上，所述源漏金属层被设置在所述有源层上，所述像素电极层被设置在所述源漏金属层上，并且其中，
    所述阵列基板还包括：设置在所述栅金属层和所述有源层之间的栅绝缘层，设置在所述有源层和所述源漏金属层之间的刻蚀阻挡层，以及设置在所述源漏金属层和所述像素电极层之间的钝化层。
  3. 根据权利要求2所述的阵列基板，其中，在所述存储电容区域，所述像素电极层存储图案通过在所述钝化层、刻蚀阻挡层和栅绝缘层中的第一过孔与所述栅金属层存储图案电连接；
    所述源漏金属层存储图案通过在所述刻蚀阻挡层中的第二过孔与所述有源层存储图案电连接。
  4. 根据权利要求1-3中任一项所述的阵列基板，其中，所述存储电容区域中的有源层存储图案为通过等离子处理或离子注入后的有源层存储图案。
  5. 根据权利要求2-4中任一项所述的阵列基板，其中，
    所述栅绝缘层、所述刻蚀阻挡层和所述钝化层分别包括硅的氧化物、硅的氮化物、铪的氧化物、硅的氮氧化物和铝的氧化物中的至少一种；所 述衬底包括玻璃基板、石英基板和有机树脂基板中的至少一种；
    所述栅金属层包括钼、钼铌合金、铝、铝钕合金、钛和铜中的至少一种；
    所述有源层包括透明金属氧化物半导体；
    所述源漏金属层包括钼、钼铌合金、铝、铝钕合金、钛和铜中的至少一种；
    所述像素电极层包括透明导电金属氧化物。
  6. 一种阵列基板的制备方法，包括：在衬底上形成栅金属层、有源层、源漏金属层、像素电极层，其中，所述阵列基板具有存储电容区域；
    其中，在所述存储电容区域，所述栅金属层包括栅金属层存储图案、所述有源层包括有源层存储图案、所述源漏金属层包括源漏金属层存储图案、所述像素电极层包括像素电极层存储图案，
    并且其中，所述栅金属层存储图案、所述有源层存储图案、所述源漏金属层存储图案和所述像素电极层存储图案在所述衬底上的投影至少部分重合，且所述像素电极层存储图案与所述栅金属层存储图案电连接以构成存储电容的第一电极，所述有源层存储图案与所述源漏金属层存储图案电连接以构成所述存储电容的第二电极。
  7. 根据权利要求6所述的方法，进一步包括，在所述栅金属层上设置所述有源层，在所述有源层上设置所述源漏金属层，在所述源漏金属层上设置所述像素电极层，并且其中，所述方法还包括：
    在所述栅金属层和所述有源层之间形成栅绝缘层，在所述有源层和所述源漏金属层之间形成刻蚀阻挡层，以及在所述源漏金属层和所述像素电极层之间形成钝化层。
  8. 根据权利要求7所述的方法，进一步包括，在形成所述刻蚀阻挡层之前，对预形成在所述存储电容区域中的有源层存储图案进行等离子处理或离子注入处理。
  9. 根据权利要求7所述的方法，进一步包括，在形成所述钝化层之后，形成在所述钝化层、刻蚀阻挡层和栅绝缘层中的第一过孔，用于使所述存 储电容区域的像素电极层存储图案与栅金属层存储图案电连接。
  10. 根据权利要求7所述的方法，进一步包括，在形成所述刻蚀阻挡层之后，在所述刻蚀阻挡层中形成第二过孔，用于使所述存储电容区域的源漏金属层存储图案与所述有源层存储图案电连接。
  11. 根据权利要求7-10中任一项所述的方法，其中，所述栅绝缘层、所述刻蚀阻挡层和所述钝化层分别包括硅的氧化物、硅的氮化物、铪的氧化物、硅的氮氧化物和铝的氧化物中的至少一种；
    所述衬底包括玻璃基板、石英基板和有机树脂基板中的至少一种；
    所述栅金属层包括钼、钼铌合金、铝、铝钕合金、钛和铜中的至少一种；
    所述有源层包括透明金属氧化物半导体；
    所述源漏金属层包括钼、钼铌合金、铝、铝钕合金、钛和铜中的至少一种；
    所述像素电极层包括透明导电金属氧化物。
  12. 一种显示装置，，包括如权利要求1-5中任一项所述的阵列基板。
  13. 一种显示装置的制备方法，包括如权利要求6-11中任一项所述的阵列基板的制备方法。
PCT/CN2016/079359 2015-06-04 2016-04-15 一种阵列基板及其制备方法、显示装置及其制备方法 WO2016192471A1 (zh)

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