CN104965362A - 一种阵列基板及其制备方法、显示装置 - Google Patents
一种阵列基板及其制备方法、显示装置 Download PDFInfo
- Publication number
- CN104965362A CN104965362A CN201510303519.1A CN201510303519A CN104965362A CN 104965362 A CN104965362 A CN 104965362A CN 201510303519 A CN201510303519 A CN 201510303519A CN 104965362 A CN104965362 A CN 104965362A
- Authority
- CN
- China
- Prior art keywords
- metal level
- stored pattern
- layer
- source
- active layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
Abstract
本发明公开了一种阵列基板及其制备方法、显示装置,该阵列基板包括:衬底、栅金属层、有源层、源漏金属层、像素电极层、以及存储电容区域;在存储电容区域,栅金属层包括栅金属层存储图案、有源层包括有源层存储图案、源漏金属层包括源漏金属层存储图案、像素电极层包括像素电极层存储图案;栅金属层存储图案、有源层存储图案、源漏金属层存储图案和像素电极层存储图案在衬底上的投影至少部分重合,且像素电极层存储图案与栅金属层存储图案电连接构成存储电容的第一电极,有源层存储图案与源漏金属层存储图案电连接构成存储电容的第二电极。采用两个存储电容并联的方式,进而减少了存储电容的占用面积,提高了像素的开口率。
Description
技术领域
本发明涉及显示技术领域,具体涉及一种阵列基板及其制备方法、显示装置。
背景技术
近年来,显示技术得到快速的发展,如薄膜晶体管(Thin FilmTransistor,简称TFT)技术由原来的非晶硅薄膜晶体管发展到现在的低温多晶硅薄膜晶体管、金属氧化物半导体薄膜晶体管等。而发光技术也由原来的液晶显示(Liquid Crystal Display,简称LCD)技术发展为现在的有机发光二极管显示(Organic Light-Emitting Diode,简称OLED)技术。
根据液晶显示器的原理,通过控制栅线的输入信号,位于同一行的薄膜晶体管被同时打开,在一定时间后,下一行的薄膜晶体管被同时打开,依次类推。然而,由于每一行薄膜晶体管打开的时间比较短,很难达到液晶的响应时间,从而会使液晶显示器出现闪烁现象。因此,为了避免这样的问题,目前一般通过存储电容避免液晶显示屏出现闪烁的现象。这样,在薄膜晶体管关闭之后的一定时间内,该存储电容便可以用于维持像素电极的电压,从而为液晶响应提供时间。
目前,为了满足液晶显示面板的高分辨率的需求,像素的尺寸做的越来越小,这样会引起存储电容的减小,使得液晶的响应时间不够,从而导致闪烁现象的发生,严重影响显示效果。然而如果增大存储电容,则占用面积较大的存储电容会影响像素的开口率。
发明内容
针对现有技术中的缺陷,本发明提供了一种阵列基板及其制备方法、显示装置,通过并联存储电容,有效减少了存储电容的占用面积,提高像素的开口率。
第一方面,本发明提供一种阵列基板,包括:衬底、栅金属层、有源层、源漏金属层、像素电极层、以及存储电容区域;
在所述存储电容区域,所述栅金属层包括栅金属层存储图案、所述有源层包括有源层存储图案、所述源漏金属层包括源漏金属层存储图案、所述像素电极层包括像素电极层存储图案;
其中,所述栅金属层存储图案、有源层存储图案、源漏金属层存储图案和像素电极层存储图案在所述衬底上的投影至少部分重合,且所述像素电极层存储图案与所述栅金属层存储图案电连接构成存储电容的第一电极,所述有源层存储图案与所述源漏金属层存储图案电连接构成所述存储电容的第二电极。
可选的,所述阵列基板还包括:设置在所述栅金属层和所述有源层之间的栅绝缘层,设置在所述有源层和所述源漏金属层之间的刻蚀阻挡层,以及设置在所述源漏金属层和所述像素电极层之间的钝化层。
可选的,在所述存储电容区域,所述像素电极层存储图案通过贯穿所述钝化层、刻蚀阻挡层和栅绝缘层上的第一过孔与所述栅金属层存储图案电连接;
所述源漏金属层存储图案通过贯穿所述刻蚀阻挡层上的第二过孔与所述有源层存储图案电连接。
可选的,所述存储电容区域中的有源层存储图案为通过等离子处理或离子注入后的有源层存储图案。
第二方面,本发明还提供了一种阵列基板的制备方法,包括:在衬底上形成栅金属层、有源层、源漏金属层、像素电极层、以及存储电容区域;
其中,在所述存储电容区域,所述栅金属层包括栅金属层存储图案、所述有源层包括有源层存储图案、所述源漏金属层包括源漏金属层存储图案、所述像素电极层包括像素电极层存储图案,所述栅金属层存储图案、有源层存储图案、源漏金属层存储图案和像素电极层存储图案在所述衬底上的投影至少部分重合,且所述像素电极层存储图案与所述栅金属层存储图案电连接构成存储电容的第一电极,所述有源层存储图案与所述源漏金属层存储图案电连接构成所述存储电容的第二电极。
可选的,所述方法还包括:
在所述栅金属层和所述有源层之间形成栅绝缘层,在所述有源层和所述源漏金属层之间形成刻蚀阻挡层,以及在所述源漏金属层和所述像素电极层之间形成钝化层。
可选的,在形成所述刻蚀阻挡层之前,对预形成在所述存储电容区域中的有源层存储图案进行等离子处理或离子注入处理。
可选的,在形成所述钝化层之后,形成贯穿所述钝化层、刻蚀阻挡层和栅绝缘层的第一过孔,用于使所述存储电容区域的像素电极层存储图案与栅金属层存储图案电连接。
可选的,在形成所述刻蚀阻挡层之后,在所述刻蚀阻挡层上形成第二过孔,用于使所述存储电容区域的源漏金属层存储图案与所述有源层存储图案电连接。
第三方面,本发明还提供了一种显示装置,包括上述的阵列基板。
由上述技术方案可知,本发明提供的一种阵列基板及其制备方法、显示装置,该阵列基板中的存储电容采用两个存储电容并联的方式,且两个存储电容在衬底上的投影重合,进而减少了两个并联存储电容的占用面积,提高了像素的开口率。
附图说明
图1至图9为本发明一实施例提供的制备阵列基板的过程示意图;
其中附图标记说明:
1、衬底;2、栅金属层;3、栅绝缘层;4、有源层;5、光刻胶完全保留区域;6、光刻胶完全去除区域;7、光刻胶半保留区域;8、刻蚀阻挡层;9、源漏金属层;10、钝化层;11、像素电极层;12、第一过孔;13、第二过孔;14、第三过孔;15、第四过孔;16、第五过孔;21、栅极图案;22、栅金属层存储图案;41、有源层图案;42、有源层存储图案;91、源极图案;92、漏极图案;93、源漏金属层存储图案;111、像素电极图案;112、像素电极层存储图案。
具体实施方式
下面结合附图,对发明的具体实施方式作进一步描述。以下实施例仅用于更加清楚地说明本发明的技术方案,而不能以此来限制本发明的保护范围。
本发明提供了一种阵列基板,如图9所示,包括:衬底1、栅金属层2、有源层4、源漏金属层9、像素电极层11、以及存储电容区域;
在存储电容区域,上述栅金属层2包括栅金属层存储图案22、有源层4包括有源层存储图案42、源漏金属层9包括源漏金属层存储图案93、像素电极层11包括像素电极层存储图案112;
其中,栅金属层存储图案22、有源层存储图案42、源漏金属层存储图案93和像素电极层存储图案112在衬底1上的投影至少部分重合,且像素电极层存储图案112与栅金属层存储图案22电连接构成存储电容的第一电极,有源层存储图案42与源漏金属层存储图案93电连接构成存储电容的第二电极。
上述阵列基板中的存储电容采用两个存储电容并联的方式,其中栅金属层存储图案22与有源层存储图案42构成一个存储电容,源漏金属层存储图案93与像素电极层存储图案112构成另外一个存储电容,且两个存储电容在同一存储电容区域并联,在衬底上的投影重合,进而减少了两个并联存储电容的占用面积,提高了像素的开口率。
为了形成上述两个存储电容,故上述阵列基板还包括:设置在栅金属层2和有源层4之间的栅绝缘层3,设置在有源层4和源漏金属层9之间的刻蚀阻挡层8,以及设置在源漏金属层9和像素电极层11之间的钝化层10。
可理解的是,上述栅绝缘层3、刻蚀阻挡层8和钝化层10均为绝缘的,其材质可以为由硅的氧化物(SiOx)、硅的氮化物(SiNx)、铪的氧化物(HfOx)、硅的氮氧化物(SiON)、AlOx等中的一种或两种组成的多层复合膜组成。例如钝化层10的两层结构可以为SiNx/SiOx的叠层结构,也可以为SiNx/SiON/SiOx的叠层结构,膜层的总厚度可以控制在100~600nm左右,至于各膜层厚度可依照实际情况做调整。上述的栅绝缘层3和刻蚀阻挡层8与钝化层10类似,本实施例不进行详细说明。
在形成存储电容的第一电极和第二电极时,例如可以通过在存储电容区域,像素电极层存储图案111通过贯穿钝化层10、刻蚀阻挡层8和栅绝缘层3上的第一过孔12与栅金属层存储图案22电连接;
源漏金属层存储图案93通过贯穿刻蚀阻挡层8上的第二过孔13与有源层存储图案42电连接。
需要说明的是,由于上述有源层4的材质为氧化物半导体,故为了使该有源层4形成的有源层存储图案42能够作为存储电容的一个电极,该有源层存储图案42可以理解为通过等离子处理或离子注入后处理为导体的有源层存储图案。
本发明实施例还提供了一种阵列基板的制备方法,该方法包括:在衬底1上形成栅金属层2、有源层4、源漏金属层9、像素电极层11、以及存储电容区域;
其中,在存储电容区域,栅金属层2包括栅金属层存储图案22、有源层4包括有源层存储图案42、源漏金属层9包括源漏金属层存储图案93、像素电极层11包括像素电极层存储图案112;栅金属层存储图案22、有源层存储图案42、源漏金属层存储图案93和像素电极层存储图案112在衬底1上的投影至少部分重合,且像素电极层存储图案112与栅金属层存储图案22电连接构成存储电容的第一电极,有源层存储图案42与源漏金属层存储图案93电连接构成所述存储电容的第二电极。
上述方法中在存储电容区域形成存储电容采用两个存储电容并联的方式,其中栅金属层存储图案22与有源层存储图案42构成一个存储电容,源漏金属层存储图案93与像素电极层存储图案112构成另外一个存储电容,且两个存储电容在同一存储电容区域,在衬底上的投影重合,进而减少了两个并联存储电容的占用面积,提高了像素的开口率。
下面通过具体的实施例对上述阵列基板的制备方法的过程进行详细说明,该阵列基板的制备方法的流程可以包括以下步骤:
步骤S1、在衬底1上形成栅金属层2,如图1所示。
举例来说,上述的衬底1可以为玻璃基板、石英基板或有机树脂基板;栅金属层2的材质可以为钼(Mo)、钼铌合金(MoNb)、铝(Al)、铝钕合金(AlNd)、钛(Ti)和铜(Cu)中的一种或多种材料形成的单层或多层复合叠层,优先为Mo、Al或含Mo、Al的合金组成的单层或多层复合膜;厚度为100nm~500nm。
上述栅金属层2可以利用溅射或热蒸发的方式在衬底1上沉积一层栅金属层。
步骤S2、通过一次构图工艺形成栅极图案21和栅金属层存储图案22,如图2所示。
上述构图工艺可以理解为,在上述步骤S1沉积的栅金属层2上涂覆一层光刻胶,利用掩膜板对涂覆的光刻胶进行曝光和显影处理,然后混合酸液去除无光刻胶区域的栅金属层2,最后将光刻胶剥离,形成如图2所示的栅极图案21和栅金属层存储图案22。
步骤S3、在栅极图案21和栅金属层存储图案22、以及衬底1上沉积栅绝缘层3,如图3所示。
在本实施例中,栅绝缘层3的材质可以由硅的氧化物(SiOx)、硅的氮化物(SiNx)、铪的氧化物(HfOx)、硅的氮氧化物(SiON)、AlOx等中的一种或两种组成的多层复合膜组成。栅绝缘层3用等离子体增强化学气相沉积法PECVD,即Plasma Enhanced ChemicalVapor Deposition制作,且在制作过程中,需控制膜层的氢含量在较低的水平。例如栅绝缘层二代结构可以为SiNx/SiOx的叠层结构,也可以为SiNx/SiON/SiOx的叠层结构,膜层的总厚度可以控制在100~600nm左右,至于各膜层厚度可依照实际情况做调整。
步骤S4、在栅绝缘层3上沉积有源层4,以及在有源层4上形成一层光刻胶。
上述有源层的材质可以为采用铟镓锌氧化物(Indium GalliumZinc Oxide,简称IGZO)、铟锡锌氧化物(Indium Tin Zinc Oxide,简称ITZO)、氧化铟(In2O3)、以及氧化锌(ZnO)等透明金属氧化物半导体材料中的至少一种,厚度控制在10-150nm。
步骤S5、利用灰阶掩膜板通过曝光显影工艺后形成完全曝光区域、未曝光区域以及灰度曝光区域,去掉完全曝光区域的光刻胶(光刻胶完全去除区域6),以及灰度曝光区域的部分光刻胶(光刻胶半保留区域7),如图4所示;
可理解的是,灰阶掩膜板包括完全不透明部分、半透明部分和完全透明部分;即灰阶掩膜板是指在透明衬底材料上在某些区域形成不透光的遮光金属层,在另外一些区域形成半透光的遮光金属层,其他区域不形成任何遮光金属层;其中,半透光的遮光金属层的厚度小于完全不透光的遮光金属层的厚度,此外,还可以通过调节半透光的遮光金属层的厚度来改变半透光的遮光金属层对紫外光的透过率。
基于此,灰阶掩膜板的工作原理说明如下:通过控制灰阶掩膜板上下不同区域处遮光金属层的厚度,使曝光在不同区域的透过光的强度有所不同,从而使光刻胶进行有选择性的曝光显影后,形成与灰阶掩膜板的完全不透明部分、半透明部分以及完全透明部分分别对应的未曝光区域、灰度曝光区域和完全曝光区域。
本实施例中所指的光刻胶均为正性光刻胶,可以为由感光树脂、增感剂和溶剂三种主要成分组成的对光敏感的混合液体。感光树脂经过光照后,在曝光区域能很快地发生光固化反应,后续通过特定的溶液可以将固化的感光树脂清洗掉。
步骤S6、刻蚀完全曝光区域对应的有源层4,如图5所示。
步骤S7、剥离灰度曝光区域的光刻胶,并对露出的预形成的有源层存储图案的半导体通过等离子处理(H-plasma处理)或离子注入后处理为导体的有源层存储图案42,如图6所示。
上述剥离灰度曝光区域的光刻胶可以通过刻蚀的方法也可以再次通过上述灰阶掩膜板再一次曝光显影,将灰度曝光区域的光刻胶剥离,本实施例不对其具体的实施方式进行限定。
步骤S8、去掉未曝光区域的光刻胶(光刻胶完全保留区域5),形成有源层图案41,并在有源层图案41以及有源层存储图案42上形成刻蚀阻挡层8,通过一次构图工艺形成第二过孔13、第三过孔14和第四过孔15,如图7所示。
可理解的是,上述构图工艺与步骤S2类似,本实施例不再进行详细说明。
另外,上述第二过孔13可以理解为预形成存储电容一个电极的过孔,上述第三过孔14和第四过孔15可以理解为形成在有源层图案41的相对位置上,预将有源层图案41与源极图案91和漏极图案92电连接的过孔。
步骤S9、在刻蚀阻挡层8上沉积源漏金属层9,并通过一次构图工艺形成源极图案91、漏极图案92和源漏金属层存储图案93,如图8所示。
上述源漏金属层9的材质可以为钼(Mo)、钼铌合金(MoNb)、铝(Al)、铝钕合金(AlNd)、钛(Ti)和铜(Cu)中的一种或多种材料形成的单层或多层复合叠层,优先为Mo、Al或含Mo、Al的合金组成的单层或多层复合膜。
其中,形成源极图案91、漏极图案92和源漏金属层存储图案93的构图工艺可以与步骤S2类似,本实施例不进行详细说明。
可理解的是,上述源极图案91和漏极图案92的位置也可以互换,根据电流的流向不同,该位置也不同。
步骤S10、沉积钝化层10,并在形成钝化层10之后,形成贯穿钝化层10、刻蚀阻挡层8和栅绝缘层3的第一过孔12,用于使存储电容区域的像素电极层存储图案112与栅金属层存储图案22电连接。
钝化层10的材质可以由硅的氧化物(SiOx)、硅的氮化物(SiNx)、铪的氧化物(HfOx)、硅的氮氧化物(SiON)、AlOx等中的一种或两种组成的多层复合膜组成。该钝化层10用等离子体增强化学气相沉积法PECVD,即Plasma Enhanced Chemical Vapor Deposition制作,且在制作过程中,需控制膜层的氢含量在较低的水平。例如钝化层10两层结构可以为SiNx/SiOx的叠层结构,也可以为SiNx/SiON/SiOx的叠层结构,膜层的总厚度可以控制在100~600nm左右,至于各膜层厚度可依照实际情况做调整。
步骤S11、形成像素电极层11,并通过一次构图工艺形成像素电极图案111和像素电极层存储图案112,如图9所示。
像素电极层11可以为透明的导电金属氧化物,如ITO,IZO等,可以通过溅射的方式进行沉积,沉积厚度可以为40-200nm。
形成像素电极图案111和像素电极层存储图案112的构图工艺可以与步骤S2类似,本实施例不进行详细说明。
可理解的是,上述阵列基板制备过程中,各层比如栅金属层2、栅绝缘层3、有源层4、刻蚀阻挡层8、源漏金属层9、钝化层10、像素电极层11等可以通过真空沉积或磁控溅射的方式形成,本实施例不再进行详细说明。
另外,需要说明的是,像素电极层11可以理解为包括栅极图案21和栅金属层存储图案22或预形成栅极图案21和栅金属层存储图案22的层;有源层4可以理解为包括有源层图案41和有源层存储图案42或预形成有源层图案41和有源层存储图案42的层;源漏金属层为包括源极图案91、漏极图案92和源漏金属层存储图案93或预形成源极图案91、漏极图案92和源漏金属层存储图案93的层;像素电极层为包括像素电极图案111和像素电极层存储图案112或预形成像素电极图案111和像素电极层存储图案112的层。
本实施例还提供了一种显示装置,包括如上述的阵列基板。
本实施例中的显示装置可以为:手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本发明的说明书中,说明了大量具体细节。然而,能够理解,本发明的实施例可以在没有这些具体细节的情况下实践。在一些实例中,并未详细示出公知的方法、结构和技术,以便不模糊对本说明书的理解。
本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性,而只是用来区分不同的组成部分。同样,“一个”、“一”或者“该”等类似词语也不表示数量限制,而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同,而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接,而是可以包括电性的连接,不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系,当被描述对象的绝对位置改变后,则该相对位置关系也可能相应地改变。
最后应说明的是:以上各实施例仅用以说明本发明的技术方案,而非对其限制;尽管参照前述各实施例对本发明进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分或者全部技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本发明各实施例技术方案的范围,其均应涵盖在本发明的权利要求和说明书的范围当中。
Claims (10)
1.一种阵列基板,其特征在于,包括:衬底、栅金属层、有源层、源漏金属层、像素电极层、以及存储电容区域;
在所述存储电容区域,所述栅金属层包括栅金属层存储图案、所述有源层包括有源层存储图案、所述源漏金属层包括源漏金属层存储图案、所述像素电极层包括像素电极层存储图案;
其中,所述栅金属层存储图案、有源层存储图案、源漏金属层存储图案和像素电极层存储图案在所述衬底上的投影至少部分重合,且所述像素电极层存储图案与所述栅金属层存储图案电连接构成存储电容的第一电极,所述有源层存储图案与所述源漏金属层存储图案电连接构成所述存储电容的第二电极。
2.根据权利要求1所述的阵列基板,其特征在于,所述阵列基板还包括:设置在所述栅金属层和所述有源层之间的栅绝缘层,设置在所述有源层和所述源漏金属层之间的刻蚀阻挡层,以及设置在所述源漏金属层和所述像素电极层之间的钝化层。
3.根据权利要求2所述的阵列基板,其特征在于,在所述存储电容区域,所述像素电极层存储图案通过贯穿所述钝化层、刻蚀阻挡层和栅绝缘层上的第一过孔与所述栅金属层存储图案电连接;
所述源漏金属层存储图案通过贯穿所述刻蚀阻挡层上的第二过孔与所述有源层存储图案电连接。
4.根据权利要求1-3中任一项所述的阵列基板,其特征在于,所述存储电容区域中的有源层存储图案为通过等离子处理或离子注入后的有源层存储图案。
5.一种阵列基板的制备方法,其特征在于,包括:在衬底上形成栅金属层、有源层、源漏金属层、像素电极层、以及存储电容区域;
其中,在所述存储电容区域,所述栅金属层包括栅金属层存储图案、所述有源层包括有源层存储图案、所述源漏金属层包括源漏金属层存储图案、所述像素电极层包括像素电极层存储图案,所述栅金属层存储图案、有源层存储图案、源漏金属层存储图案和像素电极层存储图案在所述衬底上的投影至少部分重合,且所述像素电极层存储图案与所述栅金属层存储图案电连接构成存储电容的第一电极,所述有源层存储图案与所述源漏金属层存储图案电连接构成所述存储电容的第二电极。
6.根据权利要求5所述的方法,其特征在于,所述方法还包括:
在所述栅金属层和所述有源层之间形成栅绝缘层,在所述有源层和所述源漏金属层之间形成刻蚀阻挡层,以及在所述源漏金属层和所述像素电极层之间形成钝化层。
7.根据权利要求6所述的方法,其特征在于,在形成所述刻蚀阻挡层之前,对预形成在所述存储电容区域中的有源层存储图案进行等离子处理或离子注入处理。
8.根据权利要求6所述的方法,其特征在于,在形成所述钝化层之后,形成贯穿所述钝化层、刻蚀阻挡层和栅绝缘层的第一过孔,用于使所述存储电容区域的像素电极层存储图案与栅金属层存储图案电连接。
9.根据权利要求6所述的方法,其特征在于,在形成所述刻蚀阻挡层之后,在所述刻蚀阻挡层上形成第二过孔,用于使所述存储电容区域的源漏金属层存储图案与所述有源层存储图案电连接。
10.一种显示装置,其特征在于,包括如权利要求1-4中任一项所述的阵列基板。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510303519.1A CN104965362A (zh) | 2015-06-04 | 2015-06-04 | 一种阵列基板及其制备方法、显示装置 |
PCT/CN2016/079359 WO2016192471A1 (zh) | 2015-06-04 | 2016-04-15 | 一种阵列基板及其制备方法、显示装置及其制备方法 |
US15/547,410 US20180011356A1 (en) | 2015-06-04 | 2016-04-15 | Array substrate and manufacturing method thereof, display device and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510303519.1A CN104965362A (zh) | 2015-06-04 | 2015-06-04 | 一种阵列基板及其制备方法、显示装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN104965362A true CN104965362A (zh) | 2015-10-07 |
Family
ID=54219401
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201510303519.1A Pending CN104965362A (zh) | 2015-06-04 | 2015-06-04 | 一种阵列基板及其制备方法、显示装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20180011356A1 (zh) |
CN (1) | CN104965362A (zh) |
WO (1) | WO2016192471A1 (zh) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2016192471A1 (zh) * | 2015-06-04 | 2016-12-08 | 京东方科技集团股份有限公司 | 一种阵列基板及其制备方法、显示装置及其制备方法 |
CN106502018A (zh) * | 2016-12-30 | 2017-03-15 | 惠科股份有限公司 | 像素结构和显示面板 |
CN106527005A (zh) * | 2016-12-30 | 2017-03-22 | 惠科股份有限公司 | 像素结构的制造方法 |
CN108962181A (zh) * | 2018-09-21 | 2018-12-07 | 京东方科技集团股份有限公司 | 移位寄存器、栅极驱动电路及显示装置 |
CN109103204A (zh) * | 2018-08-01 | 2018-12-28 | 武汉华星光电半导体显示技术有限公司 | 一种阵列基板及其制作方法 |
CN109143772A (zh) * | 2018-10-10 | 2019-01-04 | 信利半导体有限公司 | 灰阶掩膜板 |
CN111312772A (zh) * | 2020-02-25 | 2020-06-19 | 京东方科技集团股份有限公司 | Oled显示基板及其制作方法、显示装置 |
CN111724736A (zh) * | 2020-07-24 | 2020-09-29 | 京东方科技集团股份有限公司 | 一种阵列基板、oled显示面板及显示装置 |
CN111739896A (zh) * | 2020-07-01 | 2020-10-02 | 京东方科技集团股份有限公司 | 显示基板及其制备方法、显示面板 |
WO2021027160A1 (zh) * | 2019-08-13 | 2021-02-18 | 深圳市华星光电半导体显示技术有限公司 | 显示面板及其制作方法 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10535566B2 (en) | 2016-04-28 | 2020-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of manufacture |
US10553614B2 (en) * | 2018-02-05 | 2020-02-04 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Thin-film transistor array substrate and manufacturing method for the same |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103293790A (zh) * | 2013-05-27 | 2013-09-11 | 京东方科技集团股份有限公司 | 像素单元及其制备方法、阵列基板、显示装置 |
CN203311138U (zh) * | 2013-05-27 | 2013-11-27 | 京东方科技集团股份有限公司 | 像素单元、阵列基板及显示装置 |
US20140131717A1 (en) * | 2012-11-15 | 2014-05-15 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Pixel Unit Structure, Array Substrate and Display Device |
CN104064688A (zh) * | 2014-07-11 | 2014-09-24 | 深圳市华星光电技术有限公司 | 具有存储电容的tft基板的制作方法及该tft基板 |
CN104517996A (zh) * | 2013-10-08 | 2015-04-15 | 乐金显示有限公司 | 显示装置及其制造方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101392276B1 (ko) * | 2007-10-31 | 2014-05-07 | 삼성디스플레이 주식회사 | 박막 트랜지스터 기판 및 이의 제조 방법 |
US9673267B2 (en) * | 2013-03-26 | 2017-06-06 | Lg Display Co., Ltd. | Organic light emitting diode display device having a capacitor with stacked storage electrodes and method for manufacturing the same |
CN104795428A (zh) * | 2015-04-10 | 2015-07-22 | 京东方科技集团股份有限公司 | 一种阵列基板及其制作方法以及显示装置 |
CN104965362A (zh) * | 2015-06-04 | 2015-10-07 | 京东方科技集团股份有限公司 | 一种阵列基板及其制备方法、显示装置 |
-
2015
- 2015-06-04 CN CN201510303519.1A patent/CN104965362A/zh active Pending
-
2016
- 2016-04-15 US US15/547,410 patent/US20180011356A1/en not_active Abandoned
- 2016-04-15 WO PCT/CN2016/079359 patent/WO2016192471A1/zh active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140131717A1 (en) * | 2012-11-15 | 2014-05-15 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Pixel Unit Structure, Array Substrate and Display Device |
CN103293790A (zh) * | 2013-05-27 | 2013-09-11 | 京东方科技集团股份有限公司 | 像素单元及其制备方法、阵列基板、显示装置 |
CN203311138U (zh) * | 2013-05-27 | 2013-11-27 | 京东方科技集团股份有限公司 | 像素单元、阵列基板及显示装置 |
CN104517996A (zh) * | 2013-10-08 | 2015-04-15 | 乐金显示有限公司 | 显示装置及其制造方法 |
CN104064688A (zh) * | 2014-07-11 | 2014-09-24 | 深圳市华星光电技术有限公司 | 具有存储电容的tft基板的制作方法及该tft基板 |
Cited By (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2016192471A1 (zh) * | 2015-06-04 | 2016-12-08 | 京东方科技集团股份有限公司 | 一种阵列基板及其制备方法、显示装置及其制备方法 |
CN106502018B (zh) * | 2016-12-30 | 2019-02-26 | 惠科股份有限公司 | 像素结构和显示面板 |
CN106502018A (zh) * | 2016-12-30 | 2017-03-15 | 惠科股份有限公司 | 像素结构和显示面板 |
CN106527005A (zh) * | 2016-12-30 | 2017-03-22 | 惠科股份有限公司 | 像素结构的制造方法 |
WO2018120543A1 (zh) * | 2016-12-30 | 2018-07-05 | 惠科股份有限公司 | 像素结构的制造方法 |
CN106527005B (zh) * | 2016-12-30 | 2020-03-27 | 惠科股份有限公司 | 像素结构的制造方法 |
CN109103204A (zh) * | 2018-08-01 | 2018-12-28 | 武汉华星光电半导体显示技术有限公司 | 一种阵列基板及其制作方法 |
CN108962181A (zh) * | 2018-09-21 | 2018-12-07 | 京东方科技集团股份有限公司 | 移位寄存器、栅极驱动电路及显示装置 |
CN109143772A (zh) * | 2018-10-10 | 2019-01-04 | 信利半导体有限公司 | 灰阶掩膜板 |
CN109143772B (zh) * | 2018-10-10 | 2024-03-19 | 信利半导体有限公司 | 灰阶掩膜板 |
WO2021027160A1 (zh) * | 2019-08-13 | 2021-02-18 | 深圳市华星光电半导体显示技术有限公司 | 显示面板及其制作方法 |
CN111312772A (zh) * | 2020-02-25 | 2020-06-19 | 京东方科技集团股份有限公司 | Oled显示基板及其制作方法、显示装置 |
CN111312772B (zh) * | 2020-02-25 | 2022-10-25 | 京东方科技集团股份有限公司 | Oled显示基板及其制作方法、显示装置 |
US11711944B2 (en) | 2020-02-25 | 2023-07-25 | Boe Technology Group Co., Ltd. | Organic light-emitting diode display substrate, manufacturing method thereof, and display device |
CN111739896A (zh) * | 2020-07-01 | 2020-10-02 | 京东方科技集团股份有限公司 | 显示基板及其制备方法、显示面板 |
CN111739896B (zh) * | 2020-07-01 | 2023-08-18 | 京东方科技集团股份有限公司 | 显示基板及其制备方法、显示面板 |
CN111724736A (zh) * | 2020-07-24 | 2020-09-29 | 京东方科技集团股份有限公司 | 一种阵列基板、oled显示面板及显示装置 |
US11696471B2 (en) | 2020-07-24 | 2023-07-04 | Boe Technology Group Co., Ltd. | Array substrate including a second electrode of the second capacitor disposed on the same layer with the power supply voltage line, OLED display panel, and display device having the same |
Also Published As
Publication number | Publication date |
---|---|
WO2016192471A1 (zh) | 2016-12-08 |
US20180011356A1 (en) | 2018-01-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN104965362A (zh) | 一种阵列基板及其制备方法、显示装置 | |
CN106981520B (zh) | 薄膜晶体管及其制备方法、阵列基板和显示装置 | |
CN106684155B (zh) | 双栅薄膜晶体管及其制备方法、阵列基板及显示装置 | |
US20160370621A1 (en) | Array substrate, manufacturing method thereof and liquid crystal display | |
CN102768992B (zh) | 一种薄膜晶体管驱动背板的制作方法 | |
WO2015100898A1 (zh) | 薄膜晶体管、tft阵列基板及其制造方法和显示装置 | |
CN106531692A (zh) | 阵列基板的制备方法、阵列基板及显示装置 | |
US8895334B2 (en) | Thin film transistor array substrate and method for manufacturing the same and electronic device | |
CN108807547B (zh) | 薄膜晶体管及其制备方法、阵列基板及其制备方法 | |
CN101132011A (zh) | 阵列基板及其制造方法和具有阵列基板的显示器件 | |
CN104102059A (zh) | Tft阵列基板及其制造方法 | |
CN103325841A (zh) | 薄膜晶体管及其制作方法和显示器件 | |
CN102543864B (zh) | 一种薄膜晶体管阵列基板及其制作方法 | |
CN103474434A (zh) | 阵列基板、制备方法以及显示装置 | |
CN203521413U (zh) | 一种阵列基板及显示装置 | |
US9171941B2 (en) | Fabricating method of thin film transistor, fabricating method of array substrate and display device | |
CN202473925U (zh) | 一种顶栅型tft阵列基板及显示装置 | |
WO2014153958A1 (zh) | 阵列基板、阵列基板的制造方法以及显示装置 | |
CN104133313A (zh) | 阵列基板及其制备方法、液晶显示装置 | |
CN103531640A (zh) | 薄膜晶体管、阵列基板及其制造方法和显示装置 | |
CN102629592A (zh) | 阵列基板及其制作方法、显示装置 | |
CN107799466A (zh) | Tft基板及其制作方法 | |
CN104157608B (zh) | Tft基板的制作方法及其结构 | |
CN104992950A (zh) | 一种阵列基板及其制备方法、显示装置 | |
CN108305879A (zh) | 薄膜晶体管阵列基板及制作方法和显示装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
RJ01 | Rejection of invention patent application after publication | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20151007 |