WO2021027160A1 - 显示面板及其制作方法 - Google Patents

显示面板及其制作方法 Download PDF

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Publication number
WO2021027160A1
WO2021027160A1 PCT/CN2019/118484 CN2019118484W WO2021027160A1 WO 2021027160 A1 WO2021027160 A1 WO 2021027160A1 CN 2019118484 W CN2019118484 W CN 2019118484W WO 2021027160 A1 WO2021027160 A1 WO 2021027160A1
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WIPO (PCT)
Prior art keywords
source
anode
display panel
drain electrode
layer
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PCT/CN2019/118484
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English (en)
French (fr)
Inventor
蔡振飞
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深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US16/621,239 priority Critical patent/US11056552B2/en
Publication of WO2021027160A1 publication Critical patent/WO2021027160A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H10K50/813—Anodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/85—Arrangements for extracting light from the devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass

Definitions

  • This application relates to the field of electronic display, and in particular to a display panel and a manufacturing method thereof.
  • OLED display panels have high contrast, wide viewing angles and fast response speeds. It is expected that liquid crystal display panels will become the mainstream choice for next-generation displays.
  • the aperture ratio is probably between 20% and 30%.
  • the light emitted by the organic layer needs to pass through each film layer of the driving circuit.
  • the opening area of the 3T1C pixel driving circuit is usually It is designed separately from the storage capacitor, as shown in Figure 1, thereby reducing the aperture ratio of the pixel.
  • the pixel patterns in the pixel points are concentrated in a small space, it is easy to cause electrical defects such as short circuits and open circuits, which reduces the product yield.
  • the present application provides a display panel and a manufacturing method thereof to increase the aperture ratio of the bottom emission type OLED display panel.
  • the present application provides a display panel including a storage capacitor and a light emitting structure; wherein,
  • the light emitting structure is located above the storage capacitor, and the light emitting surface of the light emitting structure faces the storage capacitor;
  • the first plate of the storage capacitor includes an anode and an active area electrically connected, and the second plate of the storage capacitor includes a source and drain electrode layer, and the source and drain electrode layer is a transparent electrode.
  • the light-emitting structure includes an anode, a light-emitting material, and a cathode; wherein,
  • the anode is a transparent electrode
  • the luminescent material is located between the anode and the cathode;
  • the cathode is a reflective electrode.
  • the transparent electrode is one or a combination of indium tin oxide, aluminum-doped zinc oxide, or fluorine-doped tin oxide.
  • the reflective electrode is one or a combination of silver, aluminum, copper, and gold.
  • the active region is an indium gallium zinc oxide film.
  • the display panel includes:
  • a buffer layer, the buffer layer is located on the substrate
  • the active region is located on the buffer layer, and the active region includes a channel region and source and drain regions located on both sides of the channel region;
  • a gate stack the gate stack is located above the active region and covers the channel region;
  • An interlayer dielectric layer covering the active area and the gate stack;
  • the source and drain electrode layer is located above the interlayer dielectric layer, and is electrically connected to the source and drain regions through a first through hole penetrating the interlayer dielectric layer;
  • a planarization layer covers the source and drain electrode layers;
  • the anode is located on the planarization layer, and is electrically connected to the source and drain electrode layers through a second through hole;
  • a light emitting structure the light emitting structure is located on the anode.
  • the area of the source-drain electrode layer is greater than or equal to twice the area of the active region, and the projection of the source-drain electrode layer on the substrate completely covers the active region And the projection of the anode on the substrate.
  • this application also provides a manufacturing method of a display panel, the method including the following steps:
  • the active region is located on the buffer layer, the active region includes a channel region and source and drain regions located on both sides of the channel region;
  • the source and drain electrode layers are transparent electrodes, and the source and drain electrode layers constitute the second plate of the storage capacitor on the display surface;
  • planarization layer Forming a planarization layer, the planarization layer covering the source and drain electrode layers;
  • the anode is located on the planarization layer, and the anode is electrically connected to the active area to form a first plate of the storage capacitor on the display surface;
  • a light emitting structure is formed, and the light emitting structure is located on the anode.
  • the method of forming the light-emitting structure includes the following steps:
  • the anode is located on the planarization layer, and the anode is a transparent electrode;
  • a cathode is formed, the cathode covers the luminescent material, and the cathode is a reflective electrode.
  • the transparent electrode is one or a combination of indium tin oxide, aluminum-doped zinc oxide, or fluorine-doped tin oxide.
  • the reflective electrode is one or a combination of silver, aluminum, copper, and gold.
  • the active region is an indium gallium zinc oxide film.
  • the area of the source-drain electrode layer is greater than or equal to twice the area of the active region, and the projection of the source-drain electrode layer on the substrate completely covers the active region And the projection of the anode on the substrate.
  • the display panel provided by the present application uses transparent electrodes to make the source and drain electrode layers in the bottom-emitting OLED display panel. Since the light emitted by the light-emitting structure can penetrate the source and drain electrode layers, the storage capacitor in the present application can be located directly under the light-emitting structure without placing the light-emitting structure in the metal avoidance area of the thin film transistor.
  • the present application not only effectively increases the aperture ratio of the 3T1C pixel driving circuit, but also effectively increases the layout area of the thin film transistor, avoids the occurrence of electrical defects such as short circuits and open circuits, and improves the product yield.
  • FIG. 1 is a schematic structural diagram of a driving circuit of an OLED display panel in the prior art
  • FIG. 2 is a schematic structural diagram of a driving circuit of an OLED display panel in a specific embodiment of the application
  • FIG. 3 is a schematic cross-sectional view of the driving circuit of the OLED display panel in FIG. 2.
  • the 3T1C pixel driving circuit in the prior art includes a functional area 010 and a transparent area 020.
  • the gate line 012, the data line 011 and the storage capacitor 013 are distributed in different film layers of the functional area 010, and are isolated from each other by an insulating layer.
  • the opening area of the 3T1C pixel driving circuit and the storage capacitor are usually designed separately, thereby reducing the pixel aperture ratio.
  • the pixel patterns in the pixel points are concentrated in a small space, it is easy to cause electrical defects such as short circuits and open circuits, which reduces the product yield.
  • the present application provides a display panel and a manufacturing method thereof to improve the aperture ratio of the bottom emission type OLED display panel.
  • FIG. 2 is a schematic structural diagram of a driving circuit of an OLED display panel in a specific embodiment of the application
  • FIG. 3 is a schematic cross-sectional view of the driving circuit of an OLED display panel in FIG.
  • the display panel includes a functional area 10 and a light emitting structure 20.
  • the functional area includes a data line 11, a gate line 12 and a storage capacitor 13.
  • the light emitting structure is located above the storage capacitor 13, and the light emitting surface of the light emitting structure 20 faces the storage capacitor 13.
  • the first plate of the storage capacitor 13 includes an anode 38 and an active area 33 electrically connected, and the second plate of the storage capacitor 13 includes a source and drain electrode layer 36, and the source and drain electrode layer 36 is a transparent electrode.
  • the source-drain electrode layer 36 includes a first part 361 and a second part 362 spaced apart from the first part 361. Wherein, the first part 361 and the second part 362 are separated by the planarization layer 37.
  • the first part 361 is used to electrically connect the anode 38 and the active region 33.
  • the second part 362 is used as a second plate of the storage capacitor 13 and is connected to an electrical signal different from the first plate.
  • the light-emitting structure 20 includes an anode 38, a light-emitting material 42 and a cathode 43.
  • the anode 38 is a transparent electrode.
  • the active region 33 is an indium gallium zinc oxide film.
  • the luminescent material 42 is located between the anode 38 and the cathode 43.
  • the cathode 43 is a reflective electrode.
  • the transparent electrode is one or a combination of indium tin oxide, aluminum-doped zinc oxide, or fluorine-doped tin oxide.
  • the reflective electrode is one or a combination of silver, aluminum, copper, and gold.
  • the storage capacitor in the present application can be located directly under the light emitting structure instead of The light emitting structure needs to be arranged in the metal avoidance area of the thin film transistor.
  • the display panel further includes a substrate 31, a buffer layer 32, a gate stack 34, an interlayer dielectric layer 35, a planarization layer 37, and a light emitting structure 20.
  • the buffer layer 32 is located on the substrate 31.
  • the active region 33 is located on the buffer layer 32, and the active region 33 includes a channel region and source and drain regions located on both sides of the channel region.
  • the gate stack 34 is located above the active region 33 and covers the channel region.
  • the interlayer dielectric layer 35 covers the active region 33 and the gate stack 34.
  • the source/drain electrode layer 36 is located above the interlayer dielectric layer 35 and is electrically connected to the source and drain regions through a first through hole penetrating the interlayer dielectric layer 35.
  • the planarization layer 37 covers the source and drain electrode layer 36.
  • the anode 38 is located on the planarization layer 37 and is electrically connected to the source and drain electrode layer 36 through a second through hole.
  • the light emitting structure 20 is located on the anode 38.
  • the resistance of the transparent electrode is generally greater than that of metals such as silver, aluminum, copper, gold, etc.
  • the area of the source and drain electrode layers 36 is larger than Or equal to twice the area of the active region 33, the projection of the source and drain electrode layer 36 on the substrate 31 completely covers the projection of the active region 33 and the anode 38 on the substrate 31. This arrangement effectively reduces the resistance of the transparent electrode, and prevents excessive voltage drop on the source and drain electrode layers from affecting the operation of the driving circuit.
  • this application also provides a manufacturing method of a display panel, the method including the following steps:
  • the formation layer covers the buffer layer 32 of the substrate 31;
  • the active region 33 is located on the buffer layer 32, the active region 33 includes a channel region and source and drain regions located on both sides of the channel region;
  • the source/drain electrode layer 36 is a transparent electrode, and the source/drain electrode layer 36 constitutes the second plate of the storage capacitor 13 on the display surface;
  • An anode 38 is formed, the anode 38 is located on the planarization layer 37, and the anode 38 is electrically connected to the active region 33 to form the first plate of the storage capacitor 13 on the display surface;
  • a light emitting structure 20 is formed, and the light emitting structure 20 is located on the anode 38.
  • the method of forming the light-emitting structure 20 includes the following steps:
  • anode 38 Forming an anode 38, the anode 38 is located on the planarization layer 37, and the anode 38 is a transparent electrode;
  • a cathode 43 is formed, the cathode 43 covers the luminescent material 42, and the cathode 43 is a reflective electrode.
  • the display panel includes a storage capacitor 12 and a light emitting structure 20.
  • the light emitting structure is located above the storage capacitor 13, and the light emitting surface of the light emitting structure 20 faces the storage capacitor 13.
  • the first plate of the storage capacitor 13 includes an anode 38 and an active area 33 electrically connected, and the second plate of the storage capacitor 13 includes a source and drain electrode layer 36, and the source and drain electrode layer 36 is a transparent electrode.
  • the light-emitting structure 20 includes an anode 38, a light-emitting material 42 and a cathode 43.
  • the anode 38 is a transparent electrode.
  • the active region 33 is an indium gallium zinc oxide film.
  • the luminescent material 42 is located between the anode 38 and the cathode 43.
  • the cathode 43 is a reflective electrode.
  • the transparent electrode is one or a combination of indium tin oxide, aluminum-doped zinc oxide, or fluorine-doped tin oxide.
  • the reflective electrode is one or a combination of silver, aluminum, copper, and gold.
  • the storage capacitor in the present application can be located directly under the light emitting structure instead of The light emitting structure needs to be arranged in the metal avoidance area of the thin film transistor.
  • the resistance of the transparent electrode is generally greater than that of metals such as silver, aluminum, copper, gold, etc.
  • the area of the source and drain electrode layers 36 is larger than Or equal to twice the area of the active region 33, the projection of the source and drain electrode layer 36 on the substrate 31 completely covers the projection of the active region 33 and the anode 38 on the substrate 31. This arrangement effectively reduces the resistance of the transparent electrode, and prevents excessive voltage drop on the source and drain electrode layers from affecting the operation of the driving circuit.
  • the display panel provided by the present application uses transparent electrodes to make the source and drain electrode layers 36 in the bottom-emitting OLED display panel. Since the light emitted by the light-emitting structure 20 can penetrate the source and drain electrode layers 36, the storage capacitor 13 in the present application can be located directly under the light-emitting structure 20 without the need to arrange the light-emitting structure 20 in the metal avoidance area of the thin film transistor in.
  • the present application not only effectively increases the aperture ratio of the 3T1C pixel driving circuit, but also effectively increases the layout area of the thin film transistor, avoids the occurrence of electrical defects such as short circuits and open circuits, and improves the product yield.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

本申请提供了一种显示面板及其制作方法。所述显示面板包括存储电容和发光结构。所述发光结构位于所述存储电容上方，所述发光结构的出光面朝向所述存储电容。所述存储电容的第一极板包括电连接的阳极和有源区，所述存储电容的第二极板包括源漏电极层，所述源漏电极层为透明电极。

Description

显示面板及其制作方法 技术领域
本申请涉及电子显示领域，尤其涉及一种显示面板及其制作方法。
 背景技术
有机发光二极管（organic light-emitting diode, OLED）显示面板的对比度高、可视角度广且响应速度快，有望取缔液晶显示面板成为下一代显示器主流选择。
 技术问题
目前，大尺寸OLED显示面板采用3T1C驱动电路，其开口率大概在20%~30%之间。现有的底发光式显示面板中，有机层发出的光需要穿过驱动电路的各个膜层射出，由于电容区的金属不透光，光线无法穿透，因此通常将3T1C像素驱动电路的开口区和存储电容分开设计，如图1所示，从而降低了像素点的开口率。同时，由于像素点中的像素图案集中在一个狭小的空间内，很容易造成短路、断路等电性不良，降低了产品良率。
 技术解决方案
本申请提供了一种显示面板及其制作方法，以提高底发光式OLED显示面板的开口率。
为解决上述问题，本申请提供了一种显示面板，所述显示面板包括存储电容和发光结构；其中，
所述发光结构位于所述存储电容上方，所述发光结构的出光面朝向所述存储电容；
所述存储电容的第一极板包括电连接的阳极和有源区，所述存储电容的第二极板包括源漏电极层，所述源漏电极层为透明电极。
根据本申请的其中一个方面，所述发光结构包括阳极、发光材料和阴极；其中，
所述阳极为透明电极；
所述发光材料位于所述阳极和阴极之间；
所述阴极为反射电极。
根据本申请的其中一个方面，所述透明电极为氧化铟锡、铝掺杂的氧化锌或氟掺杂的氧化锡中的一种或多种的组合。
根据本申请的其中一个方面，所述反射电极为银、铝、铜、金中的一种或多种的组合。
根据本申请的其中一个方面，所述有源区为所述有源区为铟镓锌氧化物薄膜。
根据本申请的其中一个方面，所述显示面板包括：
基板；
缓冲层，所述缓冲层位于所述基板上；
所述有源区位于所述缓冲层上，所述有源区包括沟道区和位于沟道区两侧的源漏区；
栅极叠层，所述栅极叠层位于所述有源区上方，并覆盖所述沟道区；
层间介质层，所述层间介质层覆盖所述有源区和栅极叠层；
所述源漏电极层位于所述层间介质层上方，通过贯穿所述层间介质层的第一通孔与所述源漏区电连接；
平坦化层，所述平坦化层覆盖所述源漏电极层；
所述阳极位于所述平坦化层上，通过第二通孔与所述源漏电极层电连接；
发光结构，所述发光结构位于所述阳极上。
根据本申请的其中一个方面，所述源漏电极层的面积大于或等于所述有源区的面积的两倍，所述源漏电极层在所述基板上的投影完全覆盖所述有源区和阳极在所述基板上的投影。
相应的，本申请还提供了一种显示面板的制作方法，该方法包括以下步骤：
提供基板；
形成层覆盖所述基板的缓冲层；
形成有源区，所述有源区位于所述缓冲层上，所述有源区包括沟道区和位于沟道区两侧的源漏区；
在所述有源区上方形成覆盖所述沟道区的栅极叠层；
形成覆盖所述有源区和栅极叠层的层间介质层；
形成位于所述层间介质层上方的源漏电极层，所述源漏电极层为透明电极，所述源漏电极层构成所述显示面的存储电容的第二极板；
形成平坦化层，所述平坦化层覆盖所述源漏电极层；
形成阳极，所述阳极位于所述平坦化层上，所述阳极与所述有源区电连接，构成所述显示面的存储电容的第一极板；
形成发光结构，所述发光结构位于所述阳极上。
根据本申请的其中一个方面，形成所述发光结构的方法包括以下步骤：
形成阳极，所述阳极位于所述平坦化层上，且所述阳极为透明电极；
形成发光材料，所述发光材料位于所述阳极上；
形成阴极，所述阴极覆盖所述发光材料，且所述阴极为反射电极。
根据本申请的其中一个方面，所述透明电极为氧化铟锡、铝掺杂的氧化锌或氟掺杂的氧化锡中的一种或多种的组合。
根据本申请的其中一个方面，所述反射电极为银、铝、铜、金中的一种或多种的组合。
根据本申请的其中一个方面，所述有源区为铟镓锌氧化物薄膜。
根据本申请的其中一个方面，所述源漏电极层的面积大于或等于所述有源区的面积的两倍，所述源漏电极层在所述基板上的投影完全覆盖所述有源区和阳极在所述基板上的投影。
 有益效果
本申请提供的显示面板采用透明电极制作底发光式OLED显示面板中的源漏电极层。由于发光结构发出的光线能够穿透所述源漏电极层，因此本申请中的存储电容可以位于所述发光结构正下方而不需要将发光结构设置在薄膜晶体管的金属避让区中。本申请不仅有效的增大了3T1C像素驱动电路的开口率，同时有效的增大了薄膜晶体管的版图面积，避免了短路、断路等电性不良的产生，提高了产品良率。
 附图说明
图1为现有技术的OLED显示面板的驱动电路的结构示意图；
图2为本申请的一个具体实施例中的OLED显示面板的驱动电路的结构示意图；
图3为图2中的OLED显示面板的驱动电路的示意性剖面图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
参见图1，首先对现有技术进行简要说明。现有技术中的3T1C像素驱动电路包括功能区010和透光区020。其中，栅极线012、数据线011和存储电容013分布在功能区010的不同膜层中，通过绝缘层彼此隔离。
对于底发光显示面板，由于电容区的金属不透光，光线无法穿透，因此通常将3T1C像素驱动电路的开口区和存储电容分开设计，从而降低了像素点的开口率。同时，由于像素点中的像素图案集中在一个狭小的空间内，很容易造成短路、断路等电性不良，降低了产品良率。
因此，本申请提供了一种显示面板及其制作方法，以提高底发光式OLED显示面板的开口率。
参见图2和图3，图2为本申请的一个具体实施例中的OLED显示面板的驱动电路的结构示意图，图3为图2中的OLED显示面板的驱动电路的示意性剖面图。
本实施例中，所述显示面板包括功能区10和发光结构20。所述功能区包括数据线11、栅极线12和存储电容13。所述发光结构位于所述存储电容13上方，所述发光结构20的出光面朝向所述存储电容13。所述存储电容13的第一极板包括电连接的阳极38和有源区33，所述存储电容13的第二极板包括源漏电极层36，所述源漏电极层36为透明电极。
参见图3，本实施例中，所述源漏电极层36包括第一部分361和与所述第一部分361间隔设置的第二部分362。其中，所述第一部分361和第二部分362被所述平坦化层37隔离。所述第一部分361用于电连接所述阳极38和有源区33。所述第二部分362用于作为所述存储电容13的第二极板，连接与所述第一极板不同的电信号。
本实施例中，所述发光结构20包括阳极38、发光材料42和阴极43。所述阳极38为透明电极。所述有源区33为所述有源区33为铟镓锌氧化物薄膜。所述发光材料42位于所述阳极38和阴极43之间。所述阴极43为反射电极。所述透明电极为氧化铟锡、铝掺杂的氧化锌或氟掺杂的氧化锡中的一种或多种的组合。所述反射电极为银、铝、铜、金中的一种或多种的组合。采用透明电极制作底发光式OLED显示面板中的源漏电极层能够使发光结构发出的光线穿透所述源漏电极层，因此本申请中的存储电容可以位于所述发光结构正下方，而不需要将发光结构设置在薄膜晶体管的金属避让区中。
参见图3，本实施例中，所述显示面板还包括基板31、缓冲层32、栅极叠层34、层间介质层35、平坦化层37和发光结构20。
所述缓冲层32位于所述基板31上。所述有源区33位于所述缓冲层32上，所述有源区33包括沟道区和位于沟道区两侧的源漏区。所述栅极叠层34位于所述有源区33上方，并覆盖所述沟道区。所述层间介质层35覆盖所述有源区33和栅极叠层34。所述源漏电极层36位于所述层间介质层35上方，通过贯穿所述层间介质层35的第一通孔与所述源漏区电连接。所述平坦化层37覆盖所述源漏电极层36。所述阳极38位于所述平坦化层37上，通过第二通孔与所述源漏电极层36电连接。所述发光结构20位于所述阳极38上。
由于透明电极的电阻通常大于银、铝、铜、金等金属，因此为了避免源漏电极层的电阻率过大影响驱动电路的工作，本实施例中，所述源漏电极层36的面积大于或等于所述有源区33的面积的两倍，所述源漏电极层36在所述基板31上的投影完全覆盖所述有源区33和阳极38在所述基板31上的投影。这样设置有效的减小了透明电极的电阻，避免源漏电极层上产生过大的压降影响驱动电路的工作。
相应的，本申请还提供了一种显示面板的制作方法，该方法包括以下步骤：
提供基板31；
形成层覆盖所述基板31的缓冲层32；
形成有源区33，所述有源区33位于所述缓冲层32上，所述有源区33包括沟道区和位于沟道区两侧的源漏区；
在所述有源区33上方形成覆盖所述沟道区的栅极叠层34；
形成覆盖所述有源区33和栅极叠层34的层间介质层35；
形成位于所述层间介质层35上方的源漏电极层36，所述源漏电极层36为透明电极，所述源漏电极层36构成所述显示面的存储电容13的第二极板；
形成平坦化层37，所述平坦化层37覆盖所述源漏电极层36；
形成阳极38，所述阳极38位于所述平坦化层37上，所述阳极38与所述有源区33电连接，构成所述显示面的存储电容13的第一极板；
形成发光结构20，所述发光结构20位于所述阳极38上。
本实施例中，形成所述发光结构20的方法包括以下步骤：
形成阳极38，所述阳极38位于所述平坦化层37上，且所述阳极38为透明电极；
形成发光材料42，所述发光材料42位于所述阳极38上；
形成阴极43，所述阴极43覆盖所述发光材料42，且所述阴极43为反射电极。
本实施例中，所述显示面板包括存储电容12和发光结构20。所述发光结构位于所述存储电容13上方，所述发光结构20的出光面朝向所述存储电容13。所述存储电容13的第一极板包括电连接的阳极38和有源区33，所述存储电容13的第二极板包括源漏电极层36，所述源漏电极层36为透明电极。
本实施例中，所述发光结构20包括阳极38、发光材料42和阴极43。所述阳极38为透明电极。所述有源区33为所述有源区33为铟镓锌氧化物薄膜。所述发光材料42位于所述阳极38和阴极43之间。所述阴极43为反射电极。所述透明电极为氧化铟锡、铝掺杂的氧化锌或氟掺杂的氧化锡中的一种或多种的组合。所述反射电极为银、铝、铜、金中的一种或多种的组合。采用透明电极制作底发光式OLED显示面板中的源漏电极层能够使发光结构发出的光线穿透所述源漏电极层，因此本申请中的存储电容可以位于所述发光结构正下方，而不需要将发光结构设置在薄膜晶体管的金属避让区中。
由于透明电极的电阻通常大于银、铝、铜、金等金属，因此为了避免源漏电极层的电阻率过大影响驱动电路的工作，本实施例中，所述源漏电极层36的面积大于或等于所述有源区33的面积的两倍，所述源漏电极层36在所述基板31上的投影完全覆盖所述有源区33和阳极38在所述基板31上的投影。这样设置有效的减小了透明电极的电阻，避免源漏电极层上产生过大的压降影响驱动电路的工作。
本申请提供的显示面板采用透明电极制作底发光式OLED显示面板中的源漏电极层36。由于发光结构20发出的光线能够穿透所述源漏电极层36，因此本申请中的存储电容13可以位于所述发光结构20正下方而不需要将发光结构20设置在薄膜晶体管的金属避让区中。本申请不仅有效的增大了3T1C像素驱动电路的开口率，同时有效的增大了薄膜晶体管的版图面积，避免了短路、断路等电性不良的产生，提高了产品良率。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (13)

  1. 一种显示面板，其中，所述显示面板包括存储电容和发光结构；其中，
    所述发光结构位于所述存储电容上方，所述发光结构的出光面朝向所述存储电容；
    所述存储电容的第一极板包括电连接的阳极和有源区，所述存储电容的第二极板包括源漏电极层，所述源漏电极层为透明电极。
  2. 根据权利要求1所述的显示面板，其中，所述发光结构包括阳极、发光材料和阴极；其中，
    所述阳极为透明电极；
    所述发光材料位于所述阳极和阴极之间；
    所述阴极为反射电极。
  3. 根据权利要求2所述的显示面板，其中，所述透明电极为氧化铟锡、铝掺杂的氧化锌或氟掺杂的氧化锡中的一种或多种的组合。
  4. 根据权利要求2所述的显示面板，其中，所述反射电极为银、铝、铜、金中的一种或多种的组合。
  5. 根据权利要求1所述的显示面板，其中，所述有源区为铟镓锌氧化物薄膜。
  6. 根据权利要求1所述的显示面板，其中，所述显示面板包括：
    基板；
    缓冲层，所述缓冲层位于所述基板上；
    所述有源区位于所述缓冲层上，所述有源区包括沟道区和位于沟道区两侧的源漏区；
    栅极叠层，所述栅极叠层位于所述有源区上方，并覆盖所述沟道区；
    层间介质层，所述层间介质层覆盖所述有源区和栅极叠层；
    所述源漏电极层位于所述层间介质层上方，通过贯穿所述层间介质层的第一通孔与所述源漏区电连接；
    平坦化层，所述平坦化层覆盖所述源漏电极层；
    所述阳极位于所述平坦化层上，通过第二通孔与所述源漏电极层电连接；
    发光结构，所述发光结构位于所述阳极上。
  7. 根据权利要求6所述的显示面板，其中，所述源漏电极层的面积大于或等于所述有源区的面积的两倍，所述源漏电极层在所述基板上的投影完全覆盖所述有源区和阳极在所述基板上的投影。
  8. 一种显示面板的制作方法，其中，该方法包括以下步骤：
    提供基板；
    形成层覆盖所述基板的缓冲层；
    形成有源区，所述有源区位于所述缓冲层上，所述有源区包括沟道区和位于沟道区两侧的源漏区；
    在所述有源区上方形成覆盖所述沟道区的栅极叠层；
    形成覆盖所述有源区和栅极叠层的层间介质层；
    形成位于所述层间介质层上方的源漏电极层，所述源漏电极层为透明电极，所述源漏电极层构成所述显示面的存储电容的第二极板；
    形成平坦化层，所述平坦化层覆盖所述源漏电极层；
    形成阳极，所述阳极位于所述平坦化层上，所述阳极与所述有源区电连接，构成所述显示面的存储电容的第一极板；
    形成发光结构，所述发光结构位于所述阳极上。
  9. 根据权利要求8所述的显示面板的制作方法，其中，形成所述发光结构的方法包括以下步骤：
    形成阳极，所述阳极位于所述平坦化层上，且所述阳极为透明电极；
    形成发光材料，所述发光材料位于所述阳极上；
    形成阴极，所述阴极覆盖所述发光材料，且所述阴极为反射电极。
  10. 根据权利要求9所述的显示面板的制作方法，其中，所述透明电极为氧化铟锡、铝掺杂的氧化锌或氟掺杂的氧化锡中的一种或多种的组合。
  11. 根据权利要求9所述的显示面板的制作方法，其中，所述反射电极为银、铝、铜、金中的一种或多种的组合。
  12. 根据权利要求9所述的显示面板的制作方法，其中，所述有源区为铟镓锌氧化物薄膜。
  13. 根据权利要求9所述的显示面板的制作方法，其中，所述源漏电极层的面积大于或等于所述有源区的面积的两倍，所述源漏电极层在所述基板上的投影完全覆盖所述有源区和阳极在所述基板上的投影。
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