WO2021088140A1 - 显示面板、制造方法以及拼接显示面板 - Google Patents

显示面板、制造方法以及拼接显示面板 Download PDF

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Publication number
WO2021088140A1
WO2021088140A1 PCT/CN2019/120042 CN2019120042W WO2021088140A1 WO 2021088140 A1 WO2021088140 A1 WO 2021088140A1 CN 2019120042 W CN2019120042 W CN 2019120042W WO 2021088140 A1 WO2021088140 A1 WO 2021088140A1
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WO
WIPO (PCT)
Prior art keywords
electrical connection
openings
display panel
array substrate
signal line
Prior art date
Application number
PCT/CN2019/120042
Other languages
English (en)
French (fr)
Inventor
卢马才
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US16/625,731 priority Critical patent/US20210233899A1/en
Publication of WO2021088140A1 publication Critical patent/WO2021088140A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/302—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements characterised by the form or geometrical disposition of the individual elements
    • G09F9/3026—Video wall, i.e. stackable semiconductor matrix display modules
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present application relates to the display field, and in particular to a display panel, a manufacturing method, and a spliced display panel.
  • borderless or narrow border displays have gradually become the mainstream.
  • displays such as liquid crystal displays (LiquidCrystalsDisplay, LCD), organic electroluminescence displays (Organic For Light-Emitting Display (OLED) and light emitting diode (LED) displays
  • the larger the screen size the higher the manufacturing difficulty and the higher the manufacturing cost per unit area. Therefore, large-scale displays are usually formed by splicing multiple small and medium-sized displays. The presence of the frame of the small and medium-sized display will cause striped seams to appear in the display area of the spliced display panel, which reduces the display quality.
  • the purpose of this application is to provide a frameless or narrow frame display panel and a manufacturing method thereof.
  • the present application also provides a spliced display panel that can eliminate or reduce splicing seams.
  • a display panel includes a light-emitting part, an array substrate, and a driving chip, the light-emitting part is electrically connected to one side of the array substrate, and the driving chip is electrically connected to the other side of the array substrate,
  • the array substrate includes:
  • a transparent substrate having a first surface and a second surface opposite to the first surface
  • the signal line is arranged on the first surface of the base substrate
  • a fan-out circuit arranged on the second surface of the base substrate, and the fan-out circuit is electrically connected to the signal line;
  • the driving chip is arranged on the second surface side of the base substrate and is electrically connected to the fan-out circuit,
  • the array substrate is provided with a plurality of openings, the plurality of openings are located at the edge of the array substrate and penetrate the array substrate, the array substrate includes a plurality of electrical connection portions, the electrical connection portions are arranged in the openings Wherein, the electrical connection part electrically connects the signal line and the fan-out circuit.
  • the opening is a groove opened on the side wall of the array substrate.
  • the opening is a through hole penetrating the array substrate.
  • a concave portion is formed on the side wall of the array substrate in the opening, the electrical connection portion includes an electrical connection protrusion, the signal line is exposed from the concave portion, and the The electrical connection protrusion is in contact with the signal line.
  • the plurality of openings includes a plurality of first openings arranged in a first direction
  • the plurality of electrical connection portions includes a plurality of first openings disposed in the plurality of first openings.
  • the electrical connection part, the signal line includes a gate line, and each of the first electrical connection parts is electrically connected to one of the gate lines.
  • the plurality of openings includes a plurality of second openings arranged in a second direction
  • the plurality of electrical connection portions includes a plurality of second openings arranged in the plurality of second openings.
  • the electrical connection part, the signal line includes a source/drain line, and each of the second electrical connection parts is electrically connected to one of the source/drain lines.
  • the plurality of openings includes a plurality of first openings arranged in a first direction
  • the plurality of electrical connection portions includes a plurality of first openings disposed in the plurality of first openings.
  • An electrical connection portion the signal line includes a gate line
  • each of the first electrical connection portions is electrically connected to one of the gate lines
  • the plurality of openings includes a plurality of second openings arranged in a second direction
  • the plurality of electrical connection portions includes a plurality of second electrical connection portions arranged in the plurality of second openings
  • the signal line includes a source/drain line
  • each of the second electrical connection portions is electrically connected Connected to one of the source/drain lines.
  • the light-emitting part is a micro light-emitting diode or an organic electroluminescent body.
  • a method for manufacturing a display panel includes the following steps:
  • a first substrate In the fan-out circuit forming process, a first substrate is provided.
  • the first substrate includes a base substrate and a signal line.
  • the base substrate has a first surface and a second surface opposite to the first surface.
  • the wire is arranged on the first surface of the base substrate, and a fan-out circuit is formed on the second surface;
  • a plurality of openings are opened on the edge of the base substrate, the openings pass through the intermediate substrate, the first end is connected to the fan-out circuit, and the second end is connected to the signal line;
  • An electrical connection forming step forming an electrical connection in the opening, and the electrical connection is electrically connected between the signal line and the fan-out circuit to obtain an array substrate;
  • Bonding process bonding a driving chip on the fan-out circuit
  • the light-emitting portion is electrically connected to the array substrate.
  • the step of opening a plurality of openings on the edge of the base substrate includes forming a groove on the side wall of the base substrate or opening a through hole in the base substrate. hole.
  • the process of forming the electrical connection portion includes the following steps:
  • a metal layer is formed in the opening to form the electrical connection part.
  • a spliced display panel is formed by splicing multiple display panels
  • the display panel includes a light-emitting part, an array substrate, and a driving chip, the light-emitting part is electrically connected to one side of the array substrate, and the driving chip is electrically connected to the other side of the array substrate,
  • the array substrate includes:
  • a transparent substrate having a first surface and a second surface opposite to the first surface
  • the signal line is arranged on the first surface of the base substrate
  • a fan-out circuit arranged on the second surface of the base substrate, and the fan-out circuit is electrically connected to the signal line;
  • the driving chip is arranged on the second surface side of the base substrate and is electrically connected to the fan-out circuit,
  • the array substrate is provided with a plurality of openings, the plurality of openings are located at the edge of the array substrate and penetrate the array substrate, the array substrate includes a plurality of electrical connection portions, the electrical connection portions are arranged in the openings Wherein, the electrical connection part electrically connects the signal line and the fan-out circuit.
  • the opening is a groove opened on the side wall of the array substrate.
  • the opening is a through hole penetrating the array substrate.
  • a recess is formed on the side wall of the array substrate in the opening, the electrical connection portion includes an electrical connection protrusion, and the signal line is exposed from the recess, The electrical connection protrusion is in contact with the signal line.
  • the plurality of openings includes a plurality of first openings arranged in a first direction
  • the plurality of electrical connection portions includes a plurality of first openings arranged in the plurality of first openings.
  • the first electrical connection portion, the signal line includes a gate line, and each of the first electrical connection portions is electrically connected to one of the gate lines.
  • the plurality of openings includes a plurality of second openings arranged in a second direction
  • the plurality of electrical connection portions includes a plurality of second openings arranged in the plurality of second openings.
  • the second electrical connection part, the signal line includes a source/drain line, and each second electrical connection part is electrically connected to one of the source/drain lines.
  • the plurality of openings comprise a plurality of first openings arranged in a first direction
  • the plurality of electrical connection parts comprise a plurality of first openings arranged in the plurality of first openings.
  • the plurality of first electrical connection portions includes a gate line, each of the first electrical connection portions are electrically connected to one of the gate lines, and the plurality of openings includes a plurality of Arranged second openings, the plurality of electrical connection parts includes a plurality of second electrical connection parts arranged in the plurality of second openings, the signal line includes a source/drain line, each of the second The electrical connection parts are all electrically connected to one of the source/drain lines.
  • the light-emitting part is a micro light-emitting diode or an organic electroluminescent body.
  • the fan-out circuit and the driving chip of the display panel of the present application are arranged on the back of the array substrate, and the driving chip, the fan-out circuit and the TFT layer are electrically connected by opening an opening at the edge of the array substrate and forming an electrical connection part in the opening , Can make the display area closer to the border area, so as to obtain a borderless or narrow border effect.
  • the spliced display panel of the present application can reduce the splicing seam to the size of one pixel unit by using the above-mentioned borderless or narrow-frame display panel, thereby making it difficult for the user to perceive the existence of the splicing seam visually, thereby eliminating or reducing the size of the splicing seam.
  • the effect of stitching is not limited to stitching.
  • FIG. 1 is a schematic front view of a display panel according to an embodiment of the application.
  • FIG. 2 is a schematic diagram of the back of the display panel of FIG. 1.
  • Fig. 3 is a cross-sectional view of the display panel of Fig. 1 along the line A-A.
  • Fig. 4 is a cross-sectional view of the display panel of Fig. 1 along the line B-B.
  • FIG. 5 is a schematic diagram of the back of a display panel according to another embodiment of the application.
  • FIG. 6(a)-FIG. 6(k) are schematic cross-sectional views taken along line A-A of a method for manufacturing a display panel according to an embodiment of the application.
  • FIG. 7 is a schematic front view of a spliced display panel according to an embodiment of the application.
  • the display panel 100 includes an array substrate 10, a plurality of light emitting parts 20 and a driving chip 30.
  • the plurality of light emitting parts 20 are electrically connected to one side of the array substrate 10 in a matrix
  • the driving chip 30 is electrically connected to the other side of the array substrate 10.
  • the light emitting unit 20 is electrically connected to the display side of the array substrate 10
  • the driving chip 30 is electrically connected to the non-display side of the array substrate 10.
  • the array substrate 10 includes a transparent substrate 11, a thin film transistor (TFT) layer 12 (hereinafter referred to as a TFT layer), a passivation layer 13, a pixel electrode layer 14 and a fan-out circuit 15.
  • the transparent substrate 11 has a first surface 11a and a second surface 11b opposite to the first surface 11a.
  • the TFT layer 12 is disposed on the first surface 11 a of the transparent substrate 11.
  • the passivation layer 13 and the pixel electrode layer 14 are sequentially stacked on the TFT layer 12.
  • the fan-out circuit 15 is disposed on the second surface 11 b of the transparent substrate 11.
  • the fan-out circuit 15 is used to electrically connect the TFT layer 12 and the driving chip 30.
  • a plurality of openings 101 are opened on the array substrate 10.
  • a plurality of openings 101 are located at the edge of the array substrate 10 and penetrate the array substrate 10.
  • the array substrate 10 further includes a plurality of electrical connection parts 16. Each electrical connection part 16 is disposed in an opening 101.
  • the electrical connection portion 16 is used to electrically connect the TFT layer 12 and the fan-out circuit 15.
  • the transparent substrate 11 is used to support other elements on the array substrate 10.
  • the base substrate 11 may be, for example, a plastic substrate or a glass substrate.
  • the base substrate 10 may be a flexible substrate, such as a polyimide substrate.
  • the TFT layer 12 includes a plurality of thin film transistors for display (Thin Film Transitor, TFT).
  • the TFT layer 12 includes a channel light shielding layer 121, a buffer layer 122, a semiconductor layer 123, a gate insulating layer 124, a gate metal layer 125, an interlayer insulating layer 126 and a source and drain metal layer 127 stacked on the transparent substrate 11.
  • the channel light shielding layer 121 is disposed on the first surface 11 a of the transparent substrate 11.
  • the channel light shielding layer 1211 is used to shield the channel from light.
  • the channel light shielding layer 220 may be a metal having a light shielding effect, such as molybdenum (Mo), silver (Ag), aluminum (Al), a molybdenum copper (MoCu) alloy, a stack of molybdenum (Mo) and aluminum (Al), and the like.
  • the buffer layer 122 covers the channel light shielding layer 121 and the transparent substrate 11.
  • the buffer layer 122 is used to prevent the metal of the channel light shielding layer 121 from diffusing into the semiconductor layer 123.
  • the buffer layer 122 may be SiNx, SiOx, a stack of SiNx and SiOx, or a stack of AlOx and SiOx, or the like.
  • the semiconductor layer 123 is disposed on the buffer layer 122.
  • the semiconductor layer 123 is provided corresponding to the channel light shielding layer 121.
  • the semiconductor layer 123 is a channel layer of the TFT.
  • the semiconductor layer 123 may use an oxide semiconductor material, for example, indium zinc oxide (IZO), gallium indium oxide (IGO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium gallium zinc tin oxide (IGTO), Oxide (IGZTO) and so on.
  • the semiconductor layer 123 may also use, for example, amorphous silicon, single crystal silicon, low-temperature polycrystalline silicon, or the like.
  • the gate insulating layer 124 covers the semiconductor layer 123 and the buffer layer 122.
  • the gate metal layer 125 is disposed on the gate insulating layer 124.
  • the gate metal layer 125 includes a gate 125G and a gate line 125GL connected to the gate 125G.
  • the gate 125G is disposed on the semiconductor layer 123. When viewed from above, the plurality of gate lines 125GL are arranged along the first direction X.
  • the material of the gate metal layer 125 may be tantalum (Ta), tungsten (W), molybdenum (Mo), aluminum (Al), titanium (Ti), copper-niobium (CuNb) alloy, etc., or may be, for example, copper (Cu) Laminated layers with molybdenum (Mo), laminated layers of copper (Cu) and molybdenum-titanium (MoTi) alloys, laminated layers of copper (Cu) and titanium (Ti), laminated layers of aluminum (Al) and molybdenum (Mo), and Stacked layers of molybdenum (Mo) and tantalum (Ta), stacked layers of molybdenum (Mo) and tungsten (W), stacked layers of molybdenum (Mo)-aluminum (Al)-molybdenum (Mo), etc.).
  • the interlayer insulating layer 126 covers the buffer layer 122, the semiconductor layer 123, and the gate metal layer 125.
  • As the interlayer insulating layer 126 for example, a laminate of SiOx, SiNx, and SiOx, or the like can be used.
  • the source and drain metal layer 127 is disposed on the interlayer insulating layer 126.
  • the source-drain metal layer 127 includes a source 127S, a drain 127D, and a source/drain line 127L connected to the source 127S.
  • the source electrode 127S and the drain electrode 127D are located at opposite ends of the semiconductor layer 123.
  • the source electrode 127S and the drain electrode 127D are respectively connected to the semiconductor layer 123 through through holes opened in the interlayer insulating layer 126.
  • the gate 125G and the gate insulating layer 124 are located between the source 127S and the drain 127D.
  • the plurality of source/drain lines 127L are arranged along the second direction Y.
  • the first direction X and the second direction Y are perpendicular to each other.
  • the source and drain metal layer 127 can be made of the same material as the gate metal layer 125, for example, a stack of copper (Cu) and molybdenum (Mo), a stack of copper (Cu) and molybdenum titanium (MoTi) alloy, copper (Cu) and titanium (Ti) stacks, aluminum (Al) and molybdenum (Mo) stacks, copper-niobium (CuNb) alloys, etc.
  • the passivation layer 13 is disposed on the TFT layer 12 to flatten the surface of the TFT layer 12. It can use the same material as the above-mentioned insulating layer. For example, a laminate of SiOx, SiNx, and SiOx.
  • the light-emitting electrode layer 14 is disposed on the passivation layer 13, and the light-emitting electrode layer 14 includes a pixel electrode 141 and a common electrode 142.
  • the pixel electrode 141 and the common electrode 142 are used to supply power to the light-emitting part 20 and control the light emission of the light-emitting part 20.
  • the pixel electrode 141 may be connected to one of the source electrode 127S and the drain electrode 127D.
  • the common electrode 142 is supplied with a common voltage.
  • the fan-out circuit 15 is disposed on the second surface 11 b of the base substrate 10 and located at the edge of the array substrate 10.
  • the fan-out circuit 15 includes a stacked metal circuit layer 151, a transparent circuit layer 153, and a circuit insulating layer 152 located between the metal circuit layer 151 and the transparent circuit layer 153.
  • the material of the metal circuit layer 151 may be a stack of Mo (molybdenum) and Cu (copper), or a stack of molybdenum titanium alloy (MoTi) and Cu (copper).
  • the material of the transparent circuit layer 153 is ITO and IZO.
  • the plurality of openings 101 are grooves opened on the side wall 10 a of the array substrate 10.
  • the plurality of openings 101 includes a plurality of first openings 101 a arranged in the first direction X and a plurality of second openings 101 b arranged in the second direction Y.
  • the plurality of electrical connection portions 16 includes a plurality of first electrical connection portions 16a provided in the first opening 101a and a plurality of second electrical connection portions 16b provided in the second opening 101b.
  • the first electrical connection portion 16a is electrically connected to the gate line 125GL
  • the second electrical connection portion 16b is electrically connected to the source/drain line 127L.
  • the gate line 125GL is connected to the fan-out circuit 15 through the first electrical connection portion 16a, and is finally electrically connected to the driving chip 30.
  • the source/drain line 127L is connected to the fan-out circuit 15 through the second electrical connection portion 16b, and is finally electrically connected to the source driver chip.
  • the electrical connection part is made of conductive material.
  • the electrical connection portion 16 may be a patterned metal trace.
  • the opening 101' is a through hole opened in the array substrate 210, including a plurality of first openings 101a' arranged along the first direction X and a plurality of The second openings 101b' are arranged along the second direction Y.
  • the present application may only include the first opening 101a and the first electrical connection portion 16a in the above embodiment, or only include the second opening 101b and the second electrical connection portion 16b.
  • One of the gate line 125GL and the source line 127SL is electrically connected to the driving chip 30 through the electrical connection portion 16, and the other is electrically connected to the driving chip 30 through other means.
  • the first electrical connection portion 16a includes a first electrical connection protrusion 16a1.
  • the second electrical connection portion 16b includes a second electrical connection protrusion 16b1.
  • a recess is formed in the side wall 10a of the array substrate 10 located in the opening 11.
  • the gate line 125GL is exposed from the recess 10a1 to contact the first electrical connection protrusion 16a1.
  • the source/drain line 127L is exposed from the recess 10a1 to contact the second electrical connection bump 16b1.
  • the display panel 100 is a micro light emitting diode (Micro light Emitting diode, MicroLED) type display panel.
  • the light-emitting part 20 is a micro-light-emitting diode light-emitting body, which includes a first electrode 21, a second electrode 22, a pixel defining layer, a micro-light emitting diode located in the middle of the pixel defining layer, a protective layer, and the like.
  • the first electrode 21 and the second electrode 22 are connected to the pixel electrode 141 and the common electrode 142, respectively.
  • micro light emitting diodes can be divided into vertical structure micro light emitting diodes and horizontal structure micro light emitting diodes.
  • the first electrode 21 and the second electrode 22 of the vertical structure micro light emitting diode are respectively located on the upper and lower sides of the micro light emitting diode.
  • the first electrode 21 and the second electrode 22 of the horizontal structure of the micro light emitting diode are both located on the lower side of the micro light emitting diode.
  • the micro light emitting diode 20 has a horizontal structure.
  • the driving chip 30 is disposed on the second surface 11 b side of the transparent substrate 11 and is electrically connected to the fan-out circuit 15.
  • the driving chip 30 can be in the form of a flip chip film, that is, the driving chip 30 is arranged on the film and connected to the fan-out circuit 15.
  • the driving chip 30 may include a gate driving chip and a source/drain driving chip.
  • the gate driving chip is connected to the gate line 125GL.
  • the source/drain driving chip is electrically connected to the source/drain line 127L.
  • the fan-out circuit 15 and the driving chip 30 of the display panel 100 of the present application are arranged on the back of the array substrate 10.
  • the driving chip 30 By opening an opening 101 at the edge of the array substrate 10, and forming an electrical connection part 16 in the opening 101, the driving chip 30, the fan The output circuit 16 and the TFT layer 12 are electrically connected, so that the display area can be closer to the frame area, thereby obtaining a frameless or narrow frame effect.
  • the array substrate may also include common electrode lines, power supply voltage lines and other signal lines for transmitting signals
  • the driving chip may also include other driving chips such as a power supply chip. It is also possible to open an opening at the edge of the array substrate and form an electrical connection part in the opening to electrically connect the driving chip, fan-out circuit, and signal line, so that the display area can be brought closer to the frame area, thereby obtaining a borderless or narrow frame effect.
  • An embodiment of the present application provides a method for manufacturing a display panel 100, which includes the following steps:
  • a first substrate 1000 is provided.
  • the first substrate 1000 includes a transparent substrate 11, a TFT layer 12, a passivation layer 13, and a pixel electrode layer 14.
  • the transparent substrate 11 has a first surface 11a and a first surface 11a. The surface 11a is opposite to the second surface 11b.
  • the TFT layer 12 is disposed on the first surface 11 a of the transparent substrate 11.
  • a fan-out circuit 15 is formed on the second surface 11b to obtain a base substrate 1001.
  • a plurality of openings 101 are opened on the edge of the base substrate 1001.
  • the opening 101 penetrates the intermediate substrate, the first end of the opening 101 is connected to the fan-out circuit 15, and the second end is connected to the TFT layer 12.
  • the opening 101 is located at a position where the fan-out circuit 15 overlaps the orthographic projection of the TFT layer 12.
  • the electrical connection portion 16 is formed in the opening 101, and the electrical connection portion 16 is electrically connected between the TFT layer 12 and the fan-out circuit 15 to obtain the array substrate 10.
  • the driving chip 30 is bonded on the fan-out circuit 15.
  • the light-emitting portion 20 is electrically connected to the array substrate 10.
  • the TFT layer 12 includes a channel light shielding layer 121 laminated on the transparent substrate 11, a buffer layer 122, a semiconductor layer 123, and a gate insulating layer 124, a gate metal layer 125, an interlayer insulating layer 126, and a source and drain metal layer 127.
  • the gate metal layer 125 includes a gate 125G and a gate line 125GL.
  • the source-drain metal layer 127 includes a source 127S, a drain 127D, and a source/drain line 127L.
  • the pixel electrode layer 14 is further provided with a first protective layer 12a and a second protective layer 12b.
  • the first protection layer 12a and the second protection layer 12b are used to protect the pixel electrode layer 14 when the first substrate 1000 is turned upside down to form the fan-out circuit 15.
  • the step of forming the fan-out circuit 15 on the second surface 11b includes: turning the first substrate 1000 upside down so that the second surface 11b faces upward.
  • a metal circuit layer 152 and a circuit insulating film 152 are sequentially formed on the second surface 11b.
  • a fan-out circuit metal film can be deposited and patterned into the metal circuit layer 151.
  • a circuit insulating film 152 is deposited and formed on the metal circuit layer 151.
  • a through hole 152a is opened on the fan-out circuit insulating film 152 and a transparent circuit layer 153 is formed.
  • a transparent conductive layer may be deposited in the through hole 152a, and the transparent conductive layer may be patterned to form the transparent circuit layer 153.
  • the metal circuit layer 151 and the transparent circuit layer 153 are electrically connected to form a fan-out circuit 15 together.
  • the base substrate 1001 may further include a first organic protective layer 17 covering the fan-out circuit 15 to protect the fan-out circuit 15.
  • the first organic protective layer 17 may be formed by depositing an etching barrier layer.
  • the above-mentioned substrate is turned upside down so that the first surface 11a faces upward.
  • the first protective layer 12 a and the second protective layer 12 b are removed, and a second organic protective layer 18 is formed on the pixel electrode layer 14.
  • the second organic protective layer 18 may also be formed by depositing an etching barrier layer.
  • the base substrate 1001 protected by the first organic protective layer 17 and the second organic protective layer 18 is obtained.
  • Figure 6 (d) ⁇ Figure 6 (e) is a schematic top view of the opening forming process.
  • the step of opening a plurality of openings 101 on the edge of the base substrate 1001 includes forming a groove on the sidewall 1000a of the base substrate 1001. Specifically, a groove is formed on the base substrate 1001 by laser drilling or mechanical drilling.
  • the plurality of openings 101 includes a plurality of first openings 101a arranged in the first direction X and second openings 101b arranged in the second direction Y.
  • Figure 6(f) to Figure 6(i) are schematic top views of the forming process of the electrical connection portion.
  • Fig. 6(h) to Fig. 6(i) are cross-sectional views taken along the line A-A and along the line B-B in the process of forming the electrical connection portion, respectively.
  • the process of forming the electrical connection portion includes the following steps:
  • the sidewall 10a in the opening 101 is etched to expose the gate line 125GL and the source/drain line 127L.
  • the sidewall 10a in the first opening 101a is etched to the gate metal layer 125 to form a recess 10a1 to expose the gate line 125GL.
  • the sidewall 10a in the second opening 101b is etched to the source and drain metal layer 127 to form a recess 10a1 to expose the source/drain line 127L.
  • the etching method for example, a chemical etching method can be used.
  • a metal layer 16' is formed in the opening 101 to form an electrical connection portion 16.
  • the method of forming the metal layer 16' may be, for example, plating.
  • the metal layer 16' outside the groove is removed by, for example, grinding, and only the metal layer 16' in the groove is left, and the metal layer 16' is patterned into metal traces to form the electrical connection portion 16.
  • the first electrical connection portion 16a includes a first electrical connection protrusion 16a1.
  • the second electrical connection portion 16b includes a second electrical connection protrusion 16b1.
  • the gate line 125GL is in contact with the first electrical connection bump 16a1.
  • the source/drain line 127L is in contact with the second electrical connection bump 16b1.
  • the process of forming the electrical connection portion can also be achieved by directly printing metal traces on the sidewall 10a in the opening 101, forming a metal layer in the opening, and then firing the metal traces or Damascus method by laser. Wait for it to be done.
  • the opening 101' (including the first opening 101a' and the second opening 101b') may also be a through hole opened in the array substrate 210. At this time, the through hole is filled with metal to form an electrical connection portion.
  • the bonding process includes the following steps: removing the first organic protective layer 17 and bonding the driving chip 30 on the fan-out circuit 15.
  • the light-emitting portion forming process includes the following steps: removing the second organic protective layer 18, electrically connecting the first electrode 21 of the light-emitting portion 20 to the pixel electrode 141, and electrically connecting the second electrode 22 of the light-emitting portion 20 to the common electrode 142.
  • the display panel 100 of the first embodiment of the present application is obtained.
  • the array substrate may also include common electrode lines, power supply voltage lines and other signal lines for transmitting signals
  • the driving chip may also include other driving chips such as a power supply chip. It is also possible to open an opening at the edge of the array substrate by the same method, and form an electrical connection part in the opening to electrically connect the driving chip, fan-out circuit, and signal line, so that the display area can be closer to the frame area, thereby obtaining a frameless Or narrow border effect.
  • the spliced display panel 1 of the third embodiment of the present application includes a plurality of display panels 100 of the first embodiment closely arranged in a matrix. Since the multiple display panels 100 are borderless or narrow-frame panels, the spliced display panel 1 does not have obvious splicing seams.
  • the spliced display panel 1 of the third embodiment of the present application uses the borderless or narrow border display panel 100 of the first embodiment to reduce the splicing seam to the size of one pixel unit, thereby making it difficult for users to visually perceive the splicing.
  • the existence of seams has the effect of eliminating or reducing splicing seams.
  • microled display panels are listed, and it can be understood that the present application can also be used in other active light emitting display panels.
  • organic electroluminescence Organic Light-Emitting Diode, OLED
  • OLED Organic Light-Emitting Diode
  • an organic electroluminescent body is used for the light emitting part.
  • the pixel electrode is the anode of the organic electroluminescent body. It can also be applied to passive light-emitting display panels, such as liquid crystal display panels.

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Abstract

一种显示面板(100,200)，包括发光部(20)、阵列基板(10)以及驱动芯片(30)。阵列基板(10)包括衬底基板(11)；信号线，设置于衬底基板(11)的第一表面(11a)；扇出电路(15)，设置于衬底基板(11)的第二表面(11b)；驱动芯片(30)设置于第二表面(11b)侧，电连接于扇出电路(15)，阵列基板(10)上开设有位于阵列基板(10)边缘并贯穿阵列基板(10)的多个开口(101)，和多个设置于开口(101)中的电连接部(16)，电连接部(16)电连接信号线与扇出电路(15)。

Description

显示面板、制造方法以及拼接显示面板 技术领域
本申请涉及显示领域，尤其涉及一种显示面板、制造方法以及拼接显示面板。
 背景技术
在显示领域中，无边框或者窄边框显示器逐渐成为主流。对于显示器，例如液晶显示器（LiquidCrystalsDisplay，LCD）、有机电致发光显示器（Organic Light-Emitting Display，OLED）、发光二极管（light emitting diode，LED）显示器而言，屏幕尺寸越大，制造难度以及单位面积的制造成本越高。因此，大型显示器通常采用多块中小型显示器拼接而成。中小型显示器的边框的存在会导致拼接显示面板的显示区域出现条形的拼接缝，降低显示品质。
 技术问题
有鉴于此，本申请目的在于提供一种无边框或者窄边框的显示面板及其制造方法。此外，本申请还提供一种可以消除或减小拼接缝的拼接显示面板。
 技术解决方案
一种显示面板，包括发光部、阵列基板以及驱动芯片，所述发光部电连接于所述阵列基板一侧，所述驱动芯片电连接于所述阵列基板另一侧，
所述阵列基板包括：
透明基板，具有第一表面和与所述第一表面相对的第二表面；
信号线，设置于所述衬底基板的第一表面；
扇出电路，设置于所述衬底基板的第二表面，所述扇出电路与所述信号线电连接；
所述驱动芯片设置于所述衬底基板的第二表面侧，电连接于所述扇出电路，
所述阵列基板上开设有多个开口，所述多个开口位于所述阵列基板边缘并贯穿所述阵列基板，所述阵列基板包括多个电连接部，所述电连接部设置于所述开口中，所述电连接部电连接所述信号线与所述扇出电路。
在本申请的一显示面板中，所述开口为开设于所述阵列基板的侧壁上的凹槽。
在本申请的一显示面板中，所述开口为贯穿所述阵列基板的通孔。
在本申请的一显示面板中，所述开口内的所述阵列基板侧壁上开设有凹部，所述电连接部包括电连接凸起，所述信号线从所述凹部中暴露出来，所述电连接凸起与所述信号线接触。
在本申请的一显示面板中，所述多个开口包括多个沿第一方向排列的第一开口，所述多个电连接部包括设置于所述多个第一开口中的多个第一电连接部，所述信号线包括栅极线，每一所述第一电连接部均电连接于一条所述栅极线。
在本申请的一显示面板中，所述多个开口包括多个沿第二方向排列的第二开口，所述多个电连接部包括设置于所述多个第二开口中的多个第二电连接部，所述信号线包括源/漏极线，每一所述第二电连接部均电连接于一条所述源/漏极线。
在本申请的一显示面板中，所述多个开口包括多个沿第一方向排列的第一开口，所述多个电连接部包括设置于所述多个第一开口中的多个第一电连接部，所述信号线包括栅极线，每一所述第一电连接部均电连接于一条所述栅极线，所述多个开口包括多个沿第二方向排列的第二开口，所述多个电连接部包括设置于所述多个第二开口中的多个第二电连接部，所述信号线包括源/漏极线，每一所述第二电连接部均电连接于一条所述源/漏极线。
在本申请的一显示面板中，所述发光部为微型发光二极管或者有机电致发光体。
一种显示面板的制造方法，其包括以下步骤：
扇出电路形成工序，提供一第一基板，所述第一基板包括衬底基板以及信号线，所述衬底基板具有第一表面和与所述第一表面相对的第二表面，所述信号线设置于所述衬底基板的第一表面，在所述第二表面形成扇出电路；
开口形成工序，在衬底基板的边缘开设多个开口，所述开口贯穿所述中间基板，所述第一端连接所述扇出电路，所述第二端连接所述信号线；
电连部接形成工序，在所述开口中形成电连接部，所述电连接部电连接于所述信号线和所述扇出电路之间，得到阵列基板；
绑定工序，在所述扇出电路上绑定驱动芯片，
发光部形成工序，在所述阵列基板上电连接发光部。
在本申请的一显示面板的制造方法中，所述在衬底基板的边缘开设多个开口的步骤包括在所述衬底基板的侧壁上形成凹槽或者在所述衬底基板中开设通孔。
在本申请的一显示面板的制造方法中
所述电连接部形成工序包括以下步骤：
蚀刻所述开口内的侧壁，暴露出所述信号线，
在所述开口中形成金属层，形成所述电连接部。
一种拼接显示面板，由多个显示面板拼接而成，
所述显示面板包括发光部、阵列基板以及驱动芯片，所述发光部电连接于所述阵列基板一侧，所述驱动芯片电连接于所述阵列基板另一侧，
所述阵列基板包括：
透明基板，具有第一表面和与所述第一表面相对的第二表面；
信号线，设置于所述衬底基板的第一表面；
扇出电路，设置于所述衬底基板的第二表面，所述扇出电路与所述信号线电连接；
所述驱动芯片设置于所述衬底基板的第二表面侧，电连接于所述扇出电路，
所述阵列基板上开设有多个开口，所述多个开口位于所述阵列基板边缘并贯穿所述阵列基板，所述阵列基板包括多个电连接部，所述电连接部设置于所述开口中，所述电连接部电连接所述信号线与所述扇出电路。
在本申请的一种拼接显示面板中，所述开口为开设于所述阵列基板的侧壁上的凹槽。
在本申请的一种拼接显示面板中，所述开口为贯穿所述阵列基板的通孔。
在本申请的一种拼接显示面板中，所述开口内的所述阵列基板侧壁上开设有凹部，所述电连接部包括电连接凸起，所述信号线从所述凹部中暴露出来，所述电连接凸起与所述信号线接触。
在本申请的一种拼接显示面板中，所述多个开口包括多个沿第一方向排列的第一开口，所述多个电连接部包括设置于所述多个第一开口中的多个第一电连接部，所述信号线包括栅极线，每一所述第一电连接部均电连接于一条所述栅极线。
在本申请的一种拼接显示面板中，所述多个开口包括多个沿第二方向排列的第二开口，所述多个电连接部包括设置于所述多个第二开口中的多个第二电连接部，所述信号线包括源/漏极线，每一所述第二电连接部均电连接于一条所述源/漏极线。18、如权利要求12所述的拼接显示面板，其中所述多个开口包括多个沿第一方向排列的第一开口，所述多个电连接部包括设置于所述多个第一开口中的多个第一电连接部，所述信号线包括栅极线，每一所述第一电连接部均电连接于一条所述栅极线，所述多个开口包括多个沿第二方向排列的第二开口，所述多个电连接部包括设置于所述多个第二开口中的多个第二电连接部，所述信号线包括源/漏极线，每一所述第二电连接部均电连接于一条所述源/漏极线。
在本申请的一种拼接显示面板中，所述发光部为微型发光二极管或者有机电致发光体。
 有益效果
本申请的显示面板的扇出电路及驱动芯片设置在阵列基板的背面，通过在阵列基板边缘处开设开口，并在开口中形成电连接部将驱动芯片、扇出线路以及TFT层三者电连接，能够使显示区域更加靠近边框区，从而获得无边框或窄边框效果。
本申请的拼接显示面板通过使用上述无边框或者窄边框的显示面板，能够将拼接缝缩小至一个像素单元大小，从而使用户在视觉上难以察觉拼接缝的存在，起到消除或者减小拼接缝的效果。
 附图说明
为了更清楚地说明本申请中的技术方案，下面将对实施方式描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施方式，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请一实施方式的显示面板的正面示意图。
图2为图1的显示面板的背面示意图。
图3为图1的显示面板沿A-A线的剖视图。
图4为图1的显示面板沿B-B线的剖视图。
图5为本申请另一实施方式的显示面板的背面示意图。
图6（a）-图6（k）为本申请一实施方式的显示面板的制造方法的沿A-A线的剖面示意图。
图7为本申请一实施方式的拼接显示面板的正面示意图。
 本发明的实施方式
下面将结合本申请实施方式中的附图，对本申请中的技术方案进行清楚、完整地描述。显然，所描述的实施方式仅仅是本申请一部分实施方式，而不是全部的实施方式。基于本申请中的实施方式，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施方式，都属于本申请保护的范围。
请参考图1-图4，本申请一实施方式的显示面板100包括阵列基板10、多个发光部20以及驱动芯片30。多个发光部20呈矩阵状电连接于阵列基板10一侧，驱动芯片30电连接于阵列基板10另一侧。具体地，发光部20电连接于阵列基板10显示侧，驱动芯片30电连接于阵列基板10非显示侧。
阵列基板10包括：透明基板11、薄膜晶体管（Thin Film Transistor，TFT）层12（后称TFT层）、钝化层13、像素电极层14以及扇出电路15。透明基板11具有第一表面11a和与第一表面11a相对的第二表面11b。TFT层12设置于透明基板11的第一表面11a。钝化层13以及像素电极层14依次层叠于TFT层12上。扇出电路15设置于透明基板11的第二表面11b。扇出电路15用于电连接TFT层12与驱动芯片30。
阵列基板10上开设有多个开口101。多个开口101位于阵列基板10边缘并贯穿阵列基板10。阵列基板10还包括多个电连接部16。每一电连接部16设置于一开口101中。电连接部16用于电连接TFT层12和扇出电路15。
具体地，透明基板11用于支撑阵列基板10上的其他元件。衬底基板11例如可以为塑料基板或者玻璃基板。在本申请一实施方式中，衬底基板10可以是柔性基板，例如聚酰亚胺基板。
TFT层12包括多个用于显示的薄膜晶体管（Thin Film Transitor，TFT）。TFT层12包括层叠于透明基板11上的沟道遮光层121，缓冲层122，半导体层123，栅极绝缘层124，栅极金属层125，层间绝缘层126以及源漏极金属层127。
沟道遮光层121设置于透明基板11的第一表面11a。沟道遮光层1211用于对沟道进行遮光。沟道遮光层220可以是具有遮光效果的金属，例如钼（Mo）、银（Ag）、铝（Al）、钼铜（MoCu）合金、钼（Mo）和铝（Al）的叠层等。
缓冲层122覆盖沟道遮光层121和透明基板11。缓冲层122用于防止沟道遮光层121的金属扩散进入半导体层123。缓冲层122可以为SiNx、SiOx、SiNx和SiOx的层叠体或者AlOx和SiOx的层叠体等。
半导体层123设置于缓冲层122上。半导体层123对应沟道遮光层121设置。半导体层123为TFT的沟道层。半导体层123可以采用氧化物半导体材料，例如，铟锌氧化物（IZO）、镓铟氧化物（IGO）、铟镓锌氧化物 (IGZO)、铟镓锡氧化物（IGTO）、铟镓锌锡氧化物（IGZTO）等。半导体层123也可以采用例如，非晶硅、单晶硅、低温多晶硅等。
栅极绝缘层124覆盖半导体层123和缓冲层122。栅极绝缘层124可以采用SiNx、SiOx、AlOx、SiNx和SiOx的层叠体或者AlOx和SiOx的层叠体等。
栅极金属层125设置于栅极绝缘层124上。栅极金属层125包括栅极125G和连接于栅极125G的栅极线125GL。栅极125G设置于半导体层123上。俯视时，多条栅极线125GL沿第一方向X排列。栅极金属层125的材料可以为钽(Ta)、钨(W)、钼(Mo)、铝(Al)、钛（Ti）、铜铌（CuNb）合金等，也可以为例如铜（Cu）和钼(Mo)的叠层、铜（Cu）和钼钛（MoTi）合金的叠层、铜（Cu）和钛（Ti）的叠层、铝（Al）和钼（Mo）的叠层以及钼（Mo）和钽（Ta）的叠层、钼（Mo）和钨(W)的叠层、钼（Mo）-铝(Al)-钼(Mo)的叠层等。
层间绝缘层126覆盖缓冲层122、半导体层123和栅极金属层125。层间绝缘层126可以采用例如SiOx、SiNx和SiOx的层叠体等。
源漏极金属层127设置于层间绝缘层126上。源漏极金属层127包括源极127S、漏极127D以及与源极127S连接的源/漏极线127L。源极127S和漏极127D位于半导体层123相对两端。源极127S和漏极127D通过开设于层间绝缘层126中的通孔分别与半导体层123连接。栅极125G和栅极绝缘层124位于源极127S与漏极127D之间。在TFT导通时，源极127S和漏极127D之间的半导体层123中有电流流过。多条源/漏极线127L沿第二方向Y排列。在本申请一实施方式中，第一方向X和第二方向Y相互垂直。源漏极金属层127可以采用与栅极金属层125相同的材料，例如可以采用铜（Cu）和钼(Mo)的叠层、铜（Cu）和钼钛（MoTi）合金的叠层、铜（Cu）和钛（Ti）的叠层、铝（Al）和钼（Mo）的叠层以及铜铌（CuNb）合金等。
钝化层13设置于TFT层12上，使TFT层12表面平坦化。其可以采用上述绝缘层相同的材料。例如，SiOx、SiNx和SiOx的层叠体等。
发光电极层14设置于钝化层13之上，发光电极层14包括像素电极141和公共电极142。像素电极141和公共电极142用于对发光部20供电，控制发光部20的发光。像素电极141可以连接于源极127S和漏极127D的其中一个。公共电极142被提供一个公共电压。
扇出电路15设置于衬底基板10的第二表面11b，且位于阵列基板10的边缘。扇出电路15包括层叠的金属电路层151、透明电路层153以及位于金属电路层151和透明电路层153之间的电路绝缘层152。金属电路层151的材料可以为Mo（钼）和Cu（铜）的叠层，钼钛合金（MoTi）和Cu（铜）的叠层。透明电路层153的材料为ITO、IZO。
在本申请一个实施方式中，多个开口101为开设于阵列基板10侧壁10a上的凹槽。多个开口101包括多个沿第一方向X排列的第一开口101a和多个沿第二方向Y排列的第二开口101b。多个电连接部16包括设置于第一开口101a中的多个第一电连接部16a和设置于第二开口101b中的多个第二电连接部16b。第一电连接部16a电连接于栅极线125GL，第二电连接部16b电连接于源/漏极线127L。栅极线125GL通过第一电连接部16a连接于扇出电路15，并最终与驱动芯片30电连接。源/漏极线127L通过第二电连接部16b连接于扇出电路15，并最终与源极驱动芯片电连接。电连接部由导电材料构成。在本申请一实施方式中，电连接部16可以是图案化的金属走线。
请参考图5，在本申请另一实施方式的显示面板200中，开口101’为开设于阵列基板210中的通孔，包括多个沿第一方向X排列的第一开口101a’和多个沿第二方向Y排列的第二开口101b’。
在本申请其他实施方式中，可以只包括上述实施方式中的第一开口101a以及第一电连接部16a，或者只包括第二开口101b以及第二电连接部16b。栅极线125GL和源极线127SL中的一者通过电连接部16与驱动芯片30电连接，另外一者通过其他方式与驱动芯片30电连接。
在本实施方式中，第一电连接部16a包括第一电连接凸起16a1。第二电连接部16b包括第二电连接凸起16b1。位于开口11内的阵列基板10的侧壁10a中开设有凹部。栅极线125GL从凹部10a1中暴露出来与第一电连接凸起16a1接触。源/漏极线127L从凹部10a1中暴露出来与第二电连接凸起16b1接触。
在本申请一实施方式中，显示面板100为微型发光二极管(Micro light emitting diode，MicroLED)型显示面板。发光部20为微型发光二极管发光体，其包括第一电极21，第二电极22，像素定义层，位于像素定义层中间的微发光二极管、保护层等。第一电极21和第二电极22分别连接于像素电极141和公共电极142。在本申请一实施方式中，像素电极141的电位为正，像素电极141通过开设于钝化层中的通孔电连接至漏极127D，在本申请其他实施方式中，像素电极141的电位为负，像素电极141通过开设于钝化层中的通孔电连接至源极127S。微发光二极管按照结构不同，可分为垂直结构的微发光二极管和水平结构的微发光二极管，垂直结构的微发光二极管的第一电极21和第二电极22分别位于微发光二极管的上下两侧，水平的结构的微发光二极管的第一电极21和第二电极22均位于微发光二极管的下侧。在本实施方式中，微发光二极管20为水平结构。
驱动芯片30设置于透明基板11的第二表面11b侧，且电连接于扇出电路15。驱动芯片30可采用覆晶薄膜的形式，即将驱动芯片30设置于薄膜上并连接于扇出电路15。驱动芯片30可包括栅极驱动芯片和源/漏极驱动芯片。栅极驱动芯片连接至栅极线125GL。源/漏极驱动芯片电连接至源/漏极线127L。本申请的显示面板100的扇出电路15以及驱动芯片30设置在阵列基板10的背面，通过在阵列基板10边缘处开设开口101，并在开口101中形成电连接部16将驱动芯片30、扇出线路16以及TFT层12三者电连接，能够使显示区域更加靠近边框区，从而获得无边框或窄边框效果。
在本发明其他实施方式中，阵列基板上还可以包括公共电极线、电源电压线等其他用于传递信号的信号线，驱动芯片也可以包括电源芯片等其他驱动芯片。也可以通过在阵列基板边缘处开设开口，并在开口中形成电连接部将驱动芯片、扇出线路以及信号线三者电连接，能够使显示区域更加靠近边框区，从而获得无边框或窄边框效果。
请参考图6（a）~图6（j），本申请一实施方式提供一种显示面板100的制造方法，其包括以下工序：
扇出电路形成工序，提供一第一基板1000，所述第一基板1000包括透明基板11、TFT层12、钝化层13、以及像素电极层14透明基板11具有第一表面11a和与第一表面11a相对的第二表面11b。TFT层12设置于透明基板11的第一表面11a。在第二表面11b形成扇出电路15，得到衬底基板1001。
开口形成工序，在衬底基板1001的边缘开设多个开口101。开口101贯穿中间基板，开口101第一端连接扇出电路15，第二端连接TFT层12。在本申请一实施方式中，开口101位于扇出电路15与TFT层12的正投影重叠的位置。
电连接部形成工序，在开口101中形成电连接部16，电连接部16电连接于TFT层12和扇出电路15之间，得到阵列基板10。
绑定工序，在扇出电路15上绑定驱动芯片30。
发光部形成工序，在阵列基板10上电连接发光部20。
请参考图6（a）~图6（c），扇出电路形成工序中，TFT层12包括层叠于透明基板11上的沟道遮光层121，缓冲层122，半导体层123，栅极绝缘层124，栅极金属层125，层间绝缘层126以及源漏极金属层127。栅极金属层125包括栅极125G和栅极线125GL。源漏极金属层127包括源极127S、漏极127D以及源/漏极线127L。
像素电极层14上还设置有第一保护层12a和第二保护层12b。第一保护层12a和第二保护层12b用于倒置第一基板1000形成扇出电路15时对像素电极层14进行保护。在第二表面11b形成扇出电路15的步骤包括：将上述第一基板1000倒置，使第二表面11b朝上。在第二表面11b依次形成金属电路层152以及电路绝缘膜152。例如可以是沉积扇出电路金属膜并图案化为金属电路层151。在金属电路层151上沉积形成电路绝缘膜152。
在扇出电路绝缘膜152上开设通孔152a并形成透明电路层153。例如可以是在通孔152a中沉积透明导电层，图案化透明导电层形成透明电路层153。金属电路层151与透明电路层153电连接，共同构成扇出电路15。
此外，衬底基板1001还可以包括覆盖扇出电路15的第一有机保护层17，用于保护扇出电路15。可以通过沉积蚀刻阻挡层形成第一有机保护层17。
在此，将上述基板倒置，使第一表面11a朝上。除去第一保护层12a和第二保护层12b，在像素电极层14上形成第二有机保护层18。第二有机保护层18也可以通过沉积蚀刻阻挡层形成。由此，得到被第一有机保护层17和第二有机保护层18保护的衬底基板1001。
请参考图6（d）~图6（e），图6（d）~图6（e）是开口形成工序的俯视示意图。在开口形成工序中，在衬底基板1001的边缘开设多个开口101的步骤包括在衬底基板1001的侧壁1000a上形成凹槽。具体地，通过激光钻孔或者机械钻孔的方法在衬底基板1001上形成凹槽。多个开口101包括多个沿第一方向X排列的第一开口101a和沿第二方向Y排列的第二开口101b。
请参考6（f）~图6（i），其中，图6（f）~图6（g）是电连接部形成工序的俯视示意图。图6（h）~图6（i）分别为电连接部形成工序中沿A-A线和沿B-B的剖视图。电连接部形成工序包括以下步骤：
蚀刻开口101内的侧壁10a，暴露出栅极线125GL和源/漏极线127L。
具体地，蚀刻第一开口101a中的侧壁10a至栅极金属层125，形成凹部10a1以暴露出栅极线125GL。蚀刻第二开口101b中的侧壁10a至源漏极金属层127，形成凹部10a1以暴露出源/漏极线127L。蚀刻方法例如可以采用化学蚀刻方法。
在开口101内形成金属层16’，以形成电连接部16。形成金属层16’的方法例如可以是镀膜。通过例如研磨的方式除去凹槽外的金属层16’，仅保留凹槽内的金属层16’，使金属层16’图案化为金属走线以形成电连接部16。具体地，第一电连接部16a包括第一电连接凸起16a1。第二电连接部16b包括第二电连接凸起16b1。栅极线125GL与第一电连接凸起16a1接触。源/漏极线127L与第二电连接凸起16b1接触。
在本申请其他实施方式中，电连接部形成工序还可以通过直接在开口101内的侧壁10a上印刷金属走线、在开口内形成金属层，再通过激光烧制出金属走线或者大马士革法等完成。
此外，请参考图5，在本申请另一实施方式的显示面板200中，开口101’（包括第一开口101a’和第二开口101b’）也可以为开设于阵列基板210中的通孔。此时，在通孔内填充金属形成电连接部。
请一并参考图6（j）和图6（k），绑定工序包括以下步骤：除去第一有机保护层17，在扇出电路15上绑定驱动芯片30。
发光部形成工序包括以下步骤：除去第二有机保护层18，在像素电极141上电连接发光部20的第一电极21，在公共电极142上电连接发光部20的第二电极22。
由此，得到本申请第一实施方式的显示面板100。
在本发明其他实施方式中，阵列基板上还可以包括公共电极线、电源电压线等其他用于传递信号的信号线，驱动芯片也可以包括电源芯片等其他驱动芯片。也可以通过相同的方法在阵列基板边缘处开设开口，并在开口中形成电连接部将驱动芯片、扇出线路以及信号线三者电连接，能够使显示区域更加靠近边框区，从而获得无边框或窄边框效果。
本申请第三实施方式的拼接显示面板1包括呈矩阵紧密排列的多块第一实施方式的显示面板100。多块显示面板100由于为无边框或者窄边框面板，该拼接显示面板1中并不存在明显的拼接缝。
本申请第三实施方式的拼接显示面板1通过使用第一实施方式的无边框或者窄边框的显示面板100，能够将拼接缝缩小至一个像素单元大小，从而使用户在视觉上难以察觉拼接缝的存在，起到消除或者减小拼接缝的效果。
以上的实施方式中仅列举了microled型显示面板，可以理解，本申请还可以用于其他主动发光型的显示面板中。例如，有机电致发光（Organic Light-Emitting Diode, OLED）显示器中。也就是说，发光部采用有机电致发光体。此时，像素电极为有机电致发光体的阳极。还可以应用于被动发光型的显示面板，例如液晶显示面板中。
以上对本申请实施方式提供了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施方式的说明只是用于帮助理解本申请。同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (19)

  1. 一种显示面板，其包括发光部、阵列基板以及驱动芯片，所述发光部电连接于所述阵列基板一侧，所述驱动芯片电连接于所述阵列基板另一侧，
    所述阵列基板包括：
    衬底基板，具有第一表面和与所述第一表面相对的第二表面；
    信号线，设置于所述衬底基板的第一表面；
    扇出电路，设置于所述衬底基板的第二表面，所述扇出电路与所述信号线电连接；
    所述驱动芯片设置于所述衬底基板的第二表面侧，电连接于所述扇出电路，
    所述阵列基板上开设有多个开口，所述多个开口位于所述阵列基板边缘并贯穿所述阵列基板，所述阵列基板包括多个电连接部，所述电连接部设置于所述开口中，所述电连接部电连接所述信号线与所述扇出电路。
  2. 如权利要求1所述的显示面板，其中所述开口为开设于所述阵列基板的侧壁上的凹槽。
  3. 如权利要求1所述的显示面板，其中所述开口为贯穿所述阵列基板的通孔。
  4. 如权利要求1所述的显示面板，其中所述开口内的所述阵列基板侧壁上开设有凹部，所述电连接部包括电连接凸起，所述信号线从所述凹部中暴露出来，所述电连接凸起与所述信号线接触。
  5. 如权利要求1所述的显示面板，其中所述多个开口包括多个沿第一方向排列的第一开口，所述多个电连接部包括设置于所述多个第一开口中的多个第一电连接部，所述信号线包括栅极线，每一所述第一电连接部均电连接于一条所述栅极线。
  6. 如权利要求1所述的显示面板，其中所述多个开口包括多个沿第二方向排列的第二开口，所述多个电连接部包括设置于所述多个第二开口中的多个第二电连接部，所述信号线包括源/漏极线，每一所述第二电连接部均电连接于一条所述源/漏极线。
  7. 如权利要求1所述的显示面板，其中所述多个开口包括多个沿第一方向排列的第一开口，所述多个电连接部包括设置于所述多个第一开口中的多个第一电连接部，所述信号线包括栅极线，每一所述第一电连接部均电连接于一条所述栅极线，所述多个开口包括多个沿第二方向排列的第二开口，所述多个电连接部包括设置于所述多个第二开口中的多个第二电连接部，所述信号线包括源/漏极线，每一所述第二电连接部均电连接于一条所述源/漏极线。
  8. 如权利要求1所述的显示面板，其中所述发光部为微型发光二极管或者有机电致发光体。
  9. 一种显示面板的制造方法，其包括以下步骤：
    扇出电路形成工序，提供一第一基板，所述第一基板包括衬底基板以及信号线，所述衬底基板具有第一表面和与所述第一表面相对的第二表面，所述信号线设置于所述衬底基板的第一表面，在所述第二表面形成扇出电路；
    开口形成工序，在衬底基板的边缘开设多个开口，所述开口贯穿所述中间基板，所述第一端连接所述扇出电路，所述第二端连接所述信号线；
    电连部接形成工序，在所述开口中形成电连接部，所述电连接部电连接于所述信号线和所述扇出电路之间，得到阵列基板；
    绑定工序，在所述扇出电路上绑定驱动芯片，
    发光部形成工序，在所述阵列基板上电连接发光部。
  10. 如权利要求9的显示面板的制造方法，其中所述在衬底基板的边缘开设多个开口的步骤包括在所述衬底基板的侧壁上形成凹槽或者在所述衬底基板中开设通孔。
  11. 如权利要求9的显示面板的制造方法，其中，
    所述电连接部形成工序包括以下步骤：
    蚀刻所述开口内的侧壁，暴露出所述信号线，
    在所述开口中形成金属层，形成所述电连接部。
  12. 一种拼接显示面板，其特征在于，由多个显示面板拼接而成，
    所述显示面板包括发光部、阵列基板以及驱动芯片，所述发光部电连接于所述阵列基板一侧，所述驱动芯片电连接于所述阵列基板另一侧，
    所述阵列基板包括：
    透明基板，具有第一表面和与所述第一表面相对的第二表面；
    信号线，设置于所述衬底基板的第一表面；
    扇出电路，设置于所述衬底基板的第二表面，所述扇出电路与所述信号线电连接；
    所述驱动芯片设置于所述衬底基板的第二表面侧，电连接于所述扇出电路，
    所述阵列基板上开设有多个开口，所述多个开口位于所述阵列基板边缘并贯穿所述阵列基板，所述阵列基板包括多个电连接部，所述电连接部设置于所述开口中，所述电连接部电连接所述信号线与所述扇出电路。
  13. 如权利要求12所述的拼接显示面板，其中所述开口为开设于所述阵列基板的侧壁上的凹槽。
  14. 如权利要求12所述的拼接显示面板，其中所述开口为贯穿所述阵列基板的通孔。
  15. 如权利要求12所述的拼接显示面板，其中所述开口内的所述阵列基板侧壁上开设有凹部，所述电连接部包括电连接凸起，所述信号线从所述凹部中暴露出来，所述电连接凸起与所述信号线接触。
  16. 如权利要求12所述的拼接显示面板，其中所述多个开口包括多个沿第一方向排列的第一开口，所述多个电连接部包括设置于所述多个第一开口中的多个第一电连接部，所述信号线包括栅极线，每一所述第一电连接部均电连接于一条所述栅极线。
  17. 如权利要求12所述的拼接显示面板，其中所述多个开口包括多个沿第二方向排列的第二开口，所述多个电连接部包括设置于所述多个第二开口中的多个第二电连接部，所述信号线包括源/漏极线，每一所述第二电连接部均电连接于一条所述源/漏极线。
  18. 如权利要求12所述的拼接显示面板，其中所述多个开口包括多个沿第一方向排列的第一开口，所述多个电连接部包括设置于所述多个第一开口中的多个第一电连接部，所述信号线包括栅极线，每一所述第一电连接部均电连接于一条所述栅极线，所述多个开口包括多个沿第二方向排列的第二开口，所述多个电连接部包括设置于所述多个第二开口中的多个第二电连接部，所述信号线包括源/漏极线，每一所述第二电连接部均电连接于一条所述源/漏极线。
  19. 如权利要求12所述的拼接显示面板，其中所述发光部为微型发光二极管或者有机电致发光体。
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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021226868A1 (zh) * 2020-05-13 2021-11-18 京东方科技集团股份有限公司 驱动基板及其制作方法、显示装置
TWI742681B (zh) * 2020-05-21 2021-10-11 友達光電股份有限公司 顯示裝置
US20210391404A1 (en) * 2020-06-11 2021-12-16 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Display panel, manufacturing method thereof, and display device
KR20220016347A (ko) 2020-07-30 2022-02-09 삼성디스플레이 주식회사 표시 장치 및 그의 제조 방법
CN111952331A (zh) 2020-09-01 2020-11-17 深圳市华星光电半导体显示技术有限公司 微发光二极管显示基板及其制作方法
US20220123188A1 (en) * 2020-10-15 2022-04-21 Innolux Corporation Method of manufacturing electronic device
CN112310119A (zh) * 2020-10-16 2021-02-02 深圳市华星光电半导体显示技术有限公司 显示面板及制备方法
CN112993117A (zh) * 2021-02-09 2021-06-18 深圳市华星光电半导体显示技术有限公司 微发光二极管显示面板及其制备方法、显示装置
CN113643621A (zh) * 2021-07-22 2021-11-12 惠州华星光电显示有限公司 发光二极管面板及拼接面板
WO2023008243A1 (ja) * 2021-07-30 2023-02-02 京セラ株式会社 画素構造体および表示装置
WO2023133718A1 (zh) * 2022-01-12 2023-07-20 厦门市芯颖显示科技有限公司 显示面板以及拼接显示屏
WO2024021117A1 (zh) * 2022-07-29 2024-02-01 京东方科技集团股份有限公司 一种阵列基板、显示面板、显示装置和拼接显示装置

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7791700B2 (en) * 2005-09-16 2010-09-07 Kent Displays Incorporated Liquid crystal display on a printed circuit board
CN104035253A (zh) * 2014-05-26 2014-09-10 京东方科技集团股份有限公司 阵列基板及其制备方法、显示面板
CN104134679A (zh) * 2013-04-30 2014-11-05 乐金显示有限公司 有机发光二极管显示装置及其制造方法
US20150187807A1 (en) * 2013-12-26 2015-07-02 Japan Display Inc. Display device
CN104916252A (zh) * 2015-07-13 2015-09-16 京东方科技集团股份有限公司 圆形显示面板及其制作方法、显示装置
CN107833978A (zh) * 2017-10-31 2018-03-23 昆山国显光电有限公司 一种显示器件
CN109768027A (zh) * 2019-01-29 2019-05-17 福州大学 一种Micro-LED显示屏的结构和制造方法
CN110310575A (zh) * 2019-06-28 2019-10-08 云谷（固安）科技有限公司 一种显示面板及其制作方法和显示装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102751308B (zh) * 2012-07-02 2015-07-08 广东威创视讯科技股份有限公司 Oled显示面板及带该显示面板的oled拼接显示屏
CN104678625A (zh) * 2013-11-28 2015-06-03 启耀光电股份有限公司 矩阵电路基板、显示装置及矩阵电路基板的制造方法
US10571758B2 (en) * 2018-01-05 2020-02-25 Innolux Corporation Display device
CN108957880B (zh) * 2018-08-01 2021-11-16 京东方科技集团股份有限公司 阵列基板、显示面板及其制作方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7791700B2 (en) * 2005-09-16 2010-09-07 Kent Displays Incorporated Liquid crystal display on a printed circuit board
CN104134679A (zh) * 2013-04-30 2014-11-05 乐金显示有限公司 有机发光二极管显示装置及其制造方法
US20150187807A1 (en) * 2013-12-26 2015-07-02 Japan Display Inc. Display device
CN104035253A (zh) * 2014-05-26 2014-09-10 京东方科技集团股份有限公司 阵列基板及其制备方法、显示面板
CN104916252A (zh) * 2015-07-13 2015-09-16 京东方科技集团股份有限公司 圆形显示面板及其制作方法、显示装置
CN107833978A (zh) * 2017-10-31 2018-03-23 昆山国显光电有限公司 一种显示器件
CN109768027A (zh) * 2019-01-29 2019-05-17 福州大学 一种Micro-LED显示屏的结构和制造方法
CN110310575A (zh) * 2019-06-28 2019-10-08 云谷（固安）科技有限公司 一种显示面板及其制作方法和显示装置

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