CN112599536A - 显示面板及其制作方法、拼接显示面板 - Google Patents
显示面板及其制作方法、拼接显示面板 Download PDFInfo
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- 238000000151 deposition Methods 0.000 description 9
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- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 8
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- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
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- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
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- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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Abstract
本发明提供一种显示面板及其制作方法、拼接显示面板。显示面板包括阵列基板、发光部以及驱动芯片,发光部电连接于阵列基板的一侧,驱动芯片电连接于阵列基板的另一侧。阵列基板包括衬底基板、显示电路及扇出电路,显示电路设置于衬底基板的第一侧上,显示电路包括TFT层、存储电容器以及信号走线,扇出电路设置于衬底基板的第二侧上,扇出走线的一端电连接于驱动芯片,扇出走线的另一端电连接于信号走线,TFT层的遮光层与源极层同层设置,半导体层与遮光层及源极层连接,像素电极层与半导体层连接。本发明能够简化显示面板的电路结构,减小显示面板所需的黄光制程的道数,从而有利于制作成本降低及良率提升。
Description
技术领域
本发明涉及显示技术领域,尤其涉及一种显示面板及其制作方法、拼接显示面板。
背景技术
在显示领域中,无边框或者窄边框显示器逐渐成为主流。对于显示器,例如液晶显示器(liquid crystals display,LCD)、有机电致发光显示器(display organic light-emitting diode,OLED)、发光二极管(light emitting diode,LED)显示器而言,屏幕尺寸越大,制造难度以及单位面积的制造成本越高。因此,大型显示器通常采用多块中小型显示器拼接而成。中小型显示器的边框的存在会导致拼接显示面板的显示区域出现条形的拼接缝,降低显示品质。
将扇出电路设置于显示面板的背部以形成双面电路结构的方式是避免拼接缝的一种思路,然而此种显示面板的电路结构复杂,制作步骤较为繁琐。
综上所述,需要提供一种新的显示面板及其制作方法、拼接显示面板,来解决上述技术问题。
发明内容
本发明提供的显示面板及其制作方法、拼接显示面板,解决了现有的显示面板将扇出线路设置于显示面板的背部,形成的双面电路结构复杂且制作步骤繁琐的技术问题。
为解决上述问题,本发明提供的技术方案如下:
本发明实施例提供一种显示面板,包括阵列基板、发光部以及驱动芯片,所述发光部电连接于所述阵列基板的一侧,所述驱动芯片电连接于所述阵列基板的另一侧;
所述阵列基板包括:
衬底基板,具有第一侧和与所述第一侧相对的第二侧;
显示电路,设置于所述衬底基板的所述第一侧上,所述显示电路包括TFT层、存储电容器以及信号走线,所述TFT层包括遮光层、源极层、半导体层、栅极绝缘层以及栅极层;以及
扇出电路,设置于所述衬底基板的所述第二侧上,所述扇出走线的一端电连接于所述驱动芯片,所述扇出走线的另一端电连接于所述信号走线;
其中,所述遮光层与所述源极层同层设置,所述半导体层与所述遮光层及所述源极层连接,所述像素电极层与所述半导体层连接。
根据本发明实施例提供的显示面板,所述阵列基板包括层叠设置的第一金属层和第二金属层,所述第一金属层包括所述遮光层和所述源极层,所述第二金属层包括所述栅极层,所述栅极绝缘层位于所述第一金属层和所述第二金属层之间,所述半导体层位于所述第一金属层和所述栅极绝缘层之间。
根据本发明实施例提供的显示面板,所述第一金属层和所述栅极绝缘层之间设置有层间介质层,所述层间介质层包括第一过孔和第二过孔,所述半导体层位于所述第一过孔和所述第二过孔内,所述半导体层与所述遮光层通过所述第一过孔连接,所述半导体层与所述栅极层通过所述第二过孔连接。
根据本发明实施例提供的显示面板,所述存储电容器包括绝缘设置的第一金属电极、第二金属电极以及像素电极,所述第一金属层包括所述第一金属电极,所述第二金属层包括所述第二金属电极,所述像素电极与所述半导体层连接;
其中,所述层间介质层对应所述存储电容器的位置处设置有开口,所述开口在所述衬底基板的正投影覆盖所述第一金属电极和所述第二金属电极在所述衬底基板的正投影。
根据本发明实施例提供的显示面板,所述显示电路还包括设置于所述TFT层、所述存储电容器以及所述信号走线上的第一钝化层,所述像素电极层位于所述第一钝化层上,所述第一钝化层包括第三过孔,所述像素电极层与所述半导体层通过所述第三过孔连接。
根据本发明实施例提供的显示面板,所述第一钝化层与所述TFT层对应的位置处依次层叠设置有第二钝化层和黑矩阵层,所述第二钝化层和所述黑矩阵层对准设置,所述第二钝化层的厚度小于所述第一钝化层的厚度。
本发明实施例提供一种显示面板的制作方法,包括以下步骤:
S10:扇出电路形成工序,提供衬底基板,所述衬底基板具有第一侧和与所述第一侧相对的第二侧,在所述衬底基板的所述第二侧上形成所述扇出电路;
S20:显示电路形成工序,在所述衬底基板的所述第一侧上形成TFT层、存储电容器以及信号走线,所述TFT层包括遮光层、源极层、半导体层、栅极绝缘层以及栅极层,所述遮光层和所述源极层同层设置,所述半导体层与所述遮光层及所述源极层连接;
S30:扇出电路连接工序,所述扇出走线的一端电连接于所述驱动芯片,所述扇出走线的另一端电连接于所述信号走线;以及
S40:发光部和驱动芯片绑定工序,在阵列基板的一侧上绑定发光部,所述发光部电连接至所述阵列基板,在所述阵列基板的另一侧上绑定驱动芯片,所述扇出电路的另一端与所述驱动芯片电连接。
根据本发明实施例提供的显示面板的制作方法,所述显示电路形成工序包括在所述第一金属层和所述栅极绝缘层之间形成层间介质层的步骤。
根据本发明实施例提供的显示面板的制作方法,所述显示电路形成工序包括在所述层间介质层对应所述存储电容器的位置处形成开口的步骤。
本发明实施例提供一种拼接显示面板,包括多个上述显示面板,多个所述显示面板拼接形成所述拼接显示面板。
本发明的有益效果为:本发明实施例提供的显示面板及其制作方法、拼接显示面板,显示面板的显示电路设置在阵列基板的正面,扇出电路及驱动芯片设置在阵列基板的背面,可以获得无边框或窄边框效果,本申请通过将位于显示面板正面的TFT层的遮光层和源极层同层设置,能够简化显示面板的电路结构,减小显示面板所需的黄光制程的道数,从而有利于制作成本降低及良率提升。
附图说明
为了更清楚地说明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单介绍,显而易见地,下面描述中的附图仅仅是发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的一种显示面板的截面结构示意图;
图2A~图2C为本发明实施例提供的一种显示面板的扇出电路形成工序的流程结构示意图;
图3A~图3F为本发明实施例提供的一种显示面板的显示电路形成工序的流程结构示意图;
图4A~图4C为本发明实施例提供的一种显示面板的扇出电路连接工序的流程结构示意图;
图5A~图5B为本发明实施例提供的一种显示面板的发光部和驱动芯片绑定工序的流程结构示意图;
图6为本发明实施例提供的一种拼接显示面板的平面结构示意图。
具体实施方式
以下各实施例的说明是参考附加的图示,用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语,例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等,仅是参考附加图式的方向。因此,使用的方向用语是用以说明及理解本发明,而非用以限制本发明。在图中,结构相似的单元是用以相同标号表示。
现有技术的显示面板及其制作方法、拼接显示面板中,将扇出线路设置于显示面板的背部上,其双面电路结构复杂且制作步骤繁琐。本实施例能够解决该缺陷。
如图1所示,本发明实施例提供的显示面板100,包括阵列基板10、多个发光部20以及驱动芯片30,多个发光部20呈矩阵状电连接于阵列基板10一侧上,驱动芯片30电连接于阵列基板10另一侧上。具体地,发光部20电连接于阵列基板10的显示侧,驱动芯片30电连接于阵列基板10的非显示侧,显示侧和非显示侧相对设置。
阵列基板10包括衬底基板11、显示电路12以及扇出电路13,衬底基板11具有第一侧11a和与第一侧11a相对的第二侧11b,第一侧11a为衬底基板11靠近显示侧的一侧,第二侧11b为衬底基板11靠近非显示侧的一侧。显示电路12设置于衬底基板11的第一侧11a上,扇出电路13设置于衬底基板11的第二侧11b上。显示电路12包括薄膜晶体管(thin filmtransistor,TFT层)12a、存储电容器12b以及信号走线12c。TFT层12a包括遮光层121、源极层121S、半导体层122以及栅极层121G。扇出电路13的一端电连接于驱动芯片30,扇出电路13的另一端电连接于信号走线12c。扇出电路13和信号走线12c之间可以通过设置于阵列基板10侧部边缘的连接走线14实现电连接。信号走线12c可以包括扫描线、数据线、公共电极线以及电源电压线等用于传递信号的走线,本发明实施例中,扇出电路12c与扫描线和数据线电连接,用于将驱动芯片30的信号传递至显示电路12,从而实现画面显示。
本申请中的遮光层121与源极层121S同层设置,半导体层122与遮光层121及源极层121S连接。需要说明的是,遮光层121和源极层121S共用一层金属,两者通过一道黄光制程制备,遮光层121采用不透明金属材料,本发明实施例中,遮光层121同时起到漏极和用于对沟道遮光的作用。
具体地,衬底基板11可以为塑料基板或者玻璃基板。在本发明实施例中,衬底基板11可以是柔性基板,例如聚酰亚胺基板。
遮光层121和源极层121S设置于衬底基板11的第一侧11a上且位于衬底基板11表面上,遮光层121和源极层121S可以是具有遮光效果的金属膜层,例如钼(Mo)、银(Ag)、铝(Al)、钼铜(MoCu)合金、钼(Mo)和铝(Al)的叠层、铜和氧化铟锡(ITO)的叠层、镍(Ni)和铜的叠层、铜(Cu)和钼钛(MoTi)合金的叠层、铜(Cu)和钛(Ti)的叠层、铝(Al)和钼(Mo)的叠层以及铜铌(CuNb)合金等。
半导体层122位于遮光层121和源极层121S上,半导体层122可以采用氧化物半导体或其他类型半导体,例如铟镓锌氧化物(IGZO)、铟镓锡氧化物(IGTO)、镓铟氧化物(IGO)、铟锌氧化物(IZO)以及铝铟锌氧化物(AIZO)等。
栅极绝缘层123位于半导体层122上,栅极绝缘层123可以采用SiNx、SiOx、AlOx、SiNx和SiOx的叠层或者SiOx和SiOx的叠层等。
栅极层121G位于栅极绝缘层123上,栅极121G可以采用为钼(Mo)、铜铌(CuNb)合金等,也可以为例如铜(Cu)和钼(Mo)的叠层、铜(Cu)和钼(Mo)的叠层、铜(Cu)和镍(Ni)的叠层、钼(Mo)-铜(Cu)-氧化铟锌(IZO)的叠层、铜(Cu)和氧化铟锌(IZO)的叠层、钼(Mo)-铜(Cu)-氧化铟锡(ITO)的叠层、铜(Cu)和钼钛镍(MoTiNi)合金的叠层、铜(Cu)和镍镉(NiCr)合金的叠层等。
阵列基板10包括层叠设置且相互绝缘的第一金属层101和第二金属层102,第一金属层101包括遮光层121和源极层121S,第二金属层102包括栅极层121G,栅极绝缘层123位于第一金属层101和第二金属层102之间,半导体层122位于第一金属层101和栅极绝缘层123之间。本发明实施例中的TFT层12a采用顶栅结构,第一金属层101的材料和遮光层121及源极层121S的材料相同,第二金属层102和栅极层121G的材料相同,在此不再赘述。
进一步地,第一金属层101和栅极绝缘层123之间设置有层间介质层124,层间介质层124包括第一过孔1241和第二过孔1242,半导体层122位于第一过孔1241和第二过孔1242内,半导体层122与遮光层121通过第一过孔1241连接,半导体层122与栅极层121通过第二过孔1242连接。由于第一金属层101和第二金属层102之间间隔有栅极绝缘层123和层间介质层124,膜层厚度较大,相比传统结构多了一层层间介质层124,有利于降低寄生电容,从而减少信号电路延迟。
此外,分别位于第一金属层101和第二金属层102的信号走线12c之间间隔设置有层间介质层124和栅极绝缘层123,可以降低两者发生短路的概率,提升了良率。
存储电容器12b包括绝缘设置的第一金属电极125a、第二金属电极125b以及像素电极层126,第一金属层101包括第一金属电极125a,第二金属层包括第二金属电极125b。像素电极126与半导体层122连接。第一金属电极125a和第二金属电极125b之间设置有栅极绝缘层123,则第一金属电极125a和第二金属电极125b之间形成一个子存储电容器。像素电极层126通过半导体层122连接于漏极121D或源极121S的其中一个。显示电路12还包括设置于TFT层12a、存储电容器12b以及信号走线12c上的第一钝化层127,像素电极层126位于第一钝化层127上,则像素电极层126和第二金属电极125b之间形成一个子存储电容器,第一钝化层127包括第三过孔1271,像素电极层126与半导体层122通过所述第三过孔1271连接,从而像素电极层126电连接至遮光层121。
可以理解地,存储电容器12b为像素电极层126、第一钝化层127、第二金属电极125b、栅极绝缘层123以及第一金属电极125a构成的叠层结构,上述两个子存储电容器呈并联结构,即本申请中的存储电容器12b通过三层金属层叠设置形成了两个并联的电容结构,其电容总量为两个子存储电容器的电容之和,这样的设置方式增大了存储电容器12b内的电容大小。由此,在单个像素单元所需的存储电容器总量不变的情况下,可以借此结构缩小存储电容器12b的面积,进而缩减单个像素单元在阵列基板10内的面积占比。相应的,在获得更小的所述像素单元面积占比情况下,阵列基板10可容纳的像素单元的个数得以增加,从而可以提高阵列基板10的像素密度(PPI)。
进一步地,层间介质层124对应存储电容器12b的位置处设置有开口1243,开口1243在衬底基板11的正投影覆盖第一金属电极12a和第二金属电极12b在衬底基板11的正投影。即第一金属电极12a和第二金属电极12b之间除去了层间介质层124,而层间介质层124的厚度相比栅极绝缘层123和第一钝化层127的厚度较厚,为400nm以上。栅极绝缘层123的厚度为50nm~300nm,优选地,栅极绝缘层123的厚度为140nm。第一钝化层127的厚度为200nm~400nm。故第一金属电极12a和第二金属电极12b之间形成的子存储电容器的电容、像素电极层126和第一金属电极12a之间形成的子存储电容器的电容相比传统结构可进一步增大。
第一钝化层127与TFT层12a对应的位置处依次层叠设置有第二钝化层128和黑矩阵层129,第二钝化层128和黑矩阵层129对准设置。第二钝化层128和黑矩阵层129形成的叠层可以作为起到对TFT层12a顶部进行遮光和阻隔外界水氧侵蚀的作用。第二钝化层128的厚度小于第一钝化层127的厚度,优选地,第一钝化层127的厚度为200nm~400nm,第二钝化层128的厚度为30nm~400nm。第一钝化层127和第二钝化层128的材料可以采用SiOx、SiNx以及SiNOx等。
具体地,扇出电路13包括层叠的金属电路层131、透明电路层133以及位于金属电路层131和透明电路层133之间的电路绝缘膜132。金属电路层131的材料可以为Mo(钼)和Cu(铜)的叠层,钼钛合金(MoTi)和Cu(铜)的叠层。透明电路层133的材料为ITO或IZO。
具体地,显示面板100为微型发光二极管(micro light emitting diode,MicroLED)型显示面板100。发光部20为微型发光二极管发光体,其包括第一电极21和第二电极22。第一电极21和第二电极22分别连接于像素电极层126和公共电极层。根据微发光二极管按照结构不同,可分为垂直结构的微发光二极管和水平结构的微发光二极管,垂直结构的微发光二极管的第一电极21和第二电极22分别位于微发光二极管的上下两侧,水平的结构的微发光二极管的第一电极21和第二电极22均位于微发光二极管的下侧。在本实施方式中,微发光二极管为水平结构。
具体地,驱动芯片30可采用覆晶薄膜的形式,即将驱动芯片30设置于薄膜上并连接于扇出电路13。
如图2A~图2C、图3A~图3F、图4A~图4C以及图5A~图5B所示,本发明实施例提供的显示面板100的制作方法,包括以下步骤:
S10:扇出电路13形成工序,提供一衬底基板11,所述衬底基板11具有第一侧11a和与所述第一侧11a相对的第二侧11b,在所述衬底基板11的所述第二侧11b上形成所述扇出电路13。
S20:显示电路12形成工序,在所述衬底基板11的所述第一侧11a上形成TFT层12a、存储电容器12b以及信号走线12c,所述TFT层12a包括遮光层121、源极层121S、半导体层122以及栅极层121G,所述遮光层121和所述源极层121S同层设置,所述半导体层122与所述遮光层121及所述源极层121S连接。
S30:扇出电路连接工序,所述扇出电路13的一端电连接于所述驱动芯片30,另一端电连接于所述信号走线12c。
S40:发光部20和驱动芯片30绑定工序,在阵列基板10的一侧上绑定发光部20,所述发光部20电连接至所述阵列基板10,在所述阵列基板10的另一侧上绑定驱动芯片30,所述扇出电路13的另一端与所述驱动芯片30电连接。
具体地,如图2A~图2C所示,扇出电路13形成工序包括以下步骤:
S101:提供一衬底基板11,在衬底基板11的第二侧11b上沉积并图案化形成金属电路层131;
S102:在金属电路层131上沉积并图案化形成电路绝缘膜132;
S103:在电路绝缘膜上沉积形成硬质保护层15;以及
S104:对衬底基板11进行倒置。
电路绝缘膜132可采用氮化硅、氧化硅等;硬质保护层15覆盖金属电路层131,用于对金属电路层131进行保护,硬质保护层15的材料可以为氮化硅、氧化硅等。在金属电路层131上沉积形成硬质保护层15之后,对衬底基板11进行倒置,衬底基板11的第一侧朝上,以方便后续显示电路12的制备。
具体地,如图3A~图3F所示,显示电路12形成工序包括在所述第一金属层101和所述栅极绝缘层123之间形成层间介质层124的步骤,显示电路12形成工序具体包括以下步骤:
S201:在衬底基板11的第一侧11a沉积并图案化形成第一金属层101,第一金属层101包括遮光层121、源极层121S、第一金属电极125a以及信号走线12c;
S202:在第一金属层101上沉积形成层间介质层124,并图案化形成对应所述遮光层121的第一过孔1241、对应所述源极层121S的第二过孔1242以及对应存储电容器12b的开口1243;
S203:在层间介质层124上沉积并图案化形成半导体层122;
S204:在层间介质层124和半导体层122上沉积并图案化形成栅极绝缘层123;
S205:在栅极绝缘层123上沉积并图案化形成第二金属层125a;
S206:在第二金属层125a上形成第一钝化层127,并形成贯穿所述第一钝化层127的第三过孔1271;
S207:在第一钝化层127上依次沉积并图案化形成像素电极层126、公共电极层以及第二钝化层128;以及
S208:在第二钝化层128上沉积并图案化形成黑矩阵层129。
步骤S208中,可以利用黑矩阵层129作为Hard Mask(硬掩膜)对第二钝化层128进行自对准图案化处理,使得第二钝化层128和黑矩阵层129对准设置。
具体地,如图4A~4C所示,扇出电路13连接工序包括以下步骤:
S301:在显示电路12上涂布形成第一软质保护层161;
S302:除去硬质保护层15,并在扇出电路13上涂布形成第二软质保护层162:
S303:在阵列基板10的侧部形成连接走线14,扇出电路13的一端电连接于驱动芯片30,扇出电路13的另一端电连接于信号走线12c;以及
S304:除去第一软质保护层161和第二软质保护层162。
具体地,如图5A~图5B所示,发光部20和驱动芯片30绑定工序包括以下步骤:
S401:在金属电路层131上形成透明电路层133,将驱动芯片30通过透明电路层133绑定于金属电路层131上;以及
S402:在像素电极层126上电连接发光部20的第一电极21,在公共电极层上电连接发光部20的第二电极22。
由此,得到本发明实施例中的显示面板100,本发明实施例中的显示面板100的制作方法通过将位于显示面板100的TFT层12a的遮光层121和源极层121S同层设置,能够简化显示面板100的电路结构,本发明实施例仅需7道黄光制程,与传统的显示面板的制作方法相比,减少了所需的黄光制程的道数,有利于提高生产效率、降低生产成本。
如图6所示,本发明实施例还提供一种拼接显示面板100,拼接显示面板100包括呈矩阵紧密排列的多块显示面板100。拼接显示面板100通过使用上述实施例中的无边框或者窄边框的显示面板100,能够将拼接缝缩小至一个像素单元大小,从而使用户在视觉上难以察觉拼接缝的存在,起到消除或者减小拼接缝的效果。此外,能够简化拼接显示面板100的结构,节省制程,提升良率。
有益效果为:本发明实施例提供的显示面板及其制作方法、拼接显示面板,显示面板的显示电路设置在阵列基板的正面,扇出电路及驱动芯片设置在阵列基板的背面,可以获得无边框或窄边框效果,本申请通过将位于显示面板正面的TFT层的遮光层和源极层同层设置,能够简化显示面板的电路结构,减小显示面板所需的黄光制程的道数,从而有利于制作成本降低及良率提升。
综上所述,虽然本发明已以优选实施例揭露如上,但上述优选实施例并非用以限制本发明,本领域的普通技术人员,在不脱离本发明的精神和范围内,均可作各种更动与润饰,因此本发明的保护范围以权利要求界定的范围为准。
Claims (10)
1.一种显示面板,其特征在于,包括阵列基板、发光部以及驱动芯片,所述发光部电连接于所述阵列基板的一侧,所述驱动芯片电连接于所述阵列基板的另一侧;
所述阵列基板包括:
衬底基板,具有第一侧和与所述第一侧相对的第二侧;
显示电路,设置于所述衬底基板的所述第一侧上,所述显示电路包括TFT层、存储电容器以及信号走线,所述TFT层包括遮光层、源极层、半导体层、栅极绝缘层以及栅极层;以及
扇出电路,设置于所述衬底基板的所述第二侧上,所述扇出走线的一端电连接于所述驱动芯片,所述扇出走线的另一端电连接于所述信号走线;
其中,所述遮光层与所述源极层同层设置,所述半导体层与所述遮光层及所述源极层连接,所述像素电极层与所述半导体层连接。
2.根据权利要求1所述的显示面板,其特征在于,所述阵列基板包括层叠设置的第一金属层和第二金属层,所述第一金属层包括所述遮光层和所述源极层,所述第二金属层包括所述栅极层,所述栅极绝缘层位于所述第一金属层和所述第二金属层之间,所述半导体层位于所述第一金属层和所述栅极绝缘层之间。
3.根据权利要求2所述的显示面板,其特征在于,所述第一金属层和所述栅极绝缘层之间设置有层间介质层,所述层间介质层包括第一过孔和第二过孔,所述半导体层位于所述第一过孔和所述第二过孔内,所述半导体层与所述遮光层通过所述第一过孔连接,所述半导体层与所述栅极层通过所述第二过孔连接。
4.根据权利要求3所述的显示面板,其特征在于,所述存储电容器包括绝缘设置的第一金属电极、第二金属电极以及像素电极,所述第一金属层包括所述第一金属电极,所述第二金属层包括所述第二金属电极,所述像素电极与所述半导体层连接;
其中,所述层间介质层对应所述存储电容器的位置处设置有开口,所述开口在所述衬底基板的正投影覆盖所述第一金属电极和所述第二金属电极在所述衬底基板的正投影。
5.根据权利要求1所述的显示面板,其特征在于,所述显示电路还包括设置于所述TFT层、所述存储电容器以及所述信号走线上的第一钝化层,所述像素电极层位于所述第一钝化层上,所述第一钝化层包括第三过孔,所述像素电极层与所述半导体层通过所述第三过孔连接。
6.根据权利要求5所述的显示面板,其特征在于,所述第一钝化层与所述TFT层对应的位置处依次层叠设置有第二钝化层和黑矩阵层,所述第二钝化层和所述黑矩阵层对准设置,所述第二钝化层的厚度小于所述第一钝化层的厚度。
7.一种显示面板的制作方法,其特征在于,包括以下步骤:
S10:扇出电路形成工序,提供衬底基板,所述衬底基板具有第一侧和与所述第一侧相对的第二侧,在所述衬底基板的所述第二侧上形成所述扇出电路;
S20:显示电路形成工序,在所述衬底基板的所述第一侧上形成TFT层、存储电容器以及信号走线,所述TFT层包括遮光层、源极层、半导体层、栅极绝缘层以及栅极层,所述遮光层和所述源极层同层设置,所述半导体层与所述遮光层及所述源极层连接;
S30:扇出电路连接工序,所述扇出走线的一端电连接于所述驱动芯片,所述扇出走线的另一端电连接于所述信号走线;以及
S40:发光部和驱动芯片绑定工序,在阵列基板的一侧上绑定发光部,所述发光部电连接至所述阵列基板,在所述阵列基板的另一侧上绑定驱动芯片,所述扇出电路的另一端与所述驱动芯片电连接。
8.根据权利要求7所述的显示面板的制作方法,其特征在于,所述显示电路形成工序包括在所述第一金属层和所述栅极绝缘层之间形成层间介质层的步骤。
9.根据权利要求8所述的显示面板的制作方法,其特征在于,所述显示电路形成工序包括在所述层间介质层对应所述存储电容器的位置处形成开口的步骤。
10.一种拼接显示面板,其特征在于,包括多个根据权利要求1~6中任一项所述的显示面板,多个所述显示面板拼接形成所述拼接显示面板。
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