WO2022246602A1 - 显示基板的制备方法、显示基板及显示装置 - Google Patents

显示基板的制备方法、显示基板及显示装置 Download PDF

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Publication number
WO2022246602A1
WO2022246602A1 PCT/CN2021/095516 CN2021095516W WO2022246602A1 WO 2022246602 A1 WO2022246602 A1 WO 2022246602A1 CN 2021095516 W CN2021095516 W CN 2021095516W WO 2022246602 A1 WO2022246602 A1 WO 2022246602A1
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Prior art keywords
layer
base substrate
substrate
orthographic projection
metal
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PCT/CN2021/095516
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English (en)
French (fr)
Inventor
岳阳
舒适
姚琪
于勇
李士佩
李翔
徐传祥
刘文渠
顾仁权
黄海涛
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180001234.6A priority Critical patent/CN115699321A/zh
Priority to PCT/CN2021/095516 priority patent/WO2022246602A1/zh
Priority to US17/762,239 priority patent/US20240047363A1/en
Publication of WO2022246602A1 publication Critical patent/WO2022246602A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present disclosure relates to the field of display technology, in particular to a method for preparing a display substrate, a display substrate and a display device.
  • micro/mini light-emitting diode (Micro/Mini-LED) display technology has the advantages of high brightness, high luminous efficiency, and low power consumption.
  • the metal traces in the LED display substrate are made of high-reflectivity metal materials and run through the display area. When the ambient light is strong, these metal traces will have a strong reflective phenomenon, thereby affecting the contrast of the LED display substrate.
  • the present disclosure provides a display substrate, including a display area and a peripheral area located on the periphery of the display area, and the display substrate includes:
  • a light-shielding layer disposed on the side of the first passivation layer away from the base substrate, the orthographic projection of the light-shielding layer on the base substrate is the same as the normal projection of the binding terminal on the base substrate The projections do not overlap, and in the display area, the orthographic projection of the light-shielding layer on the base substrate covers the orthographic projection of the metal traces on the base substrate.
  • the orthographic projection of the light-shielding layer on the base substrate completely coincides with the orthographic projection of the metal wiring on the base substrate.
  • the wiring functional layer includes: a first metal layer, an insulating layer and a second metal layer stacked, and the first metal layer is arranged close to the base substrate;
  • the metal wiring includes a first metal wiring on the first metal layer and a second metal wiring on the second metal layer, the binding terminal is on the second metal layer and is connected to the The second metal wires are connected to each other, and the second metal wires are connected to the first metal wires through the via holes provided on the insulating layer.
  • the second metal layer is a copper layer
  • a transparent electrode layer is further arranged between the first passivation layer and the second metal layer, and the transparent electrode layer is
  • the orthographic projection on the base substrate covers the orthographic projection of the third bonding terminal on the base substrate.
  • the second metal layer includes a copper layer and a copper-nickel alloy layer disposed on the side of the copper layer away from the base substrate, and the thickness of the first passivation layer is greater than Or equal to 8000 Angstroms.
  • the orthographic projection of the copper-nickel alloy layer on the base substrate covers the orthographic projection of the copper layer on the base substrate.
  • a first flat layer is further provided on the side of the light-shielding layer away from the base substrate, and the orthographic projection of the first flat layer on the base substrate is the same as that of the base substrate.
  • the orthographic projections of the binding terminals on the base substrate do not overlap, and the orthographic projections of the first passivation layer on the base substrate and the orthographic projections of the binding terminals on the base substrate The projections have no overlap.
  • the material of the light shielding layer is an organic black material.
  • a second flat layer is further provided between the light shielding layer and the first passivation layer, and the orthographic projection of the second flat layer on the base substrate is the same as
  • the orthographic projection of the binding terminal on the base substrate does not overlap, and the orthographic projection of the first passivation layer on the base substrate and the binding terminal on the base substrate Orthographic projections have no overlap.
  • a second passivation layer is further provided between the light shielding layer and the second flat layer, and the orthographic projection of the second passivation layer on the base substrate There is no overlap with the orthographic projection of the bonding terminal on the base substrate.
  • the material of the light-shielding layer is carbon black.
  • the insulating layer includes a third passivation layer, a third planar layer, and a fourth passivation layer stacked on the side of the first metal layer away from the base substrate, The third passivation layer is disposed close to the first metal layer.
  • an electroplating functional layer is further arranged between the base substrate and the first metal layer, and the orthographic projection of the electroplating functional layer on the base substrate is the same as the Orthographic projections of the first metal layer on the base substrate are completely overlapped.
  • the display area includes a plurality of pixel units arranged in an array
  • the first metal wiring includes:
  • At least one first sub-wiring extending along the pixel column direction in the display area, the first sub-wiring having a first line width along the pixel row direction;
  • At least one second sub-wire extending along the pixel column direction in the display area, the second sub-wire has a second line width along the pixel row direction, and the second line width is smaller than the first line width.
  • the orthographic projection of the first binding terminal on the substrate is within a range of the orthographic projection of the first sub-trace on the substrate.
  • the present disclosure provides a display device, which includes any one of the display substrates.
  • the present disclosure provides a method for preparing a display substrate.
  • the display substrate includes a display area and a peripheral area located on the periphery of the display area.
  • the preparation method includes:
  • a wiring functional layer is formed on one side of the base substrate, the wiring functional layer includes a metal wiring and a binding terminal connected to the metal wiring, and the binding terminal includes a first binding terminal, The second binding terminal and the third binding terminal, the first binding terminal is used for binding the LED chip, the second binding terminal is used for binding the driving chip, and the driving chip is used for driving the LED The chip emits light, the third binding terminal is used for binding the flexible circuit board, the first binding terminal and the second binding terminal are located in the display area, and the third binding terminal is located in the peripheral area; and,
  • a first passivation layer and a light-shielding layer are sequentially formed on the side of the wiring functional layer away from the base substrate, and the orthographic projection of the light-shielding layer on the base substrate is identical to that of the bonding terminal on the The orthographic projections on the base substrate do not overlap, and in the display area, the orthographic projection of the light-shielding layer on the base substrate covers the orthographic projection of the metal traces on the base substrate.
  • the steps of sequentially forming a first passivation layer and a light-shielding layer on the side of the wiring functional layer away from the base substrate include:
  • a first planar layer is formed on the side of the light-shielding layer away from the base substrate, and the orthographic projection of the first planar layer on the base substrate is identical to that of the binding terminal on the base substrate. Orthographic projections on the substrate substrate described above have no overlap; and,
  • the orthographic projection of the first passivation layer on the base substrate and Orthographic projections of the binding terminals on the base substrate have no overlap.
  • the step of sequentially forming a first passivation layer and a light-shielding layer on the side of the wiring functional layer away from the base substrate includes:
  • a second planar layer is formed on the side of the passivation material film away from the base substrate, and the orthographic projection of the second planar layer on the base substrate is consistent with the binding terminal Orthographic projections on the substrate substrate have no overlap;
  • the orthographic projection of the first passivation layer on the base substrate is the same as Orthographic projections of the binding terminals on the base substrate have no overlap.
  • step of forming the light-shielding layer on the side of the second planar layer away from the base substrate further comprising:
  • a second passivation layer is formed on the side of the second planar layer away from the base substrate, and the orthographic projection of the second passivation layer on the base substrate is the same as the binding Orthographic projections of the fixed terminals on the base substrate do not overlap;
  • the step of forming the light-shielding layer on the side of the second flat layer away from the base substrate includes:
  • the light shielding layer is formed on a side of the second passivation layer away from the base substrate.
  • the step of forming a wiring functional layer on one side of the base substrate includes:
  • a first metal layer, a third passivation layer, a third flat layer, a fourth passivation layer, and a second metal layer are sequentially formed on one side of the base substrate, and the metal wiring includes The first metal wiring of the layer and the second metal wiring on the second metal layer, the binding terminal is located on the second metal layer and connected to the second metal wiring, the second The metal trace is connected to the first metal trace through a via hole provided on the insulating layer;
  • the step of forming the third flat layer includes:
  • a fifth planar layer is formed on a side of the fourth planar layer away from the base substrate, and the fourth planar layer and the fifth planar layer constitute the third planar layer.
  • FIG. 1 shows a schematic plan view of a display substrate provided by an embodiment of the present disclosure
  • FIG. 2 shows a schematic cross-sectional structure diagram of a first display substrate provided by an embodiment of the present disclosure
  • FIG. 3 shows a schematic plan view of a wiring functional layer provided by an embodiment of the present disclosure
  • FIG. 4 shows a schematic plan view of a light-shielding layer provided by an embodiment of the present disclosure
  • FIG. 5 shows a schematic diagram of a wiring functional layer connection structure provided by an embodiment of the present disclosure
  • FIG. 6 shows a schematic plan view of the first metal layer and the second metal layer provided by an embodiment of the present disclosure
  • FIG. 7 shows a schematic cross-sectional structure diagram of a second display substrate provided by an embodiment of the present disclosure
  • Fig. 8 shows the scanning electron micrographs of the first passivation layer of different thickness provided in the embodiment of the present disclosure in the second display substrate;
  • Figure 9 shows a parameter comparison of several light-shielding layer materials provided by embodiments of the present disclosure.
  • FIG. 10 shows a schematic cross-sectional structure diagram of a third display substrate provided by an embodiment of the present disclosure
  • Fig. 11 shows a picture provided by an embodiment of the present disclosure without residue of the light-shielding layer
  • Fig. 12 shows a picture provided by an embodiment of the present disclosure with residual light-shielding layer
  • FIG. 13 shows a schematic structural diagram of a display device provided by an embodiment of the present disclosure
  • FIG. 14 shows a flow chart of the steps of a method for preparing a display substrate provided by an embodiment of the present disclosure
  • Fig. 15 shows a flow chart of a preparation process of a first passivation layer in a display substrate provided by an embodiment of the present disclosure
  • FIG. 16 shows a flow chart of a preparation process of a third flat layer in a display substrate provided by an embodiment of the present disclosure
  • Fig. 17a shows a flow chart of a manufacturing process of a display substrate provided by an embodiment of the present disclosure
  • Fig. 17b shows a flow chart of a manufacturing process of a display substrate provided by an embodiment of the present disclosure
  • Fig. 17c shows a flow chart of a manufacturing process of a display substrate provided by an embodiment of the present disclosure.
  • An embodiment of the present disclosure provides a display substrate.
  • FIG. 1 a schematic plan view of a display substrate provided in this embodiment is shown.
  • the display substrate includes a display area AA and a peripheral area BB located around the display area AA.
  • the display substrate includes: a base substrate 21; a wiring functional layer 22 arranged on one side of the base substrate 21; a first passivation layer 23 arranged on the side of the wiring functional layer 22 away from the base substrate 21; and, The light shielding layer 24 on the side of the first passivation layer 23 away from the base substrate 21 .
  • the wiring function layer 22 includes a metal wiring 31 and a binding terminal connected to the metal wiring 31, and the binding terminal includes a first binding terminal 32, a second binding terminal 33 and a third binding terminal 34 (as shown in FIG. 1), the first binding terminal 32 is used for binding the LED chip, the second binding terminal 33 is used for binding the driver chip, the driver chip is used for driving the LED chip to emit light, and the third binding terminal 34 is used for binding On the flexible circuit board, the first binding terminal 32 and the second binding terminal 33 are located in the display area AA, and the third binding terminal 34 is located in the peripheral area BB.
  • FIG. 4 a schematic plan view of a light-shielding layer is shown. 3 and 4, the orthographic projection of the light-shielding layer 24 on the base substrate 21 does not overlap with the orthographic projection of the binding terminal on the base substrate 21. In the display area AA, the light-shielding layer 24 is on the base substrate The orthographic projection on 21 covers the orthographic projection of metal trace 31 on base substrate 21 .
  • the light-shielding layer 24 is provided with opening areas at positions corresponding to the first binding terminal 32 , the second binding terminal 33 and the third binding terminal 34 , so as to facilitate the subsequent binding process.
  • the display area AA may include a plurality of pixel units, and each pixel unit may be divided into a transparent area TR and a non-transparent area.
  • the first binding terminal 32 and the second binding terminal 33 may be located in the non-transparent area of each pixel unit, as shown in FIG. 3 and FIG. 5 .
  • FIG. 3 shows a schematic plan view of a wiring functional layer in a pixel unit
  • FIG. 5 shows a schematic diagram of a connection structure of wiring functional layers corresponding to multiple pixel units.
  • first binding terminals 32 there may be multiple first binding terminals 32, for example, it may include a positive terminal of a red LED chip, a negative terminal of a red LED chip, a positive terminal of a green LED chip, a negative terminal of a green LED chip, and a positive terminal of a blue LED chip. terminal and blue LED chip negative terminal.
  • the metal wiring 31 may include a scanning signal supply line VCC1, a data signal line Data, a reference signal line GND, a first voltage signal line VGB, a second voltage signal line VR, and a scanning signal line VCC2, etc. .
  • FIG. 5 only shows an optional way of disposing the above-mentioned metal wires 31 , and this embodiment does not limit the connection positions between different wires.
  • the peripheral area BB may include a pad area SA and a fan-out area between the pad area SA and the display area AA.
  • the third binding terminal 34 is located in the pad area SA.
  • the substrate substrate 21 may include substrates such as glass substrates or flexible substrates, and may also include alignment marks disposed on one side of the substrate, and may also include film layers such as buffer layers. Not limited.
  • the wiring function layer 22 can be a single-layer structure, and can also be a multi-layer structure, such as including multiple metal layers and an insulating layer arranged between two adjacent metal layers. In this embodiment, the wiring function layer 22 The specific layer structure is not limited. Subsequent embodiments will introduce a structure of the wiring function layer 22 in detail.
  • the material of the first passivation layer 23 may include inorganic materials such as silicon oxide and silicon nitride, which is not limited in this embodiment.
  • the material of the light-shielding layer 24 may be carbon black material or inorganic black material, which is not limited in this embodiment.
  • the LED chip is an active light-emitting device, and a driver chip is used to drive the LED chip to emit light, so that a larger-sized display substrate can be manufactured and a larger driving current can be realized.
  • the display substrate provided in this embodiment is provided with a light-shielding layer 24 on the side of the wiring functional layer 22 away from the base substrate 21, and the orthographic projection of the light-shielding layer 24 on the base substrate 21 covers the metal wiring 31 on the base substrate. 21, so as to prevent the metal traces 31 from reflecting light and improve the contrast of the display device.
  • the orthographic projection of the light-shielding layer 24 on the base substrate 21 is the same as that of the metal wiring 31 on the base substrate 21 Orthographic projections can be perfectly coincident. In this way, the light-shielding layer 24 can not only completely cover the metal wires 31 to prevent the metal wires 31 from reflecting ambient light, but also increase the area of the transparent region TR, thereby increasing the light transmittance of the display region AA.
  • the base substrate 21 can be a flexible substrate, and a bendable area is provided between the display area AA and the pad area SA, so that the peripheral area BB can be bent to the edge of the display area AA.
  • the peripheral area BB is located on the backside of the display substrates, the gap between adjacent display substrates can be reduced, thereby improving the overall display effect of the display panel.
  • the orthographic projection of the light-shielding layer 24 on the base substrate 21 may not overlap with the peripheral area BB. If the peripheral area BB is located on the front of the display area AA, or cannot be bent to the back of the display area AA, in the peripheral area BB, the orthographic projection of the light-shielding layer 24 on the base substrate 21 can cover the metal wiring 31 on the base substrate Orthographic projection on 21.
  • the wiring functional layer 22 may include: a first metal layer 221 , an insulating layer and a second metal layer 222 arranged in stacks, the first metal layer 221 is disposed close to the base substrate 21 .
  • the metal traces 31 may include a first metal trace located on the first metal layer 221 and a second metal trace located on the second metal layer 222, and the binding terminal is located on the second metal layer 222. And the second metal wiring is connected to each other, and the second metal wiring is connected to the first metal wiring through a via hole provided on the insulating layer.
  • the display area AA includes a plurality of pixel units arranged in an array.
  • the first metal wiring may include: at least one first The sub-wires (for example, the reference signal line GND), the first sub-wire has a first line width S1 along the pixel row direction.
  • the pixel column direction is the column direction of the pixel units arranged in an array
  • the pixel row direction is the row direction of the pixel units arranged in an array
  • the first metal wiring may further include: at least one second sub-wiring (such as a first voltage signal line VGB, a second voltage signal line VR, a data signal line) extending along the pixel column direction in the display area AA. Data, scanning signal supply line VCC1, etc.), the second sub-wire has a second line width S2 along the pixel row direction, and the second line width S2 is smaller than the first line width S1.
  • the second sub-wire may have different second line widths S2 along the pixel row direction (such as including at least one second sub-wire with a line width of S21 and at least one second sub-wire with a line width of S22. line,..., at least one second sub-wire with line width S2n), but these second line widths S2 are all smaller than the first line width S1.
  • first spacing S3 wherein the first spacing S3 is greater than three times the first line width S1, that is, S3>3S1.
  • the orthographic projection of the first binding terminal 32 on the base substrate 21 is within the range of the orthographic projection of the first sub-trace (for example, the reference signal line GND) on the base substrate 21 .
  • the first metal wiring on the first metal layer 221 may include: a scan signal supply line VCC1 , a data signal line Data, a reference signal line GND, a first voltage signal line VGB, and a second voltage signal line VR.
  • the second metal wiring on the second metal layer 222 may include a scanning signal line VCC2 , and may also include a lead wire connecting the bonding terminal and the above-mentioned signal line, and the like.
  • the first binding terminal 32 , the second binding terminal 33 and the third binding terminal 34 can also be located on the second metal layer 222 .
  • the material of the first metal layer 221 may include a metal film layer such as a copper layer, a molybdenum layer, or an aluminum layer, which is not limited in this embodiment.
  • the material of the second metal layer 222 may include a metal film layer such as a copper layer, a molybdenum layer, or an aluminum layer, which is not limited in this embodiment.
  • the insulating layer disposed between the first metal layer 221 and the second metal layer 222 may include a third layer stacked on the side of the first metal layer 221 facing away from the substrate 21 .
  • the passivation layer 223 , the third planarization layer 224 and the fourth passivation layer 225 , the third passivation layer 223 is disposed close to the first metal layer 221 .
  • the material of the third passivation layer 223 may include inorganic materials such as silicon oxide and silicon nitride, which is not limited in this embodiment.
  • the material of the fourth passivation layer 225 may include inorganic materials such as silicon oxide and silicon nitride, which is not limited in this embodiment.
  • the material of the third flat layer 224 can be, for example, organic materials such as polyacrylic resin, which is not limited in this embodiment.
  • the third passivation layer 223 By disposing the third passivation layer 223 between the third planarization layer 224 and the first metal layer 221 , the first metal layer 221 can be prevented from being oxidized by oxygen released by the third planarization layer 224 in subsequent processes.
  • the fourth passivation layer 225 By disposing the fourth passivation layer 225 between the third planarization layer 224 and the second metal layer 222 , the second metal layer 222 can be prevented from being oxidized by oxygen released by the third planarization layer 224 in subsequent processes.
  • the second metal layer 222 may be a copper layer.
  • a transparent electrode layer 25 may also be provided between the first passivation layer 23 and the second metal layer 222, and the positive electrode layer 25 on the base substrate 21 The projection covers the orthographic projection of the third bonding terminal 34 on the base substrate 21 .
  • the material of the transparent electrode layer 25 may be a conductive and anti-oxidation material such as indium tin oxide, which is not limited in this embodiment.
  • the second metal layer 222 may include a copper layer and a copper-nickel alloy layer disposed on a side of the copper layer away from the substrate 21 .
  • the copper-nickel alloy layer By providing the copper-nickel alloy layer on the surface of the copper layer, oxidation of the third bonding terminal 34 in the peripheral region BB can be prevented.
  • the orthographic projection of the copper-nickel alloy layer on the base substrate 21 may cover the orthographic projection of the copper layer on the base substrate 21 .
  • the copper-nickel alloy has high strength, corrosion resistance and hardness
  • oxidation of the copper layer and binding terminals can be prevented.
  • there is no need to arrange a transparent electrode layer on the surface of the third binding terminal 34 so one mask process can be reduced, thereby simplifying process steps, improving yield and reducing cost.
  • a layer of molybdenum layer or molybdenum-niobium alloy layer, etc. can also be set between the fourth passivation layer 225 in the insulating layer and the second metal layer 222, so that the connection between the second metal layer 222 and the insulating layer can be improved.
  • the bonding firmness between the fourth passivation layer 225 can also be set between the fourth passivation layer 225.
  • the thickness of the molybdenum-niobium alloy layer may be, for example, 300 angstroms
  • the thickness of the copper layer may be, for example, 6000 angstroms
  • the thickness of the copper-nickel alloy layer may be, for example, 500 angstroms.
  • the thickness of the first passivation layer 23 may be greater than or equal to 8000 angstroms, as shown in a in FIG. 8 .
  • a first flat layer 26 may also be provided on the side of the light-shielding layer 24 away from the base substrate 21, and the orthographic projection of the first flat layer 26 on the base substrate 21 and the binding terminal are on the substrate.
  • the orthographic projections on the substrate 21 do not overlap, and the orthographic projections of the first passivation layer 23 on the base substrate 21 and the orthographic projections of the binding terminals on the base substrate 21 do not overlap.
  • the material of the first flat layer 26 may be, for example, an organic material such as polyacrylic resin, which is not limited in this embodiment.
  • the positions corresponding to the first passivation layer 23 and the bonding terminals may not be etched in the display substrate manufacturing process, but may be etched before the bonding process.
  • the first passivation layer 23 is etched, so that the orthographic projection of the first passivation layer 23 on the base substrate 21 and the bonding terminal are on the base substrate 21 Orthographic projections on , without overlap; the binding process is performed afterwards.
  • the orthographic projection of the layer 101 on the base substrate 21 does not overlap with the orthographic projection of the binding terminal on the base substrate 21, and the orthographic projection of the first passivation layer 23 on the base substrate 21 and the binding terminal on the substrate The orthographic projections on the substrate 21 have no overlap.
  • the material of the second flat layer 101 may be, for example, an organic material such as polyacrylic resin, which is not limited in this embodiment.
  • the distance between the light shielding layer 24 and the second metal layer 222 can be increased, thereby reducing the distance between the light shielding layer 24 and the second metal layer 222.
  • the negative impact of the coupling capacitance is not limited to
  • the positions corresponding to the first passivation layer 23 and the bonding terminals may not be etched in the display substrate manufacturing process, but may be etched before the bonding process.
  • the first passivation layer 23 is etched, so that the orthographic projection of the first passivation layer 23 on the base substrate 21 and the orthographic projection of the bonding terminal on the base substrate 21 Projection without overlap; do binding process later.
  • the material of the light-shielding layer 24 has a small contact angle on the hydrophilic surface (-OH interface), which can form better graphics, as shown in Figure 11; There are residues, which are particles visible under the scanning electron microscope, as shown in Figure 12, and the residues have nothing to do with the exposure and development process.
  • the interface of the second flat layer 101 is made of polyacrylic resin, which is a hydrophobic material, and the material of the light-shielding layer 24 is likely to remain on the surface.
  • the remaining light-shielding layer 24 may have two consequences. One is that remaining in the transparent area will seriously affect the transmittance of the transparent area, and the other is that remaining in the binding area may cause poor binding.
  • the material of the second passivation layer 102 may include inorganic materials such as silicon oxide and silicon nitride, which is not limited in this embodiment.
  • the second passivation layer 102 By disposing the second passivation layer 102 between the light shielding layer 24 and the second planar layer 101 , it is possible to prevent the light shielding layer 24 from remaining on the second planar layer 101 .
  • the light shielding layer 24 can be an organic black material.
  • columns b and c in Figure 9 are the parameters of the two organic black materials. Since the dielectric constants of organic black materials are relatively low, being 3.7 and 3.5 respectively, using organic black materials to make the light-shielding layer 24 in FIGS. The coupling capacitance is used to avoid the influence of the light shielding layer 24 on the load of the second metal layer 222 . In practical applications, since the resolution capability ( ⁇ 5 ⁇ m) of the organic black materials in the c-column is better than that of the b-column materials (>9 ⁇ m) in the exposure process, the organic black material in the c-column can be selected to make the light-shielding layer 24, In this way, the control precision of the exposure process can be improved.
  • the material of the light-shielding layer 24 may be carbon black.
  • FIG. 9 is a parameter of a carbon black material.
  • the relative permittivity (3.7 and 3.5) of the dielectric constant (15) of the carbon black material is higher, but because the second flat layer 101 is arranged between the light-shielding layer 24 and the second metal layer 222 in Fig. 10, The distance between the light-shielding layer 24 and the second metal layer 222 is increased, so the material of the light-shielding layer 24 can be selected from a carbon black material with a slightly higher dielectric constant, and the coupling between the light-shielding layer 24 and the second metal layer 222 can also be avoided.
  • the influence of the capacitance avoids the influence of the light-shielding layer 24 on the load of the second metal layer 222 .
  • the light-shielding layer 24 in FIG. 10 can also be made of organic black material, which can further reduce the coupling capacitance.
  • the resolution capability ( ⁇ 0 ⁇ m) of the carbon black material in the a column is better than that of the organic black material in the exposure process, choosing the carbon black material in the a column to make the light-shielding layer 24 can improve the control precision of the exposure process.
  • the thickness of the light-shielding layer 24 may be determined according to the optical density value of a specific material and the design value of the transmittance of the light-shielding layer 24 , which is not limited in this embodiment.
  • the thickness of the light shielding layer 24 will be described below by taking the transmittance of the light shielding layer 24 less than or equal to 1% as an example.
  • the optical density (optical density, OD) value of a column material in Fig. 9 is 4.0/ ⁇ m, in order to make the transmittance of the shading layer 24 of a column material less than or equal to 1%, the thickness of the shading layer 24 can be greater than or equal to 0.5 ⁇ m.
  • optical density (optical density, OD) value of the b column material in Fig. 9 is 2.0/ ⁇ m, in order to make the transmittance of the shading layer 24 of the b column material less than or equal to 1%, the thickness of the shading layer 24 can be greater than or equal to 1.0 ⁇ m.
  • optical density (optical density, OD) value of c row material among Fig. 9 is 2.6/ ⁇ m, in order to make the transmittance of the light-shielding layer 24 of c-row material less than or equal to 1%, the thickness of light-shielding layer 24 can be greater than or equal to 0.77 ⁇ m.
  • an electroplating functional layer 27 may also be provided between the base substrate 21 and the first metal layer 221 , and the electroplating functional layer 27 is formed on the base substrate.
  • the orthographic projection on the first metal layer 221 on the base substrate 21 completely coincides with the orthographic projection of the first metal layer 221 on the base substrate 21 , and the electroplating functional layer 27 is used to improve the bonding firmness between the first metal layer 221 and the base substrate 21 .
  • the material of the electroplating functional layer 27 may be, for example, molybdenum or molybdenum-niobium alloy, which is not limited in this embodiment.
  • Another embodiment of the present disclosure further provides a display device, which may include the display substrate as described in any embodiment.
  • the display device in this embodiment can be any product or component with 2D or 3D display function, such as display panel, electronic paper, mobile phone, tablet computer, television, notebook computer, digital photo frame, and navigator.
  • a display device may include a plurality of display substrates as described in any embodiment. As shown in FIG. 13 , multiple display substrates can be fixed by cabinet locks and vertical beams. Vertical seamless splicing can be realized between multiple display substrates, that is, there is no horizontal splicing, and the visual effect is brighter and more transparent.
  • the display device can be applied to outdoor transparent display. Since the LED chips use inorganic materials, they are more reliable in outdoor or semi-outdoor scenes.
  • the pixels in the display substrate can be in a rectangular array, and the light-transmitting area is uniform, thereby improving the visual effect.
  • the display device provided in this embodiment can use 100-micron-level LED chips/wires to achieve a transmittance >70%, and a wide viewing angle >160°C; it adopts an active drive scheme, precise light control, good low-gray performance, and low power consumption ; High pixel density, small viewing distance, and more detailed picture performance; light and thin, easy to disassemble and assemble, and unlimited splicing; wireless signal transmission, good scalability, and easy maintenance.
  • the pixel unit pitch can be 3mm, the viewing distance is >8 meters, the transmittance reaches 85%, and the brightness reaches 2000nit (before correction).
  • the display substrate includes a display area and a peripheral area located on the periphery of the display area.
  • the preparation method includes:
  • Step 1401 providing a base substrate.
  • Step 1402 Form a wiring functional layer on one side of the base substrate, the wiring functional layer includes metal wiring and binding terminals connected to the metal wiring, and the binding terminals include first binding terminals and second binding terminals and the third binding terminal, the first binding terminal is used to bind the LED chip, the second binding terminal is used to bind the driver chip, the driver chip is used to drive the LED chip to emit light, and the third binding terminal is used to bind the flexible On the circuit board, the first binding terminal and the second binding terminal are located in the display area, and the third binding terminal is located in the peripheral area.
  • Step 1403 Form a first passivation layer and a light-shielding layer in sequence on the side of the wiring functional layer away from the base substrate, and the orthographic projection of the light-shielding layer on the base substrate has no intersection with the orthographic projection of the binding terminal on the base substrate In the display area, the orthographic projection of the light-shielding layer on the base substrate covers the orthographic projection of the metal traces on the base substrate.
  • the display substrate described in any of the above embodiments can be prepared.
  • step 1403 may specifically include:
  • a light-shielding layer is formed on the side of the passivation material film facing away from the substrate;
  • a first flat layer is formed on the side of the light-shielding layer away from the base substrate, and the orthographic projection of the first flat layer on the base substrate does not overlap with the orthographic projection of the binding terminal on the base substrate; as well as,
  • the passivation material film is etched to form a first passivation layer, the orthographic projection of the first passivation layer on the base substrate and the orthographic projection of the binding terminal on the base substrate The projections have no overlap.
  • the first passivation layer 23 may not be etched during the manufacturing process of the display backplane.
  • the first passivation layer 23 is etched using the patterned first flat layer 26 as a mask, and then the bonding process is performed.
  • step 1403 may specifically include:
  • a second flat layer is formed on the side of the passivation material film away from the base substrate, and the orthographic projection of the second flat layer on the base substrate has no intersection with the orthographic projection of the binding terminal on the base substrate. stack;
  • the second flat layer as a mask, etch the passivation material film to form the first passivation layer, the orthographic projection of the first passivation layer on the base substrate and the orthographic projection of the binding terminal on the base substrate
  • the projections have no overlap.
  • the first passivation layer may not be etched during the manufacturing process of the display backplane.
  • the patterned second flat layer is used as a mask to etch the first passivation layer, and then the bonding process is performed.
  • the following step may also be included: using a fifth patterning process to form a second planar layer on the side of the second planar layer away from the base substrate.
  • the second passivation layer, the orthographic projection of the second passivation layer on the base substrate does not overlap with the orthographic projection of the binding terminal on the base substrate.
  • the step of forming the light-shielding layer on the side of the second flat layer away from the base substrate may include: forming the light-shielding layer on the side of the second passivation layer away from the base substrate.
  • step 1402 may specifically include:
  • a first metal layer, a third passivation layer, a third flat layer, a fourth passivation layer and a second metal layer are sequentially formed on one side of the substrate, and the metal traces include the first metal traces located on the first metal layer. line and the second metal wiring on the second metal layer, the binding terminal is located on the second metal layer and connected to the second metal wiring, the second metal wiring and the first metal wiring are arranged on the insulating layer Via connection.
  • the step of forming the third flat layer may include:
  • a fourth planar layer is formed on the side of the third passivation layer away from the base substrate; and, using the seventh patterning process, a fifth planar layer is formed on the side of the fourth planar layer away from the base substrate , the fourth flat layer and the fifth flat layer constitute the third flat layer.
  • the third flat layer 224 is formed by two patterning processes, which can reduce process difficulty and improve process control precision.
  • the patterning process in this embodiment may include at least one of the following process steps: a film forming process, an exposure and development process, an etching process, and a photoresist removal process.
  • the film forming process may be one of magnetron sputtering process, thermal evaporation process, electron beam evaporation process or electroplating process.
  • the etching process can be a dry etching process or a wet etching process.
  • the specific patterning process steps can be designed according to the material and the structure of the film layer, which is not limited in this embodiment.
  • FIG. 17a to FIG. 17c a flow chart of the preparation process of the first display substrate is shown. Specifically, the following steps may be included:
  • Electroplated copper layer as shown in d in Figure 17a;
  • a light-shielding layer 24 is formed, as shown by m in FIG. 17c;
  • the second patterning process is used to form the second flat layer 26, and the second flat layer 26 is used as a mask to etch the passivation material film to form the first passivation layer 23, as shown by n in FIG. 17c ; Obtain the display substrate as shown in FIG. 2 .
  • This embodiment provides a method for preparing a display substrate, a display substrate, and a display device, wherein the display substrate includes a display area and a peripheral area located on the periphery of the display area, and the display substrate includes: a base substrate;
  • the wiring function layer, the wiring function layer includes metal wiring and binding terminals connected to the metal wiring, the binding terminals include the first binding terminal, the second binding terminal and the third binding terminal, the first binding terminal
  • the fixed terminal is used for binding the LED chip
  • the second binding terminal is used for binding the driving chip
  • the driving chip is used for driving the LED chip to emit light
  • the third binding terminal is used for binding the flexible circuit board
  • the first binding terminal is connected to the second binding terminal.
  • the second binding terminal is located in the display area, and the third binding terminal is located in the peripheral area; the first passivation layer is arranged on the side of the wiring functional layer away from the substrate; and the first passivation layer is arranged on a side away from the substrate.
  • the light-shielding layer on the side, the orthographic projection of the light-shielding layer on the base substrate does not overlap with the orthographic projection of the bonding terminal on the base substrate, and in the display area, the orthographic projection of the light-shielding layer on the base substrate covers the metal traces Orthographic projection on the substrate substrate.
  • a light-shielding layer is provided on the side of the wiring functional layer away from the base substrate, and the orthographic projection of the light-shielding layer on the base substrate covers the orthographic projection of the metal wiring on the base substrate, thereby avoiding metal traces.
  • the lines reflect light and improve the contrast of the display device.
  • any reference signs placed between parentheses shall not be construed as limiting the claim.
  • the word “comprising” does not exclude the presence of elements or steps not listed in a claim.
  • the word “a” or “an” preceding an element does not exclude the presence of a plurality of such elements.
  • the disclosure can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means can be embodied by one and the same item of hardware.
  • the use of the words first, second, and third, etc. does not indicate any order. These words can be interpreted as names.

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Abstract

显示基板的制备方法、显示基板及显示装置。显示基板包括显示区域(AA)以及位于显示区域(AA)外围的周边区域(BB)。显示基板包括：衬底基板(21)；设置在衬底基板(21)一侧的走线功能层(22)，走线功能层(22)包括金属走线(31)以及与金属走线(31)连接的绑定端子，绑定端子包括第一绑定端子(32)、第二绑定端子(33)和第三绑定端子(34)，第一绑定端子(32)与第二绑定端子(33)位于显示区域(AA)，第三绑定端子(34)位于周边区域(BB)；设置在走线功能层(22)背离衬底基板(21)一侧的第一钝化层(23)；以及，设置在第一钝化层(23)背离衬底基板(21)一侧的遮光层(24)，遮光层(24)在衬底基板(21)上的正投影与绑定端子在衬底基板(24)上的正投影无交叠，在显示区域内，遮光层(24)在衬底基板(21)上的正投影覆盖金属走线(31)在衬底基板(21)上的正投影。

Description

显示基板的制备方法、显示基板及显示装置 技术领域
本公开涉及显示技术领域，特别是涉及一种显示基板的制备方法、显示基板及显示装置。
背景技术
微型/迷你发光二极管(Micro/Mini-LED)显示技术作为新一代显示技术，具有亮度高、发光效率高、功耗低等优点。
目前，LED显示基板中的金属走线采用高反射率的金属材料制成且贯穿于显示区域。当环境光较强时，这些金属走线会出现强烈的反光现象，从而影响LED显示基板的对比度。
概述
本公开提供了一种显示基板，包括显示区域以及位于所述显示区域外围的周边区域，所述显示基板包括：
衬底基板；
设置在所述衬底基板一侧的走线功能层，所述走线功能层包括金属走线以及与所述金属走线连接的绑定端子，所述绑定端子包括第一绑定端子、第二绑定端子和第三绑定端子，所述第一绑定端子用于绑定LED芯片，所述第二绑定端子用于绑定驱动芯片，所述驱动芯片用于驱动所述LED芯片发光，所述第三绑定端子用于绑定柔性电路板，所述第一绑定端子与所述第二绑定端子位于所述显示区域，所述第三绑定端子位于所述周边区域；
设置在所述走线功能层背离所述衬底基板一侧的第一钝化层；以及，
设置在所述第一钝化层背离所述衬底基板一侧的遮光层，所述遮光层在所述衬底基板上的正投影与所述绑定端子在所述衬底基板上的正投影无交叠，在所述显示区域内，所述遮光层在所述衬底基板上的正投影覆盖所述金属走线在所述衬底基板上的正投影。
在一种可选的实现方式中，在所述显示区域内，所述遮光层在所述衬底 基板上的正投影与所述金属走线在所述衬底基板上的正投影完全重合。
在一种可选的实现方式中，所述走线功能层包括：层叠设置的第一金属层、绝缘层和第二金属层，所述第一金属层靠近所述衬底基板设置；
所述金属走线包括位于所述第一金属层的第一金属走线以及位于所述第二金属层的第二金属走线，所述绑定端子位于所述第二金属层且与所述第二金属走线相互连接，所述第二金属走线与所述第一金属走线通过设置在所述绝缘层上的过孔连接。
在一种可选的实现方式中，所述第二金属层为铜层，在所述第一钝化层与所述第二金属层之间还设置有透明电极层，所述透明电极层在所述衬底基板上的正投影覆盖所述第三绑定端子在所述衬底基板上的正投影。
在一种可选的实现方式中，所述第二金属层包括铜层以及设置在所述铜层背离所述衬底基板一侧的铜镍合金层，所述第一钝化层的厚度大于或等于8000埃。
在一种可选的实现方式中，所述铜镍合金层在所述衬底基板上的正投影覆盖所述铜层在所述衬底基板上的正投影。
在一种可选的实现方式中，在所述遮光层背离所述衬底基板的一侧还设置有第一平坦层，所述第一平坦层在所述衬底基板上的正投影与所述绑定端子在所述衬底基板上的正投影无交叠，所述第一钝化层在所述衬底基板上的正投影与所述绑定端子在所述衬底基板上的正投影无交叠。
在一种可选的实现方式中，所述遮光层的材料为有机黑材料。
在一种可选的实现方式中，在所述遮光层与所述第一钝化层之间还设置有第二平坦层，所述第二平坦层在所述衬底基板上的正投影与所述绑定端子在所述衬底基板上的正投影无交叠，所述第一钝化层在所述衬底基板上的正投影与所述绑定端子在所述衬底基板上的正投影无交叠。
在一种可选的实现方式中，在所述遮光层与所述第二平坦层之间还设置有第二钝化层，所述第二钝化层在所述衬底基板上的正投影与所述绑定端子在所述衬底基板上的正投影无交叠。
在一种可选的实现方式中，所述遮光层的材料为炭黑材料。
在一种可选的实现方式中，所述绝缘层包括层叠设置在所述第一金属层背离所述衬底基板一侧的第三钝化层、第三平坦层和第四钝化层，所述第三 钝化层靠近所述第一金属层设置。
在一种可选的实现方式中，在所述衬底基板与所述第一金属层之间还设置有电镀功能层，所述电镀功能层在所述衬底基板上的正投影与所述第一金属层在所述衬底基板上的正投影完全重合。
在一种可选的实现方式中，所述显示区域包括多个阵列排布的像素单元，所述第一金属走线包括：
在所述显示区域内沿像素列方向延伸的至少一条第一子走线，所述第一子走线沿像素行方向具有第一线宽；以及，
在所述显示区域内沿像素列方向延伸的至少一条第二子走线，所述第二子走线沿像素行方向具有第二线宽，所述第二线宽小于所述第一线宽。
在一种可选的实现方式中，与所述第一子走线沿像素行方向相邻的第二子走线和所述第一子走线之间具有第一间距，所述第一间距大于所述第一线宽的三倍。
在一种可选的实现方式中，所述第一绑定端子在所述衬底基板上的正投影位于所述第一子走线在所述衬底基板上的正投影范围内。
本公开提供了一种显示装置，所述显示装置包括任一项所述显示基板。
本公开提供了一种显示基板的制备方法，所述显示基板包括显示区域以及位于所述显示区域外围的周边区域，所述制备方法包括：
提供衬底基板；
在所述衬底基板的一侧形成走线功能层，所述走线功能层包括金属走线以及与所述金属走线连接的绑定端子，所述绑定端子包括第一绑定端子、第二绑定端子和第三绑定端子，所述第一绑定端子用于绑定LED芯片，所述第二绑定端子用于绑定驱动芯片，所述驱动芯片用于驱动所述LED芯片发光，所述第三绑定端子用于绑定柔性电路板，所述第一绑定端子与所述第二绑定端子位于所述显示区域，所述第三绑定端子位于所述周边区域；以及，
在所述走线功能层背离所述衬底基板的一侧依次形成第一钝化层和遮光层，所述遮光层在所述衬底基板上的正投影与所述绑定端子在所述衬底基板上的正投影无交叠，在所述显示区域内，所述遮光层在所述衬底基板上的正投影覆盖所述金属走线在所述衬底基板上的正投影。
在一种可选的实现方式中，在所述走线功能层背离所述衬底基板的一侧 依次形成第一钝化层和遮光层的步骤，包括：
在所述走线功能层背离所述衬底基板的一侧形成钝化材料薄膜；
采用第一构图工艺，在所述钝化材料薄膜背离所述衬底基板的一侧形成所述遮光层；
采用第二构图工艺，在所述遮光层背离所述衬底基板的一侧形成第一平坦层，所述第一平坦层在所述衬底基板上的正投影与所述绑定端子在所述衬底基板上的正投影无交叠；以及，
以所述第一平坦层为掩膜版，对所述钝化材料薄膜进行刻蚀，形成所述第一钝化层，所述第一钝化层在所述衬底基板上的正投影与所述绑定端子在所述衬底基板上的正投影无交叠。
在一种可选的实现方式中，在所述走线功能层背离所述衬底基板的一侧依次形成第一钝化层和遮光层的步骤，包括：
在所述走线功能层背离所述衬底基板的一侧形成钝化材料薄膜；
采用第三构图工艺，在所述钝化材料薄膜背离所述衬底基板的一侧形成第二平坦层，所述第二平坦层在所述衬底基板上的正投影与所述绑定端子在所述衬底基板上的正投影无交叠；
采用第四构图工艺，在所述第二平坦层背离所述衬底基板的一侧形成所述遮光层；以及，
以所述第二平坦层为掩膜版，对所述钝化材料薄膜进行刻蚀，形成所述第一钝化层，所述第一钝化层在所述衬底基板上的正投影与所述绑定端子在所述衬底基板上的正投影无交叠。
在一种可选的实现方式中，在所述第二平坦层背离所述衬底基板的一侧形成所述遮光层的步骤之前，还包括：
采用第五构图工艺，在所述第二平坦层背离所述衬底基板的一侧形成第二钝化层，所述第二钝化层在所述衬底基板上的正投影与所述绑定端子在所述衬底基板上的正投影无交叠；
所述在所述第二平坦层背离所述衬底基板的一侧形成所述遮光层的步骤，包括：
在所述第二钝化层背离所述衬底基板的一侧形成所述遮光层。
在一种可选的实现方式中，在所述衬底基板的一侧形成走线功能层的步 骤，包括：
在所述衬底基板的一侧依次形成第一金属层、第三钝化层、第三平坦层、第四钝化层和第二金属层，所述金属走线包括位于所述第一金属层的第一金属走线以及位于所述第二金属层的第二金属走线，所述绑定端子位于所述第二金属层且与所述第二金属走线相互连接，所述第二金属走线与所述第一金属走线通过设置在所述绝缘层上的过孔连接；
其中，形成所述第三平坦层的步骤，包括：
采用第六构图工艺，在所述第三钝化层背离所述衬底基板的一侧形成第四平坦层；以及，
采用第七构图工艺，在所述第四平坦层背离所述衬底基板的一侧形成第五平坦层，所述第四平坦层和所述第五平坦层构成所述第三平坦层。
上述说明仅是本公开技术方案的概述，为了能够更清楚了解本公开的技术手段，而可依照说明书的内容予以实施，并且为了让本公开的上述和其它目的、特征和优点能够更明显易懂，以下特举本公开的具体实施方式。
附图简述
为了更清楚地说明本公开实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。需要说明的是，附图中的比例仅作为示意并不代表实际比例。
图1示出了本公开实施例提供的一种显示基板的平面结构示意图；
图2示出了本公开实施例提供的第一种显示基板的剖面结构示意图；
图3示出了本公开实施例提供的一种走线功能层的平面结构示意图；
图4示出了本公开实施例提供的一种遮光层的平面结构示意图；
图5示出了本公开实施例提供的一种走线功能层的连接结构示意图；
图6示出了本公开实施例提供的第一金属层和第二金属层的平面结构示意图；
图7示出了本公开实施例提供的第二种显示基板的剖面结构示意图；
图8示出了本公开实施例提供的不同厚度的第一钝化层在第二种显示基 板中的扫描电子显微镜照片；
图9示出了本公开实施例提供的几种遮光层材料的参数对比；
图10示出了本公开实施例提供的第三种显示基板的剖面结构示意图；
图11示出了本公开实施例提供的无遮光层残留的图片；
图12示出了本公开实施例提供的有遮光层残留的图片；
图13示出了本公开实施例提供的一种显示装置的结构示意图；
图14示出了本公开实施例提供的一种显示基板的制备方法的步骤流程图；
图15示出了本公开实施例提供的一种显示基板中第一钝化层的制备工艺流程图；
图16示出了本公开实施例提供的一种显示基板中第三平坦层的制备工艺流程图；
图17a示出了本公开实施例提供的一种显示基板的制备工艺流程图；
图17b示出了本公开实施例提供的一种显示基板的制备工艺流程图；
图17c示出了本公开实施例提供的一种显示基板的制备工艺流程图。
详细描述
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开一实施例提供了一种显示基板，参照图1示出了本实施例提供的一种显示基板的平面结构示意图，该显示基板包括显示区域AA以及位于显示区域AA外围的周边区域BB。
参照图2、图7和图10示出了本实施例提供的几种显示基板的剖面结构示意图。该显示基板包括：衬底基板21；设置在衬底基板21一侧的走线功能层22；设置在走线功能层22背离衬底基板21一侧的第一钝化层23；以及，设置在第一钝化层23背离衬底基板21一侧的遮光层24。
参照图3示出了一种走线功能层的平面结构示意图。该走线功能层22包括金属走线31以及与金属走线31连接的绑定端子，绑定端子包括第一绑定 端子32、第二绑定端子33和第三绑定端子34(如图1所示)，第一绑定端子32用于绑定LED芯片，第二绑定端子33用于绑定驱动芯片，驱动芯片用于驱动LED芯片发光，第三绑定端子34用于绑定柔性电路板，第一绑定端子32与第二绑定端子33位于显示区域AA，第三绑定端子34位于周边区域BB。
参照图4示出了一种遮光层的平面结构示意图。结合图3和图4，该遮光层24在衬底基板21上的正投影与绑定端子在衬底基板21上的正投影无交叠，在显示区域AA内，遮光层24在衬底基板21上的正投影覆盖金属走线31在衬底基板21上的正投影。
参照图2至图4，遮光层24在与第一绑定端子32、第二绑定端子33和第三绑定端子34的对应位置处设置有开口区域，便于后续进行绑定工艺。
参照图1，显示区域AA可以包括多个像素单元，各像素单元可以划分为透明区域TR和非透明区域。其中，第一绑定端子32和第二绑定端子33可以位于各像素单元的非透明区域内，如图3和图5所示。其中，图3示出的是一个像素单元内走线功能层的平面结构示意图，图5示出的是多个像素单元对应的走线功能层的连接结构示意图。
参照图3，第一绑定端子32可以有多个，例如可以包括红光LED芯片正极端子、红光LED芯片负极端子、绿光LED芯片正极端子、绿光LED芯片负极端子、蓝光LED芯片正极端子以及蓝光LED芯片负极端子。
如图3和图5所示，金属走线31可以包括扫描信号供给线VCC1、数据信号线Data、参考信号线GND、第一电压信号线VGB、第二电压信号线VR和扫描信号线VCC2等。
需要说明的是，如图5所示，金属走线31中的至少一根扫描信号线VCC2与至少一根扫描信号供给线VCC1电性连接，从而使得扫描信号供给线VCC1可将从柔性电路板接收到的扫描信号传输至与其连接的相应行的扫描信号线VCC2。图5仅示意了上述金属走线31设置的一种可选方式，本实施例对其中不同走线间的连接位置不做限制。
参照图1，周边区域BB可以包括焊盘区域SA以及位于焊盘区域SA与显示区域AA之间的扇出区域。其中，第三绑定端子34位于焊盘区域SA内。
本实施例中，衬底基板21可以包括玻璃衬底或柔性衬底等衬底，还可以包括设置在衬底一侧的对位标记，还可以包括缓冲层等膜层，本实施例对此 不作限定。
走线功能层22可以为单层结构，还可以为多层结构，如可以包括多层金属层以及设置在相邻两个金属层之间的绝缘层等，本实施例对走线功能层22的具体层结构不作限定。后续实施例会详细介绍一种走线功能层22的结构。
第一钝化层23的材料可以包括氧化硅、氮化硅等无机材料，本实施例对此不作限定。通过设置第一钝化层23，可以防止走线功能层22中的金属走线31发生氧化，确保显示基板的性能稳定性，同时还可以防止遮光层24在走线功能层22的表面发生残留。
遮光层24的材料可以为炭黑材料或无机黑材料等，本实施例对此不作限定。
本实施例中，LED芯片为主动发光器件，采用驱动芯片驱动LED芯片发光，可以制作较大尺寸的显示基板，并且实现较大的驱动电流。
本实施例提供的显示基板，通过在走线功能层22背离衬底基板21的一侧设置遮光层24，且遮光层24在衬底基板21上的正投影覆盖金属走线31在衬底基板21上的正投影，从而避免金属走线31反射光线，提高显示器件的对比度。
为了提高显示区域AA的透光率，在一种可选的实现方式中，在显示区域AA内，遮光层24在衬底基板21上的正投影与金属走线31在衬底基板21上的正投影可以完全重合。这样，遮光层24既能完全覆盖住金属走线31，避免金属走线31反射环境光，同时又能增大透明区域TR的面积，从而提高显示区域AA的透光率。
在一种可选的实现方式中，衬底基板21可以采用柔性基板，在显示区域AA与焊盘区域SA之间设置可弯折区域，这样，可以将周边区域BB弯折至显示区域AA的背面，在将多个显示基板拼接作为显示面板使用时，由于周边区域BB位于显示基板背面，可使得相邻显示基板之间间隙减小，因而能提升显示面板的整体显示效果。
在具体实现中，若周边区域BB位于显示区域AA的背面，或者可弯折至显示区域AA的背面，遮光层24在衬底基板21上的正投影与周边区域BB可以无交叠。若周边区域BB位于显示区域AA的正面，或者不可弯折至显示区域AA的背面，在周边区域BB内，遮光层24在衬底基板21上的正投影可以 覆盖金属走线31在衬底基板21上的正投影。
在一种可选的实现方式中，参照图2、图7和图10，走线功能层22可以包括：层叠设置的第一金属层221、绝缘层和第二金属层222，第一金属层221靠近衬底基板21设置。
本实现方式中，参照图6，金属走线31可以包括位于第一金属层221的第一金属走线以及位于第二金属层222的第二金属走线，绑定端子位于第二金属层222且与第二金属走线相互连接，第二金属走线与第一金属走线通过设置在绝缘层上的过孔连接。
在一种可选的实现方式中，显示区域AA包括多个阵列排布的像素单元，参照图6，第一金属走线可以包括：在显示区域AA内沿像素列方向延伸的至少一条第一子走线(例如为参考信号线GND)，第一子走线沿像素行方向具有第一线宽S1。
其中，像素列方向为阵列排布的像素单元的列方向，像素行方向为阵列排布的像素单元的行方向。
参照图6，第一金属走线还可以包括：在显示区域AA内沿像素列方向延伸的至少一条第二子走线(例如第一电压信号线VGB、第二电压信号线VR、数据信号线Data、扫描信号供给线VCC1等)，第二子走线沿像素行方向具有第二线宽S2，第二线宽S2小于第一线宽S1。当第二子走线为多条时，可以沿像素行方向具有不同的第二线宽S2(如包括至少一条线宽为S21的第二子走线、至少一条线宽为S22的第二子走线,……，至少一条线宽为S2n的第二子走线)，但这些第二线宽S2均小于第一线宽S1。
参照图6，与第一子走线(例如为参考信号线GND)沿像素行方向相邻的第二子走线和该第一子走线(例如为参考信号线GND)之间具有第一间距S3，其中，第一间距S3大于第一线宽S1的三倍，即S3>3S1。
在一些示例中，参照图6，第一绑定端子32在衬底基板21上的正投影位于第一子走线(例如为参考信号线GND)在衬底基板21上的正投影范围内。
参照图6，位于第一金属层221的第一金属走线可以包括：扫描信号供给线VCC1、数据信号线Data、参考信号线GND、第一电压信号线VGB以及第二电压信号线VR。位于第二金属层222的第二金属走线可以包括扫描信号线VCC2，还可以包括连接绑定端子与上述信号线的引线等。另外，第一绑定 端子32、第二绑定端子33和第三绑定端子34也可以位于第二金属层222。
其中，第一金属层221的材料可以包括铜层、钼层或铝层等金属膜层，本实施例对此不作限定。第二金属层222的材料可以包括铜层、钼层或铝层等金属膜层，本实施例对此不作限定。
如图2、图7和图10所示，设置在第一金属层221与第二金属层222之间的绝缘层可以包括层叠设置在第一金属层221背离衬底基板21一侧的第三钝化层223、第三平坦层224和第四钝化层225，第三钝化层223靠近第一金属层221设置。
其中，第三钝化层223的材料可以包括氧化硅、氮化硅等无机材料，本实施例对此不作限定。第四钝化层225的材料可以包括氧化硅、氮化硅等无机材料，本实施例对此不作限定。第三平坦层224的材料例如可以为聚丙烯酸类树脂等有机材料，本实施例对此不作限定。
通过在第三平坦层224与第一金属层221之间设置第三钝化层223，可以防止第一金属层221被第三平坦层224在后续工艺中释放的氧气氧化。通过在第三平坦层224与第二金属层222之间设置第四钝化层225，可以防止第二金属层222被第三平坦层224在后续工艺中释放的氧气氧化。
在一种可选的实现方式中，如图2和图10所示，第二金属层222可以为铜层。为了防止周边区域BB的第三绑定端子34氧化，在第一钝化层23与第二金属层222之间还可以设置有透明电极层25，透明电极层25在衬底基板21上的正投影覆盖第三绑定端子34在衬底基板21上的正投影。
其中，透明电极层25的材料可以为氧化铟锡等导电抗氧化的材料，本实施例对此不作限定。通过在第三绑定端子34上设置一层透明电极层25，可以防止第三绑定端子34氧化。
在另一种可选的实现方式中，参照图7，第二金属层222可以包括铜层以及设置在铜层背离衬底基板21一侧的铜镍合金层。通过在铜层的表面设置铜镍合金层，可以防止周边区域BB的第三绑定端子34氧化。
其中，铜镍合金层在衬底基板21上的正投影覆盖可以铜层在衬底基板21上的正投影。
本实现方式中，由于铜镍合金具有较高的强度、耐蚀性和硬度，通过在铜层的整个表面覆盖一层铜镍合金层，可以防止铜层氧化，防止绑定端子氧 化。这样，无需在第三绑定端子34的表面设置透明电极层，因此可以减少一道掩膜工艺，从而可以简化工艺步骤，提高良率，降低成本。
本实现方式中，在绝缘层中的第四钝化层225与第二金属层222之间还可以设置一层钼层或钼铌合金层等，这样可以提高第二金属层222与绝缘层中的第四钝化层225之间的结合牢固度。
其中，钼铌合金层的厚度例如可以为300埃，铜层的厚度例如可以为6000埃，铜镍合金层的厚度例如可以为500埃。
发明人通过扫描电子显微镜分析发现，本实现方式中，由于第二金属层222中的铜层刻蚀速度较快，导致刻蚀后的铜层相对于铜镍合金层缩进，如图8所示，导致后续在制作第一钝化层23的过程中存在断裂(crack)风险，尤其是在第一钝化层23的厚度较薄时断裂风险提高，如图8中的b所示。
为了降低第一钝化层23发生断裂的风险，第一钝化层23的厚度可以大于或等于8000埃，如图8中的a所示。
参照图2和图7，在遮光层24背离衬底基板21的一侧还可以设置有第一平坦层26，第一平坦层26在衬底基板21上的正投影与绑定端子在衬底基板21上的正投影无交叠，第一钝化层23在衬底基板21上的正投影与绑定端子在衬底基板21上的正投影无交叠。
其中，第一平坦层26的材料例如可以为聚丙烯酸类树脂等有机材料，本实施例对此不作限定。
为了防止绑定端子在绑定工艺前的存放过程中发生氧化，在显示基板的制程中可以先不对第一钝化层23与绑定端子对应的位置进行刻蚀，而是在绑定工艺之前以图案化的第一平坦层26为掩膜版，对第一钝化层23进行刻蚀，使第一钝化层23在衬底基板21上的正投影与绑定端子在衬底基板21上的正投影无交叠；之后再进行绑定工艺。
为了进一步减小遮光层24与第二金属层222之间形成的耦合电容，参照图10，在遮光层24与第一钝化层23之间还可以设置有第二平坦层101，第二平坦层101在衬底基板21上的正投影与绑定端子在衬底基板21上的正投影无交叠，第一钝化层23在衬底基板21上的正投影与绑定端子在衬底基板21上的正投影无交叠。
其中，第二平坦层101的材料例如可以为聚丙烯酸类树脂等有机材料， 本实施例对此不作限定。
通过在遮光层24与第一钝化层23之间设置第二平坦层101，增大遮光层24与第二金属层222之间的距离，从而可以减少遮光层24与第二金属层222间的耦合电容带来的负面影响。
为了防止绑定端子在绑定工艺前的存放过程中发生氧化，在显示基板的制程中可以先不对第一钝化层23与绑定端子对应的位置进行刻蚀，而是在绑定工艺之前以第二平坦层101为掩膜版，对第一钝化层23进行刻蚀，使第一钝化层23在衬底基板21上的正投影与绑定端子在衬底基板21上的正投影无交叠；之后再进行绑定工艺。
发明人发现，遮光层24的材料在亲水表面(-OH界面)的接触角小，可形成较好的图形，如图11所示；在亲水性不佳的基底上接触角大，易出现残留，残留物为在扫描电子显微镜下可见的颗粒，如图12所示，残留与曝光及显影工艺无关。第二平坦层101界面为聚丙烯酸类树脂属于疏水材料，遮光层24的材料在其表面容易发生残留。遮光层24残留可能产生两方面的后果，其一是残留在透明区会严重影响透明区的透过率，其二是残留在绑定区域可能导致绑定不良。
为了避免遮光层24残留，参照图10，在遮光层24与第二平坦层101之间还可以设置有第二钝化层102，第二钝化层102在衬底基板21上的正投影与绑定端子在衬底基板21上的正投影无交叠。
其中，第二钝化层102的材料可以包括氧化硅、氮化硅等无机材料，本实施例对此不作限定。
通过在遮光层24与第二平坦层101之间设置第二钝化层102，可以防止遮光层24在第二平坦层101上发生残留。
在图2和图7示出的显示基板中，由于遮光层24与第二金属层222之间距离较近，为了避免遮光层24与第二金属层222之间形成耦合电容，遮光层24的材料可以为有机黑材料。
参照图9中的b列和c列为两种有机黑材料的参数。由于有机黑材料的介电常数相对较低，分别为3.7和3.5，采用有机黑材料制作图2和图7中的遮光层24，可以减小遮光层24与第二金属层222之间形成的耦合电容，避免遮光层24对第二金属层222负载的影响。在实际应用中，由于c列有机黑材 料在曝光工艺中的解像能力(～5μm)比b列材料解像能力(＞9μm)更好，因此可以选择c列有机黑材料制作遮光层24，这样可以提高曝光工艺控制精度。
在图10示出的显示基板中，遮光层24的材料可以选用炭黑材料。
参照图9中的a列为一种炭黑材料的参数。碳黑材料的介电常数(15)相对有机黑材料的介电常数(3.7和3.5)要高，但是由于图10中遮光层24与第二金属层222之间设置有第二平坦层101，增大了遮光层24与第二金属层222之间的距离，因此遮光层24的材料可以选用介电常数稍高的炭黑材料，也能避免遮光层24与第二金属层222之间耦合电容的影响，避免遮光层24对第二金属层222负载的影响。
需要说明的是，图10中的遮光层24也可以选用有机黑材料，这样可以进一步降低耦合电容。但是由于a列炭黑材料在曝光工艺中的解像能力(～0μm)比有机黑材料的解像能力更好，因此选择a列炭黑材料制作遮光层24，可以提高曝光工艺控制精度。
在具体实现中，遮光层24的厚度可以根据具体材料的光密度值以及遮光层24的透过率设计值确定，本实施例对此不作限定。
下面以遮光层24的透过率小于或等于1％为例对遮光层24的厚度进行说明。
图9中a列材料的光密度(optical density，OD)值为4.0/μm，为了使a列材料的遮光层24的透过率小于或等于1％，遮光层24的厚度可以大于或等于0.5μm。
图9中b列材料的光密度(optical density，OD)值为2.0/μm，为了使b列材料的遮光层24的透过率小于或等于1％，遮光层24的厚度可以大于或等于1.0μm。
图9中c列材料的光密度(optical density，OD)值为2.6/μm，为了使c列材料的遮光层24的透过率小于或等于1％，遮光层24的厚度可以大于或等于0.77μm。
在一种可选的实现方式中，参照图2、图7和图10，在衬底基板21与第一金属层221之间还可以设置有电镀功能层27，电镀功能层27在衬底基板21上的正投影与第一金属层221在衬底基板21上的正投影完全重合，电镀功 能层27用于提高第一金属层221与衬底基板21之间的结合牢固度。
电镀功能层27的材料例如可以为钼或钼铌合金等，本实施例对此不作限定。
本公开另一实施例还提供了一种显示装置，该显示装置可以包括如任一实施例所述的显示基板。
需要说明的是，本实施例中的显示装置可以为：显示面板、电子纸、手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有2D或3D显示功能的产品或部件。
在具体实现中，显示装置可以包括多个如任一实施例所述的显示基板。如图13所示，多个显示基板之间可以通过箱体锁与竖梁进行固定。多个显示基板之间可以实现纵向无缝拼接，即无横向拼缝，视觉效果更加敞亮通透。
本实施例中，显示装置可以应用于户外透明显示。由于LED芯片采用无机材料，在户外或半户外场景中的信赖性更好。
显示基板中的像素可以呈矩形阵列，透光区域均匀，从而提升视觉效果。
本实施例提供的显示装置，可以采用100微米级LED芯片/走线，实现透过率>70％，广视角>160℃；采用主动驱动方案，精准控光，低灰表现好，功耗低；像素密度高，可视距离小，画面表现更细致；重量轻薄，便于拆装，可无限拼接；信号无线传输，可扩展性好，便于维护。像素单元间距可以为3mm，观看距离>8米，透过率达到85％，亮度达到2000nit(校正前)。
本公开另一实施例还提供了一种显示基板的制备方法，显示基板包括显示区域以及位于显示区域外围的周边区域，参照图14，该制备方法包括：
步骤1401：提供衬底基板。
步骤1402：在衬底基板的一侧形成走线功能层，走线功能层包括金属走线以及与金属走线连接的绑定端子，绑定端子包括第一绑定端子、第二绑定端子和第三绑定端子，第一绑定端子用于绑定LED芯片，第二绑定端子用于绑定驱动芯片，驱动芯片用于驱动LED芯片发光，第三绑定端子用于绑定柔性电路板，第一绑定端子与第二绑定端子位于显示区域，第三绑定端子位于周边区域。
步骤1403：在走线功能层背离衬底基板的一侧依次形成第一钝化层和遮光层，遮光层在衬底基板上的正投影与绑定端子在衬底基板上的正投影无交 叠，在显示区域内，遮光层在衬底基板上的正投影覆盖金属走线在衬底基板上的正投影。
采用本实施例提供的制备方法，可以制备得到上述任一实施例所述的显示基板。
在一种可选的实现方式中，步骤1403具体可以包括：
在走线功能层背离衬底基板的一侧形成钝化材料薄膜；
采用第一构图工艺，在钝化材料薄膜背离衬底基板的一侧形成遮光层；
采用第二构图工艺，在遮光层背离衬底基板的一侧形成第一平坦层，第一平坦层在衬底基板上的正投影与绑定端子在衬底基板上的正投影无交叠；以及，
以第一平坦层为掩膜版，对钝化材料薄膜进行刻蚀，形成第一钝化层，第一钝化层在衬底基板上的正投影与绑定端子在衬底基板上的正投影无交叠。
本实现方式中，为了防止绑定端子在进行绑定工艺之前的存放过程中出现氧化问题，参照图15，在显示背板制作过程中可以先不对第一钝化层23进行刻蚀。在需要进行绑定工艺时利用已经图案化的第一平坦层26作为掩膜版对第一钝化层23进行刻蚀，然后再进行绑定工艺。
在另一种可选的实现方式中，步骤1403具体可以包括：
在走线功能层背离衬底基板的一侧形成钝化材料薄膜；
采用第三构图工艺，在钝化材料薄膜背离衬底基板的一侧形成第二平坦层，第二平坦层在衬底基板上的正投影与绑定端子在衬底基板上的正投影无交叠；
采用第四构图工艺，在第二平坦层背离衬底基板的一侧形成遮光层；以及，
以第二平坦层为掩膜版，对钝化材料薄膜进行刻蚀，形成第一钝化层，第一钝化层在衬底基板上的正投影与绑定端子在衬底基板上的正投影无交叠。
本实现方式中，为了防止绑定端子在进行绑定工艺之前的存放过程中出现氧化问题，在显示背板制作过程中可以先不对第一钝化层进行刻蚀工艺。在需要进行绑定工艺时利用已经图案化的第二平坦层作为掩膜版对第一钝化层进行刻蚀，然后再进行绑定工艺。
本实现方式中，在第二平坦层背离衬底基板的一侧形成遮光层的步骤之 前，还可以包括以下步骤：采用第五构图工艺，在第二平坦层背离衬底基板的一侧形成第二钝化层，第二钝化层在衬底基板上的正投影与绑定端子在衬底基板上的正投影无交叠。相应地，在第二平坦层背离衬底基板的一侧形成遮光层的步骤，可以包括：在第二钝化层背离衬底基板的一侧形成遮光层。
在一种可选的实现方式中，步骤1402具体可以包括：
在衬底基板的一侧依次形成第一金属层、第三钝化层、第三平坦层、第四钝化层和第二金属层，金属走线包括位于第一金属层的第一金属走线以及位于第二金属层的第二金属走线，绑定端子位于第二金属层且与第二金属走线相互连接，第二金属走线与第一金属走线通过设置在绝缘层上的过孔连接。
其中，形成第三平坦层的步骤，可以包括：
采用第六构图工艺，在第三钝化层背离衬底基板的一侧形成第四平坦层；以及，采用第七构图工艺，在第四平坦层背离衬底基板的一侧形成第五平坦层，第四平坦层和第五平坦层构成第三平坦层。
参照图16，第三平坦层224采用两次构图工艺形成，这样可以降低工艺难度，提高工艺控制精度。
本实施例中的构图工艺，可以包括以下工艺步骤至少之一：成膜工艺、曝光显影工艺、刻蚀工艺和光刻胶去除工艺等。其中，成膜工艺可以为磁控溅射工艺、热蒸镀工艺、电子束蒸镀工艺或电镀工艺中的一种。刻蚀工艺可以为干刻工艺或湿刻工艺。具体的构图工艺步骤可以根据材料以及膜层结构进行设计，本实施例对其不作限定。
参照图17a至图17c示出了第一显示基板的制备工艺流程图。具体可以包括以下步骤：
提供衬底基板21，如图17a中的a所示；
在衬底基板21上形成电镀功能材料薄膜，如图17a中的b所示；
形成PR胶掩膜，如图17a中的c所示；
电镀铜层，如图17a中的d所示；
剥离PR胶，形成第一金属层221，如图17a中的e所示；
以第一金属层221为掩膜版，刻蚀得到电镀功能层27，如图17a或图17b中的f所示；
形成第三钝化层223，如图17b中的g所示；
分别采用第六构图工艺和第七构图工艺，形成第三平坦层224，如图17b中的h所示；
形成第四钝化层225，如图17b中的i所示；
形成第二金属层222，如图17b或图17c中的j所示；
形成透明电极层25和钝化材料薄膜，如图17c中的k所示；
采用第一构图工艺，形成遮光层24，如图17c中的m所示；
采用第二构图工艺，形成第二平坦层26，并以第二平坦层26为掩膜版，对钝化材料薄膜进行刻蚀，形成第一钝化层23，如图17c中的n所示；获得如图2所示的显示基板。
本实施例提供了一种显示基板的制备方法、显示基板及显示装置，其中，显示基板包括显示区域以及位于显示区域外围的周边区域，显示基板包括：衬底基板；设置在衬底基板一侧的走线功能层，走线功能层包括金属走线以及与金属走线连接的绑定端子，绑定端子包括第一绑定端子、第二绑定端子和第三绑定端子，第一绑定端子用于绑定LED芯片，第二绑定端子用于绑定驱动芯片，驱动芯片用于驱动LED芯片发光，第三绑定端子用于绑定柔性电路板，第一绑定端子与第二绑定端子位于显示区域，第三绑定端子位于周边区域；设置在走线功能层背离衬底基板一侧的第一钝化层；以及，设置在第一钝化层背离衬底基板一侧的遮光层，遮光层在衬底基板上的正投影与绑定端子在衬底基板上的正投影无交叠，在显示区域内，遮光层在衬底基板上的正投影覆盖金属走线在衬底基板上的正投影。本公开技术方案，通过在走线功能层背离衬底基板的一侧设置遮光层，且遮光层在衬底基板上的正投影覆盖金属走线在衬底基板上的正投影，从而避免金属走线反射光线，提高显示器件的对比度。
本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。
最后，还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使 得包括一系列要素的过程、方法、商品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、商品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、商品或者设备中还存在另外的相同要素。
以上对本公开所提供的一种显示基板的制备方法、显示基板及显示装置进行了详细介绍，本文中应用了具体个例对本公开的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本公开的方法及其核心思想；同时，对于本领域的一般技术人员，依据本公开的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本公开的限制。本文中所称的“一个实施例”、“实施例”或者“一个或者多个实施例”意味着，结合实施例描述的特定特征、结构或者特性包括在本公开的至少一个实施例中。此外，请注意，这里“在一个实施例中”的词语例子不一定全指同一个实施例。
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本公开的实施例可以在没有这些具体细节的情况下被实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。单词“包含”不排除存在未列在权利要求中的元件或步骤。位于元件之前的单词“一”或“一个”不排除存在多个这样的元件。本公开可以借助于包括有若干不同元件的硬件以及借助于适当编程的计算机来实现。在列举了若干装置的单元权利要求中，这些装置中的若干个可以是通过同一个硬件项来具体体现。单词第一、第二、以及第三等的使用不表示任何顺序。可将这些单词解释为名称。
最后应说明的是：以上实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的精神和范围。

Claims (22)

  1. 一种显示基板，其中，包括显示区域以及位于所述显示区域外围的周边区域，所述显示基板包括：
    衬底基板；
    设置在所述衬底基板一侧的走线功能层，所述走线功能层包括金属走线以及与所述金属走线连接的绑定端子，所述绑定端子包括第一绑定端子、第二绑定端子和第三绑定端子，所述第一绑定端子用于绑定LED芯片，所述第二绑定端子用于绑定驱动芯片，所述驱动芯片用于驱动所述LED芯片发光，所述第三绑定端子用于绑定柔性电路板，所述第一绑定端子与所述第二绑定端子位于所述显示区域，所述第三绑定端子位于所述周边区域；
    设置在所述走线功能层背离所述衬底基板一侧的第一钝化层；以及，
    设置在所述第一钝化层背离所述衬底基板一侧的遮光层，所述遮光层在所述衬底基板上的正投影与所述绑定端子在所述衬底基板上的正投影无交叠，在所述显示区域内，所述遮光层在所述衬底基板上的正投影覆盖所述金属走线在所述衬底基板上的正投影。
  2. 根据权利要求1所述的显示基板，其中，在所述显示区域内，所述遮光层在所述衬底基板上的正投影与所述金属走线在所述衬底基板上的正投影完全重合。
  3. 根据权利要求1或2所述的显示基板，其中，所述走线功能层包括：层叠设置的第一金属层、绝缘层和第二金属层，所述第一金属层靠近所述衬底基板设置；
    所述金属走线包括位于所述第一金属层的第一金属走线以及位于所述第二金属层的第二金属走线，所述绑定端子位于所述第二金属层且与所述第二金属走线相互连接，所述第二金属走线与所述第一金属走线通过设置在所述绝缘层上的过孔连接。
  4. 根据权利要求3所述的显示基板，其中，所述第二金属层为铜层，在所述第一钝化层与所述第二金属层之间还设置有透明电极层，所述透明电极层在所述衬底基板上的正投影覆盖所述第三绑定端子在所述衬底基板上的正投影。
  5. 根据权利要求3所述的显示基板，其中，所述第二金属层包括铜层以及设置在所述铜层背离所述衬底基板一侧的铜镍合金层，所述第一钝化层的厚度大于或等于8000埃。
  6. 根据权利要求5所述的显示基板，其中，所述铜镍合金层在所述衬底基板上的正投影覆盖所述铜层在所述衬底基板上的正投影。
  7. 根据权利要求4至6任一项所述的显示基板，其中，在所述遮光层背离所述衬底基板的一侧还设置有第一平坦层，所述第一平坦层在所述衬底基板上的正投影与所述绑定端子在所述衬底基板上的正投影无交叠，所述第一钝化层在所述衬底基板上的正投影与所述绑定端子在所述衬底基板上的正投影无交叠。
  8. 根据权利要求7所述的显示基板，其中，所述遮光层的材料为有机黑材料。
  9. 根据权利要求4至6任一项所述的显示基板，其中，在所述遮光层与所述第一钝化层之间还设置有第二平坦层，所述第二平坦层在所述衬底基板上的正投影与所述绑定端子在所述衬底基板上的正投影无交叠，所述第一钝化层在所述衬底基板上的正投影与所述绑定端子在所述衬底基板上的正投影无交叠。
  10. 根据权利要求9所述的显示基板，其中，在所述遮光层与所述第二平坦层之间还设置有第二钝化层，所述第二钝化层在所述衬底基板上的正投影与所述绑定端子在所述衬底基板上的正投影无交叠。
  11. 根据权利要求9或10所述的显示基板，其中，所述遮光层的材料为炭黑材料。
  12. 根据权利要求3至11任一项所述的显示基板，其中，所述绝缘层包括层叠设置在所述第一金属层背离所述衬底基板一侧的第三钝化层、第三平坦层和第四钝化层，所述第三钝化层靠近所述第一金属层设置。
  13. 根据权利要求3至12任一项所述的显示基板，其中，在所述衬底基板与所述第一金属层之间还设置有电镀功能层，所述电镀功能层在所述衬底基板上的正投影与所述第一金属层在所述衬底基板上的正投影完全重合。
  14. 根据权利要求3至13任一项所述的显示基板，其中，所述显示区域包括多个阵列排布的像素单元，所述第一金属走线包括：
    在所述显示区域内沿像素列方向延伸的至少一条第一子走线，所述第一子走线沿像素行方向具有第一线宽；以及，
    在所述显示区域内沿像素列方向延伸的至少一条第二子走线，所述第二子走线沿像素行方向具有第二线宽，所述第二线宽小于所述第一线宽。
  15. 根据权利要求14所述的显示基板，其中，与所述第一子走线沿像素行方向相邻的第二子走线和所述第一子走线之间具有第一间距，所述第一间距大于所述第一线宽的三倍。
  16. 根据权利要求14所述的显示基板，其中，所述第一绑定端子在所述衬底基板上的正投影位于所述第一子走线在所述衬底基板上的正投影范围内。
  17. 一种显示装置，其中，所述显示装置包括权利要求1至16任一项所述显示基板。
  18. 一种显示基板的制备方法，其中，所述显示基板包括显示区域以及位于所述显示区域外围的周边区域，所述制备方法包括：
    提供衬底基板；
    在所述衬底基板的一侧形成走线功能层，所述走线功能层包括金属走线以及与所述金属走线连接的绑定端子，所述绑定端子包括第一绑定端子、第二绑定端子和第三绑定端子，所述第一绑定端子用于绑定LED芯片，所述第二绑定端子用于绑定驱动芯片，所述驱动芯片用于驱动所述LED芯片发光，所述第三绑定端子用于绑定柔性电路板，所述第一绑定端子与所述第二绑定端子位于所述显示区域，所述第三绑定端子位于所述周边区域；以及，
    在所述走线功能层背离所述衬底基板的一侧依次形成第一钝化层和遮光层，所述遮光层在所述衬底基板上的正投影与所述绑定端子在所述衬底基板上的正投影无交叠，在所述显示区域内，所述遮光层在所述衬底基板上的正投影覆盖所述金属走线在所述衬底基板上的正投影。
  19. 根据权利要求18所述的制备方法，其中，在所述走线功能层背离所述衬底基板的一侧依次形成第一钝化层和遮光层的步骤，包括：
    在所述走线功能层背离所述衬底基板的一侧形成钝化材料薄膜；
    采用第一构图工艺，在所述钝化材料薄膜背离所述衬底基板的一侧形成所述遮光层；
    采用第二构图工艺，在所述遮光层背离所述衬底基板的一侧形成第一平 坦层，所述第一平坦层在所述衬底基板上的正投影与所述绑定端子在所述衬底基板上的正投影无交叠；以及，
    以所述第一平坦层为掩膜版，对所述钝化材料薄膜进行刻蚀，形成所述第一钝化层，所述第一钝化层在所述衬底基板上的正投影与所述绑定端子在所述衬底基板上的正投影无交叠。
  20. 根据权利要求18所述的制备方法，其中，在所述走线功能层背离所述衬底基板的一侧依次形成第一钝化层和遮光层的步骤，包括：
    在所述走线功能层背离所述衬底基板的一侧形成钝化材料薄膜；
    采用第三构图工艺，在所述钝化材料薄膜背离所述衬底基板的一侧形成第二平坦层，所述第二平坦层在所述衬底基板上的正投影与所述绑定端子在所述衬底基板上的正投影无交叠；
    采用第四构图工艺，在所述第二平坦层背离所述衬底基板的一侧形成所述遮光层；以及，
    以所述第二平坦层为掩膜版，对所述钝化材料薄膜进行刻蚀，形成所述第一钝化层，所述第一钝化层在所述衬底基板上的正投影与所述绑定端子在所述衬底基板上的正投影无交叠。
  21. 根据权利要求20所述的制备方法，其中，在所述第二平坦层背离所述衬底基板的一侧形成所述遮光层的步骤之前，还包括：
    采用第五构图工艺，在所述第二平坦层背离所述衬底基板的一侧形成第二钝化层，所述第二钝化层在所述衬底基板上的正投影与所述绑定端子在所述衬底基板上的正投影无交叠；
    所述在所述第二平坦层背离所述衬底基板的一侧形成所述遮光层的步骤，包括：
    在所述第二钝化层背离所述衬底基板的一侧形成所述遮光层。
  22. 根据权利要求18至21任一项所述的制备方法，其中，在所述衬底基板的一侧形成走线功能层的步骤，包括：
    在所述衬底基板的一侧依次形成第一金属层、第三钝化层、第三平坦层、第四钝化层和第二金属层，所述金属走线包括位于所述第一金属层的第一金属走线以及位于所述第二金属层的第二金属走线，所述绑定端子位于所述第二金属层且与所述第二金属走线相互连接，所述第二金属走线与所述第一金 属走线通过设置在所述绝缘层上的过孔连接；
    其中，形成所述第三平坦层的步骤，包括：
    采用第六构图工艺，在所述第三钝化层背离所述衬底基板的一侧形成第四平坦层；以及，
    采用第七构图工艺，在所述第四平坦层背离所述衬底基板的一侧形成第五平坦层，所述第四平坦层和所述第五平坦层构成所述第三平坦层。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108878444A (zh) * 2018-06-07 2018-11-23 武汉天马微电子有限公司 显示面板及显示装置
CN110391261A (zh) * 2018-04-18 2019-10-29 英属开曼群岛商镎创科技股份有限公司 微型发光二极管显示面板
CN110707130A (zh) * 2019-09-04 2020-01-17 武汉华星光电半导体显示技术有限公司 显示面板及其制作方法
CN111766977A (zh) * 2020-06-12 2020-10-13 惠州市华星光电技术有限公司 触控面板及触控显示装置
CN112310119A (zh) * 2020-10-16 2021-02-02 深圳市华星光电半导体显示技术有限公司 显示面板及制备方法
CN112599536A (zh) * 2020-12-10 2021-04-02 深圳市华星光电半导体显示技术有限公司 显示面板及其制作方法、拼接显示面板

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110391261A (zh) * 2018-04-18 2019-10-29 英属开曼群岛商镎创科技股份有限公司 微型发光二极管显示面板
CN108878444A (zh) * 2018-06-07 2018-11-23 武汉天马微电子有限公司 显示面板及显示装置
CN110707130A (zh) * 2019-09-04 2020-01-17 武汉华星光电半导体显示技术有限公司 显示面板及其制作方法
CN111766977A (zh) * 2020-06-12 2020-10-13 惠州市华星光电技术有限公司 触控面板及触控显示装置
CN112310119A (zh) * 2020-10-16 2021-02-02 深圳市华星光电半导体显示技术有限公司 显示面板及制备方法
CN112599536A (zh) * 2020-12-10 2021-04-02 深圳市华星光电半导体显示技术有限公司 显示面板及其制作方法、拼接显示面板

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