WO2021196898A1 - 显示基板、覆晶薄膜、显示装置及其制造方法 - Google Patents

显示基板、覆晶薄膜、显示装置及其制造方法 Download PDF

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Publication number
WO2021196898A1
WO2021196898A1 PCT/CN2021/075948 CN2021075948W WO2021196898A1 WO 2021196898 A1 WO2021196898 A1 WO 2021196898A1 CN 2021075948 W CN2021075948 W CN 2021075948W WO 2021196898 A1 WO2021196898 A1 WO 2021196898A1
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WIPO (PCT)
Prior art keywords
binding
base substrate
chip
cof
layer
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PCT/CN2021/075948
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English (en)
French (fr)
Inventor
税禹单
任艳萍
向炼
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/437,012 priority Critical patent/US20230180548A1/en
Publication of WO2021196898A1 publication Critical patent/WO2021196898A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/094—Array of pads or lands differing from one another, e.g. in size, pitch, thickness; Using different connections on the pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09418—Special orientation of pads, lands or terminals of component, e.g. radial or polygonal orientation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10128—Display

Definitions

  • This application relates to the field of display technology, and in particular to a display substrate, a flip chip film, a display device and a manufacturing method thereof.
  • OLED display devices have the characteristics of high contrast, high brightness, low power consumption and flexible folding, and have made considerable progress in the current display technology field.
  • the application provides a display substrate, a flip chip film, a display device and a manufacturing method thereof.
  • a display device which includes: a base substrate; a binding structure on the base substrate; a chip-on-chip COF, the COF and the binding structure are far away from each other.
  • One side of the base substrate is bound; wherein the COF and the side of the binding structure away from the base substrate are engaged with each other; when the COF and the binding structure are bound, the The COF is in contact with both the first surface and the second surface of the side of the binding structure away from the base substrate, the first surface is parallel to the base substrate, and the second surface is in contact with the first surface. There are angles on the surface.
  • the binding structure includes: a plurality of binding pattern layers sequentially superimposed on the base substrate, and a first insulating layer located between every two adjacent binding pattern layers;
  • the COF includes: a plurality of chip-on-chip thin film layers stacked in sequence, and a second insulating layer located between every two adjacent chip-on-chip thin film layers;
  • the plurality of binding pattern layers correspond to the plurality of chip-on-chip film layers one-to-one, and each of the binding pattern layers is bound to the corresponding chip-on-chip film layer on a side away from the base substrate;
  • the edges of the plurality of binding pattern layers away from the base substrate are arranged in a stepped manner, and the first surface includes: at least part of the surface of the binding pattern layer away from the base substrate Area, the second surface includes: at least one side surface of at least one of the binding pattern layer.
  • the i-th binding pattern layer sequentially arranged in a direction away from the base substrate protrudes from the (i+1)th binding pattern layer, i ⁇ 1 .
  • the first orthographic projection is located in the second orthographic projection, and the area of the first orthographic projection is smaller than the area of the second orthographic projection;
  • the first orthographic projection is the orthographic projection of the i+1th binding pattern layer on the base substrate
  • the second orthographic projection is the i-th bound pattern layer on the base substrate Orthographic projection on.
  • the multiple binding pattern layers include: a first binding pattern layer and at least one second binding pattern layer;
  • the at least one second binding pattern layer is located between the base substrate and the first binding pattern layer, and the second binding pattern layer includes: a first sub-pattern and a second sub-pattern spaced apart , The first sub-pattern and the second sub-pattern are both bound to the chip-on-chip film layer corresponding to the second binding pattern layer;
  • the side of the first sub-pattern in the i-th binding pattern layer away from the second sub-pattern protrudes from the i+1-th binding pattern layer, and the i-th binding pattern
  • the side of the second sub-pattern in the layer away from the first sub-pattern protrudes from the i+1th binding pattern layer.
  • the i-th binding pattern layer protrudes from the first insulating layer, and the first insulating layer protrudes from the (i+1)th Layers of binding patterns.
  • the length of the first insulating layer protruding from the (i+1)th binding pattern layer is less than or equal to 60 microns.
  • the length is greater than or equal to 20 microns and less than or equal to 40 microns.
  • the bonding pattern layer includes at least one first pin
  • the chip-on-film layer includes at least one second pin
  • the first pin in the bonding pattern layer and the corresponding pin are
  • the second pins in the flip-chip film layer have a one-to-one correspondence, and each of the first pins is bound to the corresponding second pin on a side away from the base substrate;
  • the display device further includes: a plurality of leads located on the base substrate, the first pins in the binding structure correspond to the plurality of leads in a one-to-one correspondence, and the first pins are connected correspondingly Of the lead.
  • the display device further includes: a connection structure on the base substrate, and at least part of the first pins are connected to the leads corresponding to the first pins through the connection structure.
  • the display device further includes:
  • a flexible circuit board FPC the COF is bound with the FPC, and the side of the COF away from the FPC is bound with the binding structure.
  • a method for manufacturing a display device including:
  • the COF and the binding structure are engaged with each other on the side away from the base substrate; when the COF and the binding structure are bound, the COF and the binding structure are far away from the
  • the first surface and the second surface on one side of the base substrate are in contact with each other, the first surface is parallel to the base substrate, and an angle exists between the second surface and the first surface.
  • forming a binding structure on the base substrate includes: forming a plurality of binding pattern layers sequentially superimposed on the base substrate, and located between every two adjacent binding pattern layers The first insulating layer between the layers; the edges of the plurality of binding pattern layers away from the base substrate are arranged in a stepped manner; wherein, the first surface includes: the binding pattern layer is far away from the base substrate At least a partial area of the surface of the base substrate, the second surface includes: at least one side surface of at least one of the binding pattern layer;
  • the COF includes: a plurality of chip-on-chip film layers stacked in sequence, and a second insulating layer located between every two adjacent chip-on-chip film layers, the plurality of binding pattern layers and the plurality of One-to-one correspondence between the crystal film layers; binding the COF and the binding structure on the side away from the base substrate includes:
  • each binding pattern layer away from the base substrate is bound to the corresponding chip on film layer.
  • the bonding pattern layer includes at least one first pin
  • the flip chip film layer includes at least one second pin
  • the first pin in the bonding pattern layer corresponds to the corresponding pin.
  • the second pins in the flip chip film layer have a one-to-one correspondence;
  • the binding each side of the binding pattern layer away from the base substrate with the corresponding chip on film layer includes:
  • the method also includes:
  • a plurality of leads are formed on the base substrate, the first pins in the binding structure correspond to the plurality of leads one-to-one, and the first pins are connected to corresponding leads.
  • the method further includes:
  • the first pins are connected to the leads corresponding to the first pins through the connection structure.
  • the method further includes:
  • the COF is bound to the FPC, wherein the COF is bound to the binding structure on a side away from the FPC.
  • the i-th binding pattern layer sequentially arranged in a direction away from the base substrate protrudes from the (i+1)th binding pattern layer, i ⁇ 1 .
  • the first orthographic projection is located in the second orthographic projection, and the area of the first orthographic projection is smaller than the area of the second orthographic projection;
  • the first orthographic projection is the orthographic projection of the i+1th binding pattern layer on the base substrate
  • the second orthographic projection is the i-th bound pattern layer on the base substrate Orthographic projection on.
  • the multiple binding pattern layers include: a first binding pattern layer and at least one second binding pattern layer;
  • the at least one second binding pattern layer is located between the base substrate and the first binding pattern layer, and the second binding pattern layer includes: a first sub-pattern and a second sub-pattern spaced apart , The first sub-pattern and the second sub-pattern are both bound to the chip-on-chip film layer corresponding to the second binding pattern layer;
  • the side of the first sub-pattern in the i-th binding pattern layer away from the second sub-pattern protrudes from the i+1-th binding pattern layer, and the i-th binding pattern
  • the side of the second sub-pattern in the layer away from the first sub-pattern protrudes from the i+1th binding pattern layer.
  • the i-th binding pattern layer protrudes from the first insulating layer, and the first insulating layer protrudes from the (i+1)th Layers of binding patterns.
  • the length of the first insulating layer protruding from the (i+1)th binding pattern layer is less than or equal to 60 microns.
  • the length is greater than or equal to 20 microns and less than or equal to 40 microns.
  • the material of the base substrate includes: a flexible material.
  • a display substrate including:
  • a binding structure, the binding structure is located on the base substrate;
  • the side of the binding structure away from the base substrate is used for binding with the flip chip COF, and the side of the binding structure away from the base substrate is used for engaging with the COF. ;
  • the binding structure has a first surface and a second surface away from the base substrate, the first surface and the second surface have an angle, and when the binding structure is bound to the COF Both the first surface and the second surface are used to contact the COF.
  • the binding structure includes: a plurality of binding pattern layers sequentially superimposed on the base substrate, and a first insulating layer located between every two adjacent binding pattern layers;
  • the COF includes: a plurality of chip-on-chip film layers sequentially superimposed on the FPC, and a second insulating layer located between every two adjacent chip-on-chip film layers;
  • the plurality of bonding pattern layers correspond to the plurality of chip-on-chip film layers one-to-one, and the side of each of the bonding pattern layers away from the base substrate is used to bind to the corresponding chip-on-chip film layer Certainly;
  • the edges of the plurality of binding pattern layers away from the base substrate are arranged in a stepped manner, and the first surface includes: at least part of the surface of the binding pattern layer away from the base substrate Area, the second surface includes: at least one side of at least one of the binding pattern layers.
  • the i-th binding pattern layer sequentially arranged in a direction away from the base substrate protrudes from the (i+1)th binding pattern layer, i ⁇ 1 .
  • the first orthographic projection is located in the second orthographic projection, and the area of the first orthographic projection is smaller than the area of the second orthographic projection;
  • the first orthographic projection is the orthographic projection of the i+1th binding pattern layer on the base substrate
  • the second orthographic projection is the i-th bound pattern layer on the base substrate Orthographic projection on.
  • the multiple binding pattern layers include: a first binding pattern layer and at least one second binding pattern layer;
  • the at least one second binding pattern layer is located between the base substrate and the first binding pattern layer, and the second binding pattern layer includes: a first sub-pattern and a second sub-pattern spaced apart , The first sub-pattern and the second sub-pattern are both used for bonding the flip chip film layer corresponding to the second bonding pattern layer;
  • the side of the first sub-pattern in the i-th binding pattern layer away from the second sub-pattern protrudes from the i+1-th binding pattern layer, and the i-th binding pattern
  • the side of the second sub-pattern in the layer away from the first sub-pattern protrudes from the i+1th binding pattern layer.
  • the i-th binding pattern layer protrudes from the first insulating layer, and the first insulating layer protrudes from the (i+1)th Layers of binding patterns.
  • the length of the first insulating layer protruding from the (i+1)th binding pattern layer is less than or equal to 60 microns.
  • the length is greater than or equal to 20 microns and less than or equal to 40 microns.
  • the bonding pattern layer includes at least one first pin, and the flip chip layer includes at least one second pin;
  • the first pins in the bonding pattern layer correspond to the second pins in the corresponding chip-on-chip layer, and each first pin is used to correspond to the corresponding second pin.
  • the second pin is bound;
  • the display substrate further includes: a plurality of leads located on the base substrate, the first pins in the binding structure correspond to the plurality of leads in a one-to-one correspondence, and the first pins are connected correspondingly Of the lead.
  • the display substrate further includes: a connection structure on the base substrate, and at least part of the first pins are connected to corresponding leads through the connection structure.
  • the material of the base substrate includes: a flexible material.
  • a method for manufacturing a display substrate including:
  • the side of the binding structure away from the base substrate is used for binding with the flip chip COF, and the side of the binding structure away from the base substrate is used for engaging with the COF. ;
  • the binding structure has a first surface and a second surface away from the base substrate, the first surface and the second surface have an angle, and when the binding structure is bound to the COF Both the first surface and the second surface are used to contact the COF.
  • forming a binding structure on the base substrate includes: forming a plurality of binding pattern layers sequentially superimposed on the base substrate, and located between every two adjacent binding pattern layers The first insulating layer between the layers; the edges of the plurality of binding pattern layers away from the base substrate are arranged in a stepped manner; wherein, the first surface includes: the binding pattern layer is far away from the base substrate At least a partial area of the surface of the base substrate, the second surface includes: at least one side surface of at least one of the binding pattern layer;
  • the COF includes: a plurality of chip-on-chip film layers stacked in sequence, and a second insulating layer located between every two adjacent chip-on-chip film layers, the plurality of binding pattern layers and the plurality of There is a one-to-one correspondence between the crystal film layers; the side of each of the binding pattern layers away from the base substrate is used for binding with the corresponding chip on film layer.
  • the bonding pattern layer includes at least one first pin
  • the flip chip film layer includes at least one second pin
  • the first pin in the bonding pattern layer corresponds to the corresponding pin.
  • the second pins in the flip-chip film layer have a one-to-one correspondence; the side of each of the first pins away from the base substrate is used for binding with the corresponding second pins;
  • the method also includes:
  • a plurality of leads are formed on the base substrate, the first pins in the binding structure correspond to the plurality of leads one-to-one, and the first pins are connected to corresponding leads.
  • the method further includes:
  • the first pins are connected to the leads corresponding to the first pins through the connection structure.
  • the i-th binding pattern layer sequentially arranged in a direction away from the base substrate protrudes from the (i+1)th binding pattern layer, i ⁇ 1 .
  • the first orthographic projection is located in the second orthographic projection, and the area of the first orthographic projection is smaller than the area of the second orthographic projection;
  • the first orthographic projection is the orthographic projection of the i+1th binding pattern layer on the base substrate
  • the second orthographic projection is the i-th bound pattern layer on the base substrate Orthographic projection on.
  • the multiple binding pattern layers include: a first binding pattern layer and at least one second binding pattern layer;
  • the at least one second binding pattern layer is located between the base substrate and the first binding pattern layer, and the second binding pattern layer includes: a first sub-pattern and a second sub-pattern spaced apart , The first sub-pattern and the second sub-pattern are both bound to the chip-on-chip film layer corresponding to the second binding pattern layer;
  • the side of the first sub-pattern in the i-th binding pattern layer away from the second sub-pattern protrudes from the i+1-th binding pattern layer, and the i-th binding pattern
  • the side of the second sub-pattern in the layer away from the first sub-pattern protrudes from the i+1th binding pattern layer.
  • the i-th binding pattern layer protrudes from the first insulating layer, and the first insulating layer protrudes from the (i+1)th Layers of binding patterns.
  • the length of the first insulating layer protruding from the (i+1)th binding pattern layer is less than or equal to 60 microns.
  • the length is greater than or equal to 20 microns and less than or equal to 40 microns.
  • the material of the base substrate includes: a flexible material.
  • a chip-on-film COF is provided.
  • the COF has a third surface and a fourth surface.
  • the third surface and the fourth surface have an angle; the COF is used to be away from the binding structure.
  • One side of the base substrate is bound, the binding structure is located on the base substrate, and the COF is used to engage with the side of the binding structure away from the base substrate;
  • both the third surface and the fourth surface are used to contact the binding structure.
  • the binding structure includes: a plurality of binding pattern layers sequentially superimposed on the base substrate, and a first insulating layer located between every two adjacent binding pattern layers;
  • the COF includes: a plurality of chip-on-chip thin film layers stacked in sequence, and a second insulating layer located between every two adjacent chip-on-chip thin film layers;
  • the plurality of binding pattern layers correspond to the plurality of chip-on-chip thin film layers one-to-one, and each of the chip-on-chip thin film layers is used to bind a corresponding side of the binding pattern layer away from the base substrate.
  • the edges of the side where the plurality of chip-on-film layers are used for binding with the binding structure are arranged in a stepped manner, and the third surface includes: At least a partial area of the side, the fourth surface includes: at least one side surface of the at least one chip on film layer.
  • the i-th chip-on-chip film layer arranged along the target direction protrudes from the (i+1)th chip-on-chip film layer, i ⁇ 1, and the target direction is: A direction away from the side of the COF used to bind with the binding structure.
  • the third orthographic projection is located in the fourth orthographic projection, and the area of the third orthographic projection is smaller than the area of the fourth orthographic projection;
  • the third orthographic projection is the orthographic projection of the i-th binding pattern layer on a reference plane
  • the fourth orthographic projection is the orthographic projection of the i+1th binding pattern layer on the reference plane.
  • the reference plane is parallel to the flip chip film layer.
  • the multiple chip-on-chip thin film layers include: a first chip-on-chip thin film layer and at least one second chip-on-chip thin film layer;
  • the at least one second chip-on-chip film layer is located on the side of the first chip-on-chip film layer for binding with the binding structure, and the second chip-on-chip film layer includes: spaced apart third sub-patterns and second sub-patterns. Four sub-patterns, the third sub-pattern and the fourth sub-pattern are both bound to the binding pattern layer corresponding to the second chip on film layer;
  • the i+1th chip on film layer protrudes from the side of the third sub-pattern close to the fourth sub-pattern in the i-th chip on film layer, and the i+1th chip on film layer
  • the thin film layer protrudes from a side of the fourth sub-pattern away from the third sub-pattern in the i-th flip chip thin film layer.
  • the (i+1)th flip chip film layer protrudes from the second insulating layer, and the second insulating layer protrudes from the i th A flip chip film layer.
  • the length of the second insulating layer protruding from the i-th flip-chip film layer is less than or equal to 60 microns.
  • the length is greater than or equal to 20 microns and less than or equal to 40 microns.
  • the bonding pattern layer includes at least one first pin
  • the chip-on-film layer includes at least one second pin
  • the first pin in the bonding pattern layer and the corresponding pin are
  • the second pins in the flip-chip film layer have a one-to-one correspondence, and each of the second pins is used for binding to a side of the corresponding first pin away from the base substrate.
  • the COF is also used for binding with the FPC, and the COF is bound with the binding structure on the side far away from the FPC.
  • a method for manufacturing a chip-on-film COF including:
  • a COF having a third surface and a fourth surface, wherein the third surface and the fourth surface have an angle, and the COF is used to bind the side of the binding structure away from the base substrate, so The binding structure is located on the base substrate, and the COF is used to engage with the side of the binding structure away from the base substrate.
  • the COF Both the third surface and the fourth surface are used to contact the binding structure.
  • the binding structure includes: a plurality of binding pattern layers sequentially superimposed on the base substrate, and a first insulating layer located between every two adjacent binding pattern layers;
  • Manufacturing a COF with a third surface and a fourth surface includes: forming a plurality of stacked chip-on-film layers sequentially, and a second insulating layer located between every two adjacent chip-on-film layers;
  • the plurality of binding pattern layers correspond to the plurality of chip-on-chip thin film layers one-to-one, and each of the chip-on-chip thin film layers is used to bind a corresponding side of the binding pattern layer away from the base substrate.
  • Edges of one side of the plurality of chip-on-film layers used for binding with the binding structure are arranged in a stepped manner, and the third surface includes: At least a partial region of one side of the fourth surface includes: at least one side surface of the at least one chip-on-chip film layer.
  • the i-th chip-on-chip film layer arranged along the first direction protrudes from the (i+1)th chip-on-chip film layer, i ⁇ 1, and the first direction It is the direction away from the side of the COF used for binding with the binding structure.
  • the third orthographic projection is located in the fourth orthographic projection, and the area of the third orthographic projection is smaller than the area of the fourth orthographic projection;
  • the third orthographic projection is the orthographic projection of the i-th binding pattern layer on a reference plane
  • the fourth orthographic projection is the orthographic projection of the i+1th binding pattern layer on the reference plane.
  • the reference plane is parallel to the flip chip film layer.
  • the multiple chip-on-chip thin film layers include: a first chip-on-chip thin film layer and at least one second chip-on-chip thin film layer;
  • the at least one second chip-on-chip film layer is located on the side of the first chip-on-chip film layer for binding with the binding structure, and the second chip-on-chip film layer includes: spaced apart third sub-patterns and second sub-patterns. Four sub-patterns, the third sub-pattern and the fourth sub-pattern are both bound to the binding pattern layer corresponding to the second chip on film layer;
  • the i+1th chip on film layer protrudes from the side of the third sub-pattern close to the fourth sub-pattern in the i-th chip on film layer, and the i+1th chip on film layer
  • the thin film layer protrudes from a side of the fourth sub-pattern away from the third sub-pattern in the i-th flip chip thin film layer.
  • the (i+1)th flip chip film layer protrudes from the second insulating layer, and the second insulating layer protrudes from the i th A flip chip film layer.
  • the length of the second insulating layer protruding from the i-th flip-chip film layer is less than or equal to 60 microns.
  • the length is greater than or equal to 20 microns and less than or equal to 40 microns.
  • the bonding pattern layer includes at least one first pin
  • the chip-on-film layer includes at least one second pin
  • the first pin in the bonding pattern layer and the corresponding pin are
  • the second pins in the flip-chip film layer have a one-to-one correspondence, and each of the second pins is used for binding to a side of the corresponding first pin away from the base substrate.
  • the COF is also used for binding with the FPC, and the COF is bound with the binding structure on the side far away from the FPC.
  • FIG. 1 is a schematic structural diagram of a display device provided by an embodiment of the application.
  • FIG. 2 is a partial top view of the display substrate in FIG. 1 according to an embodiment of the application;
  • FIG. 3 is a partial top view of another display substrate provided by an embodiment of the application.
  • FIG. 4 is a schematic structural diagram of another display device provided by an embodiment of the application.
  • FIG. 5 is a schematic structural diagram of another display device provided by an embodiment of the application.
  • FIG. 6 is a schematic structural diagram of another display device provided by an embodiment of the application.
  • FIG. 7 is a top view of a structure other than COF in FIG. 5 according to an embodiment of the application.
  • FIG. 8 is a top view of a structure other than the COF in FIG. 6 provided by an embodiment of the application;
  • FIG. 9 is a flowchart of a manufacturing method of a display device according to an embodiment of the application.
  • FIG. 10 is a flowchart of another method for manufacturing a display device according to an embodiment of the application.
  • FIG. 11 is a schematic diagram of a partial structure of a display device according to an embodiment of the application.
  • FIG. 12 is a flowchart of a method for manufacturing a display substrate according to an embodiment of the application.
  • FIG. 13 is a flowchart of a COF manufacturing method provided by an embodiment of the application.
  • FIG. 1 is a schematic structural diagram of a display device provided by an embodiment of the application.
  • the display device includes: a display substrate (including a base substrate 011 and a bonding structure 012), a chip on film , COF) 02 and flexible circuit board (FPC) 03.
  • the base substrate 011 includes a display area Q1 (only a part of the display area is shown in FIG. 1), and a binding area Q2 located on one side of the display area Q1, and the binding structure 012 is located in the binding area Q2.
  • the COF 02 is bound to the side of the binding structure 012 away from the base substrate 011, and the COF 02 is also bound to the FPC 03.
  • FIG. 2 is a partial top view of the display substrate in FIG. 1 provided by an embodiment of the application, and FIG. 1 shows the structure of the section GG' in FIG. 2.
  • the display substrate further includes a plurality of leads 013 on the base substrate 011, and the leads 013 extend from the display area Q1 of the base substrate 011 to the bonding area Q2.
  • the binding structure 012 includes a plurality of first pins 0121 corresponding to the plurality of leads 013 one-to-one, and each lead 013 is connected to a corresponding first pin 0121.
  • the lead 013 can be connected to the COF 02 through the binding structure 012, and the lead 013 can also be connected to the FPC 03 through the binding structure 012 and COF 02.
  • the arrangement width of these leads 013 is larger.
  • the arrangement width of one pin 0121 is also larger.
  • a plurality of first pins 0121 can be arranged in two rows, and there is a certain amount of gap.
  • the first pin 0121 of the first row can be directly connected to the corresponding lead 013, and the lead 013 corresponding to the first pin 0121 of the second row needs to pass through the first pin 0121 of the first row and be connected to the first pin of the second row. 0121 connection.
  • the binding structure 012 when the binding structure 012 is bound to COF 02, the binding structure 012 The surface of the first pin 0121 away from the base substrate (parallel to the base substrate) is in contact with the COF 02. However, the other surface of the binding structure 012 on the side away from the base substrate (such as the side surface of the first pin 0121, which is perpendicular to the base substrate) is not in contact with the COF 02. Moreover, due to the existence of the first pin 0121, the location of the bonding area Q2 in the display substrate is uneven.
  • the embodiment of the present application provides another display device, which can reduce the risk of component damage at the position of the binding area in the display substrate.
  • FIG. 4 is a schematic structural diagram of another display device provided by an embodiment of the application.
  • the display device includes: a base substrate 10, a binding structure 11, and a COF 12.
  • the binding structure 11 is located on the base substrate 10, and the COF 12 is bound to the side of the binding structure 11 away from the base substrate 10.
  • the COF 12 and the binding structure 11 are engaged with each other on the side away from the base substrate 10.
  • the COF 12 and the binding structure 11 are bound, the COF 12 and the binding structure 11 are located away from the base substrate 10. Both the one surface A and the second surface B are in contact.
  • the first surface A is parallel to the base substrate 10 (for example, the first surface A is parallel to the surface of the base substrate 10 on the side where the binding structure 11 is provided), and there is a sandwich between the second surface B and the first surface A. Horn.
  • the second surface B is perpendicular or inclined to the first surface A. Since the COF 12 is engaged with the binding structure 11, the COF 12 may have a third surface (not marked in FIG.
  • the side of the binding structure away from the base substrate is in contact with the side of the COF close to the binding structure, and the side of the binding structure away from the base substrate is in contact with each other. There is almost no gap between the sides of the COF close to the binding structure.
  • the protrusions in the binding structure can be engaged with the recesses in the COF, or the recesses in the binding structure can be engaged with the protrusions in the COF.
  • the present application does not limit this.
  • the embodiment of the present application improves the structure of at least one of the binding structure and the COF, so that the binding structure and the COF can be engaged.
  • the embodiment of the application only improves the shape of the binding structure as an example. Of course, it can also only improve the shape of the COF, or both the binding structure and the shape of the COF are improved. The embodiment does not limit this.
  • the binding structure can be engaged with the COF, when the binding structure is bound to the COF, the position of the binding area in the display substrate receives uniform force, which reduces The stress at this position is reduced, thereby reducing the risk of lead breakage at this position in the display substrate.
  • the above-mentioned display device may have multiple achievable manners, and the display device will be explained by taking one of the achievable manners as an example.
  • FIG. 5 is a schematic structural diagram of another display device provided by an embodiment of the application.
  • the binding structure 11 in the display device includes: a plurality of binding pattern layers sequentially superimposed on a base substrate 10 111, and a first insulating layer 112 located between every two adjacent binding pattern layers 111. Adjacent binding pattern layers 111 are insulated by the first insulating layer 112 therebetween.
  • the COF 12 includes a plurality of chip-on-chip thin film layers 121 stacked in sequence, and a second insulating layer 122 located between every two adjacent chip-on-chip thin film layers 121. Adjacent chip on film layers 121 are insulated by the second insulating layer 122 between them.
  • the bonding structure 11 includes two bonding pattern layers 111 (respectively 111a and 111b), a first insulating layer 112, two flip-chip film layers 121 (respectively 121a and 121b), and a second insulating layer. Take layer 122 as an example.
  • the number of binding pattern layers 111 can also be greater than 2
  • the number of first insulating layers 112 can also be greater than 1
  • the number of flip-chip film layers 121 can also be greater than 2
  • the number of second insulating layers 122 It can also be greater than 1, which is not limited in the embodiment of the present application.
  • the multiple bonding pattern layers 111 correspond to the multiple chip on film layers 121 one-to-one, and each bonding pattern layer 111 is bound to the corresponding chip on film layer 121 on a side away from the base substrate 10.
  • edges of the multiple binding pattern layers 111 away from the base substrate 10 are arranged in a stepped manner. Since the COF 12 is engaged with the binding structure 11, the edges of the multiple chip-on-film layers 121 in the COF that are close to the binding structure 11 are also arranged in a stepped manner.
  • the first surface A of the binding structure 11 includes: at least a partial area of the surface of each binding pattern layer 111 away from the base substrate 10
  • the second surface B in the binding structure 11 includes: at least one side surface of at least one binding pattern layer 111.
  • at least one side surface of the binding pattern layer 111 includes a side surface of at least one of the front side, the rear side, the left side, and the right side of the binding pattern layer 111.
  • the third surface of the COF 12 includes: at least a part of the surface of each chip on film layer 121 close to the bonding structure 11, in the COF 12
  • the fourth surface of includes: at least one side surface of at least one chip on film layer 121.
  • at least one side surface of the chip on film layer includes the side surface of at least one of the front side, the back side, the left side, and the right side of the chip on film layer.
  • the first surface A of the binding structure 11 includes: the upper surface of the binding pattern layer 111a, a partial area of the upper surface of the first insulating layer 112, and the binding pattern layer Part of the upper surface of 111b.
  • the third surface of the COF 12 includes: the lower surface of the chip on film layer 121a, a partial area of the lower surface of the second insulating layer 122, and a portion of the lower surface of the chip on film layer 121b.
  • the upper surface of the binding pattern layer 111a is in contact with a part of the lower surface of the chip on film layer 121b; a part of the upper surface of the first insulating layer 112 is in contact with the second insulating layer A partial area of the lower surface of 122 is in contact; a partial area of the upper surface of the binding pattern layer 111b is in contact with the lower surface of the chip on film layer 121a.
  • the second surface B of the binding structure 11 includes: the right side of the binding pattern layer 111 a and the right side of the first insulating layer 112.
  • the fourth surface of the COF includes: the left side of the chip on film layer 121a and the left side of the second insulating layer 122.
  • the binding structure 11 further includes other side surfaces except the right side surface of the binding pattern layer 111 a and the right side surface of the first insulating layer 112.
  • the contact mode of the other side surface and the COF can refer to the right side surface of the binding pattern layer 111a and the left side surface of the second insulating layer 122 in FIG. The method of contact is not described in detail in the embodiment of the present application.
  • the film layer in the display device may include two oppositely arranged surfaces, and a plurality of side surfaces for connecting the two surfaces, and the area of the side surface is smaller than The area of each of these two surfaces.
  • the binding structure includes a plurality of binding pattern layers, since these binding pattern layers are arranged one after another, some regions of the binding pattern layers that are close to the base substrate can be moved away from the substrate. The binding pattern layer of the substrate is covered. In this way, the bonding pattern layer close to the base substrate is less likely to be broken during the bonding process, thereby improving the bonding yield.
  • the edges of the multiple binding pattern layers 111 away from the base substrate 10 are arranged in a stepped manner, and there may be multiple implementation manners.
  • the i-th binding pattern layer 111 arranged in a direction away from the base substrate 10 protrudes from the (i+1)th binding pattern layer 111, i ⁇ 1.
  • the (i+1)th chip on film layer 121 sequentially arranged along the first direction protrudes from the i th chip on film layer 121.
  • the first direction is a direction away from the base substrate 10, and can be understood as a direction away from the side of the COF 12 used for binding with the binding structure 11.
  • edges of the multiple binding pattern layers 111 away from the base substrate 10 may be arranged in a stepped manner, and other implementation manners may also be implemented, which is not limited in the embodiment of the present application.
  • the i-th binding pattern layer 111 is flush with the (i+1)th binding pattern layer 111, and the i-th binding pattern layer 111 protrudes from the i+2th binding pattern layer 111.
  • the relationship between the orthographic projections of the adjacent binding pattern layers 111 on the base substrate among the plurality of binding pattern layers 111 is not limited in the embodiment of the present application.
  • the orthographic projection of the i+1-th binding pattern layer 111 on the base substrate 10 is the first orthographic projection
  • the orthographic projection of the i-th binding pattern layer 111 on the base substrate 10 is The projection is the second orthographic projection.
  • the first orthographic projection is located in the second orthographic projection, and the area of the first orthographic projection is smaller than the area of the second orthographic projection.
  • the orthographic projection of the i-th chip on film layer 121 on the reference plane is the third orthographic projection
  • the orthographic projection of the i+1th chip on film layer 121 on the reference plane is the fourth orthographic projection.
  • the third orthographic projection is located in the fourth orthographic projection, and the area of the third orthographic projection is smaller than the area of the fourth orthographic projection.
  • the above-mentioned reference plane is parallel to the chip-on-film layer 121.
  • the reference plane may be the surface of the base substrate 10 on which the binding structure 11 is formed.
  • the relationship between the first orthographic projection and the second orthographic projection may not be the relationship shown in FIG. 5, and the relationship between the third orthographic projection and the fourth orthographic projection may not be the relationship shown in FIG. 5.
  • the multiple binding pattern layers include: a first binding pattern layer 111D and at least one second binding pattern layer 111F.
  • the at least one second binding pattern layer 111F is located between the base substrate 10 and the first binding pattern layer 111D.
  • the second binding pattern layer 111F includes a first sub-pattern F1 and a second sub-pattern F2 spaced apart, Both the first sub-pattern F1 and the second sub-pattern F2 are bound to the flip chip layer corresponding to the second bound pattern layer 111F.
  • the plurality of chip-on-chip film layers include: a first chip-on-chip film layer 121D and a plurality of second chip-on-chip film layers 121F.
  • the plurality of second chip-on-chip film layers 121F are located between the first chip-on-chip film layer 121D and the binding structure.
  • the second chip-on-chip film layer 121F includes a third sub-pattern F3 and a fourth sub-pattern F4 spaced apart from each other.
  • the three sub-patterns F3 and the fourth sub-pattern F4 are both bound to the bonding pattern layer corresponding to the second chip on film layer 121F.
  • the i+1-th chip-on-chip film layer 121 and the i+1-th chip-on-chip film layer 121 away from the bonding structure in the direction away from the base substrate 10, the i+1-th chip-on-chip film layer protrudes from the i-th
  • One side of the third sub-pattern F3 in each chip-on-chip film layer is close to the fourth sub-pattern F4
  • the (i+1)th chip-on-chip film layer 121 also protrudes from the fourth sub-pattern F4 in the i-th chip-on-film layer and is close to the fourth sub-pattern F4.
  • the device includes a first bonding pattern layer 111D, a first insulating layer 112, a second bonding pattern layer 111F, a first flip chip layer 121D, a second insulating layer 122 and a first Take the double-chip thin film layer 121F as an example.
  • the number of the second binding pattern layer 111F can also be greater than 1
  • the number of the first insulating layer 112 can also be greater than 1
  • the number of the second binding pattern layer 121F can also be greater than 1.
  • the number of 112 may also be greater than 1, which is not limited in the embodiment of the present application.
  • binding the first sub-pattern F1 and the second sub-pattern F2 in the first binding pattern layer to the COF can effectively increase the binding positions in the binding structure and improve The binding scale of the binding structure.
  • the i-th binding pattern layer 121 protrudes from the (i+1)th binding pattern layer 121, then for the i-th binding pattern layer 111 and the i-th binding pattern layer 111 and The first insulating layer 112 between i+1 binding pattern layers 111: on at least one side of the i-th binding pattern layer 111 (such as each side of the i-th binding pattern layer 111), the i-th One binding pattern layer 111 protrudes from the first insulating layer 112, and the first insulating layer 112 protrudes from the i+1 th binding pattern layer 111.
  • the first surface A of the binding structure 11 further includes: at least a partial area of the first insulating layer 112 away from the surface of the base substrate 10, and the second surface B in the binding structure 11 further includes: At least one side surface of the insulating layer 112.
  • the second insulating layer 122 between the i-th flip-chip film layer 121 and the (i+1)th chip-on-chip film layer 121 in the direction away from the base substrate On at least one side of the i-th flip-chip film layer 121, the i+1-th flip-chip film layer 121 protrudes from the second insulating layer 122, and the second insulating layer 122 protrudes from the i-th flip chip ⁇ 121 ⁇ Film layer 121.
  • At least one side of the i-th chip on film layer 121 may be: at least one of the front side, the back side, the left side, and the right side of the i-th chip on film layer 121.
  • the first insulating layer 112 may also be flush with the i-th binding pattern layer 111 (or the i+1-th binding pattern layer);
  • the second insulating layer 122 may also be flush with the i+1-th chip-on-chip film layer 121 (or the i-th chip-on-chip film layer). The embodiment of the application does not limit this.
  • the first insulating layer 112 between the i-th binding pattern layer 111 and the i+1-th binding pattern layer 111 when on at least one side of the i-th binding pattern layer 111, the When the first insulating layer 112 protrudes from the i+1th binding pattern layer 111, on each side of the at least one side, the first insulating layer 112 protrudes by the length of the i+1 th binding pattern layer 111 d1 (as shown in Figure 5 or Figure 6) is less than or equal to 60 microns.
  • the length d1 may be greater than or equal to 20 microns and less than or equal to 40 microns.
  • the second insulating layer 122 between the i-th flip-chip film layer 121 and the i+1-th chip-on-chip film layer 121 in the direction away from the base substrate 10 :
  • the second insulating layer 122 protrudes from the i-th flip-chip film layer 121, on each of the at least one side, the second insulating layer 122
  • the length d2 of the layer 122 protruding from the i-th chip on film layer 121 is less than or equal to 60 microns.
  • the length can be greater than or equal to 20 microns and less than or equal to 40 microns.
  • the length d1 of the first insulating layer 112 protruding from the i+1th binding pattern layer 111 is relatively small, therefore, the i-th binding pattern layer 111 protruding from the i+1th binding pattern layer 111 The length is also smaller. Therefore, the edges of the adjacent binding pattern layers 111 are closer together, the entire binding structure 11 occupies a smaller area on the base substrate, and the frame of the entire display device is narrow.
  • the bonding pattern layer 111 includes at least one first pin
  • the flip chip film layer 121 includes at least one first pin. Two pins.
  • the first pins in the bonding pattern layer 111 correspond to the second pins in the corresponding flip-chip film layer 121 one-to-one, and the side of each first pin away from the base substrate 10 corresponds to the second pin. Pin binding.
  • FIG. 7 is a top view of a structure other than the COF in FIG. 5 provided by an embodiment of the application, and FIG. 5 shows the structure of the section HH' in FIG. 7.
  • each bonding pattern layer 111 includes a plurality of first pins J1.
  • the first binding pattern layer 111 of the two binding pattern layers 111 close to the base substrate 10 protrudes from the second binding pattern layer 111
  • the second binding pattern layer 111 of the first binding pattern layer 111 A pin J1 protrudes from the first pin J1 in the second bonding pattern layer 111.
  • these first pins J1 can all be bound to the corresponding second pins in the COF.
  • each flip chip film layer includes a plurality of second pins, and since the second flip chip film layer far from the base substrate of the two flip chip film layers protrudes from the first flip chip film layer Therefore, the second pin in the second chip on film layer protrudes from the second pin in the first chip on film layer.
  • FIG. 8 is a top view of a structure other than COF in FIG. 6 provided by an embodiment of the application, and FIG. 6 shows the structure of section II' in FIG. 8.
  • the first bonding pattern layer 111D includes a plurality of first pins J1
  • the first sub-pattern F1 and the second sub-pattern F2 in the second bonding pattern layer 111F both include a plurality of first pins. Pin J1.
  • both the first sub-pattern F1 and the second sub-pattern F2 protrude from the first binding pattern layer 111D
  • the first pin J1 in the first sub-pattern F1 and the second sub-pattern F2 protrudes from the first binding pattern layer 111D.
  • a first pin J1 in the pattern layer 111D is bound, so that when the COF is bound to the binding structure, these first pins J1 can be bound to the corresponding second pins in the COF.
  • the first chip-on-chip film layer includes a plurality of second pins
  • the third sub-pattern and the fourth sub-pattern in the second chip-on-chip film layer each include a plurality of second pins.
  • the second pin in the first chip on film layer protrudes from the third sub-pattern and the fourth sub-pattern. The second pin.
  • the width of the first pins in the binding structure 11 is larger. , Resulting in a larger width of the binding area and a wider frame of the entire display device.
  • the first pins are not arranged in the manner shown in FIG. 2. Therefore, the display device provided by the embodiment of the present application can achieve the effect of a narrow frame.
  • the display device further includes: a plurality of leads located on the base substrate.
  • these leads may include: at least one of leads such as data lines and gate lines.
  • the first pin in the binding structure corresponds to a plurality of leads one to one, and the first pin in the binding pattern layer is connected to the lead corresponding to the first pin.
  • the first pin and the corresponding lead in the display device may be located on the same layer or on different layers, which is not limited in the embodiment of the present application.
  • each first pin J1 and the corresponding lead Y are located on the same layer.
  • the first pin J1 in the first sub-pattern F1 and the corresponding lead Y are located on the same layer, the first pin J1 in the second sub-pattern F2, and the first binding
  • the first pins J1 in the patterned layer 111D are all located in different layers from the corresponding lead Y.
  • the first pin J1 and the corresponding lead Y in the same layer can be directly connected.
  • the first pin J1 in FIGS. 5 and 7 is directly connected to the corresponding lead Y
  • the first pin J1 in the first sub-pattern F1 in FIGS. 6 and 8 is directly connected to the corresponding lead Y.
  • the first pin J1 and the corresponding lead Y located in the same layer may also be connected by a connecting structure.
  • the first pin J1 and the corresponding lead Y may be connected by a connecting structure.
  • the first pin J1 in the second sub-pattern F2 in FIG. 6 and FIG. 8 and the corresponding lead Y are connected by a connection structure, and the first pin J1 in the first bonding pattern layer 111D is also connected to the corresponding lead Y. Connect by connecting structure.
  • connection structure At least part of the first pins in the display device are connected to the corresponding leads through the connection structure.
  • connection structure may include: at least one connection unit superimposed between the base substrate and the binding structure, and each connection unit includes: a connection pattern layer and a connection insulation layer sequentially superimposed in a direction away from the base substrate, each Each connection unit corresponds to at least one first pin.
  • the connection structure includes two connection units (including two connection pattern layers Z1 and two connection insulation layers Z2).
  • the first pin J1 in the second sub-pattern F2 and the corresponding lead Y are connected through the first connection pattern layer Z1 close to the base substrate 10, and the first pin J1 in the first bonding pattern layer 111D is connected to the corresponding lead Y.
  • the lead Y is connected through the second connection pattern layer Z1 close to the base substrate 10.
  • connection structure in the embodiment of the present application is located between the base substrate and the binding structure, the connection structure can be hidden under the binding structure. Therefore, the stability of the connection structure is strong, and the connection pattern layer in the connection structure is broken. The probability is low.
  • multiple leads in the display device may be located on the same layer or on different layers.
  • multiple leads are located on different layers as an example.
  • the leads located in different layers can be insulated by the lead insulating layer T.
  • the display device provided in the embodiment of the present application further includes: FPC 13, COF 12 is bound to FPC 13, and COF 12 is bound to the binding structure 11 on the side away from FPC 13.
  • the display device in the embodiment of the present application may be a flexible display device (which can be folded and bent), and the material of the base substrate includes: a flexible material.
  • the material of the insulating layer (such as the first insulating layer, the second insulating layer, the lead insulating layer, the connecting insulating layer, etc.) in the embodiments of the present application may include: SiNx (silicon nitride), PI (polyimide) or other insulating materials. Material.
  • the display devices provided by the embodiments of the application may be: organic light emitting diode display devices, liquid crystal display devices, micro light emitting diode display devices, display panels, electronic paper, mobile phones, tablet computers, televisions, notebook computers, digital photo frames, navigators, etc. Any product or component with display function.
  • the binding structure can be engaged with the COF, when the binding structure is bound to the COF, the position of the binding area in the display substrate receives uniform force, which reduces The stress at this position is reduced, thereby reducing the risk of lead breakage at this position in the display substrate.
  • the arrangement width of the first pins in each binding pattern layer in the binding structure is smaller, and the width of the entire binding structure is smaller than the arrangement width. small.
  • the embodiments of the present application also provide a display substrate, and the display substrate may be a display substrate in any display device provided in the embodiments of the present application.
  • the display substrate may be the display substrate in the display device shown in any one of FIG. 4, FIG. 5, FIG. 6, FIG. 7 and FIG. 8.
  • the display substrate may include: a base substrate 10 and a binding structure 11.
  • the binding structure 11 is located on the base substrate 10. Wherein, the side of the binding structure 11 away from the base substrate 10 is used for binding with the COF, and the side of the binding structure 11 away from the base substrate 10 can be mutually engaged with the COF; the binding structure 11 has a distance away from the base substrate 10 of the first surface A and the second surface B, there is an angle between the first surface A and the second surface B, and when the binding structure 11 is bound to the COF, both the first surface A and the second surface B are used to COF contact.
  • the binding structure includes: a plurality of binding pattern layers sequentially superimposed on the base substrate, and a first insulating layer located between every two adjacent binding pattern layers;
  • the COF includes: a plurality of chip-on-chip film layers sequentially superimposed on the FPC, and a second insulating layer located between every two adjacent chip-on-chip film layers;
  • the multiple bonding pattern layers correspond to the multiple chip-on-chip film layers one-to-one, and the side of each bonding pattern layer away from the base substrate is used for bonding with the corresponding chip-on-chip film layer;
  • the edges of the plurality of binding pattern layers away from the base substrate are arranged in a stepped manner, the first surface includes: at least a part of the surface of the binding pattern layer away from the base substrate, and the second surface includes: at least one binding At least one side surface of the patterned layer.
  • the i-th binding pattern layer arranged in a direction away from the base substrate protrudes from the (i+1)th binding pattern layer, i ⁇ 1.
  • the first orthographic projection is located in the second orthographic projection, and the area of the first orthographic projection is smaller than the area of the second orthographic projection;
  • the first orthographic projection is the orthographic projection of the i+1th binding pattern layer on the base substrate
  • the second orthographic projection is the i-th bound pattern layer on the base substrate Orthographic projection on.
  • the multiple binding pattern layers include: a first binding pattern layer and at least one second binding pattern layer;
  • At least one second binding pattern layer is located between the base substrate and the first binding pattern layer, and the second binding pattern layer includes: a first sub-pattern and a second sub-pattern spaced apart, the first sub-pattern and the second sub-pattern The sub-patterns are all used to bind the chip-on-chip film layer corresponding to the second binding pattern layer;
  • the i-th binding pattern layer protrudes from the first insulating layer, and the first insulating layer protrudes from the i+1-th binding pattern layer.
  • the length of the first insulating layer protruding from the (i+1)-th binding pattern layer is less than or equal to 60 microns.
  • the length is greater than or equal to 20 microns and less than or equal to 40 microns.
  • the bonding pattern layer includes at least one first pin, and the flip chip layer includes at least one second pin;
  • the first pins in the binding pattern layer correspond to the second pins in the corresponding chip-on-film layer one-to-one, and each first pin is used for binding with a corresponding second pin;
  • the display substrate further includes a plurality of leads located on the base substrate, the first pins in the binding structure correspond to the plurality of leads in a one-to-one correspondence, and the first pins are connected to the corresponding leads.
  • the display substrate further includes a connection structure on the base substrate, and at least part of the first pins are connected to corresponding leads through the connection structure.
  • the material of the base substrate includes: a flexible material.
  • the embodiments of the present application also provide a COF
  • the COF may be the COF in any display device provided in the embodiments of the present application.
  • the COF may be the COF in the display device shown in any one of FIG. 4, FIG. 5, FIG. 6, FIG. 7 and FIG. 8.
  • the COF is used to bind to the side of the binding structure far away from the base substrate, and the COF can be engaged with the side of the binding structure far away from the base substrate;
  • the COF has a third surface and a fourth surface. There is an angle between the surface and the fourth surface, and when the binding structure is bound to the COF, both the third surface and the fourth surface are used to contact the binding structure.
  • the binding structure includes: a plurality of binding pattern layers sequentially superimposed on the base substrate, and a first insulating layer located between every two adjacent binding pattern layers;
  • the COF includes: a plurality of chip-on-chip film layers stacked in sequence, and a second insulating layer located between every two adjacent chip-on-chip film layers;
  • the plurality of binding pattern layers correspond to the plurality of chip-on-chip film layers one-to-one, and each chip-on-chip film layer is used for binding to a side of the corresponding binding pattern layer away from the base substrate;
  • the edges of the side of the multiple chip-on-film layers used for binding with the binding structure are arranged in a stepped manner, and the third surface includes: at least part of the side of the chip-on-film layer used for binding with the binding structure Area, the fourth surface includes: at least one side surface of at least one chip-on-film layer.
  • the i-th chip-on-chip film layer arranged along the first direction protrudes from the i+1-th chip-on-chip film layer, i ⁇ 1, and the first direction is away from The COF is used for the direction of the side bound to the binding structure.
  • the third orthographic projection is located in the fourth orthographic projection, and the area of the third orthographic projection is smaller than the area of the fourth orthographic projection;
  • the third orthographic projection is the orthographic projection of the i-th binding pattern layer on a reference plane
  • the fourth orthographic projection is the orthographic projection of the i+1th binding pattern layer on the reference plane.
  • the reference plane is parallel to the flip chip film layer.
  • the plurality of chip-on-chip film layers include: a first chip-on-chip film layer and at least one second chip-on-chip film layer;
  • At least one second chip-on-chip film layer is located on the side of the first chip-on-chip film layer for binding with the binding structure.
  • the second chip-on-chip film layer includes: a third sub-pattern and a fourth sub-pattern spaced apart from each other; Both the sub-pattern and the fourth sub-pattern are bound to the binding pattern layer corresponding to the second chip on film layer;
  • the i+1th chip-on-chip film layer protrudes from the side of the third sub-pattern in the i-th chip-on-film layer close to the fourth sub-pattern, and the i+1th chip-on-chip film layer protrudes from the i-th sub-pattern.
  • the fourth sub-pattern in the crystalline thin film layer is away from a side of the third sub-pattern.
  • the (i+1)th chip-on-chip film layer protrudes from the second insulating layer, and the second insulating layer protrudes from the i-th chip-on-chip film layer.
  • the length of the second insulating layer protruding from the i-th flip chip layer is less than or equal to 60 microns.
  • the length is greater than or equal to 20 microns and less than or equal to 40 microns.
  • the bonding pattern layer includes at least one first pin
  • the chip-on-chip film layer includes at least one second pin; the first pin in the bonding pattern layer and the corresponding second pin in the chip-on-film layer
  • the pins have a one-to-one correspondence, and each second pin is used for binding with the corresponding first pin on the side away from the base substrate.
  • the COF is also used for binding with the FPC, and the COF is bound with the binding structure on the side away from the FPC.
  • the embodiment of the application provides a method for manufacturing a display device, and the method can be used to manufacture any display device provided in the embodiment of the application (the display device shown in any one of FIGS. 4 to 8).
  • FIG. 9 is a flowchart of a method for manufacturing a display device provided by an embodiment of the application. As shown in FIG. 9, the method may include:
  • step 901 a base substrate and COF are provided.
  • step 902 a binding structure is formed on the base substrate.
  • step 903 the COF is bound to the side of the binding structure away from the base substrate; wherein the COF and the binding structure are engaged with the side away from the base substrate; when the COF is bound to the binding structure, the COF Both the first surface and the second surface on the side of the binding structure away from the base substrate are in contact, the first surface is parallel to the base substrate, and an angle exists between the second surface and the first surface.
  • the binding structure can be engaged with the COF.
  • the position of the binding area in the display substrate is stressed. Uniformity reduces the stress at this position, thereby reducing the risk of wire breakage at this position in the display substrate.
  • FIG. 10 is a flowchart of another method for manufacturing a display device according to an embodiment of the present application.
  • manufacturing the display device shown in FIG. 5 and FIG. 7 is taken as an example.
  • the method may include:
  • step 1001 a base substrate, COF and FPC are provided.
  • the material of the base substrate includes: flexible material or rigid material.
  • the COF includes: a plurality of chip-on-chip film layers stacked in sequence, and a second insulating layer located between every two adjacent chip-on-chip film layers, and the plurality of binding pattern layers correspond to the plurality of chip-on-film layers one-to-one; The edges of the binding pattern layers away from the base substrate are arranged in a stepped manner.
  • the COF may be prepared before step 1001, or it may be manufactured in step 1001, which is not limited in the embodiment of the present application.
  • the various film layers in the COF such as the flip-chip film layer and the second insulating layer, can be sequentially formed according to the structure of the COF.
  • the material layer of the film layer can be formed first, and then the material layer is processed by a patterning process to obtain the film layer.
  • a patterning process includes: photoresist coating, exposure, development, etching and photoresist stripping.
  • Using a patterning process to process the material layer includes: coating a layer of photoresist on the material layer; then using a mask to expose the photoresist so that the photoresist forms an exposed area and a non-exposed area; The development process is performed to remove the photoresist in one area of the exposed area and the non-exposed area, while the photoresist in the other area remains; then the area on the material layer that is not covered with photoresist is etched ; After the etching is completed, the photoresist on the material layer can be stripped to obtain the film layer.
  • the photoresist can be a positive photoresist or a negative photoresist. If the photoresist is a positive photoresist, after the above development process, the photoresist in the exposed area is removed, while the photoresist in the non-exposed area remains; if the photoresist is a negative photoresist, After the above development process, the photoresist in the non-exposed area is removed, while the photoresist in the exposed area remains.
  • step 1002 a bonding structure and a plurality of leads are formed on the base substrate.
  • the binding structure includes: a plurality of binding pattern layers sequentially superimposed on a base substrate, and a first insulating layer located between every two adjacent binding pattern layers, and the plurality of binding pattern layers are away from the base substrate The edge of one side is arranged in steps.
  • a plurality of bonding pattern layers superimposed in sequence and a first insulating layer located between every two adjacent bonding pattern layers may be formed on the base substrate to obtain the bonding Certain structure.
  • the side of the binding structure away from the base substrate and the COF can be engaged with each other.
  • the process of forming each film layer in the binding structure can refer to the above-mentioned process of forming each film layer in the COF, which is not described in detail in the embodiment of the present application.
  • the i-th binding pattern layer sequentially arranged in a direction away from the base substrate protrudes from the (i+1)th binding pattern layer, i ⁇ 1 .
  • the patterning process used to form the binding pattern layer can be adaptively adjusted according to the shape and structure of the binding pattern layer to be formed, so that the i-th binding pattern layer protrudes from the i+th 1 binding pattern layer.
  • the i-th binding pattern layer on at least one side of the i-th binding pattern layer, the i-th binding pattern layer.
  • the pattern layer protrudes from the first insulating layer, and the first insulating layer protrudes from the (i+1)th binding pattern layer.
  • the process of forming the first insulating layer can refer to the process of forming the binding pattern layer, which is not repeated in the embodiment of the present application.
  • the length of the first insulating layer protruding from the i+1th binding pattern layer is less than or equal to 60 microns.
  • the length is greater than or equal to 20 microns and less than or equal to 40 microns.
  • the embodiment of the present application is used to manufacture the display device shown in FIG. 5 and FIG. 7. Therefore, the first orthographic projection is located in the second orthographic projection, and the area of the first orthographic projection is smaller than that of the second orthographic projection. Projection area; the first orthographic projection is the orthographic projection of the i+1th binding pattern layer on the base substrate, and the second orthographic projection is the i-th binding pattern layer on the substrate The orthographic projection on the base substrate.
  • the multiple binding pattern layers include: a first binding pattern layer and at least one second binding pattern layer; at least one second binding pattern layer The pattern layer is located between the base substrate and the first binding pattern layer, and the second binding pattern layer includes: a first sub-pattern and a second sub-pattern spaced apart; the first sub-pattern in the i-th binding pattern layer The side away from the second sub-pattern protrudes from the i+1-th binding pattern layer, and the second sub-pattern in the i-th binding pattern layer protrudes from the i+1-th side away from the first sub-pattern Bind the pattern layer.
  • the binding pattern layer includes at least one first pin, the first pin in the binding structure corresponds to a plurality of leads one to one, and the first pin is connected to the corresponding lead.
  • the structure shown in FIG. 11 can be obtained.
  • the multiple leads in the display device may be located in the same layer or in different layers.
  • a lead insulating layer T may be formed between the leads of different layers.
  • the display device shown in FIGS. 5 and 7 takes as an example that each pin is directly connected to the corresponding lead.
  • the connection structure needs to be formed so that the at least part of the first pins are connected to the corresponding leads through the connecting structure.
  • step 1003 the COF is bound to the side of the binding structure away from the base substrate.
  • the side of each binding pattern layer away from the base substrate can be bound to the corresponding flip-chip film layer.
  • the bonding pattern layer includes at least one first pin
  • the chip-on-chip film layer includes at least one second pin
  • the first pin in the bonding pattern layer corresponds to the second pin in the corresponding chip-on-film layer.
  • the feet correspond one by one.
  • step 1004 the side of the COF away from the binding structure is bound with the FPC.
  • the side of the COF away from the FPC is bound to the binding structure.
  • the COF and the FPC may be bound first, and then the side of the COF away from the FPC is bound to the binding structure, which is not limited in the embodiment of the present application.
  • the display device as shown in FIG. 5 and FIG. 7 After binding the FPC and the binding structure to the COF, the display device as shown in FIG. 5 and FIG. 7 can be obtained.
  • the binding structure can be engaged with the COF.
  • the position of the binding area in the display substrate is stressed. Uniformity reduces the stress at this position, thereby reducing the risk of wire breakage at this position in the display substrate.
  • layer formation operations include, but are not limited to (chemical phase, physical phase) deposition film formation, (magnetron) sputtering film formation, which will not be repeated in this application.
  • FIG. 12 is a flowchart of a method for manufacturing a display substrate provided by an embodiment of the application, which is used to manufacture any display substrate provided by the embodiment of the application. As shown in Figure 12, the method may include:
  • step 1201 a base substrate is provided.
  • a binding structure is formed on the base substrate; wherein the side of the binding structure away from the base substrate is used for binding with the COF, and the side of the binding structure away from the base substrate is used for mutual interaction with the COF.
  • the binding structure has a first surface and a second surface away from the base substrate, the first surface and the second surface have an angle, and when the binding structure is bound to the COF, the first surface and the second surface are both Used for contact with COF.
  • a plurality of binding pattern layers may be sequentially superimposed on the base substrate, and a first insulating layer located between every two adjacent binding pattern layers.
  • the binding structure in the display substrate manufactured by the method provided in the embodiments of the present application can be engaged with the COF, when the binding structure is bound to the COF, the position of the binding area in the display substrate is stressed Uniformity reduces the stress at this position, thereby reducing the risk of wire breakage at this position in the display substrate.
  • FIG. 13 is a flowchart of a COF manufacturing method provided in an embodiment of the application, which is used to manufacture any COF provided in the embodiment of the application. As shown in Figure 13, the method may include:
  • a COF with a third surface and a fourth surface is manufactured, where the third surface and the fourth surface have an angle, and the COF is used to bind to the side of the binding structure away from the base substrate.
  • the structure is located on the base substrate, and the COF is used to engage with the side of the binding structure away from the base substrate.
  • both the third surface and the fourth surface are used to contact the binding structure. .
  • the various film layers in the COF can be sequentially formed according to the structure of the COF.
  • the material layer of the film layer can be formed first, and then the material layer is processed by a patterning process to obtain the film layer.
  • the COF manufactured by the method provided in the embodiments of the present application can be engaged with the binding structure, when the binding structure is bound with the COF, the force at the position of the binding area in the display substrate is uniform, and the force is reduced. The stress at this position is reduced, thereby reducing the risk of lead breakage at this position in the display substrate.
  • the manufacturing method of the display substrate provided in the embodiments of the application please refer to the steps of manufacturing the display substrate in any display device manufacturing method provided in the embodiments of the application; the manufacturing method of the COF provided in the embodiments of the application may refer to the implementation The steps of manufacturing COF in any of the display device manufacturing methods provided in the examples are not described in detail in the embodiment of the present application.
  • the method embodiments provided in the embodiments of the present application can be cross-referenced with corresponding structural embodiments (such as the embodiments of the display device, the display substrate, and the COF), which is not limited in the embodiments of the present application.
  • the order of the steps in the method embodiments provided in the embodiments of this application can be adjusted appropriately, and the steps can be increased or decreased accordingly according to the situation. Any person skilled in the art can easily think of changes within the technical scope disclosed in this application. The methods should all be covered in the scope of protection of this application, so I won’t repeat them here.

Abstract

本申请提供一种显示基板、覆晶薄膜、显示装置及其制造方法。该显示装置包括：衬底基板、绑定结构和COF；其中，绑定结构位于衬底基板上，COF与绑定结构远离衬底基板的一侧相互卡合，且COF与绑定结构远离衬底基板的一侧绑定；在COF与绑定结构绑定时，COF与绑定结构远离衬底基板的一侧的第一表面和第二表面均接触，第一表面平行于衬底基板，第二表面与第一表面存在夹角。

Description

显示基板、覆晶薄膜、显示装置及其制造方法
本申请要求于2020年04月02日提交的申请号为202010253696.4、发明名称为“显示装置及其制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种显示基板、覆晶薄膜、显示装置及其制造方法。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)显示器件，具有高对比度、高亮度、低功耗和柔性折叠化的特点，在目前的显示技术领域中得到了长足的发展。
发明内容
本申请提供了一种显示基板、覆晶薄膜、显示装置及其制造方法。
第一方面，提供了一种显示装置，包括：衬底基板；绑定结构，所述绑定结构位于所述衬底基板上；覆晶薄膜COF，所述COF与所述绑定结构远离所述衬底基板的一侧绑定；其中，所述COF与所述绑定结构远离所述衬底基板的一侧相互卡合；在所述COF与所述绑定结构绑定时，所述COF与所述绑定结构远离所述衬底基板的一侧的第一表面和第二表面均接触，所述第一表面平行于所述衬底基板，所述第二表面与所述第一表面存在夹角。
可选地，所述绑定结构包括：在所述衬底基板上依次叠加的多个绑定图案层，以及位于每相邻两个所述绑定图案层之间的第一绝缘层；
所述COF包括：依次叠加的多个覆晶薄膜层，以及位于每相邻两个所述覆晶薄膜层之间的第二绝缘层；
所述多个绑定图案层与所述多个覆晶薄膜层一一对应，每个所述绑定图案 层远离所述衬底基板的一侧与对应的所述覆晶薄膜层绑定；
所述多个绑定图案层的远离所述衬底基板的一侧的边缘呈阶梯状排布，所述第一表面包括：所述绑定图案层远离所述衬底基板的表面的至少部分区域，所述第二表面包括：至少一个所述绑定图案层的至少一个侧面。
可选地，所述多个绑定图案层中，沿远离所述衬底基板的方向依次排布的第i个绑定图案层凸出于第i+1个绑定图案层，i≥1。
可选地，第一正投影位于第二正投影内，且所述第一正投影的面积小于所述第二正投影的面积；
所述第一正投影为所述第i+1个绑定图案层在所述衬底基板上的正投影，所述第二正投影所述第i个绑定图案层在所述衬底基板上的正投影。
可选地，所述多个绑定图案层包括：第一绑定图案层和至少一个第二绑定图案层；
所述至少一个第二绑定图案层位于所述衬底基板和所述第一绑定图案层之间，所述第二绑定图案层包括：相间隔的第一子图案和第二子图案，所述第一子图案和所述第二子图案均与所述第二绑定图案层对应的覆晶薄膜层绑定；
所述第i个绑定图案层中的所述第一子图案远离所述第二子图案的一侧凸出于所述第i+1个绑定图案层，所述第i个绑定图案层中的所述第二子图案远离所述第一子图案的一侧凸出于所述第i+1个绑定图案层。
可选地，对于所述第i个绑定图案层和所述第i+1个绑定图案层之间的所述第一绝缘层：
在所述第i个绑定图案层的至少一侧，所述第i个绑定图案层凸出于所述第一绝缘层，且所述第一绝缘层凸出于所述第i+1个绑定图案层。
可选地，对于所述第i个绑定图案层和所述第i+1个绑定图案层之间的所述第一绝缘层：
在所述至少一侧的每一侧，所述第一绝缘层凸出于所述第i+1个绑定图案层的长度小于或等于60微米。
可选地，所述长度大于或等于20微米，且小于或等于40微米。
可选地，所述绑定图案层包括至少一个第一引脚，所述覆晶薄膜层包括至 少一个第二引脚；所述绑定图案层中的所述第一引脚与对应的所述覆晶薄膜层中的所述第二引脚一一对应，每个所述第一引脚远离所述衬底基板的一侧与对应的所述第二引脚绑定；
所述显示装置还包括：位于所述衬底基板上的多条引线，所述绑定结构中的所述第一引脚与所述多条引线一一对应，所述第一引脚连接对应的引线。
可选地，所述显示装置还包括：位于所述衬底基板上的连接结构，至少部分所述第一引脚通过所述连接结构连接所述第一引脚对应的引线。
可选地，所述显示装置还包括：
柔性电路板FPC，所述COF与所述FPC绑定，所述COF远离所述FPC的一侧与所述绑定结构绑定。
第二方面，提供了一种显示装置的制造方法，包括：
提供衬底基板和覆晶薄膜COF；
在所述衬底基板上形成绑定结构；
将所述COF与所述绑定结构远离所述衬底基板的一侧绑定；
其中，所述COF与所述绑定结构远离所述衬底基板的一侧相互卡合；在所述COF与所述绑定结构绑定时，所述COF与所述绑定结构远离所述衬底基板的一侧的第一表面和第二表面均接触，所述第一表面平行于所述衬底基板，所述第二表面与所述第一表面存在夹角。
可选地，在所述衬底基板上形成绑定结构，包括：在所述衬底基板上形成依次叠加的多个绑定图案层，以及位于每相邻两个所述绑定图案层之间的第一绝缘层；所述多个绑定图案层的远离所述衬底基板的一侧的边缘呈阶梯状排布；其中，所述第一表面包括：所述绑定图案层远离所述衬底基板的表面的至少部分区域，所述第二表面包括：至少一个所述绑定图案层的至少一个侧面；
所述COF包括：依次叠加的多个覆晶薄膜层，以及位于每相邻两个所述覆晶薄膜层之间的第二绝缘层，所述多个绑定图案层与所述多个覆晶薄膜层一一对应；将所述COF与所述绑定结构远离所述衬底基板的一侧绑定，包括：
将每个所述绑定图案层远离所述衬底基板的一侧与对应的所述覆晶薄膜层绑定。
可选地，所述绑定图案层包括至少一个第一引脚，所述覆晶薄膜层包括至少一个第二引脚，所述绑定图案层中的所述第一引脚与对应的所述覆晶薄膜层中的所述第二引脚一一对应；
所述将每个所述绑定图案层远离所述衬底基板的一侧与对应的所述覆晶薄膜层绑定，包括：
将每个所述第一引脚远离所述衬底基板的一侧与对应的所述第二引脚绑定；
所述方法还包括：
在所述衬底基板上形成多条引线，所述绑定结构中的所述第一引脚与所述多条引线一一对应，且所述第一引脚连接对应的引线。
可选地，所述方法还包括：
在所述衬底基板上形成连接结构；
其中，至少部分所述第一引脚通过所述连接结构连接所述第一引脚对应的引线。
可选地，所述方法还包括：
提供柔性电路板FPC；
将所述COF与所述FPC绑定，其中，所述COF远离所述FPC的一侧与所述绑定结构绑定。
可选地，所述多个绑定图案层中，沿远离所述衬底基板的方向依次排布的第i个绑定图案层凸出于第i+1个绑定图案层，i≥1。
可选地，第一正投影位于第二正投影内，且所述第一正投影的面积小于所述第二正投影的面积；
所述第一正投影为所述第i+1个绑定图案层在所述衬底基板上的正投影，所述第二正投影所述第i个绑定图案层在所述衬底基板上的正投影。
可选地，所述多个绑定图案层包括：第一绑定图案层和至少一个第二绑定图案层；
所述至少一个第二绑定图案层位于所述衬底基板和所述第一绑定图案层之间，所述第二绑定图案层包括：相间隔的第一子图案和第二子图案，所述第一 子图案和所述第二子图案均与所述第二绑定图案层对应的覆晶薄膜层绑定；
所述第i个绑定图案层中的所述第一子图案远离所述第二子图案的一侧凸出于所述第i+1个绑定图案层，所述第i个绑定图案层中的所述第二子图案远离所述第一子图案的一侧凸出于所述第i+1个绑定图案层。
可选地，对于所述第i个绑定图案层和所述第i+1个绑定图案层之间的所述第一绝缘层：
在所述第i个绑定图案层的至少一侧，所述第i个绑定图案层凸出于所述第一绝缘层，且所述第一绝缘层凸出于所述第i+1个绑定图案层。
可选地，对于所述第i个绑定图案层和所述第i+1个绑定图案层之间的所述第一绝缘层：
在所述至少一侧的每一侧，所述第一绝缘层凸出于所述第i+1个绑定图案层的长度小于或等于60微米。
可选地，所述长度大于或等于20微米，且小于或等于40微米。
可选地，所述衬底基板的材质包括：柔性材质。
第三方面，提供了一种显示基板，包括：
衬底基板；
绑定结构，所述绑定结构位于所述衬底基板上；
其中，所述绑定结构远离所述衬底基板的一侧用于与覆晶薄膜COF绑定，且所述绑定结构远离所述衬底基板的一侧用于与所述COF相互卡合；
所述绑定结构具有远离所述衬底基板的第一表面和第二表面，所述第一表面与所述第二表面存在夹角，且在所述绑定结构与所述COF绑定时，所述第一表面与所述第二表面均用于与所述COF接触。
可选地，所述绑定结构包括：在所述衬底基板上依次叠加的多个绑定图案层，以及位于每相邻两个所述绑定图案层之间的第一绝缘层；
所述COF包括：在所述FPC上依次叠加的多个覆晶薄膜层，以及位于每相邻两个所述覆晶薄膜层之间的第二绝缘层；
所述多个绑定图案层与所述多个覆晶薄膜层一一对应，每个所述绑定图案层远离所述衬底基板的一侧用于与对应的所述覆晶薄膜层绑定；
所述多个绑定图案层的远离所述衬底基板的一侧的边缘呈阶梯状排布，所述第一表面包括：所述绑定图案层远离所述衬底基板的表面的至少部分区域，所述第二表面包括：至少一个所述绑定图案层的至少一侧。
可选地，所述多个绑定图案层中，沿远离所述衬底基板的方向依次排布的第i个绑定图案层凸出于第i+1个绑定图案层，i≥1。
可选地，第一正投影位于第二正投影内，且所述第一正投影的面积小于所述第二正投影的面积；
所述第一正投影为所述第i+1个绑定图案层在所述衬底基板上的正投影，所述第二正投影所述第i个绑定图案层在所述衬底基板上的正投影。
可选地，所述多个绑定图案层包括：第一绑定图案层和至少一个第二绑定图案层；
所述至少一个第二绑定图案层位于所述衬底基板和所述第一绑定图案层之间，所述第二绑定图案层包括：相间隔的第一子图案和第二子图案，所述第一子图案和所述第二子图案均用于与所述第二绑定图案层对应的覆晶薄膜层绑定；
所述第i个绑定图案层中的所述第一子图案远离所述第二子图案的一侧凸出于所述第i+1个绑定图案层，所述第i个绑定图案层中的所述第二子图案远离所述第一子图案的一侧凸出于所述第i+1个绑定图案层。
可选地，对于所述第i个绑定图案层和所述第i+1个绑定图案层之间的所述第一绝缘层：
在所述第i个绑定图案层的至少一侧，所述第i个绑定图案层凸出于所述第一绝缘层，且所述第一绝缘层凸出于所述第i+1个绑定图案层。
可选地，对于所述第i个绑定图案层和所述第i+1个绑定图案层之间的所述第一绝缘层：
在所述至少部分方向中的每个方向上，所述第一绝缘层凸出于所述第i+1个绑定图案层的长度小于或等于60微米。
可选地，所述长度大于或等于20微米，且小于或等于40微米。
可选地，所述绑定图案层包括至少一个第一引脚，所述覆晶薄膜层包括至 少一个第二引脚；
所述绑定图案层中的所述第一引脚与对应的所述覆晶薄膜层中的所述第二引脚一一对应，每个所述第一引脚用于与对应的所述第二引脚绑定；
所述显示基板还包括：位于所述衬底基板上的多条引线，所述绑定结构中的所述第一引脚与所述多条引线一一对应，所述第一引脚连接对应的引线。
可选地，所述显示基板还包括：位于所述衬底基板上的连接结构，至少部分所述第一引脚通过所述连接结构连接对应的引线。
可选地，所述衬底基板的材质包括：柔性材质。
第四方面，提供了一种显示基板的制造方法，包括：
提供衬底基板；
在所述衬底基板上形成绑定结构；
其中，所述绑定结构远离所述衬底基板的一侧用于与覆晶薄膜COF绑定，且所述绑定结构远离所述衬底基板的一侧用于与所述COF相互卡合；
所述绑定结构具有远离所述衬底基板的第一表面和第二表面，所述第一表面与所述第二表面存在夹角，且在所述绑定结构与所述COF绑定时，所述第一表面与所述第二表面均用于与所述COF接触。
可选地，在所述衬底基板上形成绑定结构，包括：在所述衬底基板上形成依次叠加的多个绑定图案层，以及位于每相邻两个所述绑定图案层之间的第一绝缘层；所述多个绑定图案层的远离所述衬底基板的一侧的边缘呈阶梯状排布；其中，所述第一表面包括：所述绑定图案层远离所述衬底基板的表面的至少部分区域，所述第二表面包括：至少一个所述绑定图案层的至少一个侧面；
所述COF包括：依次叠加的多个覆晶薄膜层，以及位于每相邻两个所述覆晶薄膜层之间的第二绝缘层，所述多个绑定图案层与所述多个覆晶薄膜层一一对应；每个所述绑定图案层远离所述衬底基板的一侧用于与对应的所述覆晶薄膜层绑定。
可选地，所述绑定图案层包括至少一个第一引脚，所述覆晶薄膜层包括至少一个第二引脚，所述绑定图案层中的所述第一引脚与对应的所述覆晶薄膜层中的所述第二引脚一一对应；每个所述第一引脚远离所述衬底基板的一侧用于 与对应的所述第二引脚绑定；
所述方法还包括：
在所述衬底基板上形成多条引线，所述绑定结构中的所述第一引脚与所述多条引线一一对应，且所述第一引脚连接对应的引线。
可选地，所述方法还包括：
在所述衬底基板上形成连接结构；
其中，至少部分所述第一引脚通过所述连接结构连接所述第一引脚对应的引线。
可选地，所述多个绑定图案层中，沿远离所述衬底基板的方向依次排布的第i个绑定图案层凸出于第i+1个绑定图案层，i≥1。
可选地，第一正投影位于第二正投影内，且所述第一正投影的面积小于所述第二正投影的面积；
所述第一正投影为所述第i+1个绑定图案层在所述衬底基板上的正投影，所述第二正投影所述第i个绑定图案层在所述衬底基板上的正投影。
可选地，所述多个绑定图案层包括：第一绑定图案层和至少一个第二绑定图案层；
所述至少一个第二绑定图案层位于所述衬底基板和所述第一绑定图案层之间，所述第二绑定图案层包括：相间隔的第一子图案和第二子图案，所述第一子图案和所述第二子图案均与所述第二绑定图案层对应的覆晶薄膜层绑定；
所述第i个绑定图案层中的所述第一子图案远离所述第二子图案的一侧凸出于所述第i+1个绑定图案层，所述第i个绑定图案层中的所述第二子图案远离所述第一子图案的一侧凸出于所述第i+1个绑定图案层。
可选地，对于所述第i个绑定图案层和所述第i+1个绑定图案层之间的所述第一绝缘层：
在所述第i个绑定图案层的至少一侧，所述第i个绑定图案层凸出于所述第一绝缘层，且所述第一绝缘层凸出于所述第i+1个绑定图案层。
可选地，对于所述第i个绑定图案层和所述第i+1个绑定图案层之间的所述第一绝缘层：
在所述至少一侧的每一侧，所述第一绝缘层凸出于所述第i+1个绑定图案层的长度小于或等于60微米。
可选地，所述长度大于或等于20微米，且小于或等于40微米。
可选地，所述衬底基板的材质包括：柔性材质。
第五方面，提供了一种覆晶薄膜COF，所述COF具有第三表面和第四表面，所述第三表面与所述第四表面存在夹角；所述COF用于与绑定结构远离衬底基板的一侧绑定，所述绑定结构位于衬底基板上，所述COF用于与所述绑定结构远离所述衬底基板的一侧相互卡合；在所述COF与所述绑定结构绑定时，所述第三表面与所述第四表面均用于与所述绑定结构接触。
可选地，所述绑定结构包括：在所述衬底基板上依次叠加的多个绑定图案层，以及位于每相邻两个所述绑定图案层之间的第一绝缘层；
所述COF包括：依次叠加的多个覆晶薄膜层，以及位于每相邻两个所述覆晶薄膜层之间的第二绝缘层；
所述多个绑定图案层与所述多个覆晶薄膜层一一对应，每个所述覆晶薄膜层用于与对应的所述绑定图案层远离所述衬底基板的一侧绑定；
所述多个覆晶薄膜层用于与绑定结构绑定的一侧的边缘呈阶梯状排布，所述第三表面包括：所述覆晶薄膜层用于与绑定结构绑定的一侧的至少部分区域，所述第四表面包括：至少一个所述覆晶薄膜层的至少一个侧面。
可选地，所述多个覆晶薄膜层中，沿目标方向排布的第i个覆晶薄膜层凸出于第i+1个覆晶薄膜层，i≥1，所述目标方向为：远离所述COF用于与所述绑定结构绑定的一侧的方向。
可选地，第三正投影位于第四正投影内，且所述第三正投影的面积小于所述第四正投影的面积；
所述第三正投影为所述第i个绑定图案层在参考平面上的正投影，所述第四正投影所述第i+1个绑定图案层在所述参考平面上的正投影，参考平面平行于覆晶薄膜层。
可选地，所述多个覆晶薄膜层包括：第一覆晶薄膜层和至少一个第二覆晶薄膜层；
所述至少一个第二覆晶薄膜层位于所述第一覆晶薄膜层用于与绑定结构绑定的一侧，所述第二覆晶薄膜层包括：相间隔的第三子图案和第四子图案，所述第三子图案和所述第四子图案均与所述第二覆晶薄膜层对应的绑定图案层绑定；
所述第i+1个覆晶薄膜层凸出于所述第i个覆晶薄膜层中所述第三子图案靠近所述第四子图案的一侧，所述第i+1个覆晶薄膜层凸出于所述第i个覆晶薄膜层中所述第四子图案远离所述第三子图案的一侧。
可选地，对于所述第i个覆晶薄膜层和所述第i+1个覆晶薄膜层之间的所述第二绝缘层：
在所述第i个覆晶薄膜层的至少一侧，所述第i+1个覆晶薄膜层凸出于所述第二绝缘层，且所述第二绝缘层凸出于所述第i个覆晶薄膜层。
可选地，对于所述第i个覆晶薄膜层和所述第i+1个覆晶薄膜层之间的所述第二绝缘层：
在所述至少一侧的每一侧，所述第二绝缘层凸出于所述第i个覆晶薄膜层的长度小于或等于60微米。
可选地，所述长度大于或等于20微米，且小于或等于40微米。
可选地，所述绑定图案层包括至少一个第一引脚，所述覆晶薄膜层包括至少一个第二引脚；所述绑定图案层中的所述第一引脚与对应的所述覆晶薄膜层中的所述第二引脚一一对应，每个所述第二引脚用于与对应的所述第一引脚远离所述衬底基板的一侧绑定。
可选地，所述COF还用于与FPC绑定，所述COF远离所述FPC的一侧与所述绑定结构绑定。
第六方面，提供了一种覆晶薄膜COF的制造方法，包括：
制造具有第三表面和第四表面的COF，其中，所述第三表面与所述第四表面存在夹角，且所述COF用于与绑定结构远离衬底基板的一侧绑定，所述绑定结构位于衬底基板上，所述COF用于与所述绑定结构远离所述衬底基板的一侧相互卡合，在所述COF与所述绑定结构绑定时，所述第三表面与所述第四表面均用于与所述绑定结构接触。
可选地，所述绑定结构包括：在所述衬底基板上依次叠加的多个绑定图案层，以及位于每相邻两个所述绑定图案层之间的第一绝缘层；
制造具有第三表面和第四表面的COF，包括：形成依次叠加的多个覆晶薄膜层，以及位于每相邻两个所述覆晶薄膜层之间的第二绝缘层；
所述多个绑定图案层与所述多个覆晶薄膜层一一对应，每个所述覆晶薄膜层用于与对应的所述绑定图案层远离所述衬底基板的一侧绑定；
所述多个覆晶薄膜层的用于与绑定结构绑定的一侧的边缘呈阶梯状排布，所述第三表面包括：所述覆晶薄膜层的用于与绑定结构绑定的一侧的至少部分区域，所述第四表面包括：至少一个所述覆晶薄膜层的至少一个侧面。
可选地，所述多个覆晶薄膜层中，沿第一方向排布的第i个覆晶薄膜层凸出于第i+1个覆晶薄膜层，i≥1，所述第一方向为远离所述COF用于与所述绑定结构绑定的一侧的方向。
可选地，第三正投影位于第四正投影内，且所述第三正投影的面积小于所述第四正投影的面积；
所述第三正投影为所述第i个绑定图案层在参考平面上的正投影，所述第四正投影所述第i+1个绑定图案层在所述参考平面上的正投影，参考平面平行于覆晶薄膜层。
可选地，所述多个覆晶薄膜层包括：第一覆晶薄膜层和至少一个第二覆晶薄膜层；
所述至少一个第二覆晶薄膜层位于所述第一覆晶薄膜层用于与绑定结构绑定的一侧，所述第二覆晶薄膜层包括：相间隔的第三子图案和第四子图案，所述第三子图案和所述第四子图案均与所述第二覆晶薄膜层对应的绑定图案层绑定；
所述第i+1个覆晶薄膜层凸出于所述第i个覆晶薄膜层中所述第三子图案靠近所述第四子图案的一侧，所述第i+1个覆晶薄膜层凸出于所述第i个覆晶薄膜层中所述第四子图案远离所述第三子图案的一侧。
可选地，对于所述第i个覆晶薄膜层和所述第i+1个覆晶薄膜层之间的所述第二绝缘层：
在所述第i个覆晶薄膜层的至少一侧，所述第i+1个覆晶薄膜层凸出于所述第二绝缘层，且所述第二绝缘层凸出于所述第i个覆晶薄膜层。
可选地，对于所述第i个覆晶薄膜层和所述第i+1个覆晶薄膜层之间的所述第二绝缘层：
在所述至少一侧的每一侧，所述第二绝缘层凸出于所述第i个覆晶薄膜层的长度小于或等于60微米。
可选地，所述长度大于或等于20微米，且小于或等于40微米。
可选地，所述绑定图案层包括至少一个第一引脚，所述覆晶薄膜层包括至少一个第二引脚；所述绑定图案层中的所述第一引脚与对应的所述覆晶薄膜层中的所述第二引脚一一对应，每个所述第二引脚用于与对应的所述第一引脚远离所述衬底基板的一侧绑定。
可选地，所述COF还用于与FPC绑定，所述COF远离所述FPC的一侧与所述绑定结构绑定。
附图说明
图1为本申请实施例提供的一种显示装置的结构示意图；
图2为本申请实施例提供的一种图1中显示基板的局部俯视图；
图3为本申请实施例提供的另一种显示基板的局部俯视图；
图4为本申请实施例提供的另一种显示装置的结构示意图；
图5为本申请实施例提供的另一种显示装置的结构示意图；
图6为本申请实施例提供的另一种显示装置的结构示意图；
图7为本申请实施例提供的一种图5中除COF之外的结构的俯视图；
图8为本申请实施例提供的一种图6中除COF之外的结构的俯视图；
图9为本申请实施例提供的一种显示装置的制造方法的流程图；
图10为本申请实施例提供的另一种显示装置的制造方法的流程图；
图11为本申请实施例提供的一种显示装置的局部结构示意图；
图12为本申请实施例提供的一种显示基板的制造方法的流程图；
图13为本申请实施例提供的一种COF的制造方法的流程图。
具体实施方式
为使本申请的原理、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本申请进一步详细说明。
需要说明的是，除非另外定义，本申请实施例使用的技术术语或者科学术语应当为本申请所属领域内具有一般技能的人士所理解的通常意义。本申请中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1为本申请实施例提供的一种显示装置的结构示意图，如图1所示，显示装置包括：显示基板(包括：衬底基板011和绑定结构012)、覆晶薄膜(Chip On Film，COF)02和柔性线路板(FPC)03。其中，衬底基板011包括显示区Q1(图1中仅示出了部分显示区)，以及位于显示区Q1一侧的绑定区Q2，该绑定结构012位于绑定区Q2。COF 02与绑定结构012远离衬底基板011的一侧绑定，COF 02还与FPC 03绑定。
图2为本申请实施例提供的一种图1中显示基板的局部俯视图，图1示出了图2中截面GG’的结构。结合图1和图2可知，显示基板还包括：位于衬底基板011上的多条引线013，引线013从衬底基板011的显示区Q1延伸至绑定区Q2。绑定结构012包括与该多条引线013一一对应的多个第一引脚0121，每条引线013与对应的第一引脚0121连接。这样一来，引线013便可以通过绑定结构012连接至COF 02，引线013还可以通过绑定结构012和COF 02连接至FPC 03。
随着显示装置的尺寸越来越大，显示装置中引线013越来越多，若这些引线013均延伸至绑定区Q2，则这些引线013的排布宽度较大，绑定结构012中第一引脚0121的排布宽度也较大。通常为了减小引线013和第一引脚0121的 排布宽度，如图3所示，可以将多个第一引脚0121排成两排，并且两排第一引脚0121之间存在一定的间隙。第一排第一引脚0121可以直接与对应的引线013连接，第二排第一引脚0121对应的引线013需要穿过第一排第一引脚0121并与第二排的第一引脚0121连接。
然而，无论第一引脚0121采用图2所示的排布方式排布，还是采用图3所示的排布方式排布，在绑定结构012与COF 02绑定时，绑定结构012中第一引脚0121远离衬底基板的表面(平行于衬底基板)与COF 02接触。但是，绑定结构012中远离衬底基板一侧的其他表面(如第一引脚0121的侧面，该侧面垂直于衬底基板)并未与COF 02接触。并且，由于第一引脚0121的存在，显示基板中绑定区Q2所在位置都是凹凸不平的。在将COF 02与绑定结构012绑定时，显示基板中绑定区Q2的各个位置受力不均匀，绑定区Q2所在位置会产生应力，使得位于该位置的部件损坏(如该位置的引线013发生断裂)，影响显示装置的正常使用。
本申请实施例提供了另一种显示装置，该显示装置能够降低显示基板中绑定区所在位置部件损坏的风险。
示例地，图4为本申请实施例提供的另一种显示装置的结构示意图，如图4所示，该显示装置包括：衬底基板10、绑定结构11和COF 12。绑定结构11位于衬底基板10上，COF 12与绑定结构11远离衬底基板10的一侧绑定。
其中，COF 12与绑定结构11远离衬底基板10的一侧相互卡合，在COF 12与绑定结构11绑定时，COF 12与绑定结构11远离衬底基板10的一侧的第一表面A和第二表面B均接触。其中，第一表面A平行于衬底基板10(例如，第一表面A平行于衬底基板10中设置有绑定结构11的一侧的表面)，第二表面B与第一表面A存在夹角。比如，第二表面B与第一表面A垂直或倾斜。由于COF12与绑定结构11卡合，所以，COF 12可以具有第三表面(图4中未标出)和第四表面(图4中未标出)。该第三表面和第四表面存在夹角，在COF 12与绑定结构11绑定时，该第三表面与第一表面A接触，第四表面与第二表面B接触。
需要说明的是，在绑定结构与COF相互卡合时，绑定结构远离衬底基板的一侧与COF中靠近绑定结构的一侧相互接触，绑定结构远离衬底基板的一侧与 COF中靠近绑定结构的一侧之间几乎没有间隙。在绑定结构与COF相互卡合时，可以是绑定结构中的凸起与COF中的凹陷相互卡合，也可以是绑定结构中的凹陷与COF中的凸起相互卡合，本申请实施例对此不做限定。
另外，本申请实施例对绑定结构和COF中的至少一个的结构进行了改进，从而使得绑定结构与COF能够进行卡合。图4中以本申请实施例只对绑定结构的形状进行了改进为例，当然，也可以是只对COF的形状进行改进，或者，对绑定结构和COF的形状均进行改进，本申请实施例对此不作限定。
综上所述，由于本申请实施例提供的显示装置中，绑定结构能够与COF相互卡合，在绑定结构与COF绑定时，显示基板中绑定区所在位置受力均匀，减小了该位置的应力，从而降低了显示基板中该位置的引线断裂的风险。
可选地，上述显示装置可以有多种可实现方式，以下将以其中的一种可实现方式为例对该显示装置进行讲解。
图5为本申请实施例提供的另一种显示装置的结构示意图，如图5所示，该显示装置中的绑定结构11包括：在衬底基板10上依次叠加的多个绑定图案层111，以及位于每相邻两个绑定图案层111之间的第一绝缘层112。相邻的绑定图案层111通过之间的第一绝缘层112绝缘。COF 12包括：依次叠加的多个覆晶薄膜层121，以及位于每相邻两个覆晶薄膜层121之间的第二绝缘层122。相邻的覆晶薄膜层121通过两者之间的第二绝缘层122绝缘。
图5中以绑定结构11包括两个绑定图案层111(分别为111a和111b)、一个第一绝缘层112、两个覆晶薄膜层121(分别为121a和121b)和一个第二绝缘层122为例。当然，该绑定图案层111的个数也可以大于2，第一绝缘层112的个数也可以大于1，覆晶薄膜层121的个数也可以大于2，第二绝缘层122的个数也可以大于1，本申请实施例对此不作限定。
多个绑定图案层111与多个覆晶薄膜层121一一对应，每个绑定图案层111远离衬底基板10的一侧与对应的覆晶薄膜层121绑定。绑定结构11中多个绑定图案层111的远离衬底基板10的一侧的边缘呈阶梯状排布。由于COF 12与绑定结构11卡合，所以，COF中多个覆晶薄膜层121中靠近绑定结构11的一侧的边缘也呈阶梯状排布。
在绑定结构11包括绑定图案层111和第一绝缘层112的情况下，绑定结构11的第一表面A包括：每个绑定图案层111远离衬底基板10的表面的至少部分区域，绑定结构11中的第二表面B包括：至少一个绑定图案层111的至少一个侧面。对于任一绑定图案层111，该绑定图案层111的至少一个侧面包括该绑定图案层111的前侧、后侧、左侧和右侧中的至少一侧的侧面。
在COF 12包括覆晶薄膜层121和第二绝缘层122的情况下，COF 12的第三表面包括：每个覆晶薄膜层121中靠近绑定结构11的表面的至少部分区域，COF 12中的第四表面包括：至少一个覆晶薄膜层121的至少一个侧面。对于任一覆晶薄膜层，该覆晶薄膜层的至少一个侧面包括该覆晶薄膜层的前侧、后侧、左侧和右侧中的至少一侧的侧面。
以图5所示的结构为例，一方面，绑定结构11的第一表面A包括：绑定图案层111a的上表面，第一绝缘层112的上表面的部分区域，以及绑定图案层111b的上表面的部分区域。相应地，COF 12的第三表面包括：覆晶薄膜层121a的下表面，第二绝缘层122的下表面的部分区域，以及覆晶薄膜层121b的下表面的部分区域。在绑定结构11与COF 12绑定时，绑定图案层111a的上表面与覆晶薄膜层121b的下表面的部分区域接触；第一绝缘层112的上表面的部分区域与第二绝缘层122的下表面的部分区域接触；绑定图案层111b的上表面的部分区域与覆晶薄膜层121a的下表面接触。
另一方面，绑定结构11的第二表面B包括：绑定图案层111a的右侧面，以及第一绝缘层112的右侧面。相应地，COF的第四表面包括：覆晶薄膜层121a的左侧面，以及第二绝缘层122的左侧面。在绑定结构11与COF 12绑定时，绑定图案层111a的右侧面与第二绝缘层122的左侧面接触；第一绝缘层112的右侧面与覆晶薄膜层121a的左侧面接触。
绑定结构11还包括除绑定图案层111a的右侧面以及第一绝缘层112的右侧面之外的其他侧面。当绑定结构11中的第二表面B还包括该其他侧面时，该其他侧面与COF的接触方式可以参考图5中绑定图案层111a的右侧面与第二绝缘层122的左侧面的接触方式，本申请实施例在此不做赘述。
需要说明的是，显示装置中的膜层(如绑定图案层和覆晶薄膜层)可以包 括相对设置的两个表面，以及多个用于连接这两个表面的侧面，该侧面的面积小于这两个表面中每个表面的面积。
当绑定结构包括多个绑定图案层时，由于这些绑定图案层层叠排布，因此，这些绑定图案层中靠近衬底基板的一些绑定图案层中的部分区域能够被远离衬底基板的绑定图案层覆盖。这样一来，靠近衬底基板的绑定图案层较不容易在绑定工艺中发生断裂，从而提升了绑定良率。
需要说明的是，多个绑定图案层111的远离衬底基板10的一侧的边缘呈阶梯状排布可以有多种实现方式。在图5所示的实现方式中，这些绑定图案层111中，沿远离衬底基板10的方向依次排布的第i个绑定图案层111凸出于第i+1个绑定图案层111，i≥1。相应地，该多个覆晶薄膜层121中，沿第一方向依次排布的第i+1个覆晶薄膜层121凸出于第i个覆晶薄膜层121。该第一方向为远离衬底基板10的方向，可以理解为远离COF 12中用于与绑定结构11绑定的一侧的方向。
当然，多个绑定图案层111的远离衬底基板10的一侧的边缘呈阶梯状排布也可以有其他实现方式，本申请实施例对此不作限定。比如，第i个绑定图案层111与第i+1个绑定图案层111齐平，且第i个绑定图案层111凸出于第i+2个绑定图案层111。
多个绑定图案层111中相邻绑定图案层111在衬底基板上的正投影之间的关系本申请实施例不作限定。在图5所示的示例中，第i+1个绑定图案层111在衬底基板10上的正投影为第一正投影，第i个绑定图案层111在衬底基板10上的正投影为第二正投影。第一正投影位于第二正投影内，且第一正投影的面积小于第二正投影的面积。相应地，第i个覆晶薄膜层121在参考平面上的正投影为第三正投影，第i+1个覆晶薄膜层121在参考平面上的正投影为第四正投影。第三正投影位于第四正投影内，且第三正投影的面积小于第四正投影的面积。上述参考平面平行于覆晶薄膜层121，比如该参考平面可以为衬底基板10中形成有绑定结构11的表面。
可选地，该第一正投影和第二正投影的关系也可以不是图5所示的关系，第三正投影和第四正投影的关系也可以不是图5所示的关系。
比如，如图6所示，多个绑定图案层包括：第一绑定图案层111D和至少一个第二绑定图案层111F。该至少一个第二绑定图案层111F位于衬底基板10和第一绑定图案层111D之间，第二绑定图案层111F包括：相间隔的第一子图案F1和第二子图案F2，第一子图案F1和第二子图案F2均与第二绑定图案层111F对应的覆晶薄膜层绑定。第i个绑定图案层中的第一子图案F1远离第二子图案F2的一侧凸出于第i+1个绑定图案层，第i个绑定图案层中的第二子图案F2远离第一子图案F1的一侧凸出于第i+1个绑定图案层。可以看出，由于第一子图案F1与第二子图案F2有间隔，所以，第一正投影并不是位于第二正投影内，且第一正投影的面积小于第二正投影的面积。
由于COF 12与绑定结构11卡合，所以，在图6所示的示例中，多个覆晶薄膜层包括：第一覆晶薄膜层121D和多个第二覆晶薄膜层121F。该多个第二覆晶薄膜层121F位于第一覆晶薄膜层121D和绑定结构之间，第二覆晶薄膜层121F包括：相间隔的第三子图案F3和第四子图案F4，第三子图案F3和第四子图案F4均与第二覆晶薄膜层121F对应的绑定图案层绑定。对于远离绑定结构的第i个覆晶薄膜层121和第i+1个覆晶薄膜层121：在远离衬底基板10的方向上，第i+1个覆晶薄膜层凸出于第i个覆晶薄膜层中第三子图案F3靠近第四子图案F4的一侧，第i+1个覆晶薄膜层121还凸出于第i个覆晶薄膜层中第四子图案F4靠近第三子图案F3的一侧。可以看出，由于第三子图案F3与第四子图案F4有间隔，所以，第三正投影并不是位于第四正投影内，且第三正投影的面积小于第四正投影的面积。
图6中以显示装置包括一个第一绑定图案层111D、一个第一绝缘层112、一个第二绑定图案层111F、一个第一覆晶薄膜层121D、一个第二绝缘层122和一个第二覆晶薄膜层121F为例。当然，该第二绑定图案层111F的个数也可以大于1，第一绝缘层112的个数也可以大于1，第二绑定图案层121F的个数也可以大于1，第二绝缘层112的个数也可以大于1，本申请实施例对此不作限定。
从图6所示的结构可以看出，将第一绑定图案层中的第一子图案F1和第二子图案F2均与COF绑定，能够有效增多绑定结构中的绑定位置，提升绑定结构的绑定规模。
可选地，无论绑定结构采用何种实现方式，若上述第i个绑定图案层121凸出于第i+1个绑定图案层121，则对于第i个绑定图案层111和第i+1个绑定图案层111之间的第一绝缘层112：在该第i个绑定图案层111的至少一侧(如第i个绑定图案层111的每一侧)，第i个绑定图案层111凸出于该第一绝缘层112，且该第一绝缘层112凸出于第i+1个绑定图案层111。在这种情况下，绑定结构11的第一表面A还包括：第一绝缘层112远离衬底基板10的表面的至少部分区域，绑定结构11中的第二表面B还包括：第一绝缘层112的至少一个侧面。
由于COF 12与绑定结构11卡合，所以，对于在远离衬底基板的方向上的第i个覆晶薄膜层121和第i+1个覆晶薄膜层121之间的第二绝缘层122：在第i个覆晶薄膜层121的至少一侧，第i+1个覆晶薄膜层121凸出于该第二绝缘层122，且该第二绝缘层122凸出于第i个覆晶薄膜层121。第i个覆晶薄膜层121的至少一侧可以是：该第i个覆晶薄膜层121的前侧、后侧、左侧和右侧中的至少一侧。
当然，在该第i个绑定图案层111的上述至少一侧，该第一绝缘层112也可以与第i个绑定图案层111(或第i+1个绑定图案层)齐平；相应地，在该第i个覆晶薄膜层121的上述至少一侧，第二绝缘层122也可以与第i+1个覆晶薄膜层121(或第i个覆晶薄膜层)齐平，本申请实施例对此不作限定。
可选地，对于第i个绑定图案层111和第i+1个绑定图案层111之间的第一绝缘层112：当在第i个绑定图案层111的上述至少一侧，该第一绝缘层112凸出于第i+1个绑定图案层111时，在该至少一侧的每一侧，第一绝缘层112凸出于第i+1个绑定图案层111的长度d1(如图5或图6所示)小于或等于60微米。可选地，该长度d1可以大于或等于20微米，且小于或等于40微米。
由于COF 12与绑定结构11卡合，所以，对于远离衬底基板10的方向上的第i个覆晶薄膜层121和第i+1个覆晶薄膜层121之间的第二绝缘层122：当在该第i个覆晶薄膜层121的上述至少一侧，该第二绝缘层122凸出于第i个覆晶薄膜层121时，在至少一侧中的每一侧，第二绝缘层122凸出于第i个覆晶薄膜层121的长度d2(如图5或图6所示)小于或等于60微米。可选地，该长度可以大于或等于20微米，且小于或等于40微米。
可见，第一绝缘层112凸出于第i+1个绑定图案层111的长度d1较小，因此，第i个绑定图案层111凸出于第i+1个绑定图案层111的长度也较小。所以，相邻绑定图案层111的边缘相距较近，整个绑定结构11在衬底基板上所占区域较小，整个显示装置的边框较窄。
在绑定结构11包括多个绑定图案层111时，无论绑定结构11以何种方式实现，该绑定图案层111均包括至少一个第一引脚，覆晶薄膜层121包括至少一个第二引脚。并且，绑定图案层111中的第一引脚与对应的覆晶薄膜层121中的第二引脚一一对应，每个第一引脚远离衬底基板10的一侧与对应的第二引脚绑定。
示例地，图7为本申请实施例提供的一种图5中除COF之外的结构的俯视图，图5示出了图7中截面HH’的结构。请结合图5和图7，每个绑定图案层111均包括多个第一引脚J1。并且，由于两个绑定图案层111中靠近衬底基板10的第一个绑定图案层111凸出于第二个绑定图案层111，因此，第一个绑定图案层111中的第一引脚J1凸出于第二个绑定图案层111中的第一引脚J1。在COF与绑定结构绑定时，这些第一引脚J1均可以与COF中对应的第二引脚绑定。相应地，每个覆晶薄膜层均包括多个第二引脚，并且，由于两个覆晶薄膜层中远离衬底基板的第二个覆晶薄膜层凸出于第一个覆晶薄膜层，因此，第二个覆晶薄膜层中的第二引脚凸出于第一个覆晶薄膜层中的第二引脚。
又示例地，图8为本申请实施例提供的一种图6中除COF之外的结构的俯视图，图6示出了图8中截面II’的结构。请结合图6和图8，第一绑定图案层111D包括多个第一引脚J1，第二绑定图案层111F中的第一子图案F1和第二子图案F2均包括多个第一引脚J1。并且，由于第一子图案F1和第二子图案F2均凸出于第一绑定图案层111D，因此，第一子图案F1和第二子图案F2中的第一引脚J1凸出于第一绑定图案层111D中的第一引脚J1，从而在COF与绑定结构绑定时，这些第一引脚J1均可以与COF中对应的第二引脚绑定。相应地，第一覆晶薄膜层包括多个第二引脚，第二覆晶薄膜层中的第三子图案和第四子图案均包括多个第二引脚。并且，由于第一覆晶薄膜层凸出于第三子图案和第四子图案，因此，第一覆晶薄膜层中的第二引脚凸出于第三子图案和第四子图案 中的第二引脚。
需要说明的是，当绑定结构11中的第一引脚采用图2所示的排布方式排布时，在显示区到绑定区的方向上，两排第一引脚的宽度较大，导致绑定区的宽度较大，整个显示装置的边框较宽。而本申请实施例提供的显示装置中，并未采用图2所示的方式排布第一引脚，因此，本申请实施例提供的显示装置能够实现窄边框的效果。
可选地，显示装置还包括：位于衬底基板上的多条引线，例如，这些引线可以包括：数据线和栅线等引线中的至少一种引线。绑定结构中的第一引脚与多条引线一一对应，绑定图案层中的第一引脚连接该第一引脚对应的引线。
显示装置中的第一引脚与对应的引线可以位于同层，也可以位于异层，本申请实施例对此不作限定。示例地，请结合图5和图7，每个第一引脚J1与对应的引线Y位于同层。又示例地，请结合图6和图8，第一子图案F1中的第一引脚J1与对应的引线Y位于同层，第二子图案F2中的第一引脚J1，以及第一绑定图案层111D中的第一引脚J1均与对应的引线Y位于异层。
一方面，对于位于同层的第一引脚J1和对应的引线Y，该第一引脚J1和对应的引线Y可以直接连接。如图5和图7中的第一引脚J1和对应的引线Y直接连接，如图6和图8中第一子图案F1中的第一引脚J1与对应的引线Y直接连接。或者，对于位于同层的第一引脚J1和对应的引线Y，该第一引脚J1和对应的引线Y也可以通过连接结构连接。
另一方面，对于位于异层的第一引脚J1和对应的引线Y，该第一引脚J1和对应的引线Y可以通过连接结构连接。如图6和图8中第二子图案F2中的第一引脚J1和对应的引线Y通过连接结构连接，第一绑定图案层111D中的第一引脚J1均与对应的引线Y也通过连接结构连接。
可见，显示装置中的至少部分第一引脚通过该连接结构连接至对应的引线。
示例地，连接结构可以包括：在衬底基板和绑定结构之间叠加的至少一个连接单元，每个连接单元包括：沿远离衬底基板的方向依次叠加的连接图案层和连接绝缘层，每个连接单元对应至少一个第一引脚，对于需要通过连接结构连接的第一引脚和引线，该第一引脚通过对应的连接单元中的连接图案层连接 至该引线。如图6和图8所示，该连接结构包括两个连接单元(包括两个连接图案层Z1和两个连接绝缘层Z2)。第二子图案F2中的第一引脚J1和对应的引线Y通过靠近衬底基板10的第一个连接图案层Z1连接，第一绑定图案层111D中的第一引脚J1均与对应的引线Y通过靠近衬底基板10的第二个连接图案层Z1连接。
由于本申请实施例中的连接结构位于衬底基板和绑定结构之间，因此，连接结构能够隐藏在绑定结构下方，所以，连接结构的稳定性较强，连接结构中连接图案层断裂的概率较低。
可选地，显示装置中的多条引线可以位于同层，也可以位于不同层，图5和图6中均以多条引线位于不同层为例。当多条引线位于不同层时，位于不同层的引线之间可以通过引线绝缘层T绝缘。
进一步地，请继续参考图5和图6，本申请实施例提供的显示装置还包括：FPC 13，COF 12与FPC 13绑定，COF 12远离FPC 13的一侧与绑定结构11绑定。
可选地，本申请实施例中的显示装置可以是柔性显示装置(可以折叠弯曲)，衬底基板的材质包括：柔性材质。本申请实施例中绝缘层(如第一绝缘层、第二绝缘层、引线绝缘层和连接绝缘层等)的材质可以包括：SiNx(氮化硅)、PI(聚酰亚胺)或者其他绝缘材质。
本申请实施例提供的显示装置可以为：有机发光二极管显示装置、液晶显示装置、微型发光二极管显示装置、显示面板、电子纸、手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
综上所述，由于本申请实施例提供的显示装置中，绑定结构能够与COF相互卡合，在绑定结构与COF绑定时，显示基板中绑定区所在位置受力均匀，减小了该位置的应力，从而降低了显示基板中该位置的引线断裂的风险。
并且，图5和图6所示的显示装置中，绑定结构中每个绑定图案层中第一引脚的排布宽度较小，在该排布宽度上，整个绑定结构的宽度较小。
本申请实施例还提供了一种显示基板，该显示基板可以为本申请实施例提 供的任一种显示装置中的显示基板。比如，该显示基板可以为图4、图5、图6、图7和图8中任一幅图所示的显示装置中的显示基板。
示例地，如图4所示，该显示基板可以包括：衬底基板10和绑定结构11。绑定结构11位于衬底基板10上。其中，绑定结构11远离衬底基板10的一侧用于与COF绑定，且绑定结构11远离衬底基板10的一侧能够与COF相互卡合；绑定结构11具有远离衬底基板10的第一表面A和第二表面B，第一表面A与第二表面B存在夹角，且在绑定结构11与COF绑定时，第一表面A与第二表面B均用于与COF接触。
可选地，绑定结构包括：在衬底基板上依次叠加的多个绑定图案层，以及位于每相邻两个绑定图案层之间的第一绝缘层；
COF包括：在FPC上依次叠加的多个覆晶薄膜层，以及位于每相邻两个覆晶薄膜层之间的第二绝缘层；
多个绑定图案层与多个覆晶薄膜层一一对应，每个绑定图案层远离衬底基板的一侧用于与对应的覆晶薄膜层绑定；
多个绑定图案层的远离衬底基板的一侧的边缘呈阶梯状排布，第一表面包括：绑定图案层远离衬底基板的表面的至少部分区域，第二表面包括：至少一个绑定图案层的至少一个侧面。
可选地，多个绑定图案层中，沿远离衬底基板的方向排布的第i个绑定图案层凸出于第i+1个绑定图案层，i≥1。
可选地，第一正投影位于第二正投影内，且所述第一正投影的面积小于所述第二正投影的面积；
所述第一正投影为所述第i+1个绑定图案层在所述衬底基板上的正投影，所述第二正投影所述第i个绑定图案层在所述衬底基板上的正投影。
可选地，多个绑定图案层包括：第一绑定图案层和至少一个第二绑定图案层；
至少一个第二绑定图案层位于衬底基板和第一绑定图案层之间，第二绑定图案层包括：相间隔的第一子图案和第二子图案，第一子图案和第二子图案均用于与第二绑定图案层对应的覆晶薄膜层绑定；
第i个绑定图案层中的第一子图案远离第二子图案的一侧凸出于第i+1个绑定图案层，第i个绑定图案层中的第二子图案远离第一子图案的一侧凸出于第i+1个绑定图案层。
可选地，对于第i个绑定图案层和第i+1个绑定图案层之间的第一绝缘层：
在第i个绑定图案层的至少一侧，第i个绑定图案层凸出于第一绝缘层，且第一绝缘层凸出于第i+1个绑定图案层。
可选地，对于第i个绑定图案层和第i+1个绑定图案层之间的第一绝缘层：
在第i个绑定图案层的上述至少一侧中的每一侧，第一绝缘层凸出于第i+1个绑定图案层的长度小于或等于60微米。可选地，该长度大于或等于20微米，且小于或等于40微米。
可选地，绑定图案层包括至少一个第一引脚，覆晶薄膜层包括至少一个第二引脚；
绑定图案层中的第一引脚与对应的覆晶薄膜层中的第二引脚一一对应，每个第一引脚用于与对应的第二引脚绑定；
显示基板还包括：位于衬底基板上的多条引线，绑定结构中的第一引脚与多条引线一一对应，第一引脚连接对应的引线。
可选地，显示基板还包括：位于衬底基板上的连接结构，至少部分第一引脚通过连接结构连接对应的引线。
可选地，衬底基板的材质包括：柔性材质。
本申请实施例提供的显示基板的结构详见上述显示装置的实施例中显示基板的结构，本申请实施例在此不做赘述。
本申请实施例还提供了一种COF，该COF可以为本申请实施例提供的任一种显示装置中的COF。比如，该COF可以为图4、图5、图6、图7和图8中任一幅图所示的显示装置中的COF。
示例地，该COF用于与绑定结构远离衬底基板的一侧绑定，COF能够与绑定结构远离衬底基板的一侧相互卡合；COF具有第三表面和第四表面，第三表面与第四表面存在夹角，且在绑定结构与COF绑定时，第三表面与第四表面均 用于与绑定结构接触。
可选地，绑定结构包括：在衬底基板上依次叠加的多个绑定图案层，以及位于每相邻两个绑定图案层之间的第一绝缘层；
COF包括：依次叠加的多个覆晶薄膜层，以及位于每相邻两个覆晶薄膜层之间的第二绝缘层；
多个绑定图案层与多个覆晶薄膜层一一对应，每个覆晶薄膜层用于与对应的绑定图案层远离衬底基板的一侧绑定；
多个覆晶薄膜层的用于与绑定结构绑定的一侧的边缘呈阶梯状排布，第三表面包括：覆晶薄膜层的用于与绑定结构绑定的一侧的至少部分区域，第四表面包括：至少一个覆晶薄膜层的至少一个侧面。
可选地，多个覆晶薄膜层中，沿第一方向排布的第i个覆晶薄膜层凸出于第i+1个覆晶薄膜层，i≥1，所述第一方向为远离所述COF用于与所述绑定结构绑定的一侧的方向。
可选地，第三正投影位于第四正投影内，且所述第三正投影的面积小于所述第四正投影的面积；
所述第三正投影为所述第i个绑定图案层在参考平面上的正投影，所述第四正投影所述第i+1个绑定图案层在所述参考平面上的正投影，参考平面平行于覆晶薄膜层。
可选地，多个覆晶薄膜层包括：第一覆晶薄膜层和至少一个第二覆晶薄膜层；
至少一个第二覆晶薄膜层位于第一覆晶薄膜层用于与绑定结构绑定的一侧，第二覆晶薄膜层包括：相间隔的第三子图案和第四子图案，第三子图案和第四子图案均与第二覆晶薄膜层对应的绑定图案层绑定；
第i+1个覆晶薄膜层凸出于第i个覆晶薄膜层中的第三子图案靠近第四子图案的一侧，第i+1个覆晶薄膜层凸出于第i个覆晶薄膜层中的第四子图案远离第三子图案的一侧。
可选地，对于第i个覆晶薄膜层和第i+1个覆晶薄膜层之间的第二绝缘层：
在所述第i个覆晶薄膜层的至少一侧，第i+1个覆晶薄膜层凸出于第二绝缘 层，且第二绝缘层凸出于第i个覆晶薄膜层。
可选地，对于第i个覆晶薄膜层和第i+1个覆晶薄膜层之间的第二绝缘层：
在所述至少一侧中的每一侧，第二绝缘层凸出于第i个覆晶薄膜层的长度小于或等于60微米。可选地，该长度大于或等于20微米，且小于或等于40微米。
可选地，绑定图案层包括至少一个第一引脚，覆晶薄膜层包括至少一个第二引脚；绑定图案层中的第一引脚与对应的覆晶薄膜层中的第二引脚一一对应，每个第二引脚用于与对应的第一引脚远离衬底基板的一侧绑定。
可选地，COF还用于与FPC绑定，COF远离FPC的一侧与绑定结构绑定。
本申请实施例提供的COF的结构详见上述显示装置的实施例中COF的结构，本申请实施例在此不做赘述。
本申请实施例提供了一种显示装置的制造方法，该方法可以用于制造本申请实施例提供的任一种显示装置(如图4至图8任一所示的显示装置)。
示例地，图9为本申请实施例提供的一种显示装置的制造方法的流程图，如图9所示，该方法可以包括：
在步骤901中，提供衬底基板和COF。
在步骤902中，在衬底基板上形成绑定结构。
在步骤903中，将COF与绑定结构远离衬底基板的一侧绑定；其中，COF与绑定结构远离衬底基板的一侧相互卡合；在COF与绑定结构绑定时，COF与绑定结构远离衬底基板的一侧的第一表面和第二表面均接触，第一表面平行于衬底基板，第二表面与第一表面存在夹角。
综上所述，由于本申请实施例提供的方法所制造的显示装置中，绑定结构能够与COF相互卡合，在绑定结构与COF绑定时，显示基板中绑定区所在位置受力均匀，减小了该位置的应力，从而降低了显示基板中该位置的引线断裂的风险。
又示例地，图10为本申请实施例提供的另一种显示装置的制造方法的流程图，图10中以制造图5和图7所示的显示装置为例。如图10所示，该方法可以包括：
在步骤1001中，提供衬底基板、COF和FPC。
可选地，衬底基板的材质包括：柔性材质或刚性材质。
COF包括：依次叠加的多个覆晶薄膜层，以及位于每相邻两个覆晶薄膜层之间的第二绝缘层，多个绑定图案层与多个覆晶薄膜层一一对应；多个绑定图案层的远离衬底基板的一侧的边缘呈阶梯状排布。
COF可以在步骤1001之前制备好，也可以是在步骤1001中制造得到的，本申请实施例对此不作限定。在制造COF的过程中，可以根据COF的结构依次形成COF中的各个膜层，如覆晶薄膜层和第二绝缘层。
在形成COF中的每个膜层时，均可以先形成该膜层的材质层，之后采用一次构图工艺对该材质层进行处理，以得到该膜层。
其中，一次构图工艺包括：光刻胶涂覆、曝光、显影、刻蚀和光刻胶剥离。采用一次构图工艺对该材质层进行处理包括：在材质层上涂覆一层光刻胶；然后采用掩膜版对光刻胶进行曝光，使光刻胶形成曝光区和非曝光区；之后采用显影工艺进行处理，使曝光区和非曝光区中一种区域的光刻胶被去除，而另一种区域的光刻胶保留；之后对材质层上未覆盖有光刻胶的区域进行刻蚀；刻蚀完毕后剥离材质层上的光刻胶即可得到该膜层。需要说明的是，光刻胶可以为正性光刻胶或负性光刻胶。若光刻胶为正性光刻胶，则在上述显影工艺之后，曝光区的光刻胶被去除，而非曝光区的光刻胶保留；若光刻胶为负性光刻胶，则在上述显影工艺之后，非曝光区的光刻胶被去除，而曝光区的光刻胶保留。
在步骤1002中，在衬底基板上形成绑定结构和多条引线。
绑定结构包括：在衬底基板上依次叠加的多个绑定图案层，以及位于每相邻两个绑定图案层之间的第一绝缘层，多个绑定图案层的远离衬底基板的一侧的边缘呈阶梯状排布。在衬底基板上形成绑定结构时，可以在衬底基板上形成依次叠加的多个绑定图案层，以及位于每相邻两个绑定图案层之间的第一绝缘层，以得到绑定结构。绑定结构远离衬底基板的一侧与COF能够相互卡合。
形成绑定结构中各个膜层的过程可以参考上述形成COF中各个膜层的过程，本申请实施例在此不做赘述。
可选地，所述多个绑定图案层中，沿远离所述衬底基板的方向依次排布的 第i个绑定图案层凸出于第i+1个绑定图案层，i≥1。本申请实施例中，可以根据需要形成的绑定图案层的形状和结构，适应性调整形成该绑定图案层所采用的构图工艺，以使第i个绑定图案层凸出于第i+1个绑定图案层。
可选地，对于第i个绑定图案层和第i+1个绑定图案层之间的第一绝缘层：在所述第i个绑定图案层的至少一侧，第i个绑定图案层凸出于第一绝缘层，且第一绝缘层凸出于第i+1个绑定图案层。形成第一绝缘层的过程可以参考形成绑定图案层的过程，本申请实施例在此不做赘述。
可选地，对于第i个绑定图案层和第i+1个绑定图案层之间的第一绝缘层：在所述第i个绑定图案层的至少一侧中的每一侧，第一绝缘层凸出于第i+1个绑定图案层的长度小于或等于60微米。例如，该长度大于或等于20微米，且小于或等于40微米。
可选地，本申请实施例用于制造图5和图7所示的显示装置，因此，第一正投影位于第二正投影内，且所述第一正投影的面积小于所述第二正投影的面积；所述第一正投影为所述第i+1个绑定图案层在所述衬底基板上的正投影，所述第二正投影所述第i个绑定图案层在所述衬底基板上的正投影。
当本申请实施例用于制造图6和图8所示的显示装置时，多个绑定图案层包括：第一绑定图案层和至少一个第二绑定图案层；至少一个第二绑定图案层位于衬底基板和第一绑定图案层之间，第二绑定图案层包括：相间隔的第一子图案和第二子图案；第i个绑定图案层中的第一子图案远离第二子图案的一侧凸出于第i+1个绑定图案层，第i个绑定图案层中的第二子图案远离第一子图案的一侧凸出于第i+1个绑定图案层。
绑定图案层包括至少一个第一引脚，绑定结构中的第一引脚与多条引线一一对应，且第一引脚连接对应的引线。
在衬底基板上形成图5和图7所示的显示装置中的绑定结构和多条引线之后，可以得到如图11所示的结构。
显示装置中的多条引线可以位于同层，也可以位于不同层，当多条引线位于不同层时，在步骤1002中还可以在不同层的引线之间形成引线绝缘层T。
图5和图7所示的显示装置以每个引脚均与对应的引线直接连接为例，当 至少部分第一引脚通过连接结构连接第一引脚对应的引线时，在步骤1002中还需要形成该连接结构，以使该至少部分第一引脚通过该连接结构连接对应的引线。
在步骤1003中，将COF与绑定结构远离衬底基板的一侧绑定。
在将COF与绑定结构远离衬底基板的一侧绑定时，可以将每个绑定图案层远离衬底基板的一侧与对应的覆晶薄膜层绑定。
可选地，绑定图案层包括至少一个第一引脚，覆晶薄膜层包括至少一个第二引脚，绑定图案层中的第一引脚与对应的覆晶薄膜层中的第二引脚一一对应。在将每个绑定图案层远离衬底基板的一侧与对应的覆晶薄膜层绑定时，可以将每个第一引脚远离衬底基板的一侧与对应的第二引脚绑定。
在步骤1004中，将COF远离绑定结构的一侧与FPC绑定。
COF远离FPC的一侧与绑定结构绑定。
可选地，也可以是先将COF与FPC绑定，再将COF远离FPC的一侧与绑定结构绑定，本申请实施例对此不作限定。
在将FPC和绑定结构均与COF绑定后，可以得到如图5和图7所示的显示装置。
综上所述，由于本申请实施例提供的方法所制造的显示装置中，绑定结构能够与COF相互卡合，在绑定结构与COF绑定时，显示基板中绑定区所在位置受力均匀，减小了该位置的应力，从而降低了显示基板中该位置的引线断裂的风险。
需要说明的是，上述形成层的操作，包括但不仅限于(化学相、物理相)沉积成膜、(磁控)溅射成膜，本申请对此不再赘述。
图12为本申请实施例提供的一种显示基板的制造方法的流程图，用于制造本申请实施例提供的任一种显示基板。如图12所示，该方法可以包括：
在步骤1201中，提供衬底基板。
在步骤1202中，在衬底基板上形成绑定结构；其中，绑定结构远离衬底基板的一侧用于与COF绑定，且绑定结构远离衬底基板的一侧用于与COF相互卡 合；绑定结构具有远离衬底基板的第一表面和第二表面，第一表面与第二表面存在夹角，且在绑定结构与COF绑定时，第一表面与第二表面均用于与COF接触。
在形成绑定结构时，可以在衬底基板上依次叠加的多个绑定图案层，以及位于每相邻两个绑定图案层之间的第一绝缘层。
综上所述，由于本申请实施例提供的方法所制造的显示基板中的绑定结构能够与COF相互卡合，在绑定结构与COF绑定时，显示基板中绑定区所在位置受力均匀，减小了该位置的应力，从而降低了显示基板中该位置的引线断裂的风险。
图13为本申请实施例提供的一种COF的制造方法的流程图，用于制造本申请实施例提供的任一种COF。如图13所示，该方法可以包括：
在步骤1301中，制造具有第三表面和第四表面的COF，其中，第三表面与第四表面存在夹角，且COF用于与绑定结构远离衬底基板的一侧绑定，绑定结构位于衬底基板上，COF用于与绑定结构远离衬底基板的一侧相互卡合，在COF与绑定结构绑定时，第三表面与第四表面均用于与绑定结构接触。
在制造COF的过程中，可以根据COF的结构依次形成COF中的各个膜层，如覆晶薄膜层和第二绝缘层。在形成COF中的每个膜层时，均可以先形成该膜层的材质层，之后采用一次构图工艺对该材质层进行处理，以得到该膜层。
综上所述，由于本申请实施例提供的方法所制造的COF能够与绑定结构相互卡合，在绑定结构与COF绑定时，显示基板中绑定区所在位置受力均匀，减小了该位置的应力，从而降低了显示基板中该位置的引线断裂的风险。
本申请实施例提供的显示基板的制造方法，可以参考本申请实施例提供的任一种显示装置制造方法中制造显示基板的步骤；本申请实施例提供的COF的制造方法，可以参考本申请实施例提供的任一种显示装置制造方法中制造COF的步骤，本申请实施例在此不做赘述。
本申请实施例提供的方法实施例能够与相应的结构实施例(如显示装置、显示基板和COF的实施例)相互参考，本申请实施例对此不做限定。本申请实施例提供的方法实施例步骤的先后顺序能够进行适当调整，步骤也能够根据情 况进行相应增减，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化的方法，都应涵盖在本申请的保护范围之内，因此不再赘述。
需要指出的是，在附图中，为了图示的清晰可能夸大了层和区域的尺寸。而且可以理解，当元件或层被称为在另一元件或层“上”时，它可以直接在其他元件上，或者可以存在中间的层。另外，可以理解，当元件或层被称为在另一元件或层“下”时，它可以直接在其他元件下，或者可以存在一个以上的中间的层或元件。另外，还可以理解，当层或元件被称为在两层或两个元件“之间”时，它可以为两层或两个元件之间惟一的层，或还可以存在一个以上的中间层或元件。通篇相似的参考标记指示相似的元件。
所属领域的普通技术人员应当理解：以上所述仅为本申请的具体实施例而已，并不用于限制本申请，凡在本申请的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (20)

  1. 一种显示装置，包括：
    衬底基板；
    绑定结构，所述绑定结构位于所述衬底基板上；
    覆晶薄膜COF，所述COF与所述绑定结构远离所述衬底基板的一侧相互卡合，且所述COF与所述绑定结构远离所述衬底基板的一侧绑定；
    其中，在所述COF与所述绑定结构绑定时，所述COF与所述绑定结构远离所述衬底基板的一侧的第一表面和第二表面均接触，所述第一表面平行于所述衬底基板，所述第二表面与所述第一表面存在夹角。
  2. 根据权利要求1所述的显示装置，所述绑定结构包括：在所述衬底基板上依次叠加的多个绑定图案层，以及位于每相邻两个所述绑定图案层之间的第一绝缘层；
    所述COF包括：依次叠加的多个覆晶薄膜层，以及位于每相邻两个所述覆晶薄膜层之间的第二绝缘层；
    所述多个绑定图案层与所述多个覆晶薄膜层一一对应，每个所述绑定图案层远离所述衬底基板的一侧与对应的所述覆晶薄膜层绑定；
    所述多个绑定图案层的远离所述衬底基板的一侧的边缘呈阶梯状排布，所述第一表面包括：所述绑定图案层远离所述衬底基板的表面的至少部分区域，所述第二表面包括：至少一个所述绑定图案层的至少一个侧面。
  3. 根据权利要求2所述的显示装置，对于所述多个绑定图案层中，沿远离所述衬底基板的方向依次排布的第i个绑定图案层和第i+1个绑定图案层：
    所述第i个绑定图案层凸出于所述第i+1个绑定图案层，i≥1。
  4. 根据权利要求3所述的显示装置，第一正投影位于第二正投影内，且所述第一正投影的面积小于所述第二正投影的面积；
    所述第一正投影为所述第i+1个绑定图案层在所述衬底基板上的正投影，所 述第二正投影所述第i个绑定图案层在所述衬底基板上的正投影。
  5. 根据权利要求3所述的显示装置，所述多个绑定图案层包括：第一绑定图案层和至少一个第二绑定图案层；
    所述至少一个第二绑定图案层位于所述衬底基板和所述第一绑定图案层之间，所述第二绑定图案层包括：相间隔的第一子图案和第二子图案，所述第一子图案和所述第二子图案均与所述第二绑定图案层对应的覆晶薄膜层绑定；
    所述第i个绑定图案层中的所述第一子图案远离所述第二子图案的一侧凸出于所述第i+1个绑定图案层，所述第i个绑定图案层中的所述第二子图案远离所述第一子图案的一侧凸出于所述第i+1个绑定图案层。
  6. 根据权利要求3至5任一所述的显示装置，对于所述第i个绑定图案层和所述第i+1个绑定图案层之间的所述第一绝缘层：
    在所述第i个绑定图案层的至少一侧，所述第i个绑定图案层凸出于所述第一绝缘层，且所述第一绝缘层凸出于所述第i+1个绑定图案层。
  7. 根据权利要求6所述的显示装置，对于所述第i个绑定图案层和所述第i+1个绑定图案层之间的所述第一绝缘层：
    在所述至少一侧的每一侧，所述第一绝缘层凸出于所述第i+1个绑定图案层的长度小于或等于60微米。
  8. 根据权利要求7所述的显示装置，所述长度大于或等于20微米，且小于或等于40微米。
  9. 根据权利要求2至8任一所述的显示装置，所述绑定图案层包括至少一个第一引脚，所述覆晶薄膜层包括至少一个第二引脚；所述绑定图案层中的所述第一引脚与对应的所述覆晶薄膜层中的所述第二引脚一一对应，每个所述第一引脚远离所述衬底基板的一侧与对应的所述第二引脚绑定；
    所述显示装置还包括：位于所述衬底基板上的多条引线，所述绑定结构中 的所述第一引脚与所述多条引线一一对应，所述第一引脚连接对应的引线。
  10. 根据权利要求9所述的显示装置，所述显示装置还包括：位于所述衬底基板上的连接结构，至少部分所述第一引脚通过所述连接结构连接所述第一引脚对应的引线。
  11. 根据权利要求1至10任一所述的显示装置，所述显示装置还包括：
    柔性电路板FPC，所述COF与所述FPC绑定，所述COF远离所述FPC的一侧与所述绑定结构绑定。
  12. 一种显示装置的制造方法，包括：
    提供衬底基板和覆晶薄膜COF；
    在所述衬底基板上形成绑定结构；
    将所述COF与所述绑定结构远离所述衬底基板的一侧绑定；
    其中，所述COF与所述绑定结构远离所述衬底基板的一侧相互卡合；在所述COF与所述绑定结构绑定时，所述COF与所述绑定结构远离所述衬底基板的一侧的第一表面和第二表面均接触，所述第一表面平行于所述衬底基板，所述第二表面与所述第一表面存在夹角。
  13. 根据权利要求12所述的方法，在所述衬底基板上形成绑定结构，包括：
    在所述衬底基板上形成依次叠加的多个绑定图案层，以及位于每相邻两个所述绑定图案层之间的第一绝缘层；所述多个绑定图案层的远离所述衬底基板的一侧的边缘呈阶梯状排布；其中，所述第一表面包括：所述绑定图案层远离所述衬底基板的表面的至少部分区域，所述第二表面包括：至少一个所述绑定图案层的至少一个侧面；
    所述COF包括：依次叠加的多个覆晶薄膜层，以及位于每相邻两个所述覆晶薄膜层之间的第二绝缘层，所述多个绑定图案层与所述多个覆晶薄膜层一一对应；将所述COF与所述绑定结构远离所述衬底基板的一侧绑定，包括：
    将每个所述绑定图案层远离所述衬底基板的一侧与对应的所述覆晶薄膜层绑定。
  14. 根据权利要求13所述的方法，所述绑定图案层包括至少一个第一引脚，所述覆晶薄膜层包括至少一个第二引脚，所述绑定图案层中的所述第一引脚与对应的所述覆晶薄膜层中的所述第二引脚一一对应；
    所述将每个所述绑定图案层远离所述衬底基板的一侧与对应的所述覆晶薄膜层绑定，包括：
    将每个所述第一引脚远离所述衬底基板的一侧与对应的所述第二引脚绑定；
    所述方法还包括：
    在所述衬底基板上形成多条引线，所述绑定结构中的所述第一引脚与所述多条引线一一对应，且所述第一引脚连接对应的引线。
  15. 根据权利要求14所述的方法，所述方法还包括：
    在所述衬底基板上形成连接结构；
    其中，至少部分所述第一引脚通过所述连接结构连接所述第一引脚对应的引线。
  16. 根据权利要求12至15任一所述的方法，所述方法还包括：
    提供柔性电路板FPC；
    将所述COF与所述FPC绑定，其中，所述COF远离所述FPC的一侧与所述绑定结构绑定。
  17. 一种显示基板，包括：
    衬底基板；
    绑定结构，所述绑定结构位于所述衬底基板上；
    其中，所述绑定结构远离所述衬底基板的一侧用于与覆晶薄膜COF绑定， 且所述绑定结构远离所述衬底基板的一侧用于与所述COF相互卡合；
    所述绑定结构具有远离所述衬底基板的第一表面和第二表面，所述第一表面与所述第二表面存在夹角，且在所述绑定结构与所述COF绑定时，所述第一表面与所述第二表面均用于与所述COF接触。
  18. 一种显示基板的制造方法，包括：
    提供衬底基板；
    在所述衬底基板上形成绑定结构；
    其中，所述绑定结构远离所述衬底基板的一侧用于与覆晶薄膜COF绑定，且所述绑定结构远离所述衬底基板的一侧用于与所述COF相互卡合；
    所述绑定结构具有远离所述衬底基板的第一表面和第二表面，所述第一表面与所述第二表面存在夹角，且在所述绑定结构与所述COF绑定时，所述第一表面与所述第二表面均用于与所述COF接触。
  19. 一种覆晶薄膜COF，所述COF具有第三表面和第四表面，所述第三表面与所述第四表面存在夹角；所述COF用于与绑定结构远离衬底基板的一侧绑定，所述绑定结构位于衬底基板上，所述COF用于与所述绑定结构远离所述衬底基板的一侧相互卡合；在所述COF与所述绑定结构绑定时，所述第三表面与所述第四表面均用于与所述绑定结构接触。
  20. 一种覆晶薄膜COF的制造方法，包括：
    制造具有第三表面和第四表面的COF，其中，所述第三表面与所述第四表面存在夹角，且所述COF用于与绑定结构远离衬底基板的一侧绑定，所述绑定结构位于衬底基板上，所述COF用于与所述绑定结构远离所述衬底基板的一侧相互卡合，在所述COF与所述绑定结构绑定时，所述第三表面与所述第四表面均用于与所述绑定结构接触。
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