WO2019179339A1 - 阵列基板及其制造方法、显示面板、显示装置 - Google Patents

阵列基板及其制造方法、显示面板、显示装置 Download PDF

Info

Publication number
WO2019179339A1
WO2019179339A1 PCT/CN2019/077903 CN2019077903W WO2019179339A1 WO 2019179339 A1 WO2019179339 A1 WO 2019179339A1 CN 2019077903 W CN2019077903 W CN 2019077903W WO 2019179339 A1 WO2019179339 A1 WO 2019179339A1
Authority
WO
WIPO (PCT)
Prior art keywords
data line
layer
substrate
interlayer dielectric
retaining wall
Prior art date
Application number
PCT/CN2019/077903
Other languages
English (en)
French (fr)
Inventor
于亚楠
徐敬义
任艳伟
赵欣
王晓康
王跃林
张慧杰
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/621,325 priority Critical patent/US11145682B2/en
Publication of WO2019179339A1 publication Critical patent/WO2019179339A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate and a method of manufacturing the same, a display panel, and a display device.
  • narrow bezel technology has become the main development direction of existing display technologies.
  • the wiring on the array substrate is required to be finer and denser.
  • the narrow bezel product is routed in the source/drain (SD) layer, the critical size of the data line in the fanout area ( Critical Dimension (CD) and space (Space) are small, and it is prone to weak connection or even disconnection of the line. Open circuit and dark line are displayed, resulting in a certain yield loss.
  • SD source/drain
  • CD Critical Dimension
  • Space space
  • the source and drain layers are usually dry etched by a plasma etching technique, and patterned to form data line leads.
  • a plasma etching technique When the data line leads are prepared on the source and drain layers of the array substrate, the source and drain layers are usually dry etched by a plasma etching technique, and patterned to form data line leads.
  • the plasma bombards the source/drain layer of the edge region, the plasma is likely to further affect the data line to be retained near the edge region, resulting in an edge region near the edge of the array substrate.
  • the data line is too thin, and the data line is easily broken.
  • a first aspect of an embodiment of the present disclosure provides an array substrate including a display area and a peripheral area surrounding the display area,
  • peripheral region includes a data line lead region and a driving circuit region, and the data line lead region is located between the driving circuit region and the display region;
  • the driving circuit region includes a driving circuit
  • the data line lead region includes a plurality of data line leads
  • the plurality of data line leads are led out from the display region and electrically connected to the driving circuit
  • the data line lead region includes an edge data line lead, an area of the peripheral area adjacent to the edge data line lead includes at least one retaining wall, and the at least one retaining wall is for preventing plasma from affecting the edge data Wire lead.
  • the at least one retaining wall includes two retaining walls, the two retaining walls being oppositely disposed.
  • the array substrate further includes a base substrate and an interlayer dielectric layer on a side of the substrate substrate,
  • the retaining wall is in the same layer and the same material as the interlayer dielectric layer, and the height of the retaining wall perpendicular to the base substrate is greater than the height of the interlayer dielectric layer perpendicular to the base substrate.
  • the data line lead is located on a surface of the interlayer dielectric layer away from the substrate substrate, and the height of the retaining wall perpendicular to the base substrate is not less than the layer A sum of a dielectric layer and a height of the data line lead perpendicular to the base substrate.
  • the array substrate further includes a base substrate and an interlayer dielectric layer on a side of the base substrate, and a gate between the base substrate and the interlayer dielectric layer a layer, wherein the retaining wall is in the same layer and the same material as the gate layer, and a sum of a height of the interlayer dielectric layer and the retaining wall perpendicular to the substrate substrate is greater than the interlayer dielectric layer and The gate layer is perpendicular to a sum of heights of the substrate substrates.
  • the array substrate further includes a base substrate and a gate insulating layer, a gate layer, and an interlayer dielectric layer disposed in sequence away from the substrate substrate, wherein the retaining wall and the The gate insulating layer is of the same layer and of the same material, and a sum of a height of the interlayer dielectric layer, the gate layer and the barrier wall perpendicular to the substrate substrate is greater than the interlayer dielectric layer, the gate a pole layer, the gate insulating layer being perpendicular to a sum of heights of the substrate substrates.
  • the array substrate further includes a base substrate and a light shielding layer, a gate insulating layer, a gate layer, and an interlayer dielectric layer disposed in sequence away from the substrate substrate, wherein the retaining wall The same layer and the same material as the light shielding layer, and the sum of the heights of the interlayer dielectric layer, the gate layer, the gate insulating layer and the retaining wall perpendicular to the substrate substrate is greater than The interlayer dielectric layer, the gate layer, the gate insulating layer, and the light shielding layer are perpendicular to a sum of heights of the substrate substrates.
  • the array substrate further includes a blank lead located on a side of the interlayer dielectric layer away from the base substrate, and the blank lead is located in the retaining wall and the Between data line leads.
  • a spacing between the retaining wall and the blank lead is equal to a spacing between the data line leads.
  • the spacing between the retaining wall and the blank lead ranges from about 2.0 ⁇ m to 2.5 ⁇ m.
  • the retaining wall has a width ranging from about 2.5 ⁇ m to 20 ⁇ m.
  • the width of the retaining wall ranges from about 2.5 ⁇ m and the width of the data line leads is 2.5 ⁇ m.
  • an array substrate manufacturing method wherein the array substrate includes a display area and a peripheral area surrounding the display area, wherein the peripheral area includes a data line lead area and a driving circuit a region, and the data line lead region is located between the driving circuit region and the display region; wherein the driving circuit region includes a driving circuit, the data line lead region includes a plurality of data line leads, and the plurality a strip of data line leads from the display area and electrically coupled to the drive circuit; wherein the data line lead area includes an edge data line lead, and the method includes: approaching the edge data line in the peripheral area The area of the lead forms at least one retaining wall for preventing plasma from affecting the edge data line leads.
  • the step of forming at least one retaining wall in a region of the peripheral region proximate the edge data line lead includes forming a relative arrangement in a region of the peripheral region proximate the edge data line lead Two retaining walls.
  • the step of forming at least one retaining wall in a region of the peripheral region proximate the edge data line lead includes:
  • the method further includes:
  • the step of forming at least one retaining wall in the region of the peripheral region proximate the edge data line lead includes:
  • the step of forming at least one retaining wall in a region of the peripheral region proximate the edge data line lead includes:
  • the step of forming at least one retaining wall in a region of the peripheral region proximate the edge data line lead includes:
  • the light shielding film is patterned by a halftone mask to form the retaining wall and the light shielding layer.
  • a gate insulating layer, a gate layer, and an interlayer dielectric layer on the barrier wall and the light shielding layer wherein the interlayer dielectric layer, the gate layer, the gate insulating layer, and the A sum of heights of the retaining walls perpendicular to the base substrate is greater than a sum of heights of the interlayer dielectric layer, the gate layer, the gate insulating layer, and the light shielding layer perpendicular to the base substrate.
  • the method further includes forming a blank lead on a side of the interlayer dielectric layer away from the base substrate, wherein the blank lead is located between the retaining wall and the data line lead .
  • the spacing between the retaining wall and the blank lead is equal to the spacing between the data line leads.
  • the spacing between the retaining wall and the blank lead ranges from about 2.0 ⁇ m to 2.5 ⁇ m.
  • the retaining wall has a width ranging from about 2.5 ⁇ m to 20 ⁇ m.
  • the width of the retaining wall ranges from about 2.5 ⁇ m and the width of the data line leads is 2.5 ⁇ m.
  • a display panel comprising the array substrate as described above.
  • a display device comprising the array substrate as described above.
  • FIG. 1 is a schematic structural view of an embodiment of an array substrate provided by the present disclosure
  • FIG. 2 is a schematic diagram showing a region distribution of a fan-out area of an embodiment of an array substrate provided by the present disclosure
  • FIG. 3 is a schematic structural view of another embodiment of an array substrate provided by the present disclosure.
  • FIG. 4 is a schematic structural view of still another embodiment of an array substrate provided by the present disclosure.
  • FIG. 5 is a schematic structural diagram of still another embodiment of an array substrate provided by the present disclosure.
  • FIG. 6 is a schematic flow chart of one embodiment of a method for fabricating an array substrate according to the present disclosure
  • FIG. 7 is a schematic flow chart of another embodiment of a method for fabricating an array substrate according to the present disclosure.
  • FIG. 8a is a schematic structural view of an array substrate after forming an interlayer dielectric film in an embodiment of a method for fabricating an array substrate according to the present disclosure
  • FIG. 8b is a schematic structural view of an array substrate after forming an interlayer dielectric layer in an embodiment of a method for fabricating an array substrate according to the present disclosure
  • 8c is a schematic structural view of an array substrate after forming a metal material layer in an embodiment of a method for fabricating an array substrate according to the present disclosure
  • FIG. 8 is a schematic structural diagram of an array substrate when exposing a photoresist layer in an embodiment of a method for fabricating an array substrate according to the present disclosure
  • FIG. 8 e is a schematic structural view of an array substrate after developing a photoresist layer in an embodiment of a method for fabricating an array substrate according to the present disclosure
  • 8f is a schematic structural view of an array substrate after etching a metal material layer to form a data line lead in an embodiment of the method for fabricating an array substrate according to the present disclosure
  • FIG. 8g is a schematic structural diagram of an array substrate after removing a photoresist in an embodiment of a method for fabricating an array substrate according to the present disclosure
  • FIG. 8h is a schematic structural diagram of an array substrate after forming a flat layer in an embodiment of a method for fabricating an array substrate according to the present disclosure.
  • an array substrate is proposed.
  • 1 is a schematic cross-sectional view of an array substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic plan view of the array substrate.
  • the cross-sectional view of Fig. 1 is cut along line A-B of Fig. 2.
  • the array substrate includes, for example, a display area 100 and a peripheral area 200 surrounding the display area.
  • the peripheral region 200 includes a data line lead region 210 and a drive circuit region 220.
  • the data line lead region 210 is located between the driving circuit region 220 and the display region 100.
  • the drive circuit region 220 includes, for example, a drive circuit 220'.
  • the data line lead region 210 includes a plurality of data line leads 20, and these data line leads 20 are taken out from the display area 100 and electrically connected to the driving circuit 220' in the driving circuit region 220.
  • the data line lead area 210 includes edge data line leads, and the area 230 of the peripheral area 200 near the edge data line leads includes at least one retaining wall 101, and the at least one retaining wall is used to prevent plasma from affecting the edge data line leads.
  • the data line lead region 210 includes a first boundary, a second boundary, a third boundary, and a fourth boundary.
  • the first boundary is opposite the second boundary, such as the upper and lower boundaries of the data line lead region 210, respectively, in FIG.
  • the third boundary is opposite to the fourth boundary, such as the left and right boundaries of the data line lead region 210, respectively, in FIG. That is, the data line lead region 210 is adjacent to the display region 100 at the first boundary, adjacent to the drive circuit region 220 at the second boundary, and adjacent to the region 230 of the peripheral region 200 at the third and fourth boundaries. .
  • the region 230 of the peripheral region 200 near the edge data line lead refers to the region of the peripheral region 200 that is adjacent to the third and fourth boundaries of the data line lead region 210.
  • the at least one retaining wall comprises two retaining walls, the two retaining walls being oppositely disposed.
  • the two regions 230 of the peripheral region 200 near the edge data line leads each include a retaining wall 101.
  • the array substrate includes a base substrate 90 and an interlayer dielectric layer 10 on a side of the substrate substrate.
  • the retaining wall 101 is the same layer and the same material as the interlayer dielectric layer 10, and the height of the retaining wall 101 perpendicular to the base substrate 90 is greater than the height of the interlayer dielectric layer 10 perpendicular to the base substrate 90.
  • the retaining wall 101 is located in a region 230 of the peripheral region 200 adjacent the left boundary of the data line lead region 210.
  • the portion of the interlayer dielectric layer 10 that is located in the data line lead region 210 is indicated at 102.
  • the hierarchical structure shown in FIG. 1 is a hierarchical structure that the array substrate generally has, and the hierarchical structure may include a light Shield (LS) 40, a gate insulating layer (GI) 50, and a gate layer. 60, interlayer dielectric layer 10, and the like.
  • LS light Shield
  • GI gate insulating layer
  • the hierarchical structure of the array substrate is not limited to the foregoing hierarchical structure, and other layers (not shown) may be added as needed, such as a substrate substrate, an active layer, and a source/drain layer. , flattening layers, etc., or selecting any one or more of them as needed.
  • the arrangement order is not limited to the arrangement order shown in FIG. 1, and therefore the scope of protection should not be limited to the hierarchical structure actually given by the embodiment of the present disclosure.
  • the array substrate provided by the embodiment of the present disclosure is configured to set the height of the barrier wall 101 of the interlayer dielectric layer 10 in the region 230 of the data line lead region 210 to be larger than that of the interlayer dielectric layer 10.
  • the height of the portion 102 of the data line lead region 210 when a metal material layer (for preparing data line leads) continues to be formed on the interlayer dielectric layer 10, the metal material layer above the barrier wall 101 can also be formed higher.
  • the layer of metallic material above the remaining portion 102 will be correspondingly lower.
  • the barrier wall 101 of the interlayer dielectric layer 10 near the edge of the array substrate is set higher.
  • the retaining wall 101 can block the plasma from being sputtered in the horizontal direction. This horizontal sputtering causes the data line leads close to the retaining wall 101 to be too thin, thereby causing problems such as disconnection. It should be noted here that in a dry etching such as plasma etching, a plasma is ionized by a glow discharge to generate a plasma and bombard the target target, and the metal or non-metal material is separated from the target to form a desired pattern. .
  • FIG. 1 is a schematic structural view of an array substrate corresponding to a fan-out area.
  • FIG. 1 is a schematic structural view of an array substrate corresponding to a fan-out area.
  • Embodiments of the present disclosure also propose another embodiment of an array substrate that can improve product yield.
  • FIG. 3 is a schematic structural view of another embodiment of an array substrate provided by the present disclosure.
  • the data line lead 20 is located on a surface of the interlayer dielectric layer 10 away from the substrate substrate 90, and the height of the barrier wall 101 perpendicular to the base substrate is not less than the interlayer dielectric layer 10 and the data line lead 20 A sum of heights perpendicular to the substrate substrate.
  • the array substrate further includes a data line lead 20 formed on the remaining portion 102 of the interlayer dielectric layer 10, which can effectively utilize an interlayer dielectric layer (ILD) having a high edge.
  • the data line lead of the blocking protection edge of 10 does not have an overetching phenomenon, so that when the metal material layer is dry etched by plasma etching, in the process of patterning the data line lead, due to the proximity
  • the retaining wall 101 of the interlayer dielectric layer 10 at the edge of the array substrate is disposed higher.
  • the retaining wall 101 can block the plasma from being sputtered in the horizontal direction to the remaining portion 102, so that the data close to the retaining wall 101
  • the wire leads eg, the data line leads 202 are too thin, causing problems such as wire breakage.
  • the difference in thickness between the retaining wall 101 and the remaining portion 102 is greater than the thickness of the data line lead 20, so that plasma can be better prevented from being sputtered into the remaining portion 102 in the horizontal direction, thereby preventing data lines from being generated.
  • the leads are too thin.
  • the two expressions of the thickness of the retaining wall and the height of the retaining wall perpendicular to the substrate substrate are equivalent and interchangeable.
  • FIG. 4 shows still another embodiment of the array substrate, wherein the data line lead 20 includes active leads 202, 203 and blank leads 201, the blank leads 201 are located at the active leads 202 and Between the retaining walls 101, the blank lead 201 (Dummy SD) does not work, and can further block the effective leads 202 and 203 of the plasma affecting the work during dry etching.
  • the data line lead 20 includes active leads 202, 203 and blank leads 201
  • the blank leads 201 are located at the active leads 202 and Between the retaining walls 101, the blank lead 201 (Dummy SD) does not work, and can further block the effective leads 202 and 203 of the plasma affecting the work during dry etching.
  • the widths of the active leads 202, 203 and the blank leads 201 in the data line leads 20 in the fan-out region are uniform; better blocking can be achieved without increasing process complexity.
  • the hierarchical structure shown in FIG. 3 is a hierarchical structure that the array substrate generally has, and the hierarchical structure may include a light shielding layer 40, a gate insulating layer (GI) 50, a gate layer 60, and an interlayer dielectric layer 10. Wait.
  • the hierarchical structure of the array substrate is not limited to the foregoing hierarchical structure, and other layers (not shown) may be added as needed, such as a substrate substrate, an active layer, and a source/drain layer. , flattening layers, etc., or selecting any one or more of them as needed.
  • the arrangement order is not limited to the arrangement order shown in FIG. 3, and therefore the scope of protection should not be limited to the hierarchical structure actually given by the embodiment of the present disclosure.
  • the array substrate includes a base substrate 90 and an interlayer dielectric layer 10 on a side of the base substrate 90, and a gate between the base substrate 90 and the interlayer dielectric layer 10.
  • Polar layer 60 The retaining wall 101 is the same layer and the same material as the gate layer 60, and the sum of the heights of the interlayer dielectric layer 10 and the retaining wall 101 perpendicular to the substrate substrate is greater than the interlayer dielectric layer 10 and the gate layer 60 perpendicular to the substrate. The sum of heights.
  • the array substrate includes a base substrate 90 and a gate insulating layer 50, a gate layer 60, and an interlayer dielectric layer 10 disposed in sequence away from the substrate substrate 90 side.
  • the retaining wall 101 is in the same layer and the same material as the gate insulating layer 50.
  • the sum of the heights of the interlayer dielectric layer 10, the gate layer 60, and the barrier wall 101 perpendicular to the substrate substrate is greater than the sum of the heights of the interlayer dielectric layer 10, the gate layer 60, and the gate insulating layer 50 perpendicular to the substrate substrate.
  • the array substrate includes a base substrate 90 and a light shielding layer 40, a gate insulating layer 50, a gate layer 60, and an interlayer dielectric layer 10 disposed in sequence away from the substrate substrate.
  • the retaining wall 101 is in the same layer and the same material as the light shielding layer 40.
  • the sum of the heights of the interlayer dielectric layer 10, the gate layer 60, the gate insulating layer 50, and the barrier wall 40 perpendicular to the substrate substrate is greater than the interlayer dielectric layer 10, the gate layer 60, the gate insulating layer 50, and the light shielding layer 40.
  • the array substrate provided by the embodiment of the present disclosure continues to form a metal on the interlayer dielectric layer 10 by setting the thickness of the barrier wall 101 of the interlayer dielectric layer 10 to be larger than the thickness of the remaining portion 102.
  • the material layer used to prepare the data line leads
  • the layer of metallic material above the retaining wall 101 can also be formed higher, and the layer of metallic material above the remaining portion 102 will be correspondingly lower.
  • the metal material layer is dry etched by plasma etching, in the process of patterning the data line leads, the barrier wall 101 of the interlayer dielectric layer 10 near the edge of the array substrate is set higher.
  • the retaining wall 101 can block the plasma from being sputtered in the horizontal direction, and the horizontal sputtering causes the data line leads close to the retaining wall 101 to be too thin, thereby causing problems such as disconnection.
  • FIG. 3 is a schematic structural diagram of an array substrate corresponding to a fan-out area.
  • FIG. 3 is a schematic structural diagram of an array substrate corresponding to a fan-out area.
  • FIG. 5 is a schematic structural view of still another embodiment of an array substrate provided by the present disclosure.
  • a flat layer 30 is formed on the data line lead 20.
  • the array substrate is filled by a flat layer such that the region where the interlayer dielectric layer is thickened does not affect the flatness of the array substrate.
  • FIG. 5 is a schematic structural diagram of an array substrate corresponding to a fan-out area.
  • FIG. 5 is a schematic structural diagram of an array substrate corresponding to a fan-out area.
  • a spacing between the retaining wall 101 and a data line lead 20 (eg, a blank lead) adjacent thereto is equal to a spacing between adjacent data line leads 20, such that Between the retaining wall 101 and the data line lead 20 adjacent thereto, the arrangement structure of the internal data line leads of the lead area of the fan-out area can be simulated to achieve an optimal blocking effect.
  • the spacing between the retaining wall 101 and the data line lead 20 adjacent thereto ranges from about 2.0 ⁇ m to 2.5 ⁇ m.
  • the width of the retaining wall 101 may range from 2.5 ⁇ m to 20 ⁇ m, so that the blank lead and the adjacent SD line are too thin due to excessive exposure, and the dry In the etching process, the overetching phenomenon caused by the rebound of the particles can be effectively avoided.
  • the width of the retaining wall 101 is 2.5 ⁇ m. Since the width of the effective lead is usually about 2.5 ⁇ m, the surrounding structure of the blank lead can be simulated as the surrounding structure of the internal effective lead, so that the blank lead and SD with good uniformity can be obtained in the lead area of the fan-out area. line.
  • FIG. 6 is a schematic flow chart of an embodiment of a method for fabricating an array substrate provided by the present disclosure.
  • the array substrate manufacturing method includes:
  • Step 901 Form at least one retaining wall in a region of the peripheral region of the array substrate near the edge data line lead, the at least one retaining wall for preventing plasma from affecting the edge data line lead.
  • the interlayer dielectric layer 10 includes a retaining wall 101 and a remaining portion 102, and the thickness of the retaining wall 101 is greater than the remaining portion 102.
  • the thickness of the barrier wall 101 is disposed in the region 230 of the peripheral region 200 of the array substrate near the edge data line lead, and the remaining portion 102 is disposed in the data line lead region 210 of the array substrate (refer to FIG. 2).
  • the hierarchical structure of the array substrate may be a hierarchical structure that is generally provided.
  • the hierarchical structure may include a light shielding layer 40 , a gate insulating layer (GI) 50 , a gate layer 60 , and a layer Inter-media layer 10 and the like.
  • GI gate insulating layer
  • the hierarchical structure of the array substrate is not limited to the foregoing hierarchical structure, and other layers (not shown) may be added as needed, such as a substrate substrate, an active layer, and a source/drain layer. , flattening layers, etc., or selecting any one or more of them as needed.
  • the arrangement order is not limited to the arrangement order shown in FIG. 1, and therefore the scope of protection should not be limited to the hierarchical structure actually given by the embodiment of the present disclosure.
  • the array substrate manufacturing method continues to form on the interlayer dielectric layer 10 by setting the thickness of the barrier wall 101 of the interlayer dielectric layer 10 to be larger than the thickness of the remaining portion 102.
  • the layer of metallic material used to prepare the data line leads
  • the layer of metallic material above the retaining wall 101 can also be formed higher, and the layer of metallic material above the remaining portion 102 will be correspondingly lower.
  • the metal material layer is dry etched by plasma etching, in the process of patterning the data line leads, the barrier wall 101 of the interlayer dielectric layer 10 near the edge of the array substrate is set higher.
  • the retaining wall 101 can block the plasma from being sputtered in the horizontal direction, and the horizontal sputtering causes the data line leads close to the retaining wall 101 to be too thin, thereby causing problems such as disconnection.
  • Embodiments of the present disclosure also provide another embodiment of an array substrate manufacturing method that can improve product yield.
  • FIG. 7 is a schematic flow chart of another embodiment of a method for fabricating an array substrate provided by the present disclosure.
  • the array substrate manufacturing method includes:
  • Step 1001 Referring to FIG. 8a, an interlayer dielectric film 11 is formed.
  • Step 1002 forming an interlayer dielectric layer 10 (refer to FIG. 8b) by a patterning process using a halftone mask (refer to FIG. 8b); wherein the interlayer dielectric layer 10 includes a retaining wall 101 and a remaining portion 102, The thickness of the retaining wall 101 is greater than the thickness of the remaining portion 102; the retaining wall 101 is in the region 230 of the peripheral region 200 of the array substrate near the edge data line lead, and the remaining portion 102 is in the array substrate In the data line lead area 210 (refer to FIG. 2). Forming the interlayer dielectric layer by a halftone mask can simplify the process and achieve good consistency.
  • the method for manufacturing the array substrate may further include:
  • Step 1003 Referring to FIG. 8g, a data line lead 20 is formed on the interlayer dielectric layer 10, the data line lead 20 including active leads 202, 203 and blank leads 201.
  • the blank lead is disposed between the active lead and the retaining wall, and since the blank lead does not work, it can further block the effective lead of the plasma to affect the operation during dry etching.
  • the data line leads 20 fabricated by the above method have the same widths of the effective leads 202, 203 and the blank leads 201, so that the effective leads 202, 203 and the blank leads 201 can better perform their functions.
  • forming the data line leads 20 on the interlayer dielectric layer 10 can be implemented by the following steps:
  • a thin film 21 of a metal material is formed (refer to FIG. 8c), and a pattern including the data line leads 201, 202, 203 is formed by a patterning process (refer to FIG. 8g).
  • the thin film 21 of the metal material may be formed by one or more of various methods such as deposition, coating, sputtering, and the like.
  • a patterning process suitable for a classical mask process may generally include photoresist coating to form a photoresist layer 70, exposure using a mask 80 (refer to FIG. 8d), development to form a photoresist 701 as a resist layer. 702, 703 (refer to FIG. 8e), etching the metal material film 21 to form data line leads 201, 202, 203 (refer to FIG. 8f), photoresist stripping (refer to FIG. 8g), and the like.
  • composition can be completed without using a mask, such as printing, printing, and the like. That is, as long as the process in which the desired pattern can be formed can be referred to as a patterning process.
  • the method for manufacturing the array substrate may further include:
  • Step 1004 Referring to Figure 8h, a planar layer 30 is formed on the data line leads 20.
  • the array substrate is filled by a flat layer such that the region where the interlayer dielectric layer is thickened does not affect the flatness of the array substrate.
  • the array substrate manufacturing method continues to form on the interlayer dielectric layer 10 by setting the thickness of the barrier wall 101 of the interlayer dielectric layer 10 to be larger than the thickness of the remaining portion 102.
  • the layer of metallic material used to prepare the data line leads
  • the layer of metallic material above the retaining wall 101 can also be formed higher, and the layer of metallic material above the remaining portion 102 will be correspondingly lower.
  • the metal material layer is dry etched by plasma etching, in the process of patterning the data line leads, the barrier wall 101 of the interlayer dielectric layer 10 near the edge of the array substrate is set higher.
  • the retaining wall 101 can block the plasma from being sputtered in the horizontal direction, and the horizontal sputtering causes the data line leads close to the retaining wall 101 to be too thin, thereby causing problems such as disconnection.
  • a plasma is ionized by a glow discharge to generate a plasma and bombard the target target, and the metal or non-metal material is separated from the target to form a desired pattern. .
  • the steps of the array substrate manufacturing method described in the foregoing steps may further include steps of fabricating other layers, which are merely examples in the embodiments of the present disclosure, and do not represent the present disclosure. Other necessary layer structures are excluded from the array substrate embodiment.
  • an embodiment of a display panel is proposed to improve product yield.
  • the display panel includes the array substrate described in any of the above embodiments.
  • an embodiment of a display device is proposed to improve product yield.
  • the display device includes a display panel as described above.
  • the display device in this embodiment may be any product or component having a display function, such as an electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator, and the like.
  • Embodiments of the present disclosure provide an array substrate and a method of manufacturing the same, a display panel, and a display device.
  • the metal formed on the interlayer dielectric layer is formed by setting a thickness of a barrier wall of the interlayer dielectric layer to be larger than a thickness of the second portion.
  • the material layer (used to prepare the data lines), the layer of metallic material above the retaining wall can also be formed higher, and the layer of metallic material above the second portion will be correspondingly lower.
  • the metal material layer is dry etched by plasma etching, in the process of patterning the data lines, since the barrier layer of the interlayer dielectric layer near the edge of the array substrate is set higher, when the plasma is When the body bombards the metal material, the retaining wall can block the plasma from being sputtered in the horizontal direction, and the horizontal sputtering causes the data line close to the retaining wall to be too thin, thereby causing problems such as disconnection.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Nonlinear Science (AREA)
  • Ceramic Engineering (AREA)
  • Optics & Photonics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

公开了一种阵列基板，包括显示区域以及围绕所述显示区域的周边区域，其中所述周边区域包括数据线引线区域和驱动电路区域，并且所述数据线引线区域位于所述驱动电路区域和所述显示区域之间；其中所述驱动电路区域包含驱动电路，所述数据线引线区域包含多条数据线引线，并且所述多条数据线引线从所述显示区域引出并与所述驱动电路电连接；以及其中所述数据线引线区域包含边缘数据线引线，所述周边区域的靠近所述边缘数据线引线的区域包含至少一个挡墙，并且所述至少一个挡墙用于防止等离子体影响所述边缘数据线引线。还公开了一种阵列基板制作方法、显示面板和显示装置。(图1)

Description

阵列基板及其制造方法、显示面板、显示装置
相关专利申请
本申请主张于2018年3月23日提交的中国专利申请No.201810247221.7的优先权，其全部内容通过引用结合于此。
技术领域
本公开涉及显示技术领域，特别是指一种阵列基板及其制造方法、显示面板、显示装置。
背景技术
随着显示技术的发展，窄边框技术已经成为现有显示技术的主要发展方向。然而随着产品边框逐渐变窄，则要求在阵列基板上布线更细且更密，当窄边框产品在源漏(SD)层进行布线时，扇出(fanout)区的数据线的关键尺寸(Critical Dimension，简称CD)和间距(Space)均较小，容易出现线路弱连接甚至断开的情况，发生开路(Open)、显示暗线等不良，从而造成一定的良率损失。
在阵列基板的源漏层上制备数据线引线时，通常利用等离子体刻蚀技术对源漏层进行干法刻蚀，经图案化后形成数据线引线。但是在靠近阵列基板边缘的区域通常不需要形成数据线引线，等离子体在轰击此边缘区域的源漏层时容易进一步影响到靠近此边缘区域的需要保留的数据线，造成靠近阵列基板边缘区域的数据线过细，进而出现数据线易断裂的问题。
发明内容
本公开实施例的第一个方面，提供了一种阵列基板，包括显示区域以及围绕所述显示区域的周边区域，
其中所述周边区域包括数据线引线区域和驱动电路区域，并且所述数据线引线区域位于所述驱动电路区域和所述显示区域之间；
其中所述驱动电路区域包含驱动电路，所述数据线引线区域包含多条数据线引线，并且所述多条数据线引线从所述显示区域引出并与所述驱动电路电连接；以及
其中所述数据线引线区域包含边缘数据线引线，所述周边区域的靠近所述边缘数据线引线的区域包含至少一个挡墙，并且所述至少一个挡墙用于防止等离子体影响所述边缘数据线引线。
在示例性实施例中，所述至少一个挡墙包括两个挡墙，所述两个挡墙相对设置。
在示例性实施例中，所述阵列基板还包括衬底基板和位于所述衬底基板一侧的层间介质层，
其中所述挡墙与所述层间介质层同层且同材料，并且所述挡墙垂直于所述衬底基板的高度大于所述层间介质层垂直于所述衬底基板的高度。
在示例性实施例中，所述数据线引线位于所述层间介质层远离所述衬底基板一侧的表面上，并且所述挡墙垂直于所述衬底基板的高度不小于所述层间介质层与所述数据线引线垂直于所述衬底基板的高度之和。
在示例性实施例中，所述阵列基板还包括衬底基板和位于所述衬底基板一侧的层间介质层，以及位于所述衬底基板和所述层间介质层之间的栅极层，其中所述挡墙与所述栅极层同层且同材料，并且所述层间介质层和所述挡墙垂直于所述衬底基板的高度之和大于所述层间介质层与所述栅极层垂直于所述衬底基板的高度之和。
在示例性实施例中，所述阵列基板还包括衬底基板和远离所述衬底基板一侧依次设置的栅极绝缘层、栅极层和层间介质层，其中所述挡墙与所述栅极绝缘层同层且同材料，并且所述层间介质层、所述栅极层和所述挡墙垂直于所述衬底基板的高度之和大于所述层间介质层、所述栅极层、所述栅极绝缘层垂直于所述衬底基板的高度之和。
在示例性实施例中，所述阵列基板还包括衬底基板和远离所述衬底基板一侧依次设置的遮光层、栅极绝缘层、栅极层和层间介质层，其中所述挡墙与所述遮光层同层且同材料，并且所述层间介质层、所述栅极层、所述栅极绝缘层和所述挡墙垂直于所述衬底基板的高度之和大于所述层间介质层、所述栅极层、所述栅极绝缘层和所述遮光层垂直于所述衬底基板的高度之和。
在示例性实施例中，所述阵列基板还包括空白引线，所述空白引线位于所述层间介质层远离所述衬底基板的一侧，并且所述空白引线 位于所述挡墙和所述数据线引线之间。
在示例性实施例中，所述挡墙与所述空白引线之间的间距，与所述数据线引线之间的间距相等。
在示例性实施例中，所述挡墙和所述空白引线之间的间距范围为约2.0μm～2.5μm。
在示例性实施例中，所述挡墙的宽度范围为约2.5μm～20μm。
在示例性实施例中，所述挡墙的宽度范围为约2.5μm，并且所述数据线引线的宽度为2.5μm。
本公开实施例的第二个方面，提供了一种阵列基板制造方法，其中所述阵列基板包括显示区域以及围绕所述显示区域的周边区域，其中所述周边区域包括数据线引线区域和驱动电路区域，并且所述数据线引线区域位于所述驱动电路区域和所述显示区域之间；其中所述驱动电路区域包含驱动电路，所述数据线引线区域包含多条数据线引线，并且所述多条数据线引线从所述显示区域引出并与所述驱动电路电连接；其中所述数据线引线区域包含边缘数据线引线，并且所述方法包括：在所述周边区域的靠近所述边缘数据线引线的区域形成至少一个挡墙，所述至少一个挡墙用于防止等离子体影响所述边缘数据线引线。
在示例性实施例中，在所述周边区域的靠近所述边缘数据线引线的区域形成至少一个挡墙的步骤包括：在所述周边区域的靠近所述边缘数据线引线的区域形成相对设置的两个挡墙。
在示例性实施例中，在所述周边区域的靠近所述边缘数据线引线的区域形成至少一个挡墙的步骤包括：
准备衬底基板，
在所述衬底基板上形成层间介质薄膜，以及
利用半色调掩膜版，对所述层间介质薄膜进行构图工艺，以形成所述挡墙和所述层间介质层，其中所述挡墙垂直于所述衬底基板的高度大于所述层间介质层垂直于所述衬底基板的高度。
在示例性实施例中，所述方法还包括：
在所述层间介质层远离所述衬底基板一侧的表面上形成所述数据线引线，其中所述挡墙垂直于所述衬底基板的高度不小于所述层间介质层与所述数据线引线垂直于所述衬底基板的高度之和。
在示例性实施例中，在所述周边区域的靠近所述边缘数据线引线 的区域形成至少一个挡墙的步骤包括：
准备衬底基板，
在所述衬底基板上形成栅极薄膜，
利用半色调掩膜版，对所述栅极薄膜进行构图工艺，以形成所述挡墙和栅极层，
在所述挡墙和所述栅极层上形成层间介质层，其中所述层间介质层和所述挡墙垂直于所述衬底基板的高度之和大于所述层间介质层与所述栅极层垂直于所述衬底基板的高度之和。
在示例性实施例中，在所述周边区域的靠近所述边缘数据线引线的区域形成至少一个挡墙的步骤包括：
准备衬底基板，
在所述衬底基板上形成栅极绝缘薄膜，
利用半色调掩膜版，对所述栅极绝缘薄膜进行构图工艺，以形成所述挡墙和栅极绝缘层，
在所述挡墙和所述栅极绝缘层上依次形成栅极层和层间介质层，其中所述层间介质层、所述栅极层和所述挡墙垂直于所述衬底基板的高度之和大于所述层间介质层、所述栅极层、所述栅极绝缘层垂直于所述衬底基板的高度之和。
在示例性实施例中，在所述周边区域的靠近所述边缘数据线引线的区域形成至少一个挡墙的步骤包括：
准备衬底基板，
在所述衬底基板上形成遮光薄膜，
利用半色调掩膜版，对所述遮光薄膜进行构图工艺，以形成所述挡墙和遮光层，
在所述挡墙和所述遮光层上依次形成栅极绝缘层、栅极层和层间介质层，其中所述层间介质层、所述栅极层、所述栅极绝缘层和所述挡墙垂直于所述衬底基板的高度之和大于所述层间介质层、所述栅极层、所述栅极绝缘层和所述遮光层垂直于所述衬底基板的高度之和。
在示例性实施例中，所述方法还包括在所述层间介质层远离所述衬底基板的一侧形成空白引线，其中所述空白引线位于所述挡墙和所述数据线引线之间。
在示例性实施例中，所述挡墙与所述空白引线之间的间距，与所 述数据线引线之间的间距相等。
在示例性实施例中，所述挡墙和所述空白引线之间的间距范围为约2.0μm～2.5μm。
在示例性实施例中，所述挡墙的宽度范围为约2.5μm～20μm。
在示例性实施例中，所述挡墙的宽度范围为约2.5μm，并且所述数据线引线的宽度为2.5μm。
本公开实施例的第三个方面，提供了一种显示面板，包括如上所述的阵列基板。
本公开实施例的第四个方面，提供了一种显示装置，包括如上所述的阵列基板。
附图说明
图1为本公开提供的阵列基板的一个实施例的结构示意图；
图2为本公开提供的阵列基板的一个实施例的扇出区的区域分布示意图；
图3为本公开提供的阵列基板的另一个实施例的结构示意图；
图4为本公开提供的阵列基板的又一个实施例的结构示意图；
图5为本公开提供的阵列基板的又一个实施例的结构示意图；
图6为本公开提供的阵列基板制造方法的一个实施例的流程示意图；
图7为本公开提供的阵列基板制造方法的另一个实施例的流程示意图；
图8a为本公开提供的阵列基板制造方法实施例中形成层间介质薄膜后的阵列基板结构示意图；
图8b为本公开提供的阵列基板制造方法实施例中形成层间介质层后的阵列基板结构示意图；
图8c为本公开提供的阵列基板制造方法实施例中形成金属材料层后的阵列基板结构示意图；
图8d为本公开提供的阵列基板制造方法实施例中曝光光刻胶层时的阵列基板结构示意图；
图8e为本公开提供的阵列基板制造方法实施例中显影光刻胶层后的阵列基板结构示意图；
图8f为本公开提供的阵列基板制造方法实施例中刻蚀金属材料层形成数据线引线后的阵列基板结构示意图；
图8g为本公开提供的阵列基板制造方法实施例中去除光刻胶后的阵列基板结构示意图；
图8h为本公开提供的阵列基板制造方法实施例中形成平坦层后的阵列基板结构示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本公开进一步详细说明。
本公开实施例的第一个方面，提出了一种阵列基板。图1为本公开一实施例提供的阵列基板的示意剖面图，并且图2为该阵列基板的示意性俯视图。图1的剖面图为沿图2的线A-B切割得到。
如图2所示，该阵列基板例如包括显示区域100以及围绕所述显示区域的周边区域200。周边区域200包括数据线引线区域210和驱动电路区域220。数据线引线区域210位于驱动电路区域220和显示区域100之间。
驱动电路区域220例如包含驱动电路220′。数据线引线区域210包含多条数据线引线20，并且这些数据线引线20从显示区域100引出并与驱动电路区域220中的驱动电路220′电连接。数据线引线区域210包含边缘数据线引线，周边区域200的靠近边缘数据线引线的区域230包含至少一个挡墙101，并且所述至少一个挡墙用于防止等离子体影响所述边缘数据线引线。
如图2所示，数据线引线区域210包括第一边界、第二边界、第三边界和第四边界。第一边界和第二边界相对，例如在图2中分别为数据线引线区域210的上边界和下边界。第三边界和第四边界相对，例如在图2中分别为数据线引线区域210的左边界和右边界。也就是说，数据线引线区域210在第一边界与显示区域100相邻，在第二边界与驱动电路区域220相邻，并且在第三边界和第四边界与周边区域200的区域230相邻。
在本公开的上下文中，周边区域200的靠近边缘数据线引线的区域230是指周边区域200的靠近数据线引线区域210的第三边界和第 四边界的区域。
需要说明的是，通常情况下，一个阵列基板中仅包含一个数据线引线区域，但并不代表该方案仅能适用于仅有一个数据线引线区域的阵列基板。可以知道，当阵列基板中存在两个数据线引线区域时，也存在同样的技术问题，此时，该方案则可同时适用于两个数据线引线区域中。当然多个数据线引线区域同理，在此不再赘述。
在一实施例中，所述至少一个挡墙包括两个挡墙，所述两个挡墙相对设置。例如，如图2所示，周边区域200的靠近边缘数据线引线的两个区域230分别包括一个挡墙101。
在一实施例中，阵列基板包括衬底基板90和位于所述衬底基板一侧的层间介质层10。如图1所示，挡墙101与层间介质层10同层且同材料，并且挡墙101垂直于衬底基板90的高度大于层间介质层10垂直于衬底基板90的高度。结合图2所示，挡墙101位于周边区域200的与数据线引线区域210的左边界相邻的区域230。层间介质层10的位于数据线引线区域210的部分用102表示。
可选的，图1中所示的层级结构是阵列基板通常会具有的层级结构，所述层级结构可包括遮光层(Light Shield，简称LS)40、栅绝缘层(GI)50、栅极层60、层间介质层10等。在此需要说明的是，所述阵列基板的层级结构不限于前述的层级结构，也可以根据需要增加其他的层(图中未示出)，例如衬底基板、有源层、源漏极层、平坦化层等，或者根据需要选择其中的任意一层或多层。并且，排列顺序也不限于图1所示的排列顺序，因此不应把保护范围限制在本公开实施例实际给出的层级结构之上。
从上述实施例可以看出，本公开实施例提供的阵列基板，通过将层间介质层10的位于数据线引线区域210的区域230的挡墙101的高度设置成大于层间介质层10的位于数据线引线区域210的部分102的高度，在层间介质层10上继续形成的金属材料层(用于制备数据线引线)时，位于挡墙101之上的金属材料层也能形成得较高，位于其余部分102之上的金属材料层会相应较低。当采用等离子体刻蚀对所述金属材料层进行干法刻蚀，经图案化制作数据线引线的过程中，由于靠近所述阵列基板边缘的层间介质层10的挡墙101设置的较高，当等离子体轰击金属材料时，挡墙101能阻挡等离子体在水平方向溅射， 这种水平方向溅射使得靠近挡墙101的数据线引线过细，进而造成断线等问题。在此需要说明的是，在诸如等离子体刻蚀的干法刻蚀中，通过辉光放电，电离特定气体产生等离子体并轰击目标靶材，使金属或非金属材料脱离靶材形成所需图案。
需要说明的是，图1所示为扇出区对应的阵列基板结构示意图。所述阵列基板的其他部分的结构可参照已有结构，在此不再赘述。
本公开实施例还提出了一种阵列基板的另一个实施例，可提升产品良率。如图3所示，为本公开提供的阵列基板的另一个实施例的结构示意图。在此实施例中，数据线引线20位于层间介质层10远离衬底基板90一侧的表面上，并且挡墙101垂直于衬底基板的高度不小于层间介质层10与数据线引线20垂直于所述衬底基板的高度之和。
如图3所示，所述阵列基板还包括数据线引线20，所述数据线引线20形成在所述层间介质层10的其余部分102上，能有效利用边缘高的层间介质层(ILD)10的阻挡保护边缘的数据线引线不出现过刻现象，从而当采用等离子体刻蚀对所述金属材料层进行干法刻蚀，经图案化制作数据线引线的过程中，由于靠近所述阵列基板边缘的层间介质层10的挡墙101设置的较高，当等离子体轰击金属材料时，挡墙101能阻挡等离子体在水平方向溅射到其余部分102，使得靠近挡墙101的数据线引线(例如数据线引线202)过细，进而造成断线等问题。
可选的，所述挡墙101和其余部分102的厚度差大于所述数据线引线20的厚度，从而能够较好地防止等离子体在水平方向溅射到其余部分102中，进而防止造成数据线引线过细。
应指出，在本公开上下文中，挡墙的厚度与挡墙垂直于衬底基板的高度这两个表述是等效且可互换的。
可选的，图4示出了所述阵列基板的又一实施例，其中，所述数据线引线20包括有效引线202、203和空白引线201，所述空白引线201位于所述有效引线202和所述挡墙101之间，空白引线201(Dummy SD)不工作，能进一步阻挡干法刻蚀时等离子体影响工作的有效引线202和203。
可选的，处于扇出区的所述数据线引线20中的有效引线202、203和空白引线201的宽度一致；在不增加工艺复杂度的情况下能够起到更好的阻挡作用。
可选的，图3中所示的层级结构是阵列基板通常会具有的层级结构，所述层级结构可包括遮光层40、栅绝缘层(GI)50、栅极层60、层间介质层10等。在此需要说明的是，所述阵列基板的层级结构不限于前述的层级结构，也可以根据需要增加其他的层(图中未示出)，例如衬底基板、有源层、源漏极层、平坦化层等，或者根据需要选择其中的任意一层或多层。并且，排列顺序也不限于图3所示的排列顺序，因此不应把保护范围限制在本公开实施例实际给出的层级结构之上。
在一实施例中，阵列基板包括衬底基板90和位于所述衬底基板90一侧的层间介质层10，以及位于所述衬底基板90和所述层间介质层10之间的栅极层60。挡墙101与栅极层60同层且同材料，并且层间介质层10和挡墙101垂直于衬底基板的高度之和大于层间介质层10与栅极层60垂直于衬底基板的高度之和。
在一实施例中，阵列基板包括衬底基板90和远离衬底基板90一侧依次设置的栅极绝缘层50、栅极层60和层间介质层10。挡墙101与栅极绝缘层50同层且同材料。层间介质层10、栅极层60和挡墙101垂直于衬底基板的高度之和大于层间介质层10、栅极层60、栅极绝缘层50垂直于衬底基板的高度之和。
在一实施例中，阵列基板包括衬底基板90和远离衬底基板一侧依次设置的遮光层40、栅极绝缘层50、栅极层60和层间介质层10。挡墙101与遮光层40同层且同材料。层间介质层10、栅极层60、栅极绝缘层50和挡墙40垂直于衬底基板的高度之和大于层间介质层10、栅极层60、栅极绝缘层50和遮光层40垂直于衬底基板的高度之和。
从上述实施例可以看出，本公开实施例提供的阵列基板，通过将层间介质层10的挡墙101的厚度设置成大于其余部分102的厚度，在层间介质层10上继续形成的金属材料层(用于制备数据线引线)，位于挡墙101之上的金属材料层也能形成得较高，位于其余部分102之上的金属材料层会相应较低。当采用等离子体刻蚀对所述金属材料层进行干法刻蚀，经图案化制作数据线引线的过程中，由于靠近所述阵列基板边缘的层间介质层10的挡墙101设置的较高，当等离子体轰击金属材料时，挡墙101能阻挡等离子体在水平方向溅射，该水平方向溅射使得靠近挡墙101的数据线引线过细，进而造成断线等问题。
需要说明的是，图3所示为扇出区对应的阵列基板结构示意图。所述阵列基板的其他部分的结构可参照已有结构，在此不再赘述。
本公开实施例还提出了一种阵列基板的又一个实施例，可提升产品良率。如图5所示，为本公开提供的阵列基板的又一个实施例的结构示意图。
如图5所示，所述数据线引线20上形成有平坦层30。通过平坦层填平阵列基板，使得所述层间介质层增厚的区域不对阵列基板的平坦度产生影响。
需要说明的是，图5所示为扇出区对应的阵列基板结构示意图。所述阵列基板的其他部分的结构可参照已有结构，在此不再赘述。
可选的，在上述任意实施例中，所述挡墙101和与其相邻的数据线引线20(例如空白引线)之间的间距，与相邻数据线引线20之间的间距相等，使得所述挡墙101和与其相邻的数据线引线20之间可以模拟扇出区的引线区域内部数据线引线的排布结构，从而达到最佳的阻挡效果。
可选的，所述挡墙101和与其相邻的数据线引线20之间的间距范围为约2.0μm～2.5μm。
可选的，在上述任意实施例中，所述挡墙101的宽度范围可以为2.5μm～20μm，从而能够更为有效避免因曝光过量导致的空白引线及相邻SD线过细问题，并且在干法刻蚀过程中能有效避免由于粒子反弹导致的过刻现象。
例如，在上述任意实施例中，所述挡墙101的宽度为2.5μm。由于有效引线的宽度通常为2.5μm左右，因此这样能够将空白引线的周围结构模拟为内部的有效引线的周围结构，从而能够在扇出区的引线区域中得到均一性较好的空白引线及SD线。
本公开实施例的第二个方面，提出了一种阵列基板制造方法的一个实施例，可提升产品良率。如图6所示，为本公开提供的阵列基板制造方法的一个实施例的流程示意图。
所述阵列基板制造方法，包括：
步骤901：在阵列基板的周边区域的靠近边缘数据线引线的区域形成至少一个挡墙，所述至少一个挡墙用于防止等离子体影响所述边缘数据线引线。
例如，在制备图2所示的层间介质层10的过程中(参考图8b)，层间介质层10包括挡墙101和其余部分102，所述挡墙101的厚度大于所述其余部分102的厚度；将挡墙101设置在阵列基板的周边区域200的靠近边缘数据线引线的区域230中，并且其余部分102设置在阵列基板的数据线引线区域210中(参考图2所示)。
可选的，所述阵列基板的层级结构可以是通常会具有的层级结构，参考图1所示，所述层级结构可包括遮光层40、栅绝缘层(GI)50、栅极层60、层间介质层10等。在此需要说明的是，所述阵列基板的层级结构不限于前述的层级结构，也可以根据需要增加其他的层(图中未示出)，例如衬底基板、有源层、源漏极层、平坦化层等，或者根据需要选择其中的任意一层或多层。并且，排列顺序也不限于图1所示的排列顺序，因此不应把保护范围限制在本公开实施例实际给出的层级结构之上。
从上述实施例可以看出，本公开实施例提供的阵列基板制造方法，通过将层间介质层10的挡墙101的厚度设置成大于其余部分102的厚度，在层间介质层10上继续形成的金属材料层(用于制备数据线引线)，位于挡墙101之上的金属材料层也能形成得较高，位于其余部分102之上的金属材料层会相应较低。当采用等离子体刻蚀对所述金属材料层进行干法刻蚀，经图案化制作数据线引线的过程中，由于靠近所述阵列基板边缘的层间介质层10的挡墙101设置的较高，当等离子体轰击金属材料时，挡墙101能阻挡等离子体在水平方向溅射，该水平方向溅射使得靠近挡墙101的数据线引线过细，进而造成断线等问题。
本公开实施例还提出了一种阵列基板制造方法的另一个实施例，可提升产品良率。如图7所示，为本公开提供的阵列基板制造方法的另一个实施例的流程示意图。
所述阵列基板制造方法，包括：
步骤1001：参考图8a，形成层间介质薄膜11。
步骤1002：利用半色调掩膜版(Halftone Mask)，通过构图工艺，形成层间介质层10(参考图8b)；其中，所述层间介质层10包括挡墙101和其余部分102，所述挡墙101的厚度大于所述其余部分102的厚度；所述挡墙101处于所述阵列基板的周边区域200的靠近边缘数据线引线的区域230中，所述其余部分102处于所述阵列基板的数据 线引线区域210中(参考图2所示)。通过半色调掩膜版形成所述层间介质层，能够简化工艺且一致性较好。
可选的，所述阵列基板制造方法，还可包括：
步骤1003：参考图8g，在所述层间介质层10上形成数据线引线20，所述数据线引线20包括有效引线202、203和空白引线201。将所述空白引线设置在所述有效引线和所述挡墙之间，由于空白引线不工作，使得其能进一步阻挡干法刻蚀时等离子体影响工作的有效引线。
例如，采用上述方法制作得到的数据线引线20，其中的有效引线202、203和空白引线201的宽度相等，使得有效引线202、203和空白引线201均能更好地实现其功能。
可选的，在所述层间介质层10上形成数据线引线20可采用以下步骤实现：
形成金属材料薄膜21(参考图8c)，通过构图工艺形成包括数据线引线201、202、203的图案(参考图8g)。
可选的，形成所述金属材料薄膜21通常可采用沉积、涂敷、溅射等多种方式中的一种或多种。
适用于经典掩膜版过程的构图工艺通常可包括光刻胶涂敷以形成光刻胶层70、利用掩膜版80进行曝光(参考图8d)、显影形成作为抗蚀层的光刻胶701、702、703(参考图8e)、刻蚀金属材料薄膜21以形成数据线引线201、202、203(参考图8f)、光刻胶剥离(参考图8g)等工艺。
有时候也不需要传统的构图工艺即可制作图案，比如利用离地剥离技术等。此外，在一些情况下，还存在无需采用掩膜版即能完成构图的情况，比如可以为打印、印刷等更多其他的构图方式。也就是说，只要可以形成所需的图案的工艺都可以称为构图工艺。
可选的，所述阵列基板制造方法，还可包括：
步骤1004：参考图8h，在所述数据线引线20上形成平坦层30。通过平坦层填平阵列基板，使得所述层间介质层增厚的区域不对阵列基板的平坦度产生影响。
从上述实施例可以看出，本公开实施例提供的阵列基板制造方法，通过将层间介质层10的挡墙101的厚度设置成大于其余部分102的厚度，在层间介质层10上继续形成的金属材料层(用于制备数据线引线)， 位于挡墙101之上的金属材料层也能形成得较高，位于其余部分102之上的金属材料层会相应较低。当采用等离子体刻蚀对所述金属材料层进行干法刻蚀，经图案化制作数据线引线的过程中，由于靠近所述阵列基板边缘的层间介质层10的挡墙101设置的较高，当等离子体轰击金属材料时，挡墙101能阻挡等离子体在水平方向溅射，该水平方向溅射使得靠近挡墙101的数据线引线过细，进而造成断线等问题。在此需要说明的是，在诸如等离子体刻蚀的干法刻蚀中，通过辉光放电，电离特定气体产生等离子体并轰击目标靶材，使金属或非金属材料脱离靶材形成所需图案。
需要说明的是，在必要的情况下，前述步骤中所描述的阵列基板制造方法的步骤可能还包括制作其他层的步骤，本公开实施例中仅仅是给出示例，并不代表在本公开的阵列基板实施例中排除其他必要层结构。
本公开实施例的第三个方面，提出了一种显示面板的一个实施例，可提升产品良率。
所述显示面板包括如上任一实施例所述的阵列基板。
本公开实施例的第四个方面，提出了一种显示装置的一个实施例，可提升产品良率。
所述显示装置，包括如前所述显示面板。
需要说明的是，本实施例中的显示装置可以为：电子纸、手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开实施例提供一种阵列基板及其制造方法、显示面板、显示装置，通过将层间介质层的挡墙的厚度设置成大于第二部分的厚度，在层间介质层上继续形成的金属材料层(用于制备数据线)，位于挡墙之上的金属材料层也能形成得较高，位于第二部分之上的金属材料层会相应较低。当采用等离子体刻蚀对所述金属材料层进行干法刻蚀，经图案化制作数据线的过程中，由于靠近所述阵列基板边缘的层间介质层的挡墙设置的较高，当等离子体轰击金属材料时，挡墙能阻挡等离子体在水平方向溅射，该水平方向溅射使得靠近挡墙的数据线过细，进而造成断线等问题。
需要说明的是，上述形成层的操作，包括但不仅限于(化学相、 物理相)沉积成膜、(磁控)溅射成膜，并且本领域技术人员可以理解，在形成每个层之后，可以根据需要在其上进一步形成相应的图案，本公开对此不再赘述。
需要指出的是，在附图中，为了图示的清晰可能夸大了层和区域的尺寸。而且可以理解，当元件或层被称为在另一元件或层“上”时，它可以直接在其他元件上，或者可以存在中间的层。另外，可以理解，当元件或层被称为在另一元件或层“下”时，它可以直接在其他元件下，或者可以存在一个以上的中间的层或元件。另外，还可以理解，当层或元件被称为在两层或两个元件“之间”时，它可以为两层或两个元件之间惟一的层，或还可以存在一个以上的中间层或元件。通篇相似的参考标记指示相似的元件。
在本公开中，术语“第一”、“第二”、“第三”、“第四”仅用于描述目的，而不能理解为指示或暗示相对重要性。术语“多个”指两个或两个以上，除非另有明确的限定。
所属领域的普通技术人员应当理解：以上所述仅为本公开的具体实施例而已，并不用于限制本公开，凡在本公开的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (26)

  1. 一种阵列基板，包括显示区域以及围绕所述显示区域的周边区域，
    其中所述周边区域包括数据线引线区域和驱动电路区域，并且所述数据线引线区域位于所述驱动电路区域和所述显示区域之间；
    其中所述驱动电路区域包含驱动电路，所述数据线引线区域包含多条数据线引线，并且所述多条数据线引线从所述显示区域引出并与所述驱动电路电连接；以及
    其中所述数据线引线区域包含边缘数据线引线，所述周边区域的靠近所述边缘数据线引线的区域包含至少一个挡墙，并且所述至少一个挡墙用于防止等离子体影响所述边缘数据线引线。
  2. 根据权利要求1所述的阵列基板，其中所述至少一个挡墙包括两个挡墙，所述两个挡墙相对设置。
  3. 根据权利要求1所述的阵列基板，还包括衬底基板和位于所述衬底基板一侧的层间介质层，
    其中所述挡墙与所述层间介质层同层且同材料，并且所述挡墙垂直于所述衬底基板的高度大于所述层间介质层垂直于所述衬底基板的高度。
  4. 根据权利要求3所述的阵列基板，其中所述数据线引线位于所述层间介质层远离所述衬底基板一侧的表面上，并且所述挡墙垂直于所述衬底基板的高度不小于所述层间介质层与所述数据线引线垂直于所述衬底基板的高度之和。
  5. 根据权利要求1所述的阵列基板，还包括衬底基板和位于所述衬底基板一侧的层间介质层，以及位于所述衬底基板和所述层间介质层之间的栅极层，其中所述挡墙与所述栅极层同层且同材料，并且所述层间介质层和所述挡墙垂直于所述衬底基板的高度之和大于所述层间介质层与所述栅极层垂直于所述衬底基板的高度之和。
  6. 根据权利要求1所述的阵列基板，还包括衬底基板和远离所述衬底基板一侧依次设置的栅极绝缘层、栅极层和层间介质层，其中所述挡墙与所述栅极绝缘层同层且同材料，并且所述层间介质层、所述栅极层和所述挡墙垂直于所述衬底基板的高度之和大于所述层间介质 层、所述栅极层、所述栅极绝缘层垂直于所述衬底基板的高度之和。
  7. 根据权利要求1所述的阵列基板，还包括衬底基板和远离所述衬底基板一侧依次设置的遮光层、栅极绝缘层、栅极层和层间介质层，其中所述挡墙与所述遮光层同层且同材料，并且所述层间介质层、所述栅极层、所述栅极绝缘层和所述挡墙垂直于所述衬底基板的高度之和大于所述层间介质层、所述栅极层、所述栅极绝缘层和所述遮光层垂直于所述衬底基板的高度之和。
  8. 根据权利要求3-7中任意一项所述的阵列基板，还包括空白引线，所述空白引线位于所述层间介质层远离所述衬底基板的一侧，并且所述空白引线位于所述挡墙和所述数据线引线之间。
  9. 根据权利要求8所述的阵列基板，其中所述挡墙与所述空白引线之间的间距，与所述数据线引线之间的间距相等。
  10. 根据权利要求8所述的阵列基板，其中所述挡墙和所述空白引线之间的间距范围为约2.0μm～2.5μm。
  11. 根据权利要求1-7中任一项所述的阵列基板，其中所述挡墙的宽度范围为约2.5μm～20μm。
  12. 根据权利要求1-7中任一项所述的阵列基板，其中所述挡墙的宽度范围为约2.5μm，并且所述数据线引线的宽度为2.5μm。
  13. 一种显示面板，包括如权利要求1-12中任一项所述的阵列基板。
  14. 一种显示装置，包括如权利要求1-12中任一项所述的阵列基板。
  15. 一种阵列基板制造方法，
    其中所述阵列基板包括显示区域以及围绕所述显示区域的周边区域，
    其中所述周边区域包括数据线引线区域和驱动电路区域，并且所述数据线引线区域位于所述驱动电路区域和所述显示区域之间；
    其中所述驱动电路区域包含驱动电路，所述数据线引线区域包含多条数据线引线，并且所述多条数据线引线从所述显示区域引出并与所述驱动电路电连接；
    其中所述数据线引线区域包含边缘数据线引线，并且所述方法包括：在所述周边区域的靠近所述边缘数据线引线的区域形成至少一个 挡墙，所述至少一个挡墙用于防止等离子体影响所述边缘数据线引线。
  16. 根据权利要求15所述的方法，其中在所述周边区域的靠近所述边缘数据线引线的区域形成至少一个挡墙的步骤包括：在所述周边区域的靠近所述边缘数据线引线的区域形成相对设置的两个挡墙。
  17. 根据权利要求15所述的方法，其中在所述周边区域的靠近所述边缘数据线引线的区域形成至少一个挡墙的步骤包括：
    准备衬底基板，
    在所述衬底基板上形成层间介质薄膜，以及
    利用半色调掩膜版，对所述层间介质薄膜进行构图工艺，以形成所述挡墙和所述层间介质层，其中所述挡墙垂直于所述衬底基板的高度大于所述层间介质层垂直于所述衬底基板的高度。
  18. 根据权利要求17所述的方法，还包括：
    在所述层间介质层远离所述衬底基板一侧的表面上形成所述数据线引线，其中所述挡墙垂直于所述衬底基板的高度不小于所述层间介质层与所述数据线引线垂直于所述衬底基板的高度之和。
  19. 根据权利要求15所述的方法，在所述周边区域的靠近所述边缘数据线引线的区域形成至少一个挡墙的步骤包括：
    准备衬底基板，
    在所述衬底基板上形成栅极薄膜，
    利用半色调掩膜版，对所述栅极薄膜进行构图工艺，以形成所述挡墙和栅极层，
    在所述挡墙和所述栅极层上形成层间介质层，其中所述层间介质层和所述挡墙垂直于所述衬底基板的高度之和大于所述层间介质层与所述栅极层垂直于所述衬底基板的高度之和。
  20. 根据权利要求15所述的方法，其中在所述周边区域的靠近所述边缘数据线引线的区域形成至少一个挡墙的步骤包括：
    准备衬底基板，
    在所述衬底基板上形成栅极绝缘薄膜，
    利用半色调掩膜版，对所述栅极绝缘薄膜进行构图工艺，以形成所述挡墙和栅极绝缘层，
    在所述挡墙和所述栅极绝缘层上依次形成栅极层和层间介质层，其中所述层间介质层、所述栅极层和所述挡墙垂直于所述衬底基板的 高度之和大于所述层间介质层、所述栅极层、所述栅极绝缘层垂直于所述衬底基板的高度之和。
  21. 根据权利要求15所述的方法，在所述周边区域的靠近所述边缘数据线引线的区域形成至少一个挡墙的步骤包括：
    准备衬底基板，
    在所述衬底基板上形成遮光薄膜，
    利用半色调掩膜版，对所述遮光薄膜进行构图工艺，以形成所述挡墙和遮光层，
    在所述挡墙和所述遮光层上依次形成栅极绝缘层、栅极层和层间介质层，其中所述层间介质层、所述栅极层、所述栅极绝缘层和所述挡墙垂直于所述衬底基板的高度之和大于所述层间介质层、所述栅极层、所述栅极绝缘层和所述遮光层垂直于所述衬底基板的高度之和。
  22. 根据权利要求17-21中任意一项所述的方法，还包括在所述层间介质层远离所述衬底基板的一侧形成空白引线，其中所述空白引线位于所述挡墙和所述数据线引线之间。
  23. 根据权利要求22所述的方法，其中所述挡墙与所述空白引线之间的间距，与所述数据线引线之间的间距相等。
  24. 根据权利要求22所述的方法，其中所述挡墙和所述空白引线之间的间距范围为约2.0μm～2.5μm。
  25. 根据权利要求15-21中任一项所述的方法，其中所述挡墙的宽度范围为约2.5μm～20μm。
  26. 根据权利要求15-21中任一项所述的方法，其中所述挡墙的宽度范围为约2.5μm，并且所述数据线引线的宽度为2.5μm。
PCT/CN2019/077903 2018-03-23 2019-03-13 阵列基板及其制造方法、显示面板、显示装置 WO2019179339A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/621,325 US11145682B2 (en) 2018-03-23 2019-03-13 Array substrate and method for fabricating the same, display panel, display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810247221.7 2018-03-23
CN201810247221.7A CN108305881B (zh) 2018-03-23 2018-03-23 阵列基板及其制造方法、显示面板、显示装置

Publications (1)

Publication Number Publication Date
WO2019179339A1 true WO2019179339A1 (zh) 2019-09-26

Family

ID=62846705

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/077903 WO2019179339A1 (zh) 2018-03-23 2019-03-13 阵列基板及其制造方法、显示面板、显示装置

Country Status (3)

Country Link
US (1) US11145682B2 (zh)
CN (1) CN108305881B (zh)
WO (1) WO2019179339A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108305881B (zh) * 2018-03-23 2020-08-11 京东方科技集团股份有限公司 阵列基板及其制造方法、显示面板、显示装置
CN109768054B (zh) 2019-02-25 2020-11-10 云谷（固安）科技有限公司 阵列基板及显示屏
CN112068366B (zh) * 2020-09-04 2021-08-24 深圳市华星光电半导体显示技术有限公司 显示面板及显示面板制作方法
CN117356194A (zh) * 2022-04-29 2024-01-05 京东方科技集团股份有限公司 显示背板、显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5721164A (en) * 1996-11-12 1998-02-24 Industrial Technology Research Institute Method of manufacturing thin film transistors
CN104867940A (zh) * 2015-04-22 2015-08-26 合肥鑫晟光电科技有限公司 一种阵列基板及其制备方法、显示面板、显示装置
CN105655295A (zh) * 2016-01-28 2016-06-08 京东方科技集团股份有限公司 一种阵列基板、其制作方法及显示装置
CN108305881A (zh) * 2018-03-23 2018-07-20 京东方科技集团股份有限公司 阵列基板及其制造方法、显示面板、显示装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100583979B1 (ko) * 2000-02-11 2006-05-26 엘지.필립스 엘시디 주식회사 액정 표시장치 제조방법 및 그 제조방법에 따른액정표시장치
JP3700674B2 (ja) * 2002-05-02 2005-09-28 セイコーエプソン株式会社 電気光学装置及び電子機器
US20040224241A1 (en) * 2003-02-03 2004-11-11 Samsung Electronics Co., Ltd. Thin film transistor array panel, manufacturing method thereof, and mask therefor
US7190000B2 (en) * 2003-08-11 2007-03-13 Samsung Electronics Co., Ltd. Thin film transistor array panel and manufacturing method thereof
KR100997968B1 (ko) 2003-10-13 2010-12-02 삼성전자주식회사 박막 트랜지스터 표시판의 제조 방법
US8363191B2 (en) * 2006-11-21 2013-01-29 Sharp Kabushiki Kaisha Active matrix substrate, display panel and display device
KR101395282B1 (ko) * 2006-12-04 2014-05-15 삼성디스플레이 주식회사 박막 트랜지스터 기판 및 이의 제조방법
CN101393363B (zh) * 2007-09-21 2010-06-09 北京京东方光电科技有限公司 Ffs型tft-lcd阵列基板结构及其制造方法
KR101646100B1 (ko) * 2008-12-02 2016-08-08 삼성디스플레이 주식회사 유기 발광 표시 장치 및 그 제조 방법
CN101840922B (zh) * 2009-03-16 2012-05-30 北京京东方光电科技有限公司 阵列基板及制造方法
CN107527894B (zh) * 2017-08-31 2023-12-26 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN207924332U (zh) * 2018-03-23 2018-09-28 京东方科技集团股份有限公司 阵列基板、显示面板和显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5721164A (en) * 1996-11-12 1998-02-24 Industrial Technology Research Institute Method of manufacturing thin film transistors
CN104867940A (zh) * 2015-04-22 2015-08-26 合肥鑫晟光电科技有限公司 一种阵列基板及其制备方法、显示面板、显示装置
CN105655295A (zh) * 2016-01-28 2016-06-08 京东方科技集团股份有限公司 一种阵列基板、其制作方法及显示装置
CN108305881A (zh) * 2018-03-23 2018-07-20 京东方科技集团股份有限公司 阵列基板及其制造方法、显示面板、显示装置

Also Published As

Publication number Publication date
CN108305881A (zh) 2018-07-20
CN108305881B (zh) 2020-08-11
US20200168639A1 (en) 2020-05-28
US11145682B2 (en) 2021-10-12

Similar Documents

Publication Publication Date Title
WO2019179339A1 (zh) 阵列基板及其制造方法、显示面板、显示装置
US8692258B2 (en) Array substrate of TFT-LCD including a black matrix and method for manufacturing the same
CN109671726B (zh) 阵列基板及其制造方法、显示面板、显示装置
JP5512180B2 (ja) フォトレジストの縁部のバリの形成方法とアレイ基板の製造方法
KR101253497B1 (ko) 액정표시장치용 어레이 기판의 제조방법
US10504943B2 (en) Method for manufacturing an array substrate motherboard
JP2003297850A (ja) 薄膜トランジスタアレイ及びその製造方法並びにこれを用いた液晶表示装置
US10381382B2 (en) Array substrate, method for manufacturing the same and display device
JP2007171951A (ja) フォトマスク及びこれを利用した液晶表示装置用アレイ基板の製造方法
US10481445B2 (en) Array substrate and fabrication method thereof, and display device
WO2015109738A1 (zh) 显示面板母板及其制备方法
WO2015085772A1 (zh) 基板的制作方法
WO2013166831A1 (zh) 薄膜晶体管阵列基板及制作方法和显示装置
US9791755B2 (en) Color filter-on-array substrate, display device, and method for manufacturing the color filter-on-array substrate
WO2020082623A1 (zh) 薄膜晶体管及其制造方法
WO2016155429A1 (zh) 显示基板及其制造方法、显示装置
WO2014015617A1 (zh) 阵列基板及显示装置
WO2020147495A1 (zh) 阵列基板及其制备方法、显示面板
WO2016206203A1 (zh) 导电结构及其制作方法、阵列基板、显示装置
JP7295808B2 (ja) アレイ基板、表示パネル及び表示装置
KR101264713B1 (ko) 인쇄판의 제조 방법 및 이를 이용한 액정 표시 장치의 제조방법
US10942403B2 (en) Display substrate and display apparatus
CN109212920B (zh) 显示基板及其对位标记的制作方法、显示面板和显示装置
WO2023103013A1 (zh) 阵列基板及其制作方法
WO2020207400A1 (zh) 薄膜晶体管及其制备方法、显示基板和显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19772489

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205 DATED 22/01/2021)

122 Ep: pct application non-entry in european phase

Ref document number: 19772489

Country of ref document: EP

Kind code of ref document: A1