WO2023103013A1 - 阵列基板及其制作方法 - Google Patents

阵列基板及其制作方法 Download PDF

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Publication number
WO2023103013A1
WO2023103013A1 PCT/CN2021/138862 CN2021138862W WO2023103013A1 WO 2023103013 A1 WO2023103013 A1 WO 2023103013A1 CN 2021138862 W CN2021138862 W CN 2021138862W WO 2023103013 A1 WO2023103013 A1 WO 2023103013A1
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WIPO (PCT)
Prior art keywords
via hole
layer
common electrode
hole
metal
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PCT/CN2021/138862
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English (en)
French (fr)
Inventor
刘倩
Original Assignee
Tcl华星光电技术有限公司
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Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Priority to JP2021576398A priority Critical patent/JP7487238B2/ja
Priority to US17/621,290 priority patent/US12038660B2/en
Publication of WO2023103013A1 publication Critical patent/WO2023103013A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1303—Apparatus specially adapted to the manufacture of LCDs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H01L27/124—
    • H01L27/1248—
    • H01L27/1288—
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes

Definitions

  • the present application relates to the field of display technology, in particular to an array substrate and a manufacturing method thereof.
  • the common electrode 91 is used as one end of liquid crystal deflection, and forms a horizontal electric field together with the pixel electrode 92 (As shown in Figure 1), the liquid crystal is deflected to realize the display.
  • the part where the pixel is used as the display area and the backlight passes through to generate the three primary colors of red, green, and blue is called the opening area.
  • the pixel electrodes 92 in the opening area for deflecting the liquid crystal are usually designed in stripes.
  • the common electrode stripe shape In the liquid crystal display mode, there are usually two designs of the common electrode stripe shape and the pixel electrode stripe shape. When one electrode is designed in a stripe shape, the other electrode is designed to cover the entire surface of the opening area. In the case of stripe-shaped pixel electrodes and frontal common electrodes, the resistance of the common electrodes will be increased, and the coupling effect of the signal disturbance of the gate lines and data lines on the capacitance formed by the common electrodes will be further increased.
  • Common electrodes are commonly prepared using halftone mask (halftone mask, HTM) process.
  • HTM halftone mask
  • the thickness of the remaining HTM photoresist film meets the process requirements and does not break the film; and there is no photoresist in the pixel electrode connection via hole.
  • the design needs to have a certain safety distance from the edge of the via hole of the common electrode photoresist to the pixel connection hole, so as to provide enough space to prevent the photoresist from falling into the connection hole.
  • the safety distance required by the current manufacturing process is quite large, resulting in an increase in the required space, thereby reducing the area of the opening area, reducing the penetration rate, increasing the power consumption of the LCD screen, and deteriorating the display effect.
  • the safety distance is not enough, when the process alignment shifts or the critical dimension fluctuates, it is easy to cause difficulty in ashing in the hole, and the common electrode under the residual photoresist cannot be etched, which becomes a foreign object in the hole, making the pixel electrode and the second The overlapping of the metal layer is abnormal and causes abnormal display.
  • the present application provides an array substrate and its manufacturing method to solve the problem that photoresist is easy to remain in the traditional common electrode in the preparation process corresponding to the pixel via hole, resulting in abnormal overlap between the pixel electrode and the second metal layer, resulting in abnormal display technology question.
  • An embodiment of the present application provides an array substrate, including a substrate, a first metal layer, a second metal layer, a first metal wiring, a second metal wiring and a thin film transistor disposed on the substrate.
  • the array substrate further includes a first passivation layer covering the thin film transistor; an organic film layer is disposed on the first passivation layer and includes a first via hole, and the first via hole is located on the Above the thin film transistor; the common electrode is arranged on the organic film layer, including a second via hole and a slow wall surrounding the second via hole, the second via hole communicates with the first via hole, and the There is a distance between the bottom edge of the slow wall and the top edge of the first via hole; the second passivation layer covers the common electrode layer and the organic film layer, and includes a first passivation layer communicating with the second via hole.
  • the through hole exposes part of the common electrode
  • the first via hole, the second via hole and the third via hole jointly define a first via hole
  • the first via hole extends to the first passivation layer, and penetrate part of the first passivation layer to expose part of the thin film transistor
  • a pixel electrode layer disposed on the second passivation layer, and connected to the The thin film transistor is connected to the common electrode through the through hole.
  • the array substrate further includes a third metal layer, the third metal layer is disposed on the common electrode and contacts the common electrode, wherein the bottom edge of the slow wall of the second via hole is in contact with the common electrode.
  • the spacing between top edges of the first vias is less than 2.5 microns.
  • the orthographic projection of the second via hole on the substrate is greater than and covers the orthographic projection of the first via hole on the substrate
  • the second passivation layer further includes a cladding wall, wherein the The cladding wall is arranged along the first communication hole, and covers the hole wall of the first via hole and the slow wall of the second via hole.
  • the array substrate further includes a second via hole, the second via hole is located on the second metal wiring, and penetrates through the second passivation layer, the common electrode, the organic film layer and part of the first passivation layer, the second via hole exposes the second metal trace, wherein the pixel electrode is connected to the second metal trace through the second via hole, the The third metal layer is electrically connected to the second metal wire through the common electrode and the pixel electrode layer through the second via hole.
  • the first metal wiring includes a gate line
  • the second metal wiring includes a data line
  • a plurality of pixel regions are defined between the gate line and the data line
  • the pixel electrode layer It includes a plurality of pixel electrodes arranged at intervals in the pixel area, and the common electrode is block-shaped and covers the pixel area.
  • the embodiment of the present application also provides a method for manufacturing an array substrate, the array substrate includes a substrate, a first metal layer, a second metal layer, a first metal wiring, a second metal wiring and thin film transistor.
  • the manufacturing method of the array substrate includes: depositing a first passivation layer on the substrate, the first passivation layer covering the thin film transistor; depositing an organic film layer on the first passivation layer; The organic film layer is patterned by an engraving process, and a first via hole is formed, and the first via hole corresponds to the top of the thin film transistor; a common electrode layer is deposited on the organic film layer; a common electrode layer is deposited on the common electrode layer A photoresist layer is deposited on it; a half-tone mask is used to perform a photolithography process on the common electrode layer to form a common electrode and a second via hole corresponding to the first via hole, and the common electrode is adjacent to the A slow wall is formed at the second via hole, wherein the halftone mask includes at least one hole-forming area and
  • the step of depositing a common electrode layer on the organic film layer further includes depositing a third metal layer on the common electrode layer;
  • the third metal layer is subjected to multiple photolithography processes to pattern the common electrode layer and the third metal layer.
  • the halftone mask further includes a film-forming area, and the slit is located between the film-forming area and the hole-forming area, wherein the film-forming area is used to form the common electrode , the hole forming area is used to form the second via hole, and the slit is used to form a slow wall surrounding the second via hole, wherein the bottom edge of the slow wall is in contact with the first via hole
  • the spacing between the top edges is less than 2.5 microns.
  • the step of forming the thin film transistor is further included before the step of depositing the first passivation layer.
  • the step of forming the thin film transistor includes: forming the first metal layer on the substrate, and the first metal layer includes a gate and a first metal wiring; Depositing a gate insulating layer on the metal layer; forming an active layer above the gate on the gate insulating layer; using a photolithography process to form a contact hole on the gate insulating layer to expose the first metal wiring; depositing a second metal layer on the active layer and the gate insulating layer; and forming a source, a drain, and a second metal wiring on the second metal layer by photolithography, wherein The second metal trace is connected to the first metal trace through the contact hole.
  • the manufacturing method of the array substrate further includes: forming a second via hole above the second passivation layer corresponding to the second metal trace, the second via hole penetrating through the second passivation layer, the common electrode layer, the organic film layer and part of the first passivation layer to expose the second metal wiring, wherein the pixel electrode layer is connected to the the second metal wiring and the first metal wiring.
  • An embodiment of the present application also provides an array substrate, including a substrate, a first metal layer, a second metal layer, a first metal wiring, a second metal wiring, a thin film transistor, and a third metal layer disposed on the substrate.
  • the first metal layer includes gate lines
  • the second metal layer includes data lines
  • a plurality of pixel regions are defined between the gate lines and the data lines.
  • the array substrate further includes: a first passivation layer covering the thin film transistor; an organic film layer disposed on the first passivation layer and including a first via hole, and the first via hole is located on the above the thin film transistor; the common electrode is arranged on the organic film layer, and includes a second via hole and a slow wall surrounding the second via hole, the second via hole communicates with the first via hole, and the There is a distance between the bottom edge of the slow wall and the top edge of the first via hole; the second passivation layer covers the common electrode and the organic film layer, and includes a first passivation layer connected to the second via hole Three via holes, and a via hole, wherein the via hole exposes part of the common electrode, and the first via hole, the second via hole and the third via hole jointly define a first via hole, and the first via hole extending to the first passivation layer and penetrating part of the first passivation layer to expose part of the thin film transistor; and a pixel electrode layer disposed on the second passivation layer through the first
  • the present application provides an array substrate and a manufacturing method thereof.
  • a half-tone mask with slits is used to carry out a photolithography process on the third metal layer and the common electrode layer, thereby adding a photomask to the hole-digging area of the common electrode layer.
  • Correction optimize the photoresist morphology at the edge of the via hole of the common electrode, reduce the thickness of the photoresist at the edge of the hole, and realize the condition that the common electrode has a small via hole edge (safety distance), and provide Sufficient space to reduce the risk of photoresist accumulation on the edge of the via hole falling into the hole of the organic film layer, effectively solving the traditional process requirements.
  • the technical problem is that the power consumption of the LCD screen increases and the display effect deteriorates.
  • the resistance of the common electrode can be reduced, and the coupling effect of the capacitance formed by the common electrode caused by the signal disturbance of the gate line and the data line can be effectively reduced.
  • FIG. 1 is a schematic structural diagram of a conventional pixel electrode and a common electrode.
  • FIG. 2 is a schematic cross-sectional structure diagram of an array substrate provided by an embodiment of the present application.
  • FIG. 3 is a flowchart of a method for manufacturing an array substrate provided in an embodiment of the present application.
  • FIG. 4 to FIG. 10 are schematic diagrams of the film layer structure obtained in each step of the method for manufacturing the array substrate provided in the embodiment of the present application.
  • FIG. 11A is a schematic diagram of the structure of the common electrode prepared in the present application.
  • FIG. 11B is a schematic plan view of the common electrode prepared in the present application.
  • the present application provides an array substrate for a liquid crystal display panel and a manufacturing method thereof.
  • the array substrate of the present application is based on a liquid crystal display panel in which a common electrode and a pixel electrode jointly form a horizontal electric field as one end of liquid crystal deflection.
  • FIG. 2 is a schematic cross-sectional structure diagram of the array substrate 1 provided by the embodiment of the present application.
  • the array substrate 1 of the present application includes a substrate 10 and a first metal layer 11 , a gate insulating layer 12 , an active layer 20 , and a second metal layer 21 stacked from bottom to top on the substrate 10 in sequence. , the third metal layer 31 , the first passivation layer 13 , the organic film layer 14 , the bulk common electrode 152 , the second passivation layer 16 and the pixel electrode layer 17 .
  • the first metal layer 11 includes a gate 111 and a first metal wire 112 ;
  • the second metal layer 21 includes a source 211 , a second metal wire 212 and a drain 213 .
  • the gate 111, gate insulating layer 12, active layer 20, source 211 and drain 213 of the present application together form a thin film transistor T
  • the second metal wiring 212 includes a data line
  • the first metal wiring 112 includes a gate line
  • the area between the data line and the gate line is defined as a pixel area (ie, a display area).
  • the organic film layer 14 is disposed on the first passivation layer 13 and includes a first via hole 140 , and the first via hole 140 is located above the TFT.
  • the common electrode 152 is disposed on the organic film layer 14 and covers the pixel area, and includes a second via hole 150 and a slow wall 151 surrounding the second via hole 150 .
  • the second via hole 150 communicates with the first via hole 140 , and there is a distance D1 between the bottom edge of the slow wall 151 and the top edge of the first via hole 140 .
  • the second passivation layer 16 covers the common electrode 15 and the organic film layer 14 , and includes a third via hole 160 connected to the second via hole 150 , and a through hole 162 , wherein the through hole 162 exposes part of the common electrode 15 .
  • the first via hole 140 , the second via hole 150 and the third via hole 160 jointly define the first communication hole 101 .
  • the first communication hole 101 extends to the first passivation layer 13 and penetrates part of the first passivation layer 13 to expose part of the TFT T.
  • the pixel electrode layer 17 includes a plurality of pixel electrodes 171 arranged at intervals, and contacts the drain electrode 213 of the second metal layer 21 through the first via hole 101 , and connects to the common electrode 15 through the via hole 162 .
  • the common electrode 152 is in a block shape, and both the pixel electrode 171 and the common electrode 152 are transparent.
  • the pixel electrode 171 and the common electrode 152 are located on the same side to jointly form a horizontal electric field to deflect the liquid crystal, thereby realizing the display function.
  • a third metal layer 31 is provided on the common electrode layer 15, and is electrically connected to the data line of the second metal trace 212 and the first metal layer 31 through the second via hole 102 through the pixel electrode 171.
  • the gate line of trace 112 Since the third metal layer 31 is directly overlapped with the common electrode 152, the resistance generated by the structure of the two is much smaller than that of only the common electrode layer, which can effectively reduce the signal disturbance caused by the gate line and the data line to the common electrode. Capacitive coupling.
  • the embodiment of the present application further provides a method for manufacturing an array substrate, that is, a method for manufacturing the array substrate 1 of the above-mentioned embodiment.
  • FIG. 3 is a flow chart of the manufacturing method of the array substrate 1 provided in the embodiment of the present application
  • FIGS. 4 to 10 are schematic diagrams of the film layer structure obtained in each step of the manufacturing method of the array substrate provided in the embodiment of the present application.
  • the manufacturing method of the array substrate 1 of the present application includes step S10 to step S90 . It is particularly noted that the step of forming the thin film transistor T is also included before the step S10 .
  • the film structure corresponding to the step of forming the thin film transistor T is shown in FIG. 4 to FIG. 7 .
  • a first metal layer 11 is formed on the substrate 10 , and the first metal layer 11 includes a gate 111 and a first metal wire 112 .
  • the first metal layer 11 is deposited on the substrate 10 using a physical vapor deposition (Physical Vapor Deposition, PVD) process, and the first metal layer 11 is patterned by a photolithography process and a wet etching process to form the gate 111 and
  • the first metal wire 112 includes a gate wire.
  • the photolithography process includes steps such as coating photoresist, prebaking, exposing using a mask, developing, postbaking, etching, and stripping photoresist.
  • the wet etching process is the same as the general wet etching process, and will not be described in detail here.
  • the material of the substrate 10 may be glass or transparent plastic, preferably glass.
  • a gate insulating layer 12 is deposited on the substrate 10 and the first metal layer 11 .
  • the gate insulating layer 12 is deposited by a chemical vapor deposition (chemical vapor deposition, CVD) process, wherein the gate insulating layer 12 is made of silicon nitride or silicon oxide.
  • the active layer 20 above the gate 111 is formed on the gate insulating layer 12 .
  • indium gallium zinc oxide indium gallium zinc oxide
  • the material of the active layer 20 can be IGZO, indium zinc tin oxide (indium zinc tin oxide, IZTO) or indium gallium zinc tin oxide (indium gallium zinc tin oxide, IGZTO) metal oxide semiconductor , preferably IGZO.
  • the active layer 20 is formed by a photolithography process and a wet etching process.
  • a contact hole 120 is formed on the gate insulating layer 12 by using a photolithography process to expose the first metal wire 112 (ie, the gate wire). Specifically, the gate insulating layer 12 is patterned by dry etching, and the contact hole 120 is formed.
  • a second metal layer 21 is deposited on the active layer 20 and the gate insulating layer 12 .
  • the second metal layer 21 is deposited by a PVD process.
  • a source 211, a drain 213, and a second metal wiring 212 are formed on the second metal layer 21 by a wet etching process, wherein the second metal wiring 212 includes a data line and is connected to the first metal wiring through the contact hole 120.
  • Wires 112 ie gate wires. Accordingly, the preparation of the thin film transistor T of the present application is completed.
  • the area between the data line and the gate line is defined as a pixel area (ie, a display area).
  • Step S10 Depositing a first passivation layer on the substrate to cover the thin film transistor. Specifically, a nitride (silicon nitride, etc.) or oxide (silicon oxide, silicon dioxide) material is deposited as the first passivation layer 13 under the film layer structure having the thin film transistor T by a CVD process.
  • a nitride silicon nitride, etc.
  • oxide silicon oxide, silicon dioxide
  • Step S20 Depositing an organic film layer on the first passivation layer.
  • the material of the organic film layer 14 may be polyfluoroalkoxy (PFA), which can further change the flatness of the lower film surface, realize planarization and prevent electric fields from interfering with each other.
  • PFA polyfluoroalkoxy
  • Step S30 patterning the organic film layer by using a photolithography process, and forming a first via hole, and the first via hole corresponds to the top of the thin film transistor.
  • the organic film layer 14 is patterned to form a first via hole 140 and a first opposite via hole 140a, wherein the first via hole 140 is located directly above the thin film transistor T, and the first opposite via hole 140a is formed.
  • the second metal wiring 212 ie, the data line
  • the first metal wiring 112 the gate line
  • Step S40 depositing a common electrode layer on the organic film layer.
  • the common electrode layer 15 is first deposited by PVD, which can be made of indium tin oxide (Indium Tin Oxide, ITO); then, the third metal layer 31 is deposited by PVD, which can be made of copper. system, wherein the common electrode layer 15 covers the pixel area.
  • PVD indium tin oxide
  • ITO Indium Tin Oxide
  • Step S50 performing a photolithography process on the common electrode layer using a half-tone mask to form a common electrode and a second via hole corresponding to the first via hole, and the common electrode is adjacent to the first via hole
  • Slow walls are formed at the two via holes, wherein the halftone mask includes at least one hole-forming area and at least one slit, the slit is arranged around and spaced from the hole-forming area, and the hole-forming area corresponds to the hole-forming area
  • the second via hole, and the slit corresponds to the slow wall, wherein there is a distance between the bottom edge of the slow wall and the top edge of the first via hole.
  • FIG. 11A is a schematic diagram of the structure of the common electrode prepared in the present application.
  • FIG. 11B is a schematic plan view of the common electrode prepared in the present application.
  • the present application uses a half-tone mask 4 to perform a multi-pass photolithography process on the common electrode layer 15 and the third metal layer 31 to pattern the common electrode layer 15 and the third metal layer 31, thereby forming a common electrode layer 15 and the third metal layer 31.
  • the electrode 152 and the patterned third metal layer 31 As shown in FIG. 11A , the halftone mask 4 is used to expose and develop the photoresist layer 40 covering the organic film layer 14 .
  • the halftone mask 4 includes a film forming area 41 , a hole forming area 42 and at least one slit 43 , and the slit 43 surrounds and is spaced from the hole forming area 42 .
  • the film forming region 41 of the halftone mask 4 is used to form the common electrode 152
  • the hole forming region 42 is used to form the second via hole 150
  • the slit 43 is used to form a buffer around the second via hole 150 .
  • Wall 151 As shown in FIG. 11B , the surrounding upper part of the second via hole 150 of the common electrode layer 15 corresponds to the slit 43 .
  • the slit 43 of the present application is used as a weak light-shielding band at the edge of the halftone mask to reduce the thickness of the photoresist near the edge of the hole.
  • the mask plate makes the slope of the via hole relatively steep, so that the photoresist layer 40 coated on the common electrode layer 15 and the third metal layer 31 in this application forms a section around the corresponding first via hole 140. Via slopes with gentle slope angles.
  • the photolithography process in step S50 includes: coating the photoresist layer 40 on the common electrode layer 15 and the third metal layer 31, and performing exposure and development.
  • the third metal layer 31 corresponds to the half-tone mask
  • the common electrode 152 corresponds to the semi-transparent area (i.e. film-forming area) of the halftone mask
  • the hole-digging area of the common electrode layer 15 and the display area That is, the periphery of the pixel area
  • the first etching is carried out, so that the third metal layer 31 corresponding to the periphery of the display area and the hole-digging area of the common electrode layer 15 is etched;
  • the photoresist is ashed and removed; after that, the second etching is performed to etch the common electrode layer 15 without the pattern position of the third metal layer 31, thereby forming the second via hole 150 of the common electrode layer 15; finally, the second etching is performed.
  • a second relative via hole 150a is formed above the corresponding first relative via hole 140a, which communicates with the first relative via hole 140a (as shown in FIG. 9 ).
  • the distance between the bottom edge of the slow wall 151 of the common electrode layer 15 and the top edge of the first via hole 140 is less than 2.5 microns, and the orthographic projection of the second via hole 150 on the substrate 10 is larger than and covers the first via hole 140. Orthographic projection of the hole 140 on the substrate 10 (as shown in FIG. 2 ).
  • the present application uses a half-tone mask with slits to perform a photolithography process on the third metal layer 31 and the common electrode layer 15, that is, to add a photomask to the hole-digging area of the common electrode layer 15 , thereby optimizing the photoresist morphology at the edge of the third via hole of the common electrode, reducing the thickness of the photoresist at the edge of the hole, and reducing the risk of photoresist accumulation at the edge of the hole falling into the hole of the organic film layer.
  • Step S60 Depositing a second passivation layer to cover the first via hole, the organic film layer and the common electrode layer. Specifically, as shown in FIG. 10 , a second passivation layer 16 is deposited on the substrate 10 through a CVD process, and its material may be silicon nitride.
  • Step S70 patterning the second passivation layer by using a photolithography process, and forming third via holes and via holes.
  • the through hole 162 exposes part of the common electrode 15 .
  • the first via hole 140, the second via hole 150 and the third via hole 160 jointly define the first via hole 101, and the first via hole 101 extends to the first passivation layer 13 and penetrates part of the first passivation layer. layer 13 to expose the drain 213 of the thin film transistor T.
  • a third opposing via hole 160 a corresponding to the second opposing via hole 150 a is formed in the second passivation layer 16 at the same time.
  • the first opposing via hole 140 a , the second opposing via hole 150 a and the third opposing via hole 160 a jointly form the second communication hole 102 .
  • the prepared second passivation layer 16 also includes a cladding wall 161 .
  • the covering wall 161 is arranged along the first communication hole 101 and is inclined from top to bottom toward the bottom of the first via hole 140 to cover the wall of the first via hole 140 and the second via hole 150 The slow wall 151 .
  • Step S80 depositing a pixel electrode layer on the second passivation layer.
  • Step S90 patterning the pixel electrode layer by photolithography to form a pixel electrode, and the pixel electrode is connected to the source of the thin film transistor through the first via hole.
  • the pixel electrode layer 17 is deposited and patterned on the substrate 10 through a PVD process to form the pixel electrode 171 .
  • the pixel electrode 171 is connected to the drain 213 of the TFT T through the first via hole 101 , and is connected to the common electrode 152 through the via hole 162 .
  • the second via hole 102 penetrates the second passivation layer 16, the common electrode layer 15, the organic film layer 14 and part of the first passivation layer 13 to expose the second metal wire 212,
  • the pixel electrode 171 is connected to the second metal wiring 212 (ie data line) of the second metal layer 21 and the first metal wiring 112 (ie gate line) of the first metal layer 11 through the second via hole 102 .
  • the present application provides an array substrate and a manufacturing method thereof.
  • a half-tone mask with slits is used to perform a photolithography process on the third metal layer and the common electrode layer, so that the hole-digging area of the common electrode layer Added optical correction of the mask, optimizes the photoresist morphology of the via hole edge of the common electrode, reduces the thickness of the photoresist at the hole edge, and can realize the condition that the common electrode has a smaller via hole edge (safety distance) It can provide enough space to reduce the risk of photoresist accumulation on the edge of the via hole falling into the hole of the organic film layer, and effectively solve the traditional process requirements. Penetration, the technical problem of increasing the power consumption of the liquid crystal display and deteriorating the display effect.
  • the resistance of the common electrode can be reduced, and the coupling effect of the capacitance formed by the common electrode caused by the signal disturbance of the gate line and the data line can be effectively reduced.

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Abstract

本申请公开一种阵列基板及其制作方法。阵列基板包括基板、薄膜晶体管、第一钝化层、有机膜层、公共电极、第二钝化层及像素电极层。有机膜层包括第一过孔。公共电极覆盖像素区域，并包括第二过孔及围绕第二过孔的缓壁。第二过孔连通第一过孔，且缓壁的底缘与第一过孔的顶缘之间具有间距。第二钝化层包括连通第二过孔的第三过孔。像素电极层设在第二钝化层上，并通过第一过孔、第二过孔及第三过孔连接第二金属层。

Description

阵列基板及其制作方法 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及其制作方法。
 背景技术
在液晶显示面板的面内开关（In-Plane Switching, IPS）模式或边界电场开关(Fringe Field Switching, FFS)的显示模式中，公共电极91作为液晶偏转的一端，与像素电极92共同形成水平电场(如图1所示)，使液晶偏转从而实现显示。以像素作为显示区域、让背光通过从而产生红、绿、蓝三原色的部分称作开口区。为改善视角及提升显示效率，通常将开口区内让液晶偏转的像素电极92设计成条纹状。在液晶显示模式中，通常有公共电极条纹状、像素电极条纹状两种设计情况。当一种电极为条纹状设计时，另一种电极为开口区整面性覆盖设计。在像素电极条纹状、公共电极正面性的情况时，会增加公共电极的电阻，更加大栅线、数据线的信号扰动对公共电极构成的电容的耦合作用。
常用制备公共电极是使用半色调掩膜(halftone mask, HTM)工艺制作，在制作流程中，由于大面积HTM以及像素电极与第二金属层联通过孔的存在，需在HTM曝光流程后，同时满足以下要求：残留HTM 光刻胶膜厚满足工艺要求且不破膜；及像素电极连通过孔中无光刻胶存在。通常情况下，为达到上述要求，设计需要将公共电极光刻胶的过孔边缘距离像素连通孔有一定的安全距离，提供足够空间以防止光刻胶掉落连通孔内。然而，目前制程要求的安全距离相当大，造成所需空间加大，从而减小开口区面积，降低穿透率，使得液晶显示屏功耗增加、显示效果变差。此外，若所述安全距离不够，则当制程对位偏移或关键尺寸波动，容易造成孔内灰化困难，残留光刻胶下公共电极无法蚀刻，成为孔内异物，使像素电极与第二金属层搭接异常，并导致显示异常。
 技术问题
本申请提供一种阵列基板及其制作方法，以解决传统公共电极在对应像素连通孔的制备工艺中容易残留光刻胶，造成像素电极与第二金属层搭接异常，从而导致显示异常的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供一种阵列基板，包括基板、设在所述基板上的第一金属层、第二金属层、第一金属走线、第二金属走线及薄膜晶体管。所述阵列基板还包括第一钝化层，覆盖所述薄膜晶体管；有机膜层，设在所述第一钝化层上，并包括第一过孔，且所述第一过孔位于所述薄膜晶体管上方；公共电极，设在所述有机膜层上，包括第二过孔及围绕所述第二过孔的缓壁，所述第二过孔连通所述第一过孔，且所述缓壁的底缘与所述第一过孔的顶缘之间具有间距；第二钝化层，覆盖所述公共电极层及所述有机膜层，并包括连通所述第二过孔的第三过孔，及通孔。所述通孔显露部分所述公共电极，且所述第一过孔、第二过孔及第三过孔共同定义第一连通孔，且所述第一连通孔延伸至所述第一钝化层，并穿透部分所述第一钝化层，用以显露部分所述薄膜晶体管；以及像素电极层，设在所述第二钝化层上，并通过所述第一连通孔连接所述薄膜晶体管，及通过所述通孔连接所述公共电极。
可选地，所述阵列基板还包括第三金属层，所述第三金属层设在所述公共电极上，并接触所述公共电极，其中所述第二过孔的缓壁的底缘与所述第一过孔的顶缘之间的所述间距小于2.5微米。
可选地，所述第二过孔在所述基板的正投影大于并覆盖所述第一过孔在所述基板的正投影，所述第二钝化层还包括包覆壁，其中所述包覆壁沿所述第一连通孔设置，并覆盖所述第一过孔的孔壁及所述第二过孔的缓壁。
可选地，所述阵列基板还包括第二连通孔，所述第二连通孔位于所述第二金属走线上，并穿透所述第二钝化层、所述公共电极、所述有机膜层及部分所述第一钝化层，所述第二连通孔显露所述第二金属走线，其中所述像素电极通过所述第二连通孔连接所述第二金属走线，所述第三金属层通过所述公共电极和所述像素电极层由第二连通孔电性连接于第二金属走线。
可选地，所述第一金属走线包括栅线，所述第二金属走线包括数据线，所述栅线及所述数据线之间定义有多个像素区域，其中所述像素电极层包括多个相互间隔设置于所述像素区域的像素电极，所述公共电极为块状，并覆盖所述像素区域。
本申请实施例还提供一种阵列基板的制作方法，所述阵列基板包括基板、设在所述基板上的第一金属层、第二金属层、第一金属走线、第二金属走线及薄膜晶体管。所述阵列基板的制作方法包括：在所述基板上沉积第一钝化层，所述第一钝化层覆盖所述薄膜晶体管；在所述第一钝化层上沉积有机膜层；利用光刻工艺图形化所述有机膜层，并形成第一过孔，且所述第一过孔对应于所述薄膜晶体管上方；在所述有机膜层上沉积公共电极层；在所述公共电极层上沉积光刻胶层；利用半色调掩膜板对所述公共电极层进行光刻工艺，以形成公共电极及对应于所述第一过孔的第二过孔，所述公共电极在相邻所述第二过孔处形成有缓壁，其中所述半色调掩膜板包括至少一成孔区及至少一狭缝，所述狭缝围绕并间隔于所述成孔区设置，所述成孔区对应所述第二过孔，且所述狭缝对应所述缓壁，其中所述缓壁的底缘与所述第一过孔的顶缘之间具有间距；沉积第二钝化层，并覆盖第一过孔、所述有机膜层及所述公共电极层；利用光刻工艺图形化所述第二钝化层，并形成第三过孔及通孔，其中所述通孔显露部分所述公共电极，且所述第一过孔、第二过孔及第三过孔共同定义第一连通孔，所述第一连通孔延伸至所述第一钝化层，并穿透部分所述第一钝化层，所述第一连通孔显露部分所述薄膜晶体管；在所述第二钝化层上沉积像素电极层；以及利用光刻工艺图形化所述像素电极层，以形成像素电极，所述像素电极层通过所述第一连通孔连接所述薄膜晶体管，及通过所述通孔连接所述公共电极。
可选地，在所述有机膜层上沉积公共电极层的步骤还包括在所述公共电极层上沉积第三金属层；及利用所述半色调掩膜板对所述公共电极层及所述第三金属层进行多道光刻工艺，以图形化所述公共电极层及所述第三金属层。
可选地，所述半色调掩膜板还包括成膜区，且所述狭缝位于所述成膜区及所述成孔区之间，其中所述成膜区用于形成所述公共电极，所述成孔区用以形成所述第二过孔，且所述狭缝用于形成围绕所述第二过孔的缓壁，其中所述缓壁的底缘与所述第一过孔的顶缘之间的间距小于2.5微米。
可选地，在沉积所述第一钝化层的步骤前还包括形成所述薄膜晶体管的步骤。所述形成所述薄膜晶体管的步骤包括：在所述基板上形成所述第一金属层，且所述第一金属层包括栅极及第一金属走线；在所述基板及所述第一金属层上沉积栅极绝缘层；在所述栅极绝缘层形成位于所述栅极上方的有源层；利用光刻工艺在所述栅极绝缘层上形成接触孔，以暴露所述第一金属走线；在所述有源层及所述栅极绝缘层上沉积第二金属层；以及利用光刻工艺在所述第二金属层形成源极、漏极及第二金属走线，其中所述第二金属走线通过所述接触孔连接所述第一金属走线。
可选地，所述阵列基板的制作方法还包括：在所述第二钝化层对应所述第二金属走线的上方形成第二连通孔，所述第二连通孔穿透所述第二钝化层、所述公共电极层、所述有机膜层及部分所述第一钝化层以显露所述第二金属走线，其中所述像素电极层通过所述第二连通孔连接所述第二金属走线及所述第一金属走线。
本申请实施例还提供一种阵列基板，包括基板、设在所述基板上的第一金属层、第二金属层、第一金属走线、第二金属走线、薄膜晶体管及第三金属层，其中所述第一金属层包括栅线，所述第二金属层包括数据线，所述栅线及所述数据线之间定义有多个像素区域。所述阵列基板还包括：第一钝化层，覆盖所述薄膜晶体管；有机膜层，设在所述第一钝化层上，并包括第一过孔，且所述第一过孔位于所述薄膜晶体管上方；公共电极，设在所述有机膜层上，包括第二过孔及围绕所述第二过孔的缓壁，所述第二过孔连通所述第一过孔，且所述缓壁的底缘与所述第一过孔的顶缘之间具有间距；第二钝化层，覆盖所述公共电极及所述有机膜层，并包括连通所述第二过孔的第三过孔，及通孔，其中所述通孔显露部分所述公共电极，且所述第一过孔、第二过孔及第三过孔共同定义第一连通孔，所述第一连通孔延伸至所述第一钝化层，并穿透部分所述第一钝化层，以显露部分所述薄膜晶体管；以及像素电极层，设在所述第二钝化层上，通过所述第一连通孔连接所述薄膜晶体管，及通过所述通孔连接所述公共电极。所述像素电极层包括多个相互间隔设置于所述像素区域的像素电极，所述公共电极为块状，并覆盖所述像素区域所述第三金属层设在所述公共电极上，并接触所述公共电极。
 有益效果
本申请提供一种阵列基板及其制作方法，利用具有狭缝的半色调掩膜板对第三金属层及公共电极层进行光刻工艺，从而对公共电极层的挖孔区新增光罩光学补正，优化公共电极的过孔边缘的光刻胶形貌，减小孔边缘的光刻胶厚度，并可实现在公共电极具有较小的过孔边缘(安全距离)的条件下，即可提供足够空间降低过孔边缘光刻胶堆积掉落有机膜层孔内风险，有效解决传统制程要求的安全距离相当大，造成所需空间加大，从而减小开口区面积，降低穿透率，使得液晶显示屏功耗增加、显示效果变差的技术问题。此外，通过第三金属层的设计，可以减小公共电极的电阻，并可有效减小栅线与数据线的信号扰动造成对公共电极构成的电容的耦合作用。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为传统的像素电极与公共电极的结构示意图。
图2为本申请实施例提供的阵列基板的剖面结构示意图。
图3为本申请实施例提供的阵列基板的制作方法的流程图。
图4至图10为本申请实施例提供的阵列基板的制备方法中各步骤制得的膜层结构示意图。
图11A为本申请制备公共电极的结构示意图。
图11B为本申请制备公共电极的平面结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。在附图中，为了清晰理解和便于描述，夸大了一些层和区域的厚度。即附图中示出的每个组件的尺寸和厚度是任意示出的，但是本申请不限于此。
本申请提供一种用于液晶显示面板的阵列基板及其制作方法。特别地，本申请的阵列基板是基于以公共电极与像素电极共同形成水平电场作为液晶偏转的一端的液晶显示面板。
请参阅图2，其为本申请实施例提供的阵列基板1的剖面结构示意图。如图2所示，本申请的阵列基板1包括基板10及依序由基板10由下往上叠置的第一金属层11、栅极绝缘层12、有源层20、第二金属层21、第三金属层31、第一钝化层13、有机膜层14、块状的公共电极152、第二钝化层16及像素电极层17。具体地，在此实施例中，第一金属层11包括栅极111及第一金属走线112；第二金属层21包括源极211、第二金属走线212及漏极213。相同于一般的薄膜晶体管结构，本申请的栅极111、栅极绝缘层12、有源层20、源极211及漏极213共同构成一薄膜晶体管T，且第二金属走线212包括数据线，第一金属走线112包括栅线，数据线及栅线之间定义为像素区域(即显示区域)。
如图2所示，有机膜层14设在第一钝化层13上，并包括第一过孔140，且第一过孔140位于薄膜晶体管T上方。公共电极152设在有机膜层14上，并覆盖所述像素区域，且包括第二过孔150及围绕第二过孔150的缓壁151。第二过孔150连通第一过孔140，且缓壁151的底缘与第一过孔140的顶缘之间具有间距D1。第二钝化层16覆盖公共电极15及有机膜层14，并包括连通第二过孔150的第三过孔160，及通孔162，其中通孔162显露部分公共电极15。特别说明的是，第一过孔140、第二过孔150及第三过孔160共同定义第一连通孔101。所述第一连通101孔延伸至第一钝化层13，并穿透部分第一钝化层13，以显露部分所述薄膜晶体管T。
在本申请实施例中，像素电极层17包括多个相互间隔设置的像素电极171，并通过第一连通孔101接触第二金属层21的漏极213，及通过通孔162连接公共电极15。如图2所示，像素电极层17，所述公共电极152为块状，且所述像素电极171及所述公共电极152皆为透明。本申请的像素电极171与公共电极152位于同一侧，以共同形成水平电场使液晶偏转，从而实现显示功能。
续请参阅图2，本申请在公共电极层15上设置有第三金属层31，且通过像素电极171由第二连通孔102电性连接于第二金属走线212的数据线及第一金属走线112的栅线。由于第三金属层31与公共电极152直接搭接，两者构成的结构所产生的电阻远比只有公共电极层小，从而可以有效减小栅线与数据线的信号扰动造成对公共电极构成的电容的耦合作用。上述本申请实施例的阵列基板1的制作方法及细部构造如后所述。
本申请实施例另外提供一种阵列基板的制作方法，亦即，一种用于制作上述实施例的阵列基板1的方法。
请参阅图3及图4至图10。图3为本申请实施例提供的阵列基板1的制作方法的流程图，图4至图10为本申请实施例提供的阵列基板的制备方法中各步骤制得的膜层结构示意图。如图3所示，本申请阵列基板1的制作方法包括步骤S10~步骤S90。特别说明的是，在步骤S10之前还包括形成所述薄膜晶体管T的步骤。
所述形成薄膜晶体管T的步骤所对应的膜层结构如图4至图7所示。
如图4所示，在基板10上形成第一金属层11，且所述第一金属层11包括栅极111及第一金属走线112。具体的，利用物理气相沉积(physical vapor deposition，PVD)工艺在基板10上沉积第一金属层11，并通过光刻工艺及湿法刻蚀工艺图形化第一金属层11以形成栅极111及第一金属走线112，其包括栅线。需要注意的是，所述光刻工艺包括涂布光刻胶、预焙、采用掩模板曝光、显影、后焙、蚀刻、剥离光刻胶等工序。所述湿法刻蚀工艺与一般湿法刻蚀的流程相同，与此不再详述。此外，基板10的材料可为玻璃或透明塑料等材料，优选为玻璃。
请参阅图5，在基板10及第一金属层11上沉积栅极绝缘层12。具体地，通过化学气相沉积(chemical vapor deposition，CVD)工艺沉积栅极绝缘层12，其中栅极绝缘层12为氮化硅或氧化硅所制。
续请参阅图5，在栅极绝缘层12形成位于栅极111上方的有源层20。具体地，通过PVD工艺沉积铟镓锌氧化物(indium gallium zinc oxide, IGZO)作为有源层20。在此实施例中，有源层20的材料可以是IGZO、铟锌锡氧化物(indium zinc tin oxide, IZTO)或铟镓锌锡氧化物(indium gallium zinc tin oxide, IGZTO)的金属氧化物半导体，优选为IGZO。通过光刻工艺及湿法刻蚀工艺形成有源层20。
请参阅图6，利用光刻工艺在栅极绝缘层12上形成接触孔120，以暴露第一金属走线112(即栅线)。具体地，通过干法刻蚀图形化栅极绝缘层12，并形成接触孔120。
请参阅图7，在有源层20及栅极绝缘层12上沉积第二金属层21。具体地，通过PVD工艺沉积第二金属层21。此外，利用湿法刻蚀工艺在第二金属层21形成源极211、漏极213及第二金属走线212，其中第二金属走线212包括数据线，并通过接触孔120连接第一金属走线112(即栅线)。据此，本申请的薄膜晶体管T的制备完成。特别说明的是，数据线和栅线之间定义为像素区域(即显示区域)。
请参阅图8为对应本申请的的制作方法的步骤S10所制作的膜层结构。步骤S10：在基板上沉积第一钝化层，以覆盖薄膜晶体管。具体地，通过CVD工艺在前述具有薄膜晶体管T的膜层结构下沉积氮化物(氮化硅等)、氧化物(氧化硅、二氧化硅)的材料作为第一钝化层13。
步骤S20：在第一钝化层上沉积有机膜层。具体地，有机膜层14的材料可为全氟烧基乙烯基醚共聚物(Polyfluoroalkoxy,PFA)，其可进一步改变下层膜表面的平整性，实现平坦化并防止电场互相干扰。
步骤S30：利用光刻工艺图形化有机膜层，并形成第一过孔，且所述第一过孔对应于薄膜晶体管上方。如图8所示，有机膜层14经过图性化后形成第一过孔140及第一相对过孔140a，其中第一过孔140位于薄膜晶体管T的正上方，第一相对过孔140a形成在第二金属走线212(即数据线)上方，亦即，位在第一金属走线112(栅线)上方。
步骤S40：在有机膜层上沉积公共电极层。具体地，如图8所示，通过PVD先沉积公共电极层15，其可为氧化铟锡(Indium Tin Oxide, ITO)所制；接着，通过PVD沉积第三金属层31，其可为铜所制，其中公共电极层15覆盖所述像素区域。
步骤S50：利用半色调掩膜板对所述公共电极层进行光刻工艺，以形成公共电极及对应于所述第一过孔的第二过孔，且所述公共电极在相邻所述第二过孔处形成缓壁，其中所述半色调掩膜板包括至少一成孔区及至少一狭缝，所述狭缝围绕并间隔于所述成孔区设置，所述成孔区对应所述第二过孔，且所述狭缝对应所述缓壁，其中所述缓壁的底缘与所述第一过孔的顶缘之间具有间距。
请参阅图9并配合图11A及图11B。图11A为本申请制备公共电极的结构示意图。图11B为本申请制备公共电极的平面结构示意图。如图11A所示，本申请利用半色调掩膜板4对公共电极层15及第三金属层31进行多道光刻工艺，以图形化公共电极层15及第三金属层31，从而形成公共电极152及图形化的第三金属层31。如图11A所示，半色调掩膜板4用于对覆盖在有机膜层14上的光刻胶层40进行曝光显影。在此实施例中，半色调掩膜板4包括成膜区41、成孔区42及至少一狭缝43，且狭缝43围绕并间隔于所述成孔区42。特别说明的是，半色调掩膜板4的成膜区41用于形成公共电极152，成孔区42以形成第二过孔150，且狭缝43用于形成围绕第二过孔150的缓壁151。如图11B所示，公共电极层15的第二过孔150的周围上方对应于狭缝43。本申请的狭缝43作为半色调掩膜板边缘弱遮光带，以降低靠近孔边缘光刻胶的厚度。
进一步说，由于半色调掩膜板4上的狭缝43，会有部分光透过狭缝43，并在光与其下方的膜层界面发生反射，于是不同于现有技术中不带有狭缝的掩膜板而使得过孔坡度较陡的情况，使得本申请涂布在公共电极层15及第三金属层31上的光刻胶层40，在对应第一过孔140的周围形成了一段坡度角较缓的过孔坡度。
具体地，步骤S50的光刻工艺包括：在公共电极层15及第三金属层31上涂布光刻胶层40，并进行曝光显影，此时，第三金属层31对应于半色调掩膜板的不透光区(即成膜区)，公共电极152对应于半色调掩膜板的半透光区(即成膜区)，而公共电极层15的挖孔区和所述显示区域(即像素区域)外围对应半色调掩膜板的透光区(即成孔区)。之后，进行第一次刻蚀，使对应所述显示区域外围及公共电极层15的挖孔区的第三金属层31被刻蚀；接着，进行灰化工艺，将所述刻蚀后残留的光刻胶灰化去掉；之后，进行第二次刻蚀，将无第三金属层31图形位置的公共电极层15刻蚀，从而形成公共电极层15的第二过孔150；最后，进行第三次刻蚀，将对应于半透光区的第三金属层31刻蚀，留下半透光区下的公共电极图形，以及被光刻胶保护的第三金属层31及第三金属层31下方的公共电极152图形；之后，将第三金属层31上的光刻胶去除，从而完成步骤S50的光刻工艺。此外，在制备完第二过孔150的过程中，同时在对应于第一相对过孔140a的上方形成第二相对过孔150a，其连通于第一相对过孔140a(如图9所示)。
通过上述步骤，公共电极层15的缓壁151的底缘与第一过孔140的顶缘之间的间距小于2.5微米，且第二过孔150在基板10的正投影大于并覆盖第一过孔140在基板10的正投影(如图2所示)。换句话说，本申请利用具有狭缝的半色调掩膜板对第三金属层31及公共电极层15进行光刻工艺，亦即，对公共电极层15的挖孔区新增光罩光学补正，从而优化公共电极的第三过孔边缘的光刻胶形貌，减小孔边缘的光刻胶厚度，降低孔边缘光刻胶堆积掉落有机膜层孔内风险。
步骤S60：沉积第二钝化层，并覆盖第一过孔、所述有机膜层及所述公共电极层。具体地，如图10所示，通过CVD工艺在基板10上沉积第二钝化层16，其材料可为氮化硅。
步骤S70：利用光刻工艺图形化所述第二钝化层，并形成第三过孔及通孔。具体地，如图10所示，通孔162显露部分公共电极15。第一过孔140、第二过孔150及第三过孔160共同定义第一连通孔101，且所述第一连通孔101延伸至第一钝化层13，并穿透部分第一钝化层13，以显露所述薄膜晶体管T的漏极213。此外，在形成第三过孔160的过程中，同时形成在第二钝化层16对应第二相对过孔150a的第三相对过孔160a。如图10所示，第一相对过孔140a、第二相对过孔150a及第三相对过孔160a共同形成第二连通孔102。
此外，制备完成的第二钝化层16还包括包覆壁161。所述包覆壁161沿第一连通孔101设置，并由上往下朝第一过孔140的底部内倾斜，以覆盖所述第一过孔140的孔壁及所述第二过孔150的缓壁151。
步骤S80：在所述第二钝化层上沉积像素电极层。
步骤S90：利用光刻工艺图形化所述像素电极层，以形成像素电极，且所述像素电极通过所述第一连通孔连接所述薄膜晶体管的源极。具体地，如图2所示，通过PVD工艺在基板10上沉积并图形化像素电极层17，以形成像素电极171。如图2所示，像素电极171通过第一连通孔101连接薄膜晶体管T的漏极213，并通过所述通孔162连接公共电极152。
续请参阅图2，第二连通孔102穿透第二钝化层16、公共电极层15、有机膜层14及部分所述第一钝化层13以显露所述第二金属走线212，其中所述像素电极171通过所述第二连通孔102连接第二金属层21的第二金属走线212(即数据线)及第一金属层11的第一金属走线112(即栅线)。
综上所述，本申请提供一种阵列基板及其制作方法，利用具有狭缝的半色调掩膜板对第三金属层及公共电极层进行光刻工艺，从而对公共电极层的挖孔区新增光罩光学补正，优化公共电极的过孔边缘的光刻胶形貌，减小孔边缘的光刻胶厚度，并可实现在公共电极具有较小的过孔边缘(安全距离)的条件下，即可提供足够空间降低过孔边缘光刻胶堆积掉落有机膜层孔内风险，有效解决传统制程要求的安全距离相当大，造成所需空间加大，从而减小开口区面积，降低穿透率，使得液晶显示屏功耗增加、显示效果变差的技术问题。此外，通过第三金属层的设计，可以减小公共电极的电阻，并可有效减小栅线与数据线的信号扰动造成对公共电极构成的电容的耦合作用。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (14)

  1. 一种阵列基板，包括基板、设在所述基板上的第一金属层、第二金属层、第一金属走线、第二金属走线及薄膜晶体管，所述阵列基板还包括：
    第一钝化层，覆盖所述薄膜晶体管；
    有机膜层，设在所述第一钝化层上，并包括第一过孔，且所述第一过孔位于所述薄膜晶体管上方；
    公共电极，设在所述有机膜层上，包括第二过孔及围绕所述第二过孔的缓壁，所述第二过孔连通所述第一过孔，且所述缓壁的底缘与所述第一过孔的顶缘之间具有间距；
    第二钝化层，覆盖所述公共电极及所述有机膜层，并包括连通所述第二过孔的第三过孔，及通孔，其中所述通孔显露部分所述公共电极，且所述第一过孔、第二过孔及第三过孔共同定义第一连通孔，所述第一连通孔延伸至所述第一钝化层，并穿透部分所述第一钝化层，以显露部分所述薄膜晶体管；以及
    像素电极层，设在所述第二钝化层上，通过所述第一连通孔连接所述薄膜晶体管，及通过所述通孔连接所述公共电极。
  2. 如权利要求1所述的阵列基板，其中所述阵列基板还包括第三金属层，所述第三金属层设在所述公共电极上，并接触所述公共电极，其中所述第二过孔的缓壁的底缘与所述第一过孔的顶缘之间的所述间距小于2.5微米。
  3. 如权利要求1所述的阵列基板，其中所述第二过孔在所述基板的正投影大于并覆盖所述第一过孔在所述基板的正投影，所述第二钝化层还包括包覆壁，其中所述包覆壁沿所述第一连通孔设置，并覆盖所述第一过孔的孔壁及所述第二过孔的缓壁。
  4. 如权利要求2所述的阵列基板，其中所述阵列基板还包括第二连通孔，所述第二连通孔位于所述第二金属走线上，并穿透所述第二钝化层、所述公共电极、所述有机膜层及部分所述第一钝化层，所述第二连通孔显露所述第二金属走线，其中所述像素电极通过所述第二连通孔连接所述第二金属走线，所述第三金属层通过所述公共电极和所述像素电极层由第二连通孔电性连接于第二金属走线。
  5. 如权利要求1所述的阵列基板，其中所述第一金属层包括栅线，所述第二金属层包括数据线，所述栅线及所述数据线之间定义有多个像素区域，其中所述像素电极层包括多个相互间隔设置于所述像素区域的像素电极，所述公共电极为块状，并覆盖所述像素区域。
  6. 一种阵列基板的制作方法，所述阵列基板包括基板、设在所述基板上的第一金属层、第二金属层、第一金属走线、第二金属走线及薄膜晶体管，所述制作方法包括：
    在所述基板上沉积第一钝化层，所述第一钝化层覆盖所述薄膜晶体管；
    在所述第一钝化层上沉积有机膜层；
    利用光刻工艺图形化所述有机膜层，并形成第一过孔，且所述第一过孔对应于所述薄膜晶体管上方；
    在所述有机膜层上沉积公共电极层；
    利用半色调掩膜板对所述公共电极层进行光刻工艺，以形成公共电极及对应于所述第一过孔的第二过孔，所述公共电极在相邻所述第二过孔处形成有缓壁，其中所述半色调掩膜板包括至少一成孔区及至少一狭缝，所述狭缝围绕并间隔于所述成孔区设置，所述成孔区对应所述第二过孔，且所述狭缝对应所述缓壁，其中所述缓壁的底缘与所述第一过孔的顶缘之间具有间距；
    沉积第二钝化层，并覆盖第一过孔、所述有机膜层及所述公共电极层；
    利用光刻工艺图形化所述第二钝化层，并形成第三过孔及通孔，其中所述通孔显露部分所述公共电极，且所述第一过孔、第二过孔及第三过孔共同定义第一连通孔，所述第一连通孔延伸至所述第一钝化层，并穿透部分所述第一钝化层，所述第一连通孔显露部分所述薄膜晶体管；
    在所述第二钝化层上沉积像素电极层；以及
    利用光刻工艺图形化所述像素电极层，以形成像素电极，所述像素电极层通过所述第一连通孔连接所述薄膜晶体管，及通过所述通孔连接所述公共电极。
  7. 如权利要求6所述的阵列基板的制作方法，其中在所述有机膜层上沉积公共电极层的步骤还包括：
    在所述公共电极层上沉积第三金属层；及
    利用所述半色调掩膜板对所述公共电极层及所述第三金属层进行多道光刻工艺，以图形化所述公共电极层及所述第三金属层。
  8. 如权利要求6所述的阵列基板的制作方法，其中所述半色调掩膜板还包括成膜区，且所述狭缝位于所述成膜区及所述成孔区之间，其中所述成膜区用于形成所述公共电极，所述成孔区用以形成所述第二过孔，且所述狭缝用于形成围绕所述第二过孔的缓壁，其中所述缓壁的底缘与所述第一过孔的顶缘之间的间距小于2.5微米。
  9. 如权利要求6所述的阵列基板的制作方法，其中在沉积所述第一钝化层的步骤前还包括形成所述薄膜晶体管的步骤，其中所述形成所述薄膜晶体管的步骤包括：
    在所述基板上形成所述第一金属层，且所述第一金属层包括栅极及第一金属走线；
    在所述基板及所述第一金属层上沉积栅极绝缘层；
    在所述栅极绝缘层形成位于所述栅极上方的有源层；
    利用光刻工艺在所述栅极绝缘层上形成接触孔，以暴露所述第一金属走线；
    在所述有源层及所述栅极绝缘层上沉积第二金属层；以及
    利用光刻工艺在所述第二金属层形成源极、漏极及第二金属走线，其中所述第二金属走线通过所述接触孔连接所述第一金属走线。
  10. 如权利要求9所述的阵列基板的制作方法，其中所述阵列基板的制作方法还包括：
    在所述第二钝化层对应所述第二金属走线的上方形成第二连通孔，所述第二连通孔穿透所述第二钝化层、所述公共电极层、所述有机膜层及部分所述第一钝化层以显露所述第二金属走线，其中所述像素电极层通过所述第二连通孔连接所述第二金属走线及所述第一金属走线。
  11. 一种阵列基板，包括基板、设在所述基板上的第一金属层、第二金属层、第一金属走线、第二金属走线、薄膜晶体管及第三金属层，其中所述第一金属层包括栅线，所述第二金属层包括数据线，所述栅线及所述数据线之间定义有多个像素区域，所述阵列基板还包括：
    第一钝化层，覆盖所述薄膜晶体管；
    有机膜层，设在所述第一钝化层上，并包括第一过孔，且所述第一过孔位于所述薄膜晶体管上方；
    公共电极，设在所述有机膜层上，包括第二过孔及围绕所述第二过孔的缓壁，所述第二过孔连通所述第一过孔，且所述缓壁的底缘与所述第一过孔的顶缘之间具有间距；
    第二钝化层，覆盖所述公共电极及所述有机膜层，并包括连通所述第二过孔的第三过孔，及通孔，其中所述通孔显露部分所述公共电极，且所述第一过孔、第二过孔及第三过孔共同定义第一连通孔，所述第一连通孔延伸至所述第一钝化层，并穿透部分所述第一钝化层，以显露部分所述薄膜晶体管；以及
    像素电极层，设在所述第二钝化层上，通过所述第一连通孔连接所述薄膜晶体管，及通过所述通孔连接所述公共电极；
    其中所述像素电极层包括多个相互间隔设置于所述像素区域的像素电极，所述公共电极为块状，并覆盖所述像素区域所述第三金属层设在所述公共电极上，并接触所述公共电极。
  12. 如权利要求11所述的阵列基板，其中所述第二过孔的缓壁的底缘与所述第一过孔的顶缘之间的所述间距小于2.5微米。
  13. 如权利要求11所述的阵列基板，其中所述第二过孔在所述基板的正投影大于并覆盖所述第一过孔在所述基板的正投影，所述第二钝化层还包括包覆壁，其中所述包覆壁沿所述第一连通孔设置，并覆盖所述第一过孔的孔壁及所述第二过孔的缓壁。
  14. 如权利要求11所述的阵列基板，其中所述阵列基板还包括第二连通孔，所述第二连通孔位于所述第二金属走线上，并穿透所述第二钝化层、所述公共电极、所述有机膜层及部分所述第一钝化层，所述第二连通孔显露所述第二金属走线，其中所述像素电极通过所述第二连通孔连接所述第二金属走线，所述第三金属层通过所述公共电极和所述像素电极层由第二连通孔电性连接于第二金属走线。
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