CN107240590B - 阵列基板及其制作方法 - Google Patents

阵列基板及其制作方法 Download PDF

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CN107240590B
CN107240590B CN201710606999.8A CN201710606999A CN107240590B CN 107240590 B CN107240590 B CN 107240590B CN 201710606999 A CN201710606999 A CN 201710606999A CN 107240590 B CN107240590 B CN 107240590B
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CN107240590A (zh
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张占东
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Wuhan China Star Optoelectronics Technology Co Ltd
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Abstract

本发明提供了一种阵列基板，包括基板、依次设置于基板上的缓冲层、有源层、栅极绝缘层、栅极、层间绝缘层、经层间绝缘层的第一过孔以及栅极绝缘层的第二过孔与有源层接触的源极、平坦层、公共电极、钝化层，公共电极上位于有源层处设有第四过孔，平坦层上位于第四过孔处设有第三过孔，在钝化层上设有贯通第四过孔、第三过孔、平坦层、层间绝缘层、栅极绝缘层的第五过孔，在钝化层上还设置有像素电极，所述像素电极经第五过孔与有源层接触。本发明还提供了一种阵列基板的制作方法。与现有技术相比，有效防止在层间绝缘层到钝化层制作中所产生的静电传输至有源层造成静电释放，避免有源层被炸伤，导致产品性能失效的问题，进一步提升产品的品质。

Description

阵列基板及其制作方法
技术领域
本发明涉及一种显示面板技术，特别是一种低温多晶硅的阵列基板及其制作方法。
背景技术
在低温多晶硅液晶显示面板(LTPS TFT(thin film transistor)LCD(liquidcrystal display))在传统的薄膜晶体管阵列基板的制作工艺流程中，首先于基板上依次制作缓冲层、有源层、栅极绝缘层、栅极、然后制作层间绝缘层并进行蚀刻至有源层的源漏极端的过孔，过孔均将有源层的部分裸露，然后制作源\漏极、制作平坦层、公共电极、钝化层以及像素电极，像素电极与漏极接触；在传统工艺中，用于像素电极与有源层接触的过孔从层间绝缘层开始即成形，在层间绝缘层(ILD)刻蚀后用于与像素电极接触的有源层(poly)为裸露状态；在后面的制程中，如源\漏极(SD)、平坦层(PLN)、公共电极(Com ITO)、钝化层(PV CVD)、像素电极(Pixel ITO)，会将产生的静电及易传递至有源层(多晶硅polySi)，从而导致位于层间绝缘层过孔与栅极处的有源层发生静电释放(ESD、Electro-Staticdischarge)炸伤，造成制程异常，影响产品品质。
发明内容
为克服现有技术的不足，本发明提供一种阵列基板及其制作方法，防止制作中产生的静电传输至有源层造成静电释放，避免产品性能失效，提升产品品质。
本发明提供了一种阵列基板，包括基板、依次设置于基板上的缓冲层、有源层、栅极绝缘层、栅极、层间绝缘层、经层间绝缘层的第一过孔以及栅极绝缘层的第二过孔与有源层接触的源极、平坦层、公共电极、钝化层，所述公共电极上位于有源层处设有第四过孔，平坦层上位于第四过孔处设有第三过孔，在钝化层上设有贯通第四过孔、第三过孔、平坦层、层间绝缘层、栅极绝缘层的第五过孔，在钝化层上还设置有像素电极，所述像素电极经第五过孔与有源层接触。
进一步地，所述第三过孔与第四过孔设置在同一轴线上。
进一步地，所述第五过孔由设于栅极绝缘层上的第六过孔、设于层间绝缘层上的第七过孔、设于第三过孔中的第八过孔、设于第四过孔中的第九过孔以及设于钝化层上的第十过孔构成，所述第六过孔、第七过孔、第八过孔、第九过孔以及第十过孔设置在同一轴线上。
进一步地，所述第五过孔与第三过孔以及第四过孔设置在同一轴线上。
进一步地，所述第六过孔、第七过孔、第八过孔、第九过孔以及第十过孔的孔径相等且小于第四过孔的孔径。
本发明还提供了一种阵列基板的制作方法，包括如下步骤：
提供一基板；
在基板上制作缓冲层；
在缓冲层上制作有源层；
在缓冲层以及缓冲层上制作栅极绝缘层；
在栅极绝缘层上位于有源层处制作栅极；
在栅极以及栅极绝缘层上制作层间绝缘层；
在层间绝缘层上以及栅极绝缘层位于有源层的一端制作有第一过孔、第二过孔；
在层间绝缘层上制作源极，源极经第一过孔、第二过孔与有源层接触；
在源极上以及层间绝缘层上制作平坦层，在平坦层上位于有源层另一端相对的位置处制作第三过孔；
在平坦层上制作公共电极并在公共电极上位于第三过孔处制作第四过孔；
在公共电极上制作钝化层，所述钝化层填充第三过孔、第四过孔；
在钝化层上位于第四过孔处制作贯通第四过孔、第三过孔、层间绝缘层、栅极绝缘层的第五过孔；
在钝化层上制作像素电极，像素电极经第五过孔与有源层的另一端接触。
进一步地，所述第三过孔与第四过孔设置在同一轴线上。
进一步地，所述第五过孔由设于栅极绝缘层上的第六过孔、设于层间绝缘层上的第七过孔、设于第三过孔中的第八过孔、设于第四过孔中的第九过孔以及设于钝化层上的第十过孔构成，所述第六过孔、第七过孔、第八过孔、第九过孔以及第十过孔设置在同一轴线上。
进一步地，所述第五过孔与第三过孔以及第四过孔设置在同一轴线上。
进一步地，所述第六过孔、第七过孔、第八过孔、第九过孔以及第十过孔的孔径相等且小于第四过孔的孔径。
本发明与现有技术相比，通过在制作用于与有源层接触的源漏极时仅制作源极，而用于连接像素电极与有源层的漏极不制作，使得有源层用于连接像素电极的一端从层间绝缘层至钝化层的制作中均被保护起来，从而有效防止在层间绝缘层到钝化层制作中所产生的静电传输至有源层造成静电释放，避免有源层被炸伤，导致产品性能失效的问题，进一步提升产品的品质。
附图说明
图1是本发明制作层间绝缘层的结构示意图；
图2是本发明在层间绝缘层上制作过孔的结构示意图；
图3是本发明制作源极的结构示意图；
图4是本发明制作平坦层、公共电极以及钝化层的结构示意图；
图5是本发明制作第五过孔的结构示意图；
图6是本发明制作像素电极的结构示意图。
具体实施方式
下面结合附图和实施例对本发明作进一步详细说明。
如图6所示，本发明的阵列基板包括基板1、依次设置于基板1上的缓冲层2、有源层3、栅极绝缘层4、栅极5、层间绝缘层6、经层间绝缘层6的第一过孔13以及栅极绝缘层4的第二过孔14与有源层3接触的源极7、平坦层8、公共电极9、钝化层10；所述公共电极9上位于有源层3处设有第四过孔91，平坦层8上位于第四过孔91处设有第三过孔81，在钝化层10上设有贯通第四过孔91、第三过孔81、平坦层8、层间绝缘层6、栅极绝缘层4的第五过孔11，在钝化层10上还设置有像素电极12，所述像素电极12经第五过孔11与有源层3接触。
有源层3包括未掺杂层31、分别设置于未掺杂层31两侧的重掺杂层33及设置于重掺杂层33和未掺杂层31之间的轻掺杂层32。这里，轻掺杂层32为N型轻掺杂层，重掺杂层33为N型重掺杂层，但本发明并不限制于此，例如轻掺杂层32也可以为P型轻掺杂层，重掺杂层33也可以为P型重掺杂层，源极7以及像素电极12分别与重掺杂层33接触，第一过孔13和第二过孔14设于其中一个重掺杂层33处，第三过孔81、第四过孔91及第五过孔11设于另一个重掺杂层33处，所述有源层由低温多晶硅(Poly-Si)构成。
所述第一过孔13的孔径大于第二过孔14的孔径，并且设置在同一轴线上，第一过孔13和第二过孔14均为倒梯形孔。
所述第三过孔81与第四过孔91设置在同一轴线上并且第三过孔81的孔径大于第四过孔91的孔径。
本发明中，第五过孔11由设于栅极绝缘层4上的第六过孔41、设于层间绝缘层6上的第七过孔61、设于第三过孔81中的第八过孔82、设于第四过孔91中的第九过孔92以及设于钝化层10上的第十过孔101构成，所述第六过孔41、第七过孔61、第八过孔82、第九过孔92以及第十过孔101设置在同一轴线上；其中，所述第五过孔11与第三过孔81以及第四过孔91设置在同一轴线上；第六过孔41、第七过孔61、第八过孔82、第九过孔92以及第十过孔101的孔径相等且小于第四过孔91的孔径。
本发明的阵列基板的制作方法包括如下步骤：
步骤一、提供一基板1；
步骤二、在基板1上制作缓冲层2，具体地，缓冲层2可采用化学气相沉积CVD进行制作，缓冲层2可以是SiNx/SiOx结构，但本发明并不限制于此，例如缓冲层2也可以是单层的SiNx结构或SiOx结构。；
步骤三、在缓冲层2上制作有源层3，具体地，利用等离子体增强化学气相沉积法(PECVD)在缓冲层2上制作形成非晶硅层；接着，以利用准分子镭射使所述非晶硅层再结晶，从而生成低温多晶硅(Poly-Si)的有源层3。有源层3包括未掺杂层31、分别设置于未掺杂层31两侧的重掺杂层33及设置于重掺杂层33和未掺杂层31之间的轻掺杂层32。这里，轻掺杂层32为N型轻掺杂层，重掺杂层33为N型重掺杂层，但本发明并不限制于此，例如轻掺杂层32也可以为P型轻掺杂层，重掺杂层33也可以为P型重掺杂层；
步骤四、在缓冲层2以及缓冲层上制作栅极绝缘层4，具体地，栅极绝缘层4可以是SiNx/SiOx结构，但本发明并不限制于此，例如栅极绝缘层4也可以是单层的SiNx结构或SiOx结构，本发明中栅极绝缘层4可采用化学气相沉积CVD制备得到，在此不做具体；
步骤五、在栅极绝缘层4上位于有源层3处制作栅极5，具体地，栅极5正对未掺杂层31，栅极5可以是钼铝钼(MoAlMo)结构或钛铝钛(TiAlTi)结构，也可以是单层的钼结构或者单层的铝结构，但本发明并不限制于此；本发明中栅极5可采用物理气相沉积工艺形成栅极层后通过图形化工艺制作得到，但在此不做具体；
步骤六、如图1所示，在栅极5以及栅极绝缘层4上制作层间绝缘层6，具体地，层间绝缘层6可以是SiNx/SiOx结构，但本发明并不限制于此，例如层间绝缘层6也可以是单层的SiNx结构或SiOx结构，本发明中层间绝缘层6可采用化学气相沉积CVD制备得到，在此不做具体；
步骤七、如图2所示，在层间绝缘层6上以及栅极绝缘层4位于有源层3的一端制作有第一过孔13、第二过孔14，具体地，第一过孔13以及第二过孔14设于其中一重掺杂层33处，并将该重掺杂层33裸露，第一过孔13以及第二过孔14可采用蚀刻工艺制备得到，在此不做具体限定；
步骤八、如图3所示，在层间绝缘层6上制作源极7，源极7经第一过孔13、第二过孔14与有源层3接触，具体地，源极7可采用钼铝钼(MoAlMo)结构或钛铝钛(TiAlTi)结构，也可以是单层的钼结构或者单层的铝结构，但本发明并不限制于此；所述源极7经第一过孔13、第二过孔14与重掺杂层33接触，第一过孔13的孔径大于第二过孔14的孔径，并且设置在同一轴线上，第一过孔13和第二过孔14均为倒梯形孔，所述源极7可采用物理气相沉积制作得到源极层后通过图形化工艺制备得到，在此不做具体限定；
步骤九、如图4所示，在源极7上以及层间绝缘层6上制作平坦层8，在平坦层8上位于有源层3另一端相对的位置处制作第三过孔81，具体地，第三过孔81设置在另一个重掺杂层33上方；
步骤十、如图4所示，在平坦层8上制作公共电极9并在公共电极9上位于第三过孔81处制作第四过孔91，具体地，第四过孔91的孔径大于第三过孔81的孔径且两者设置在同一轴线上；公共电极9通过在物理气相沉积在平坦层8上形成透明导电膜后通过蚀刻工艺制备得到，在此不做具体限定；
步骤十一、如图4所示，在公共电极9上制作钝化层10，所述钝化层10填充第三过孔81、第四过孔91，具体地，钝化层10可以是SiNx结构，钝化层10可通过化学气相沉积CVD制备得到，在此不作具体限定；
步骤十二、如图5所示，在钝化层10上位于第四过孔91处制作贯通第四过孔91、第三过孔81、层间绝缘层6、栅极绝缘层4的第五过孔11，所述第五过孔11与第三过孔81以及第四过孔91设置在同一轴线上；具体地，第五过孔11将另一个重掺杂层33裸露，所述第五过孔11由设于栅极绝缘层4上的第六过孔41、设于层间绝缘层6上的第七过孔61、设于第三过孔81中的第八过孔82、设于第四过孔91中的第九过孔92以及设于钝化层10上的第十过孔101构成，所述第六过孔41、第七过孔61、第八过孔82、第九过孔92以及第十过孔101设置在同一轴线上,第六过孔41、第七过孔61、第八过孔82、第九过孔92以及第十过孔101的孔径相等且小于第四过孔91的孔径，上述过孔可通过蚀刻工艺制备得到，在此不做具体限定；
步骤十三、如图6所示，在钝化层10上制作像素电极12，像素电极12经第五过孔11与有源层4的另一端接触，具体地，像素电极12直接与另一个重掺杂层33接触，像素电极12可通过在钝化层10上以物理气相沉积PVD制备方法在钝化层10上形成透明导电膜后通过蚀刻工艺制备得到，在此不做限定。
本发明与传统的LTPS工艺结构相比，在层间绝缘层上仅在其中一重掺杂层开设过孔用于源极与有源层的连接，另一个用于与像素电极接触的重掺杂层不开孔，从而在层间绝缘层至钝化层制程均被保护，有效防止层间绝缘层至钝化层制程的静电传输至有源层造成静电释放从而导致将有源层炸伤，这样能够避免产品性能失效，提升产品品质。
虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (5)

1.一种阵列基板的制作方法，其特征在于：包括如下步骤：
提供一基板(1)；
在基板(1)上制作缓冲层(2)；
在缓冲层(2)上制作有源层(3)；
在缓冲层(2)以及有源层(3)上制作栅极绝缘层(4)；
在栅极绝缘层(4)上位于有源层(3)处制作栅极(5)；
在栅极(5)以及栅极绝缘层(4)上制作层间绝缘层(6)；
在层间绝缘层(6)上以及栅极绝缘层(4)位于有源层(3)的一端制作有第一过孔(13)、第二过孔(14)；
在层间绝缘层(6)上制作源极(7)，源极(7)经第一过孔(13)、第二过孔(14)与有源层(3)接触；
在源极(7)上以及层间绝缘层(6)上制作平坦层(8)，在平坦层(8)上位于有源层(3)另一端相对的位置处制作第三过孔(81)，所述第三过孔(81)仅贯穿所述平坦层(8)；
在平坦层(8)上制作公共电极(9)并在公共电极(9)上位于第三过孔(81)处制作第四过孔(91)；
在公共电极(9)上制作钝化层(10)，所述钝化层(10)填充第三过孔(81)、第四过孔(91)；
在钝化层(10)上位于第四过孔(91)处制作贯通第四过孔(91)、第三过孔(81)、层间绝缘层(6)、栅极绝缘层(4)的第五过孔(11)；
在钝化层(10)上制作像素电极(12)，像素电极(12)经第五过孔(11)与有源层(4)的另一端接触。
2.根据权利要求1所述的阵列基板的制作方法，其特征在于：所述第三过孔(81)与第四过孔(91)设置在同一轴线上。
3.根据权利要求1或2所述的阵列基板的制作方法，其特征在于：所述第五过孔(11)由设于栅极绝缘层(4)上的第六过孔(41)、设于层间绝缘层(6)上的第七过孔(61)、设于第三过孔(81)中的第八过孔(82)、设于第四过孔(91)中的第九过孔(92)以及设于钝化层(10)上的第十过孔(101)构成，所述第六过孔(41)、第七过孔(61)、第八过孔(82)、第九过孔(92)以及第十过孔(101)设置在同一轴线上。
4.根据权利要求3所述的阵列基板的制作方法，其特征在于：所述第五过孔(11)与第三过孔(81)以及第四过孔(91)设置在同一轴线上。
5.根据权利要求4所述的阵列基板的制作方法，其特征在于：所述第六过孔(41)、第七过孔(61)、第八过孔(82)、第九过孔(92)以及第十过孔(101)的孔径相等且小于第四过孔(91)的孔径。
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