WO2020029464A1 - 柔性显示面板的制造方法及柔性显示面板 - Google Patents

柔性显示面板的制造方法及柔性显示面板 Download PDF

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Publication number
WO2020029464A1
WO2020029464A1 PCT/CN2018/116107 CN2018116107W WO2020029464A1 WO 2020029464 A1 WO2020029464 A1 WO 2020029464A1 CN 2018116107 W CN2018116107 W CN 2018116107W WO 2020029464 A1 WO2020029464 A1 WO 2020029464A1
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Prior art keywords
layer
insulating layer
gate
gate insulating
interlayer insulating
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PCT/CN2018/116107
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English (en)
French (fr)
Inventor
白思航
胡俊艳
王国超
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武汉华星光电半导体显示技术有限公司
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Priority to US16/326,371 priority Critical patent/US10847732B2/en
Publication of WO2020029464A1 publication Critical patent/WO2020029464A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/20—Changing the shape of the active layer in the devices, e.g. patterning
    • H10K71/231—Changing the shape of the active layer in the devices, e.g. patterning by etching of existing layers
    • H10K71/233—Changing the shape of the active layer in the devices, e.g. patterning by etching of existing layers by photolithographic etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/80—Manufacture or treatment specially adapted for the organic devices covered by this subclass using temporary substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H01L27/1266—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present application relates to the field of display technology, and in particular, to a method for manufacturing a flexible display panel and a flexible display panel.
  • flexible display devices have the advantages of lightness, thinness, flexibility, impact resistance, ultra-high waterproof performance, etc., and they are widely used in wearable devices and some special function display fields.
  • the existing technology of bending the flexible backplane backward, the binding structure of the flexible film mounting technology or the integrated circuit binding structure of the chip technology on the flexible substrate, and The pad extension traces of the data signals in the pixel circuits of the display area and some test circuit areas are bent under the panel together, which can reduce the lower border of the original rigid display panel.
  • part of the inorganic film layer is cut out, filled with organic materials, and the stress of the inorganic film layer is reduced.
  • the ISO (Insulation Layer Structure) design is introduced in this structure, which can give the interlayer insulating layer with a higher stress the stress during the bending process. Being released is more conducive to bending performance and device stability.
  • the ISO design space is limited, the number of designs can be small, and stress relief is not sufficient.
  • the organic interlayer insulation layer structure in the display area requires an interlayer insulation layer.
  • the organic interlayer insulating layer through hole is opened at the same position of the opening. Due to the limitation of design rules, the aperture design value of the organic interlayer insulating layer through hole needs to be greater than that of the interlayer insulating layer. This will seriously limit the design and development of high pixels. Therefore, a new structure needs to be studied to meet the bending performance of the display area.
  • the existing flexible display panel has an interlayer insulating layer and an organic interlayer insulating layer structure, and the aperture design value of the organic interlayer insulating layer through-hole needs to be larger than that of the interlayer insulating layer. This causes technical problems that severely limit the design and development of high pixels.
  • the existing flexible display panel adopts an overlapping interlayer insulating layer and an organic interlayer insulating layer structure.
  • the aperture design value of the through hole of the organic interlayer insulating layer needs to be larger than that of the interlayer insulating layer, which severely limits the design of high pixels. Development.
  • the present application provides a flexible display panel, which can avoid the large opening design of the organic interlayer insulating layer, so as to solve the existing flexible display panel. Because the overlapping interlayer insulating layer and the organic interlayer insulating layer structure are used, the organic interlayer The design value of the aperture of the through hole of the insulating layer needs to be larger than that of the interlayer insulating layer, which causes a technical problem that severely limits the design and development of high pixels.
  • the present application provides a method for manufacturing a flexible display panel.
  • the method includes:
  • a substrate is provided.
  • a flexible substrate is prepared on the surface of the substrate, a barrier layer and a buffer layer are sequentially prepared on the surface of the flexible substrate, an active layer is prepared on the surface of the buffer layer, and then the buffer layer is formed.
  • a first gate insulating layer is prepared on the surface of the layer, the first gate insulating layer completely covers the active layer, and then a first gate metal layer and a second gate are prepared on the surface of the first gate insulating layer.
  • An electrode insulating layer is formed on the first gate insulating layer and completely covers the first gate metal layer, and a second gate metal layer is prepared on the second gate insulating layer;
  • An organic interlayer insulating layer is prepared on the surface of the second gate insulating layer.
  • the organic interlayer insulating layer completely covers the second gate metal layer and fills the trench.
  • the insulating layer is etched to form a first through hole and a second through hole. The first through hole exposes the second gate insulating layer, and the second through hole exposes the second gate metal layer. ;
  • a source and drain metal layer is prepared on the surface of the organic interlayer insulating layer, and then a passivation layer is prepared on the surface of the organic interlayer insulating layer.
  • the passivation layer completely covers the source and drain metal layers.
  • An anode metal layer, a pixel isolation layer, and a pixel support layer are sequentially prepared on the surface of the passivation layer. A part of the anode metal layer is directly connected to the source and drain metal layers, and finally the substrate is removed.
  • the trenches run through the second gate insulation layer, the first gate insulation layer, the buffer layer, and the barrier layer. On the flexible substrate.
  • a material of the organic interlayer insulating layer is an organic photoresist.
  • the S40 further includes:
  • the third through hole penetrates the organic interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer. On the active layer.
  • a material of the flexible substrate is polyimide or polyethylene terephthalate
  • a material of the buffer layer is silicon nitride or One or two of silicon oxide.
  • a material of the first gate buffer layer is silicon nitride or silicon oxide, and a material of the second gate buffer layer and the first gate The material of the electrode buffer layer is the same.
  • a material of the first gate is molybdenum, and a thickness of the first gate is larger than that of the first gate insulating layer and the second gate. Sum of the thickness of the electrode insulation layer.
  • an organic light-emitting layer is formed on a surface of the pixel isolation layer by depositing an organic material, and the organic light-emitting layer includes a planarization layer and the pixels that are disposed in an overlapping manner. Isolation layer and OLED pixel layer.
  • the present application also provides a flexible display panel, including: a flexible substrate, a barrier layer, a buffer layer, an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, and a second gate. Electrode metal layer, organic interlayer insulation layer, source and drain metal layer, passivation layer, anode metal layer, pixel isolation layer and pixel support layer;
  • the organic interlayer insulating layer is located on a surface of the second gate insulating layer and covers the second gate metal layer, and a part of the organic interlayer insulating layer penetrates the second gate in a non-display area.
  • the source-drain metal layer is in communication with the active layer through the first through-hole, and the source-drain-level metal layer is in communication with the second gate metal layer through the second through-hole.
  • the beneficial effects of the present application are: the manufacturing method of the flexible array substrate and the flexible display panel provided by the present application, replacing the inorganic interlayer insulating layer with the organic interlayer insulating layer, avoiding the large opening design of the organic interlayer insulating layer, and further realizing The high pixel design of the flexible display panel further reduces the cost of the mask and the cost of raw materials.
  • FIG. 1 is a flowchart of a manufacturing method of a flexible display panel of the present application.
  • FIG. 1A-1E are schematic diagrams of a method for manufacturing the flexible display panel of FIG. 1.
  • FIG. 2 is a schematic structural diagram of a flexible display panel of the present application.
  • This application is directed to the existing flexible display panel. Because the interlayer insulating layer and the organic interlayer insulating layer structure are overlapped, the aperture design value of the through hole of the organic interlayer insulating layer needs to be larger than the through hole of the interlayer insulating layer, causing serious problems. Technical problems that limit the design and development of high pixels can be solved by this embodiment.
  • the present application further provides a process for manufacturing a flexible display panel, the method includes:
  • a substrate is provided.
  • a flexible substrate is prepared on the surface of the substrate, a barrier layer and a buffer layer are sequentially prepared on the surface of the flexible substrate, an active layer is prepared on the surface of the buffer layer, and then the buffer layer is formed.
  • a first gate insulating layer is prepared on the surface of the layer, the first gate insulating layer completely covers the active layer, and then a first gate metal layer and a second gate are prepared on the surface of the first gate insulating layer.
  • An electrode insulating layer is formed on the first gate insulating layer and completely covers the first gate metal layer.
  • a second gate metal layer is prepared on the second gate insulating layer.
  • the S10 further includes:
  • an insulating substrate is provided, and a layer of a flexible substrate 101 is deposited on the surface of the insulating substrate.
  • the material of the flexible substrate 101 is polyimide or polyethylene terephthalate.
  • a barrier layer 102 and a buffer layer 103 are sequentially deposited on the surface of the flexible substrate 101 using a physical weather deposition method.
  • the material of the barrier layer 102 is one or two of silicon nitride or silicon oxide.
  • the barrier layer 102 The thickness of the buffer layer 103 is one or two of silicon nitride or silicon oxide, and the material of the buffer layer 103 is 3000 Angstroms;
  • a semiconductor layer is formed on the surface, and a semiconductor lithography process is used to define the semiconductor layer structure to form an active layer 104.
  • a first gate insulating layer 105 is deposited on the surface of the buffer layer 103, and the first gate The electrode insulating layer 105 completely covers the active layer 104.
  • the material of the first gate buffer layer 105 is silicon nitride or silicon oxide, and the thickness of the first gate buffer layer 105 is 1000 Angstroms.
  • a light is applied to the surface of the first gate buffer layer 105.
  • the lithographic etching process defines a gate conductor structure to form a first gate metal layer 106.
  • the material of the first gate metal layer 106 is metal molybdenum, and the thickness of the first gate metal layer 106 is 2500 angstroms.
  • a second gate buffer layer 107 is deposited on the surface of the first gate buffer layer 105, and the material of the second gate buffer layer 107 is the same as that of the first gate buffer layer 105, The thickness of the second gate buffer layer 107 is 1200 ⁇ .
  • a photolithography process is used to define a gate conductor structure on the surface of the second gate buffer layer 107 to form a second The gate metal layer 108; the material of the second gate metal layer 108 is molybdenum, as shown in FIG. 1A.
  • the S20 further includes:
  • the barrier layer 102, the buffer layer 103, the second gate insulating layer 107, and the first gate insulating layer 105 are dry-etched through a mask to form trenches in the non-display area.
  • An organic interlayer insulating layer is prepared on the surface of the second gate insulating layer.
  • the organic interlayer insulating layer completely covers the second gate metal layer and fills the trench.
  • the insulating layer is etched to form a first through hole and a second through hole. The first through hole exposes the second gate insulating layer, and the second through hole exposes the second gate metal layer. .
  • the S30 further includes:
  • an organic interlayer insulating layer 110 is prepared on the surface of the second gate insulating layer 107.
  • the organic interlayer insulating layer 110 completely covers the second gate metal layer 108 and fills the trench 109.
  • the material of the organic interlayer insulating layer 110 is an organic photoresist; the organic interlayer insulating layer 110 is etched to form a first through hole 111 and a second through hole 112. The number of the first through holes 111 is two.
  • the number of the second through-holes 112 is one; the first through-hole 111 penetrates the organic interlayer insulating layer 110 and stops at the second gate insulating layer 107, and the second through-hole 112 penetrates the organic interlayer insulating layer 110 and ends at the second gate metal layer 108, as shown in FIG. 1C.
  • the S40 further includes:
  • the organic interlayer insulating layer 110 is subjected to a baking process; then, the processed organic interlayer insulating layer 110 is used as a mask without being exposed, and the first through hole 111 is directly applied to the first interlayer insulating layer 110.
  • a gate insulating layer 105 and the second gate insulating layer 107 are dry-etched; finally, the third through hole 113 is formed.
  • the number of the third through holes 113 is two, and the third through holes 113 penetrate the organic interlayer insulating layer 110, the second gate insulating layer 107, and the first gate insulating layer 105, respectively. It ends at the active layer 104, as shown in FIG. 1D.
  • a source and drain metal layer is prepared on the surface of the organic interlayer insulating layer, and then a passivation layer is prepared on the surface of the organic interlayer insulating layer.
  • the passivation layer completely covers the source and drain metal layers.
  • An anode metal layer, a pixel isolation layer, and a pixel support layer are sequentially prepared on the surface of the passivation layer. A part of the anode metal layer is directly connected to the source and drain metal layers, and finally the substrate is removed.
  • the S50 further includes:
  • a metal layer is formed on the surface of the organic interlayer insulating layer 110, and a source-drain conductor layer structure is defined by a photolithographic etching process to form a source-drain metal layer 114.
  • the source-drain metal layer The material of 114 is titanium or aluminum, and the thickness of the source and drain metal layer 114 is about 7600 Angstroms; a plurality of signal traces pass through the third through hole 113 to connect the source and drain metal layer 114 with the The active layer 104 communicates; multiple signal traces communicate the source-drain metal layer 114 and the second gate metal layer 108 through the second through-hole 112; and then, the organic interlayer insulation layer A passivation layer 115 is deposited on the surface of 110, and the passivation layer 115 completely covers the source and drain metal layer 114;
  • An anode metal layer 116, a pixel isolation layer 117, and a pixel support layer 118 are sequentially deposited on the surface of the passivation layer 115. A portion of the anode metal layer 116 is directly connected to the source and drain metal layer 114. Finally, An organic light-emitting layer is deposited on the surface of the pixel isolation layer by depositing an organic material, and the organic light-emitting layer includes a planarization layer, the pixel isolation layer, and an OLED pixel layer that are overlapped and the substrate is removed, as shown in FIG. 1E As shown.
  • the present application further provides a flexible display panel, including:
  • the blocking layer 202 is located on a surface of the flexible substrate 201;
  • An active layer 204 is located on a surface of the buffer layer 203;
  • a first gate insulating layer 205 which is located on a surface of the buffer layer 203 and covers the active layer 204;
  • the first gate metal layer 206 is located on a surface of the first gate insulating layer 205;
  • a second gate insulating layer 207 is located on a surface of the first gate insulating layer 205 and covers the first gate metal layer 206;
  • a second gate metal layer 208 which is located on a surface of the second gate insulating layer 207;
  • An organic interlayer insulating layer 209 which is located on the surface of the second gate insulating layer 207 and covers the second gate metal layer 208; the organic interlayer insulating layer 209 is A part of the region penetrates the second gate insulating layer 207, the first gate insulating layer 205, the buffer layer 203, and the barrier layer 202 and is connected to the flexible substrate 201.
  • the source and drain metal layer 210 is located on a surface of the organic interlayer insulating layer 209;
  • a passivation layer 211 located on a surface of the organic interlayer insulating layer 211 and covering the source and drain metal layer 210;
  • the pixel isolation layer 213 is located on a surface of the passivation layer 211 and covers both ends of an edge of the anode metal layer 212;
  • a pixel support layer 214 which is located on a surface of the pixel isolation layer 213;
  • the organic interlayer insulating layer 209 is formed with a first through hole and a second through hole, and the source and drain metal layer 210 is in communication with the active layer 204 through the first through hole.
  • the drain metal layer 210 is in communication with the second gate metal layer 208 through the second through hole.
  • the beneficial effects of the present application are: the manufacturing method of the flexible array substrate and the flexible display panel provided by the present application, replacing the inorganic interlayer insulating layer with the organic interlayer insulating layer, avoiding the large opening design of the organic interlayer insulating layer, and further realizing The high pixel design of the flexible display panel further reduces the cost of the mask and the cost of raw materials.

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Abstract

一种柔性显示面板的制造方法及柔性显示面板，包括柔性衬底、阻挡层、缓冲层、有源层、第一栅极绝缘层、第一栅极金属层、第二栅极绝缘层、第二栅极金属层、有机层间绝缘层、源漏极金属层、钝化层、阳极金属层、像素隔离层以及像素支撑层；其中，所述源漏极金属层分别通过两通孔与所述有源层以及所述第二栅极金属层连通。

Description

柔性显示面板的制造方法及柔性显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种柔性显示面板的制造方法及柔性显示面板。
 背景技术
目前，柔性显示器件具有轻、薄、可挠曲、耐冲击、超高防水性能等优点，在可穿戴设备及一些特殊功能显示领域有非常广泛的应用；为了实现小尺寸手机的窄边框设计，实现手机更大的屏占比，现有的将柔性背板向后弯折的技术，将软膜构装技术的绑定结构或者柔性基板上芯片技术的集成电路的绑定结构，和连接至显示区域区像素电路中数据信号的焊盘延伸式走线以及一些测试电路区域一起弯折至面板的下方，可以将原有刚性显示面板的下边框变小，现有技术的柔性显示面板，在显示区域将部分无机膜层挖掉，填充有机材料，减小无机膜层的应力，此结构中引入ISO（绝缘层结构）设计，能够给予应力较大的层间绝缘层在弯折过程中应力得以释放，更有利于弯折性能以及器件的稳定性。
但是，此种设计也有其弊端，首先对于高像素的7T1C结构中，ISO设计空间有限，可设计数量较少，应力释放不充分；其次显示区域采用有机层间绝缘层结构需要在层间绝缘层的开孔相同位置开有机层间绝缘层通孔，由于设计规则限制，有机层间绝缘层通孔的孔径设计值需要大于层间绝缘层的通孔，这会严重限制高像素的设计开发，因此需要研究新的结构以满足显示区域的弯折性能。
综上所述，现有的柔性显示面板，由于采用交叠的层间绝缘层与有机层间绝缘层结构，有机层间绝缘层通孔的孔径设计值需要大于层间绝缘层的通孔，造成严重限制高像素的设计开发的技术问题。
 技术问题
现有的柔性显示面板，采用交叠的层间绝缘层与有机层间绝缘层结构，有机层间绝缘层通孔的孔径设计值需要大于层间绝缘层的通孔，严重限制高像素的设计开发。
 技术解决方案
本申请提供一种柔性显示面板，能够避免有机层间绝缘层大开孔设计，以解决现有的柔性显示面板，由于采用交叠的层间绝缘层与有机层间绝缘层结构，有机层间绝缘层通孔的孔径设计值需要大于层间绝缘层的通孔，造成严重限制高像素的设计开发的技术问题。
为解决上述问题，本申请提供的技术方案如下：
本申请提供一种柔性显示面板的制造方法，所述方法包括：
S10，提供一基板，在所述基板表面制备柔性衬底，之后在所述柔性衬底表面依次制备阻挡层以及缓冲层，然后在所述缓冲层的表面制备有源层，之后在所述缓冲层的表面制备第一栅极绝缘层，所述第一栅极绝缘层完全覆盖所述有源层，然后在所述第一栅极绝缘层的表面制备第一栅极金属层，第二栅极绝缘层形成于所述第一栅极绝缘层并完全覆盖所述第一栅极金属层，在所述第二栅极绝缘层上制备第二栅极金属层；
S20，通过掩膜对所述阻挡层、所述缓冲层、所述第二栅极绝缘层以及所述第一栅极绝缘层进行干法刻蚀，在所述非显示区域形成沟槽，所述沟槽暴露出所述柔性衬底；
S30，在所述第二栅极绝缘层的表面制备有机层间绝缘层，所述有机层间绝缘层完全覆盖所述第二栅极金属层并填充所述沟槽，对所述有机层间绝缘层进行刻蚀，形成第一通孔以及第二通孔，所述第一通孔暴露出所述第二栅极绝缘层，所述第二通孔暴露出所述第二栅极金属层；
S40，将所述有机层间绝缘层充当掩膜经过所述第一通孔对所述第一栅极绝缘层以及所述第二栅极绝缘层进行刻蚀，形成第三通孔，暴露出所述有源层；
S50，在所述有机层间绝缘层的表面制备源漏极金属层，之后在所述有机间绝缘层的表面制备钝化层，所述钝化层完全覆盖所述源漏极金属层，最后在所述钝化层的表面依次制备阳极金属层、像素隔离层以及像素支撑层，所述阳极金属层的一部分与所述源漏极金属层直接相连，最后去除所述基板。
在本申请实施例所提供的柔性显示面板的制造方法中，所述沟槽贯穿所述第二栅极绝缘层、所述第一栅极绝缘层、所述缓冲层以及所述阻挡层并止于所述柔性衬底。
在本申请实施例所提供的柔性显示面板的制造方法中，所述有机层间绝缘层的材料为有机光阻。
在本申请实施例所提供的柔性显示面板的制造方法中，所述S40还包括：
S401，将所述有机层间绝缘层进行烘烤化处理；
S402，将经过处理的所述有机层间绝缘层充当掩膜，不经过曝光，通过所述第一通孔直接对所述第一栅极绝缘层以及所述第二栅极绝缘层进行干法蚀刻；
S403，形成所述第三通孔，暴露出所述有源层。
在本申请实施例所提供的柔性显示面板的制造方法中，所述第三通孔贯穿所述有机层间绝缘层、所述第二栅极绝缘层、所述第一栅极绝缘层并止于所述有源层。
在本申请实施例所提供的柔性显示面板的制造方法中，所述柔性衬底的材料为聚酰亚胺或聚对苯二甲酸乙二醇酯，所述缓冲层的材料为氮化硅或氧化硅其中的一种或两种。
在本申请实施例所提供的柔性显示面板的制造方法中，所述第一栅极缓冲层的材料为氮化硅或氧化硅，所述第二栅极缓冲层的材料与所述第一栅极缓冲层的材料相同。
在本申请实施例所提供的柔性显示面板的制造方法中，所述第一栅极的材料为钼，所述第一栅极的厚度大于所述第一栅极绝缘层与所述第二栅极绝缘层的厚度之和。
在本申请实施例所提供的柔性显示面板的制造方法中，沉积有机材料于所述像素隔离层的表面上形成有机发光层，所述有机发光层包括交叠设置的平坦化层、所述像素隔离层以及OLED像素层。
本申请还提供一种柔性显示面板，包括：柔性衬底、阻挡层、缓冲层、有源层、第一栅极绝缘层、第一栅极金属层、第二栅极绝缘层、第二栅极金属层、有机层间绝缘层、源漏极金属层、钝化层、阳极金属层、像素隔离层以及像素支撑层；
其中，所述有机层间绝缘层位于所述第二栅极绝缘层的表面并覆盖所述第二栅极金属层，所述有机层间绝缘层在非显示区域的一部分贯穿所述第二栅极绝缘层、所述第一栅极绝缘层、所述缓冲层以及所述阻挡层并与所述柔性衬底相连；所述有机层间绝缘层上形成有第一通孔以及第二通孔，所述源漏极金属层通过所述第一通孔与所述有源层连通，所述源漏级金属层通过所述第二通孔与所述第二栅极金属层连通。
 有益效果
本申请的有益效果为：本申请所提供的柔性阵列基板的制造方法及柔性显示面板，将有机层间绝缘层取代无机层间绝缘层，避免有机层间绝缘层大开孔设计，进一步实现了柔性显示面板高像素设计，更进一步降低光罩成本以及原料成本。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请柔性显示面板的制造方法流程图。
图1A-1E为图1柔性显示面板的制造方法示意图。
图2为本申请柔性显示面板结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
本申请针对现有的柔性显示面板，由于采用交叠的层间绝缘层与有机层间绝缘层结构，有机层间绝缘层通孔的孔径设计值需要大于层间绝缘层的通孔，造成严重限制高像素的设计开发的技术问题,本实施例能够解决该缺陷。
为解决上述问题，本申请提供的技术方案如下：
如图1所示，本申请还提供一种柔性显示面板的制造方法流程，所述方法包括：
S10，提供一基板，在所述基板表面制备柔性衬底，之后在所述柔性衬底表面依次制备阻挡层以及缓冲层，然后在所述缓冲层的表面制备有源层，之后在所述缓冲层的表面制备第一栅极绝缘层，所述第一栅极绝缘层完全覆盖所述有源层，然后在所述第一栅极绝缘层的表面制备第一栅极金属层，第二栅极绝缘层形成于所述第一栅极绝缘层并完全覆盖所述第一栅极金属层，在所述第二栅极绝缘层上制备第二栅极金属层。
具体的，所述S10还包括：
首先，提供一个绝缘基板，在所述绝缘基板的表面沉积一层柔性衬底101，所述柔性衬底101的材料为聚酰亚胺或聚对苯二甲酸乙二醇酯；之后，在所述柔性衬底101的表面使用物理气象沉积法依次沉积出阻挡层102以及缓冲层103，所述阻挡层102的材料为氮化硅或氧化硅其中的一种或两种，所述阻挡层102的厚度为5000埃米；所述缓冲层103的材料为氮化硅或氧化硅其中的一种或两种，所述缓冲层103的材料为3000埃米；之后，在所述缓冲层103的表面形成一半导体层，以一道光罩微影蚀刻制程来定义出半导体层结构，形成有源层104；接着在所述缓冲层103表面沉积出第一栅极绝缘层105，所述第一栅极绝缘层105完全覆盖所述有源层104，所述第一栅极缓冲层105的材料为氮化硅或氧化硅，所述第一栅极缓冲层105的厚度为1000埃米；接着在所述第一栅极缓冲层105的表面以一道光罩微影蚀刻制程来定义出栅极导体结构，形成第一栅极金属层106，所述第一栅极金属层106的材料为金属钼，所述第一栅极金属层106的厚度为2500埃米；接着在所述第一栅极缓冲层105的表面沉积出第二栅极缓冲层107，所述第二栅极缓冲层107的材料与所述第一栅极缓冲层105的材料相同，所述第二栅极缓冲层107的厚度为1200埃米；最后在所述第二栅极缓冲层107的表面以一道光罩微影蚀刻制程来定义出一层栅极导体结构，形成第二栅极金属层108；所述第二栅极金属层108的材料为钼，如图1A所示。
S20，通过掩膜对所述阻挡层、所述缓冲层、所述第二栅极绝缘层以及所述第一栅极绝缘层进行干法刻蚀，在所述非显示区域形成沟槽，所述沟槽暴露出所述柔性衬底。
具体的，所述S20还包括：
首先通过掩膜对所述阻挡层102、所述缓冲层103、所述第二栅极绝缘层107以及所述第一栅极绝缘层105进行干法刻蚀，在所述非显示区域形成沟槽109，所述沟槽109暴露出所述柔性衬底101；所述沟槽贯穿所述第二栅极绝缘层107、所述第一栅极绝缘层105、所述缓冲层103以及所述阻挡层102并止于所述柔性衬底101，如图1B所示。
S30，在所述第二栅极绝缘层的表面制备有机层间绝缘层，所述有机层间绝缘层完全覆盖所述第二栅极金属层并填充所述沟槽，对所述有机层间绝缘层进行刻蚀，形成第一通孔以及第二通孔，所述第一通孔暴露出所述第二栅极绝缘层，所述第二通孔暴露出所述第二栅极金属层。
具体的，所述S30还包括：
首先在所述第二栅极绝缘层107的表面制备有机层间绝缘层110，所述有机层间绝缘层110完全覆盖所述第二栅极金属层108并填充所述沟槽109，所述有机层间绝缘层110的材料为有机光阻；对所述有机层间绝缘层110进行刻蚀，形成第一通孔111以及第二通孔112，所述第一通孔111的数量有两个，所述第二通孔112的数量为1个；所述第一通孔111贯穿所述有机层间绝缘层110并止于所述第二栅极绝缘层107，所述第二通孔112贯穿所述有机层间绝缘层110并止于所述第二栅极金属层108，如图1C所示。
S40，将所述有机层间绝缘层充当掩膜经过所述第一通孔对所述第一栅极绝缘层以及所述第二栅极绝缘层进行刻蚀，形成第三通孔，暴露出所述有源层。
具体的，所述S40还包括：
首先将所述有机层间绝缘层110进行烘烤化处理；之后将经过处理的所述有机层间绝缘层110充当掩膜，不经过曝光，通过所述第一通孔111直接对所述第一栅极绝缘层105以及所述第二栅极绝缘层107进行干法蚀刻；最后形成所述第三通孔113。所述第三通孔113的数量有两个，所述第三通孔113分别贯穿所述有机层间绝缘层110、所述第二栅极绝缘层107以及所述第一栅极绝缘层105并止于所述有源层104，如图1D所示。
S50，在所述有机层间绝缘层的表面制备源漏极金属层，之后在所述有机间绝缘层的表面制备钝化层，所述钝化层完全覆盖所述源漏极金属层，最后在所述钝化层的表面依次制备阳极金属层、像素隔离层以及像素支撑层，所述阳极金属层的一部分与所述源漏极金属层直接相连，最后去除所述基板。
具体的，所述S50还包括：
在所述有机层间绝缘层110的表面上形成一金属层，以一道光罩微影蚀刻制程来定义出源漏极导体层结构，形成源漏极金属层114，所述源漏极金属层114的材料为钛或铝，所述源漏极金属层114的厚度约为7600埃米；多条信号走线穿过所述第三通孔113将所述源漏极金属层114与所述有源层104连通；多条信号走线通过所述第二通孔112将所述源漏极金属层114与所述第二栅极金属层108连通；之后，在所述有机层间绝缘层110的表面沉积出一钝化层115，所述钝化层115完全覆盖所述源漏极金属层114；
接着在所述钝化层115的表面依次沉积出阳极金属层116、像素隔离层117以及像素支撑层118，其中，所述阳极金属层116的一部分直接与所述源漏金属层114相连；最后，沉积有机材料于所述像素隔离层的表面上形成有机发光层，所述有机发光层包括交叠设置的平坦化层、所述像素隔离层以及OLED像素层并去除所述基板，如图1E所示。
如图2所示，本申请还提供一种柔性显示面板，包括：
柔性衬底201；
阻挡层202，位于所述柔性衬底201的表面；
缓冲层203，位于所述阻挡层202的表面；
有源层204，位于所述缓冲层203的表面；
第一栅极绝缘层205，位于所述缓冲层203的表面并覆盖所述有源层204；
第一栅极金属层206，位于所述第一栅极绝缘层205的表面；
第二栅极绝缘层207，位于所述第一栅极绝缘层205的表面并覆盖所述第一栅极金属层206；
第二栅极金属层208，位于所述第二栅极绝缘层207的表面；
有机层间绝缘层209，所述有机层间绝缘层209位于所述第二栅极绝缘层207的表面并覆盖所述第二栅极金属层208，所述有机层间绝缘层209在非显示区域的一部分贯穿所述第二栅极绝缘层207、所述第一栅极绝缘层205、所述缓冲层203以及所述阻挡层202并与所述柔性衬底201相连。
源漏极金属层210，位于所述有机层间绝缘层209的表面；
钝化层211，位于所述有机层间绝缘层211的表面并覆盖所述源漏极金属层210；
阳极金属层212，位于所述钝化层211的表面；
像素隔离层213，位于所述钝化层211的表面并覆盖所述阳极金属层212的边缘两端；
像素支撑层214，位于所述像素隔离层213的表面；
其中，所述有机层间绝缘层209上形成有第一通孔以及第二通孔，所述源漏极金属层210通过所述第一通孔与所述有源层204连通，所述源漏级金属层210通过所述第二通孔与所述第二栅极金属层208连通。
本申请的有益效果为：本申请所提供的柔性阵列基板的制造方法及柔性显示面板，将有机层间绝缘层取代无机层间绝缘层，避免有机层间绝缘层大开孔设计，进一步实现了柔性显示面板高像素设计，更进一步降低光罩成本以及原料成本。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (11)

  1. 一种柔性显示面板的制造方法，其中，包括：
    S10，提供一基板，在所述基板表面制备柔性衬底，之后在所述柔性衬底表面依次制备阻挡层以及缓冲层，然后在所述缓冲层的表面制备有源层，之后在所述缓冲层的表面制备第一栅极绝缘层，所述第一栅极绝缘层完全覆盖所述有源层，然后在所述第一栅极绝缘层的表面制备第一栅极金属层，第二栅极绝缘层形成于所述第一栅极绝缘层并完全覆盖所述第一栅极金属层，在所述第二栅极绝缘层上制备第二栅极金属层；
    S20，通过掩膜对所述阻挡层、所述缓冲层、所述第二栅极绝缘层以及所述第一栅极绝缘层进行干法刻蚀，在所述非显示区域形成沟槽，所述沟槽暴露出所述柔性衬底；
    S30，在所述第二栅极绝缘层的表面制备有机层间绝缘层，所述有机层间绝缘层完全覆盖所述第二栅极金属层并填充所述沟槽，对所述有机层间绝缘层进行刻蚀，形成第一通孔以及第二通孔，所述第一通孔暴露出所述第二栅极绝缘层，所述第二通孔暴露出所述第二栅极金属层；
    S40，将所述有机层间绝缘层充当掩膜经过所述第一通孔对所述第一栅极绝缘层以及所述第二栅极绝缘层进行刻蚀，形成第三通孔，暴露出所述有源层；
    S50，在所述有机层间绝缘层的表面制备源漏极金属层，之后在所述有机间绝缘层的表面制备钝化层，所述钝化层完全覆盖所述源漏极金属层，最后在所述钝化层的表面依次制备阳极金属层、像素隔离层以及像素支撑层，所述阳极金属层的一部分与所述源漏极金属层直接相连，最后去除所述基板。
  2. 根据权利要求1柔性显示面板的制造方法，其中，所述沟槽贯穿所述第二栅极绝缘层、所述第一栅极绝缘层、所述缓冲层以及所述阻挡层并止于所述柔性衬底。
  3. 根据权利要求1柔性显示面板的制造方法，其中，所述有机层间绝缘层的材料为有机光阻。
  4. 根据权利要求1柔性显示面板的制造方法，其中，所述S40还包括：
    S401，将所述有机层间绝缘层进行烘烤化处理；
    S402，将经过处理的所述有机层间绝缘层充当掩膜，不经过曝光，通过所述第一通孔直接对所述第一栅极绝缘层以及所述第二栅极绝缘层进行干法蚀刻；
    S403，形成所述第三通孔，暴露出所述有源层。
  5. 根据权利要求4柔性显示面板的制造方法，其中，所述第三通孔贯穿所述有机层间绝缘层、所述第二栅极绝缘层、所述第一栅极绝缘层并止于所述有源层。
  6. 根据权利要求1柔性显示面板的制造方法，其中，所述柔性衬底的材料为聚酰亚胺或聚对苯二甲酸乙二醇酯，所述缓冲层的材料为氮化硅或氧化硅其中的一种或两种。
  7. 根据权利要求1柔性显示面板的制造方法，其中，所述第一栅极缓冲层的材料为氮化硅或氧化硅，所述第二栅极缓冲层的材料与所述第一栅极缓冲层的材料相同。
  8. 根据权利要求1柔性显示面板的制造方法，其中，所述第一栅极的材料为钼，所述第一栅极的厚度大于所述第一栅极绝缘层与所述第二栅极绝缘层的厚度之和。
  9. 根据权利要求8柔性显示面板的制造方法，其中，沉积有机材料于所述像素隔离层的表面上形成有机发光层，所述有机发光层包括交叠设置的平坦化层、所述像素隔离层以及OLED像素层。
  10. 一种使用如权利要求1所述的方法制造的柔性显示面板，其中，包括：
    柔性衬底；
    阻挡层，位于所述柔性衬底的表面；
    缓冲层，位于所述阻挡层的表面；
    有源层，位于所述缓冲层的表面；
    第一栅极绝缘层，位于所述缓冲层的表面并覆盖所述有源层；
    第一栅极金属层，位于所述第一栅极绝缘层的表面；
    第二栅极绝缘层，位于所述第一栅极绝缘层的表面并覆盖所述第一栅极金属层；
    第二栅极金属层，位于所述第二栅极绝缘层的表面；
    有机层间绝缘层，所述有机层间绝缘层位于所述第二栅极绝缘层的表面并覆盖所述第二栅极金属层，所述有机层间绝缘层在非显示区域的一部分贯穿所述第二栅极绝缘层、所述第一栅极绝缘层、所述缓冲层以及所述阻挡层并与所述柔性衬底相连。
    源漏极金属层，位于所述有机层间绝缘层的表面；
    钝化层，位于所述有机层间绝缘层的表面并覆盖所述源漏极金属层；
    阳极金属层，位于所述钝化层的表面；
    像素隔离层，位于所述钝化层的表面并覆盖所述阳极金属层的边缘两端；
    像素支撑层，位于所述像素隔离层的表面；
    其中，所述有机层间绝缘层上形成有第一通孔以及第二通孔，所述源漏极金属层通过所述第一通孔与所述有源层连通，所述源漏级金属层通过所述第二通孔与所述第二栅极金属层连通。
  11. 一种使用如权利要求4所述的方法制造的柔性显示面板，其中，包括：
    柔性衬底；
    阻挡层，位于所述柔性衬底的表面；
    缓冲层，位于所述阻挡层的表面；
    有源层，位于所述缓冲层的表面；
    第一栅极绝缘层，位于所述缓冲层的表面并覆盖所述有源层；
    第一栅极金属层，位于所述第一栅极绝缘层的表面；
    第二栅极绝缘层，位于所述第一栅极绝缘层的表面并覆盖所述第一栅极金属层；
    第二栅极金属层，位于所述第二栅极绝缘层的表面；
    有机层间绝缘层，所述有机层间绝缘层位于所述第二栅极绝缘层的表面并覆盖所述第二栅极金属层，所述有机层间绝缘层在非显示区域的一部分贯穿所述第二栅极绝缘层、所述第一栅极绝缘层、所述缓冲层以及所述阻挡层并与所述柔性衬底相连。
    源漏极金属层，位于所述有机层间绝缘层的表面；
    钝化层，位于所述有机层间绝缘层的表面并覆盖所述源漏极金属层；
    阳极金属层，位于所述钝化层的表面；
    像素隔离层，位于所述钝化层的表面并覆盖所述阳极金属层的边缘两端；
    像素支撑层，位于所述像素隔离层的表面；
    其中，所述有机层间绝缘层上形成有第一通孔以及第二通孔，所述源漏极金属层通过所述第一通孔与所述有源层连通，所述源漏级金属层通过所述第二通孔与所述第二栅极金属层连通。
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