WO2016165241A1 - 阵列基板及其制备方法、显示装置 - Google Patents

阵列基板及其制备方法、显示装置 Download PDF

Info

Publication number
WO2016165241A1
WO2016165241A1 PCT/CN2015/085907 CN2015085907W WO2016165241A1 WO 2016165241 A1 WO2016165241 A1 WO 2016165241A1 CN 2015085907 W CN2015085907 W CN 2015085907W WO 2016165241 A1 WO2016165241 A1 WO 2016165241A1
Authority
WO
WIPO (PCT)
Prior art keywords
plate
gate
active region
disposed
array substrate
Prior art date
Application number
PCT/CN2015/085907
Other languages
English (en)
French (fr)
Inventor
辛燕霞
杨玉清
杨小飞
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/127,771 priority Critical patent/US20180197897A1/en
Publication of WO2016165241A1 publication Critical patent/WO2016165241A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Definitions

  • the present invention belongs to the field of display technologies, and in particular, to an array substrate, a preparation method thereof, and a display device.
  • FIG. 1 shows a circuit structure of a conventional shift register, which can be seen to include a plurality of storage capacitors C.
  • the plates of the storage capacitor C have the following common designs.
  • the polysilicon layer and the gate layer serve as two plates of the storage capacitor C, respectively.
  • the polysilicon layer and the data line layer serve as the two plates of the storage capacitor C, respectively.
  • the gate layer and the data line layer serve as the two plates of the storage capacitor C, respectively. In order not to increase the mask, the third mode shown in Fig. 2 is usually employed.
  • the thin film transistor of the gate driving circuit includes an active region 4', a gate 2', and a source and drain 3'.
  • the storage capacitor C is composed of two plates 21', 31', the first plate 21' is disposed in the same layer as the gate 2', and the second plate 31' is in the same layer as the source and drain 3' (ie, the data line). Settings.
  • the first and second plates 21', 31' should actually also be connected to other structures, for example, the first plate 21' can be connected to the gate of a thin film transistor, and the second plate 31' can be connected to the ground port.
  • the array substrate further includes known structures such as a substrate 9', a buffer 5', a gate insulating layer 6', and an interlayer insulating layer (ILD) 7' which are sequentially stacked, and will not be described in detail herein.
  • ILD interlayer insulating layer
  • the capacitance value of the storage capacitor C is lowered, which cannot meet the demand.
  • the area of the gate driving circuit is getting smaller and smaller, and the area of the storage capacitor is also continuously reduced, and the capacitance value is even less satisfactory. Therefore, there is a need in the art for a storage capacitor with an improved design.
  • the present invention provides an array substrate for increasing the capacitance value of the storage capacitor without increasing the area, and a method for preparing the same, and a display method, for the problem that the capacitance of the storage capacitor in the existing array substrate is insufficient and the capacitance value is small. Device.
  • an array substrate comprising:
  • a thin film transistor including an active region, a source drain, and a gate
  • a light shielding structure made of a conductive material disposed under the active region
  • a storage capacitor comprising a first plate and a second plate spaced apart and oppositely disposed
  • first plate is disposed in the same layer as the light shielding structure
  • second plate is disposed in the same layer as any one of the active region, the source drain and the gate.
  • the second plate may be disposed in the same layer as the source drain or may be disposed in the same layer as the gate.
  • the storage capacitor may further include: a third plate electrically connected to the first plate, wherein the second plate is disposed between the first plate and the third plate, and The second plate and the third plate are respectively disposed in the same layer as the two different ones of the gate, the source drain and the active region.
  • the light shielding structure, a buffer layer, the active region, a gate insulating layer, the gate electrode, and an interlayer insulating layer may be sequentially disposed in a direction away from the substrate of the array substrate.
  • the source drain; the second plate is disposed in the same layer as the gate; and the third plate is disposed in the same layer as the source drain.
  • At least one insulating layer may be disposed between the layer where the light shielding structure is located and the layer where the second electrode plate is located; and the at least one insulating layer has a thickness t1 above the first electrode plate and The light shielding structure has a thickness t2 above, wherein 0 ⁇ t1 ⁇ t2.
  • the at least one insulating layer may be a buffer layer covering the light shielding structure; and the active region may be disposed on the buffer layer.
  • the third plate may be electrically connected to the first plate by a via hole penetrating the buffer layer, the gate insulating layer, and the interlayer insulating layer.
  • the active region is composed of low temperature polysilicon.
  • the array substrate comprises a gate driving circuit at an edge portion, and the storage capacitor is a storage capacitor in the gate driving circuit.
  • a display device comprising:
  • a method for fabricating an array substrate comprising: a thin film transistor including an active region, a source drain, and a gate; and a conductive material disposed under the active region a light blocking structure; and a storage capacitor comprising a first plate and a second plate spaced and oppositely disposed,
  • first plate is disposed in the same layer as the light shielding structure
  • second plate is disposed in the same layer as any one of the active region, the source drain and the gate.
  • the method includes the steps of:
  • the method may further include:
  • Step S102 forming a buffer layer on the pattern including the first plate and the light shielding structure.
  • the method may further include:
  • Step 103 On the substrate obtained in the step S102, the active region 4 is formed by a third patterning process.
  • the method may further include:
  • Step S104 on the substrate obtained in the step S103, etching to reduce the buffer layer outside the corresponding region of the light shielding structure.
  • the method may further include:
  • Step S104' on the substrate obtained in the step S102, the active region 4 is formed by a third patterning process, and at the same time, the buffer layer outside the corresponding region of the light shielding structure is thinned.
  • the method may further include:
  • Step S105 on the substrate obtained by the step S104 or the step S104', a gate electrode located above the active region and a second electrode plate disposed opposite to the first electrode plate are formed by a fourth patterning process.
  • the method may further include:
  • Step S106 forming an interlayer insulating layer on the substrate obtained in the step S105; forming a first via hole penetrating the interlayer insulating layer and the gate insulating layer, and penetrating the interlayer insulating layer and the gate insulating layer by a fifth patterning process And a second via of the buffer layer; and forming, by the sixth patterning process, a source drain electrically connected to the active region through the first via and a third plate electrically connected to the first plate through the second via .
  • the term “same layer setting” means that two structures are formed by the same material layer through a patterning process. These two structures are in the same layer in a stacked relationship, but the distance from the substrate is not necessarily the same.
  • the first plate of the storage capacitor is disposed in the same layer as the light shielding structure, so that the layer on which the electrode plate can be disposed is increased, so that the projection area of the storage capacitor can be increased without increasing the projected area of the storage capacitor.
  • Figure 1 is a circuit diagram of a known shift register
  • FIG. 3 is a partial cross-sectional view showing an array substrate according to an embodiment of the present invention.
  • FIG. 4 is a partial cross-sectional view showing an array substrate after forming an active region according to an embodiment of the present invention
  • FIG. 5 is a partial cross-sectional view showing an array substrate after thinning a buffer layer according to an embodiment of the present invention
  • FIG. 6 is a partial cross-sectional view showing an array substrate after forming an interlayer insulating layer according to an embodiment of the present invention
  • FIG. 7 is a flowchart of a method for fabricating an array substrate according to an embodiment of the present invention.
  • the embodiment provides an array substrate.
  • the array substrate includes a thin film transistor including an active region 4, a source drain 3, and a gate 2.
  • the array substrate further includes a storage capacitor C including first and second plates 11 and 21 spaced apart and oppositely disposed.
  • the array substrate may be an array substrate for a display device including circuits for realizing different functions (such as a gate driving circuit, a pixel circuit, etc.), and these circuits include a thin film transistor and a storage capacitor C.
  • the array substrate of the present embodiment includes a gate driving circuit at an edge portion.
  • the storage capacitor C described in this embodiment also refers to the storage capacitor C in the gate drive circuit.
  • this embodiment is preferably directed to the storage capacitor C used in the gate drive circuit.
  • the storage capacitor C of the embodiment may also be a storage capacitor in other circuits such as a pixel circuit.
  • the array substrate further includes a light shielding structure 1 made of a conductive material at least under the active region 4, and the first electrode plate 11 of the storage capacitor C is disposed in the same layer as the light shielding structure 1 and has a second pole.
  • the board 21 is disposed in the same layer as any of the active region 4, the source/drain electrodes 3, and the gate electrode 2.
  • the term “same layer setting” means that two structures are formed by the same material layer through a patterning process. These two structures are in the same layer in a stacked relationship, but the distance from the substrate 9 is not necessarily the same.
  • a light shielding structure 1 made of an opaque metal such as titanium may be disposed under the active region 4.
  • the first plate 11 disposed in the same layer as the light shielding structure 1 is added and used as a part of the storage capacitor C, which is to increase the layer of the plate which may accommodate the storage capacitor C, or increase
  • the number of plates of the storage capacitor C increases the total area of the plates while increasing the projected area of the storage capacitor C, thereby increasing the capacitance.
  • the second plate 21 is disposed in the same layer as the source/drain 3 or the gate 2.
  • the second plate 21 of the storage capacitor C is preferably not disposed in the same layer as the active region 4, but is disposed in the same layer as the source/drain 3 or the gate 2 because it is in the same layer as the active region 4.
  • Plate It is inevitably composed of a semiconductor material, and its resistance is high, which is disadvantageous for improving the performance of the storage capacitor C.
  • the active region 4 is composed of low temperature polysilicon (LTPS).
  • LTPS low temperature polysilicon
  • low temperature polysilicon is preferably used as the material of the active region 4 of the thin film transistor. This is because, in general, low temperature polysilicon is sensitive to light, so it is generally necessary to provide the light shielding structure 1 when it is used as the active region 4.
  • the active region 4 is made of other semiconductor materials, the above-described light shielding structure 1 can also be used.
  • the storage capacitor C further includes a third plate 31 electrically connected to the first plate 11 through a via hole, and the second plate 21 is disposed between the first plate 11 and the third plate 31, and The two-pole plate 21 and the third electrode plate 31 are respectively disposed in the same layer as the gate electrode 2, the source/drain electrodes 3, and the two different active regions 4.
  • the plates located in different layers can also be connected to form one pole of the storage capacitor, thereby further increasing the plate without changing the projected area of the storage capacitor C.
  • the total area ie, increase the number of plates
  • a light-shielding structure 1 a buffer layer 5, an active region 4, a gate insulating layer 6, a gate 2, an interlayer insulating layer 7 source and drain electrodes 3 are sequentially disposed;
  • the second plate 21 is disposed in the same layer as the gate 2;
  • the third plate 31 is disposed in the same layer as the source and drain electrodes 3.
  • the structure of the array substrate is preferably as shown in FIG. 3, the thin film transistor is in the form of a top gate, and the layer in which the source and drain electrodes 3 are located is located above the layer where the gate electrode 2 is located.
  • the second plate 21 is disposed in the same layer as the gate 2 as one pole of the storage capacitor C and sandwiched between the first plate 11 and the third plate 31; and the third plate 31 is The source and drain electrodes 3 are disposed in the same layer and are electrically connected to the first plate 11 through the via holes to jointly form the other pole of the storage capacitor C.
  • the structure is in the above form; and in the case where it is not desirable to reduce the resistance and the plate is disposed in the same layer as the active region 4, the corresponding second plate 21 and third plate 31 are necessarily in the above form.
  • the form of the storage capacitor C is not limited thereto, and for example, it may also be set.
  • the plate in the same layer as the active region 4 is provided as a part of the storage capacitor C.
  • the positional relationship of the gate 2 and the source and drain 3 may be reversed.
  • the two poles of the storage capacitor C should actually be electrically connected to other structures in the array substrate such that they become part of the circuit.
  • the third plate 31 ie, one plate of the storage capacitor C
  • the drain of a thin film transistor of course, the source of another thin film transistor is also connected
  • its second plate 21 can be connected to the gate 2 of the thin film transistor. Since the drawings schematically show the layer relationship between the plates of the storage capacitor C, the connection between the poles and other structures is not shown.
  • At least one insulating layer is disposed between the layer where the light shielding structure 1 is located and the layer where the second electrode plate 21 is located; there is no insulating layer above the first electrode plate 11, or the insulating layer above the first electrode plate 11 is higher than the light shielding structure 1
  • the thickness of the insulating layer is small. That is, the thickness t1 of the insulating layer above the first plate and the thickness t2 above the light shielding structure satisfy 0 ⁇ t1 ⁇ t2.
  • the insulating layer is a buffer layer 5 overlying the light shielding structure 1, and the active region 4 is provided on the buffer layer 5.
  • one or more of the insulating layers may be thinned or removed at a position corresponding to the first plate 11, thereby reducing the first The distance between the plate 11 and the second plate 21.
  • the light shielding structure 1 (ie, the layer in which the first electrode plate 11 is located) is generally disposed directly on the substrate 9, which is covered with the buffer layer 5, and the active region 4 is located on the buffer layer 5, so that The buffer layer 5 is an insulating layer which is completely removed or thinned over the first plate 11, and the buffer layer 5 above the light-shielding structure 1 remains unchanged.
  • the buffer layer 5 is preferably used as the insulating layer is because the main function of the buffer layer 5 is to improve the bonding force between the active region 4 of the semiconductor material and the substrate 9, so that it is only present at the active region 4, After the active region 4 is formed, the buffer layer 5 not covered by the active region 4 can be directly etched thinned or removed without adding an additional exposure step, and the process is relatively simple.
  • the insulating layer between the other plates of the storage capacitor C can also be partially thinned.
  • the interlayer insulating layer 7 between the second plate 21 and the third plate 31 can be thinned, thereby increasing the second pole.
  • the above thinning requires a separate exposure step (because the interlayer insulating layer 7 at the gate 2 cannot be thinned) to control the shape of the interlayer insulating layer 7, so the process is complicated.
  • the embodiment provides a method for preparing the above array substrate, which comprises the steps of:
  • the array substrate in FIG. 3 is taken as an example, and the preparation method thereof is described in detail.
  • the method of preparing the array substrate may include the following steps S101-S106.
  • the light shielding structure 1 and the first electrode plate 11 are simultaneously formed on the substrate 9 by a patterning process.
  • the patterning process may be a photolithography process including steps of forming a material layer, coating a photoresist, exposing, developing, etching, photoresist stripping, and the like.
  • the light shielding structure 1 and the first electrode plate 11 are simultaneously formed by etching the same material layer, and the material may be an opaque metal such as titanium.
  • the main function of the buffer layer 5 is to increase the bonding strength between the semiconductor material and the substrate 9 (usually glass).
  • the active region 4 is preferably formed of low temperature polysilicon.
  • the low temperature polysilicon can be formed by laser annealing of amorphous silicon, and the specific process thereof will not be described in detail herein.
  • a portion of the exposed buffer layer 5 is removed by etching. That is, the buffer layer 5 outside the corresponding region of the light shielding structure 1 is partially thinned.
  • This step can utilize the pattern of the active region 4 as a mask for etching without using an additional mask.
  • the buffer layer 5 is simultaneously locally thinned by over-etching. That is, the above steps S103 and 104 can be combined into a single step S104' in which the active region 4 and the partially thinned buffer layer 5 are simultaneously formed.
  • a gate insulating layer 6 is formed on the substrate 9 on which the foregoing steps are completed, and then the gate electrode 2 and the second electrode plate 21 are formed by a patterning process to obtain a structure as shown in FIG.
  • the gate insulating layer 6 covering the active region 4 may be formed by blanket deposition.
  • the gate electrode 2 and the second electrode plate 21 are simultaneously formed.
  • the gate 2 is located above the active region 4, and the second plate 21 is disposed opposite the first plate 11.
  • a first via hole penetrating the interlayer insulating layer 7 and the gate insulating layer 6 is formed over the active region 4 by one patterning process, and a through-hole insulating layer 7 is formed in a region of the storage capacitor.
  • the source drain 3 is electrically connected to the active region 4 through the first via
  • the third plate 31 is electrically connected to the first plate 11 through the second via. It can be seen that the third plate 31 (and its second via) can be formed simultaneously with the source drain 3 (and its first via) without the need for an additional masking process.
  • the interlayer insulating layer 7 covering the gate electrode 2 and the second electrode plate 21 is formed first, and then the active region 4, the first electrode plate 11, and the second electrode plate 21 are formed in the respective insulating layers.
  • the source and drain electrodes are respectively connected to both sides of the active region 4, thereby forming a thin film transistor.
  • the two poles of the storage capacitor C, and the source and drain electrodes 3, the gate 2, and the like of the thin film transistor are also connected to other structures or signal lines, and the connection form may be different depending on the specific circuit. Adjustment, so it will not be described in detail here.
  • This embodiment provides a display device including any of the above array substrates.
  • the display device is preferably a liquid crystal display device; since the liquid crystal display device includes a backlight, it is most necessary to provide the above-described light shielding structure.
  • the display device can be any product or component having a display function, such as a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, or the like.
  • a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, or the like.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种阵列基板及其制备方法、显示装置。阵列基板包括：薄膜晶体管，包括有源区（4）、源漏极（3）、栅极（2）；设于有源区下方的由导电材料构成的遮光结构（1）；存储电容，包括间隔且相对设置的第一极片（11）和第二极片（21）；第一极片与遮光结构同层设置，第二极片与有源区、源漏极、栅极中的任意一种同层设置。解决了现有的阵列基板中的存储电容的面积不足，电容值小的问题。

Description

阵列基板及其制备方法、显示装置 技术领域
本发明属于显示技术领域，具体涉及一种阵列基板及其制备方法、显示装置。
背景技术
在GOA模式的阵列基板中，用于驱动栅线的栅极驱动电路直接制作在阵列基板的边缘部。而栅极驱动电路通常由多个级联的移位寄存器构成，图1示出了一种常用的移位寄存器的电路结构，可见，其中包括多个存储电容C。
存储电容C的极板具有下述几种常见设计。在第一种方式中，多晶硅层和栅极层分别作为存储电容C的两个极板。在第二种方式中，多晶硅层和数据线层分别作为存储电容C的两个极板。在第一和第二种方式中，由于多晶硅电阻大，需要增加一掩模板对多晶硅重掺杂以降低电阻。另外，多晶硅在重掺杂之后的电阻仍比金属大很多，因此还需要增加存储电容的极板的面积。在第三种方式中，栅极层和数据线层分别作为存储电容C的两个极板。为了不增加掩模板，通常采用图2所示的第三种方式。
如图2所示，栅极驱动电路的薄膜晶体管包括有源区4′、栅极2′和源漏极3′。存储电容C由两个极板21′、31′组成，第一极板21′与栅极2′同层设置，并且第二极板31′与源漏极3′(即数据线)同层设置。第一和第二极板21′、31′实际还应连接到其他结构，例如第一极板21′可连接到某薄膜晶体管的栅极，并且第二极板31′可连接到接地端口。阵列基板中还包括依次堆叠的基底9′、缓冲层(buffer)5′、栅绝缘层6′、层间绝缘层(ILD)7′等已知结构，在此不再详细描述。在图2所示的设计中，由于栅极所在层和源漏极(数据线)所在层之间的ILD 7′较厚，存储电容C的极板也需要非常大。
基于上述极板设计，存储电容C的电容值降低，不能满足需求。尤其随着窄边框显示装置的发展，栅极驱动电路的面积越来越小，其中存储电容的面积也不断缩小，电容值更加不能满足要求。因此，本领域中存在对一种具有改进设计的存储电容的需求。
发明内容
本发明针对现有的阵列基板中的存储电容的极板面积不足，电容值小的问题，提供一种可在不扩大面积的情况下增加存储电容的电容值的阵列基板及其制备方法、显示装置。
为此，本发明实施例采用下述技术方案。
在第一方面，提供了一种阵列基板，其包括：
薄膜晶体管，包括有源区、源漏极和栅极；
设于所述有源区下方的由导电材料构成的遮光结构；以及
存储电容，包括间隔且相对设置的第一极板和第二极板，
其中所述第一极板与遮光结构同层设置，所述第二极板与所述有源区、所述源漏极和所述栅极中的任意一种同层设置。
优选地，所述第二极板可以与所述源漏极同层设置，或者可以与所述栅极同层设置。
优选地，所述存储电容还可以包括：与所述第一极板电连接的第三极板，其中所述第二极板设于第一极板与所述第三极板之间，并且所述第二极板和所述第三极板分别与所述栅极、所述源漏极和所述有源区中的不同两个同层设置。
进一步优选地，在远离所述阵列基板的基底的方向上，可以依次设有所述遮光结构、一缓冲层、所述有源区、一栅绝缘层、所述栅极、一层间绝缘层和所述源漏极；所述第二极板与所述栅极同层设置；以及所述第三极板与所述源漏极同层设置。
优选地，所述遮光结构所在层与所述第二极板所在层之间可以设有至少一个绝缘层；以及所述至少一个绝缘层在所述第一极板上方具有厚度t1并且在所述遮光结构上方具有厚度t2，其中0≤t1≤t2。
进一步优选地，所述至少一个绝缘层可以为覆盖在所述遮光结构上的缓冲层；以及所述有源区可以设于所述缓冲层上。
优选地，所述第三极板可以通过贯穿所述缓冲层、所述栅绝缘层和所述层间绝缘层的过孔电连接到所述第一极板。
优选地，所述有源区由低温多晶硅构成。
优选地，所述阵列基板包括位于边缘部的栅极驱动电路，所述存储电容为栅极驱动电路中的存储电容。
在第二方面，提供了一种显示装置，其包括：
上述的阵列基板。
在第三方面，提供了一种阵列基板的制备方法，所述阵列基板包括：薄膜晶体管，包括有源区、源漏极和栅极；设于所述有源区下方的由导电材料构成的遮光结构；以及存储电容，包括间隔且相对设置的第一极板和第二极板，
其中所述第一极板与所述遮光结构同层设置，所述第二极板与所述有源区、所述源漏极和所述栅极中的任意一种同层设置，
所述方法包括步骤：
S1、通过第一构图工艺形成包括所述第一极板和所述遮光结构的图形；以及
S2、通过第二构图工艺形成所述第二极板的图形，同时形成所述有源区、所述源漏极和所述栅极中的任意一种的图形。
优选地，在所述步骤S1之后且在所述步骤S2之前，所述方法还可以包括：
步骤S102、在所述包括所述第一极板和所述遮光结构的图形上形成缓冲层。
优选地，在所述步骤S102之后，所述方法还可以包括：
步骤103、在所述步骤S102得到的基底上，通过第三构图工艺，形成所述有源区4。
优选地，在所述步骤S103之后，所述方法还可以包括：
步骤S104、在所述步骤S103得到的基底上，通过刻蚀以减薄所述遮光结构对应区域之外的缓冲层。
优选地，在所述步骤S102之后，所述方法还可以包括：
步骤S104′、在所述步骤S102得到的基底上，通过第三构图工艺，形成所述有源区4，并且同时减薄所述遮光结构对应区域之外的缓冲层。
优选地，在所述步骤S104或步骤S104′之后，所述方法还可以包括：
步骤S105、在所述步骤S104或步骤S104′得到的基底上，通过第四构图工艺形成位于所述有源区上方的栅极以及与所述第一极板相对设置的第二极板。
优选地，在所述步骤S105之后，所述方法还可以包括：
步骤S106、在所述步骤S105得到的基底上，形成层间绝缘层；通过第五构图工艺，形成贯穿层间绝缘层和栅绝缘层的第一过孔以及贯穿层间绝缘层、栅绝缘层和缓冲层的第二过孔；以及通过第六构图工艺，形成通过第一过孔电连接到有源区的源漏极以及通过第二过孔电连接到第一极板的第三极板。
在上下文中，术语“同层设置”是指两个结构由同一个材料层经过构图工艺形成。这两个结构在层叠关系上是处于同一个层中，但与基底的距离不一定相同。
本发明的阵列基板中，存储电容的第一极板与遮光结构同层设置，故其增加了可设置极板的层，从而可在不增大存储电容的投影面积的情况下，增大其极板总面积，进而提高存储电容的电容值；另外，遮光结构是阵列基板中原有的结构，而存储电容的第一极板与其同步形成，故不需要为形成第一极板增加新的步骤，其工艺没有变复杂。
附图说明
图1为一种已知移位寄存器的电路图；
图2为一种已知阵列基板的局部剖面图；
图3为本发明实施例的一种阵列基板的局部剖面图；
图4为本发明实施例的一种阵列基板在形成有源区后的局部剖面图；
图5为本发明实施例的一种阵列基板在对缓冲层进行减薄后的局部剖面图；
图6为本发明实施例的一种阵列基板在形成层间绝缘层后的局部剖面图；以及
图7为本发明实施例的一种阵列基板制作方法的流程图。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
附图标记：21′、11第一极板；31′、21第二极板；31、第三极板；1、遮光结构；2′、2栅极；3′、3源漏极；4’、4有源区；5′、5缓冲 层；6′、6栅绝缘层；7′、7层间绝缘层；9′、9基底；C存储电容。
实施例1
如图3至图6所示，本实施例提供一种阵列基板。该阵列基板包括：薄膜晶体管，其包括有源区4、源漏极3、栅极2。该阵列基板还包括存储电容C，其包括间隔且相对设置的第一极板11和第二极板21。
具体地，该阵列基板可为用于显示装置的阵列基板，其中包括用于实现不同功能的电路(如栅极驱动电路、像素电路等)，而这些电路中即包括薄膜晶体管和存储电容C。
优选地，本实施例的阵列基板包括位于边缘部的栅极驱动电路。本实施例中描述的存储电容C也是指栅极驱动电路中的存储电容C。
这是因为，显示区中用于驱动像素的像素电路中的存储电容一般能够满足要求，而栅极驱动电路用于驱动栅线，其中所需的存储电容C的电容值一般较大。因此，本实施例优选针对栅极驱动电路中的用存储电容C。当然，本实施例的存储电容C也可为像素电路等其他电路中的存储电容。
在本实施例中，阵列基板还包括至少设于有源区4下方的由导电材料构成的遮光结构1，而存储电容C的第一极板11与遮光结构1同层设置，并且第二极板21与有源区4、源漏极3、栅极2中的任意一种同层设置。
术语“同层设置”是指两个结构由同一个材料层经过构图工艺形成。这两个结构在层叠关系上是处于同一个层中，但与基底9的距离不一定相同。
在现有的阵列基板中，为防止来自背光源的光线照射到薄膜晶体管的有源区4，故在有源区4下方可设置由钛等不透明金属构成的遮光结构1。在本实施例中，增加与遮光结构1同层设置的第一极板11，并将其作为存储电容C的一部分，这也就是增加了可能容纳存储电容C的极板的层，或者说增加了存储电容C的极板数，从而在保证存储电容C的投影面积不变的情况下增大极板的总面积，进而增大其电容值。
优选地，第二极板21与源漏极3或栅极2同层设置。
也就是说，存储电容C的第二极板21优选不与有源区4同层设置，而是与源漏极3或栅极2同层设置，这是因为与有源区4同层的极板 必然由半导体材料构成，其电阻较高，不利于改善存储电容C的性能。
优选地，有源区4由低温多晶硅(LTPS)构成。
也就是说，优选用低温多晶硅作为薄膜晶体管的有源区4的材料。这是因为通常而言，低温多晶硅对光照敏感，故其用作有源区4时一般需要设置遮光结构1。
当然，如果有源区4采用其他的半导体材料构成，也可使用上述遮光结构1。
优选地，存储电容C还包括：通过过孔与第一极板11电连接的第三极板31，第二极板21设于第一极板11与第三极板31之间，并且第二极板21和第三极板31分别与栅极2、源漏极3、有源区4中的不同两个同层设置。
也就是说，如图3所示，还可将位于不同层中的极板连接起来，共同构成存储电容的一极，从而在不改变存储电容C投影面积的情况下，进一步增大其极板的总面积(即增大极板的个数)，提高电容值。由于上述遮光结构1和第一极板11一般直接位于基底9上，其下方没有其他层结构，故优选将第一极板11与第三极板31连接，并将第二极板21夹在二者之间。
优选地，在远离阵列基板的基底9的方向上，依次设有遮光结构1、缓冲层5、有源区4、栅绝缘层6、栅极2、层间绝缘层7源漏极3；
第二极板21与栅极2同层设置；以及
第三极板31与源漏极3同层设置。
也就是说，阵列基板的结构优选如图3所示，薄膜晶体管为顶栅形式，且源漏极3所在层位于栅极2所在层上方。由此，第二极板21与栅极2同层设置，作为存储电容C的一极，且被夹在第一极板11与第三极板31之间；而第三极板31则与源漏极3同层设置，且与第一极板11通过过孔电连接，从而共同构成存储电容C的另一极。
这是因为，理论上薄膜晶体管的有源区4、源漏极3、栅极2的位置关系虽然有很多种，但从工艺难度、可靠性、技术成熟度等多方面考虑，其最优的结构为以上的形式；而在为了减小电阻而不希望极板与有源区4同层设置的情况下，相应的第二极板21与第三极板31必然为以上形式。
当然，应当理解，存储电容C的形式并不限于此，例如，也可设 置与有源区4同层的极板作为存储电容C的一部分；或者，以上栅极2、源漏极3的位置关系也可相反等。
另外，应当理解，存储电容C的两极实际还应与阵列基板中的其他结构电连接，从而使其成为电路的一部分。例如，对于图1中靠上的存储电容C，其第三极板31(即存储电容C的一个极板)可与某薄膜晶体管的漏极连接(当然还连接另一薄膜晶体管的源极)，而其第二极板21则可与该薄膜晶体管的栅极2连接。由于各附图中主要是示意性的表示存储电容C各极板间的层关系，故未示出其各极与其他结构间的连接。
当然，根据电路构造的不同，存储电容C的两极的具体连接情况也是多样的。此外，在实际应用中，图3所示结构的上方还可能存在平坦化层、保护层等其它层或结构。这些均为本领域的常用设计或结构，故在此不再详细描述。
优选地，遮光结构1所在层与第二极板21所在层之间设有至少一个绝缘层；第一极板11上方没有绝缘层，或第一极板11上方的绝缘层比遮光结构1上方的绝缘层的厚度小。即，所述绝缘层在所述第一极板上方的厚度t1以及在所述遮光结构上方的厚度t2满足0≤t1≤t2。
更优选地，上述绝缘层为覆盖在遮光结构1上的缓冲层5，并且有源区4设于缓冲层5上。
显然，第一极板11与第二极板21间的距离越小越利于提高电容值，而第一极板11所在层(即遮光结构1所在层)与第二极板21所在层(以栅极2所在层为例)之间设有多个绝缘层，为此，可将这些绝缘层中的一个或多个在对应第一极板11的位置减薄或除去，从而减小第一极板11与第二极板21间的距离。
具体地，遮光结构1(即第一极板11所在层)通常是直接设在基底9上的，其上覆盖有缓冲层5，而有源区4则位于缓冲层5上，因此即可以该缓冲层5为绝缘层，使其在第一极板11上方被完全除去或被减薄，而遮光结构1上方的缓冲层5则保持不变。之所以优选以缓冲层5作为绝缘层，是因为缓冲层5的主要作用是改善半导体材料的有源区4与基底9间的结合力，故其只要在有源区4处存在即可，因此在形成有源区4后，可直接对没有被有源区4覆盖的缓冲层5进行刻蚀减薄或除去，而不必增加额外的曝光步骤，工艺比较简单。
当然，存储电容C的其他极板间的绝缘层也可被部分减薄，例如第二极板21与第三极板31间的层间绝缘层7可被减薄，从而增大第二极板21与第三极板31间电容值。只是，以上这种减薄需要增加单独的曝光步骤(因为栅极2处的层间绝缘层7不能减薄)以控制层间绝缘层7的形状，故其工艺比较复杂。
实施例2
本实施例提供一种上述阵列基板的制备方法，其包括步骤：
S1、通过构图工艺形成包括第一极板11和遮光结构1的图形；以及
S2、通过构图工艺形成第二极板21的图形，同时形成有源区4、源漏极3、栅极2中的任意一种的图形。
具体地，以图3中的阵列基板为例，对其制备方法进行详细介绍。该阵列基板的制备方法可以包括下述步骤S101-S106。
S101、通过构图工艺在基底9上同时形成遮光结构1和第一极板11。
构图工艺可为光刻工艺，其包括形成材料层、涂布光刻胶、曝光、显影、刻蚀、光刻胶剥离等步骤。
遮光结构1和第一极板11是由同一个材料层经过刻蚀同时形成，并且该材料可为钛等不透光金属。
S102、在完成前述步骤的基底9上形成缓冲层5。
缓冲层5的主要作用是提高半导体材料与基底9(通常为玻璃)间的结合强度。
S103、在完成前述步骤的基底9上通过构图工艺形成有源区4，得到如图4所示的结构。
有源区4优选由低温多晶硅形成。低温多晶硅可由非晶硅经过激光退火形成，其具体工艺在此不再详细描述。
S104、对完成前述步骤的基底9上的缓冲层5进行刻蚀，从而形成局部减薄的缓冲层5，得到如图5所示的结构。
利用刻蚀将暴露的缓冲层5除去一部分。即，遮光结构1对应区域之外的缓冲层5被部分减薄。此步骤可以利用有源区4的图形作为刻蚀用掩模，而无需使用额外的掩模。
优选地，可以在步骤S103中形成有源区4的构图工艺中，在形成 有源区4时，通过过刻蚀(over-etch)而同时局部减薄该缓冲层5。也就是说，上述步骤S103和104可以合并成单个步骤S104′，在该步骤中同时形成有源区4和部分减薄的缓冲层5。
S105、在完成前述步骤的基底9上形成栅绝缘层6，之后通过构图工艺形成栅极2和第二极板21，得到如图6所示的结构。
例如，可以通过毯状沉积(blanket deposition)形成覆盖有源区4的栅绝缘层6。接着，同时形成栅极2和第二极板21。栅极2位于有源区4上方，并且第二极板21与第一极板11相对设置。
S106、在完成前述步骤的基底9上形成层间绝缘层7，之后形成贯穿层间绝缘层7、栅绝缘层6、缓冲层5等的过孔，再通过构图工艺形成第三极板31和源漏极3，得到如图3所示的阵列基板。
如图3所示，通过一次构图工艺，在有源区4上方形成贯穿层间绝缘层7和栅极绝缘层6的第一过孔，同时在存储电容的区域形成贯穿层间绝缘层7、栅绝缘层6和缓冲层5的第二过孔。源漏极3通过第一过孔电连接到有源区4，并且第三极板31通过第二过孔电连接到第一极板11。由此可见，可以与源漏极3(及其第一过孔)同时形成第三极板31(及其第二过孔)，而不需要额外的掩模工艺。
也就是说，先形成覆盖栅极2和第二极板21的层间绝缘层7，之后再于各绝缘层中形成与有源区4、第一极板11、第二极板21等电连接的过孔，再形成第三极板31和源漏极3，其中第三极板31与第二极板21相对，并通过过孔与第一极板11电连接，而源漏极3中的源极和漏极，则分别连接有源区4的两侧，从而形成薄膜晶体管。
当然，在实际的阵列基板中，存储电容C的两极，以及薄膜晶体管的源漏极3、栅极2等还要与其他的结构或信号线连接，由于其连接形式可根据具体电路的不同而调整，故在此不再详细描述。
实施例3
本实施例提供了一种显示装置，其包括上述任意一种阵列基板。
具体地，该显示装置优选为液晶显示装置；因为液晶显示装置中包括使用背光源，故最需要设置上述的遮光结构。
当然，所述显示装置可以为任何具有显示功能的产品或部件，例如液晶面板、电子纸、OLED面板、液晶电视、液晶显示器、数码相框、手机、平板电脑等。
可以理解，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (17)

  1. 一种阵列基板，包括：
    薄膜晶体管，包括有源区、源漏极和栅极；
    设于所述有源区下方的由导电材料构成的遮光结构；以及
    存储电容，包括间隔且相对设置的第一极板和第二极板；
    其特征在于，
    所述第一极板与所述遮光结构同层设置，所述第二极板与所述有源区、所述源漏极和所述栅极中的任意一种同层设置。
  2. 根据权利要求1所述的阵列基板，其特征在于，
    所述第二极板与所述源漏极同层设置，或者与所述栅极同层设置。
  3. 根据权利要求1所述的阵列基板，其特征在于，所述存储电容还包括：
    与所述第一极板电连接的第三极板，其中所述第二极板设于所述第一极板与所述第三极板之间，并且所述第二极板和所述第三极板分别与所述栅极、所述源漏极和所述有源区中的不同两个同层设置。
  4. 根据权利要求3所述的阵列基板，其特征在于，在远离所述阵列基板的基底的方向上，依次设有所述遮光结构、一缓冲层、所述有源区、一栅绝缘层、所述栅极、一层间绝缘层和所述源漏极；
    所述第二极板与所述栅极同层设置；以及
    所述第三极板与所述源漏极同层设置。
  5. 根据权利要求4所述的阵列基板，其特征在于，
    所述遮光结构所在层与所述第二极板所在层之间设有至少一个绝缘层；以及
    所述至少一个绝缘层在所述第一极板上方具有厚度t1并且在所述遮光结构上方具有厚度t2，其中0≤t1≤t2。
  6. 根据权利要求5所述的阵列基板，其特征在于，
    所述至少一个绝缘层为覆盖在所述遮光结构上的缓冲层；以及
    所述有源区设于所述缓冲层上。
  7. 根据权利要求6所述的阵列极板，其特征在于，
    所述第三极板通过贯穿所述缓冲层、所述栅绝缘层和所述层间绝缘层的过孔电连接到所述第一极板。
  8. 根据权利要求1至7中任意一项所述的阵列基板，其特征在于，
    所述有源区由低温多晶硅构成。
  9. 根据权利要求1至7中任意一项所述的阵列基板，其特征在于，
    所述阵列基板包括位于边缘部的栅极驱动电路，所述存储电容为栅极驱动电路中的存储电容。
  10. 一种显示装置，其特征在于，包括：
    根据权利要求1至9中任意一项所述的阵列基板。
  11. 一种阵列基板的制备方法，其特征在于，
    所述阵列基板包括：薄膜晶体管，包括有源区、源漏极和栅极；设于所述有源区下方的由导电材料构成的遮光结构；以及存储电容，包括间隔且相对设置的第一极板和第二极板，
    其中所述第一极板与所述遮光结构同层设置，所述第二极板与所述有源区、所述源漏极和所述栅极中的任意一种同层设置，
    所述方法包括步骤：
    S1、通过第一构图工艺形成包括所述第一极板和所述遮光结构的图形；以及
    S2、通过第二构图工艺形成所述第二极板的图形，同时形成所述有源区、所述源漏极和所述栅极中的任意一种的图形。
  12. 如权利要求11所述的方法，其特征在于，在所述步骤S1之后且在所述步骤S2之前，所述方法还包括：
    步骤S102、在所述包括所述第一极板和所述遮光结构的图形上形成缓冲层。
  13. 如权利要求12所述的方法，其特征在于，在所述步骤S102之后，所述方法还包括：
    步骤103、在所述步骤S102得到的基底上，通过第三构图工艺，形成所述有源区4。
  14. 如权利要求13所述的方法，其特征在于，在所述步骤S103之后，所述方法还包括：
    步骤S104、在所述步骤S103得到的基底上，通过刻蚀以减薄所述遮光结构对应区域之外的缓冲层。
  15. 如权利要求12所述的方法，其特征在于，在所述步骤S102之后，所述方法还包括：
    步骤S104′、在所述步骤S102得到的基底上，通过第三构图工艺，形成所述有源区4，并且同时减薄所述遮光结构对应区域之外的缓冲层。
  16. 如权利要求14或15所述的方法，其特征在于，在所述步骤S104或步骤S104′之后，所述方法还包括：
    步骤S105、在所述步骤S104或步骤S104′得到的基底上，通过第四构图工艺形成位于所述有源区上方的栅极以及与所述第一极板相对设置的第二极板。
  17. 如权利要求16所述的方法，其特征在于，在所述步骤S105之后，所述方法还包括：
    步骤S106、在所述步骤S105得到的基底上，形成层间绝缘层；通过第五构图工艺，形成贯穿层间绝缘层和栅绝缘层的第一过孔以及贯穿层间绝缘层、栅绝缘层和缓冲层的第二过孔；以及通过第六构图工艺，形成通过第一过孔电连接到有源区的源漏极以及通过第二过孔电连接到第一极板的第三极板。
PCT/CN2015/085907 2015-04-14 2015-08-03 阵列基板及其制备方法、显示装置 WO2016165241A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/127,771 US20180197897A1 (en) 2015-04-14 2015-08-03 Array substrate and method for fabricating the same, display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510175829.X 2015-04-14
CN201510175829.XA CN104900655A (zh) 2015-04-14 2015-04-14 阵列基板及其制备方法、显示装置

Publications (1)

Publication Number Publication Date
WO2016165241A1 true WO2016165241A1 (zh) 2016-10-20

Family

ID=54033215

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/085907 WO2016165241A1 (zh) 2015-04-14 2015-08-03 阵列基板及其制备方法、显示装置

Country Status (3)

Country Link
US (1) US20180197897A1 (zh)
CN (1) CN104900655A (zh)
WO (1) WO2016165241A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113223420A (zh) * 2021-05-06 2021-08-06 湖北长江新型显示产业创新中心有限公司 一种显示面板及显示装置

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105428369A (zh) * 2015-11-04 2016-03-23 武汉华星光电技术有限公司 阵列基板行驱动结构及显示面板
US10790233B2 (en) * 2016-05-25 2020-09-29 Intel Corporation Package substrates with integral devices
CN109216373B (zh) * 2017-07-07 2021-04-09 京东方科技集团股份有限公司 阵列基板及其制备方法
CN107579083B (zh) * 2017-09-30 2024-06-11 京东方科技集团股份有限公司 阵列基板及制备方法和显示装置
CN107785399B (zh) * 2017-10-26 2020-02-21 武汉天马微电子有限公司 一种显示面板及显示装置
CN108257977B (zh) 2018-01-10 2021-01-01 京东方科技集团股份有限公司 显示背板及其制作方法、显示面板和显示装置
US10497519B1 (en) 2018-09-27 2019-12-03 International Business Machines Corporation Back-end-of-the line capacitor
CN110164870A (zh) 2019-05-14 2019-08-23 深圳市华星光电半导体显示技术有限公司 含电容背板构造
CN118053878A (zh) 2019-09-10 2024-05-17 合肥京东方卓印科技有限公司 栅极驱动结构、阵列基板及显示装置
CN110797353A (zh) * 2019-11-12 2020-02-14 京东方科技集团股份有限公司 阵列基板、显示面板和显示装置
KR20210065255A (ko) * 2019-11-26 2021-06-04 삼성디스플레이 주식회사 증막 마스크, 이를 이용한 디스플레이 장치의 제조 방법 및 디스플레이 장치
WO2021120166A1 (zh) * 2019-12-20 2021-06-24 京东方科技集团股份有限公司 显示基板及其制作方法、和显示装置
CN114883343B (zh) * 2022-04-21 2024-03-26 北海惠科光电技术有限公司 薄膜晶体管、显示基板和薄膜晶体管的制备方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101430463A (zh) * 2007-11-09 2009-05-13 上海广电Nec液晶显示器有限公司 液晶显示装置及其制作方法
CN103904086A (zh) * 2012-12-24 2014-07-02 上海天马微电子有限公司 一种薄膜晶体管阵列基板

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4277874B2 (ja) * 2006-05-23 2009-06-10 エプソンイメージングデバイス株式会社 電気光学装置の製造方法
JP4179393B2 (ja) * 2006-09-14 2008-11-12 エプソンイメージングデバイス株式会社 表示装置及びその製造方法
CN100526962C (zh) * 2006-09-14 2009-08-12 爱普生映像元器件有限公司 显示装置及其制造方法
JP2009169071A (ja) * 2008-01-16 2009-07-30 Sony Corp 表示装置
KR101113394B1 (ko) * 2009-12-17 2012-02-29 삼성모바일디스플레이주식회사 액정표시장치의 어레이 기판
KR101335527B1 (ko) * 2012-02-23 2013-12-02 엘지디스플레이 주식회사 유기전계발광표시장치 및 그 제조 방법
CN103268047B (zh) * 2012-12-31 2015-12-09 厦门天马微电子有限公司 一种ltps阵列基板及其制造方法
CN104008999B (zh) * 2014-05-26 2017-09-19 昆山国显光电有限公司 薄膜晶体管阵列构件、其制造方法及阵列基板

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101430463A (zh) * 2007-11-09 2009-05-13 上海广电Nec液晶显示器有限公司 液晶显示装置及其制作方法
CN103904086A (zh) * 2012-12-24 2014-07-02 上海天马微电子有限公司 一种薄膜晶体管阵列基板

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113223420A (zh) * 2021-05-06 2021-08-06 湖北长江新型显示产业创新中心有限公司 一种显示面板及显示装置
CN113223420B (zh) * 2021-05-06 2023-04-21 湖北长江新型显示产业创新中心有限公司 一种显示面板及显示装置

Also Published As

Publication number Publication date
CN104900655A (zh) 2015-09-09
US20180197897A1 (en) 2018-07-12

Similar Documents

Publication Publication Date Title
WO2016165241A1 (zh) 阵列基板及其制备方法、显示装置
KR100470890B1 (ko) 박막 트랜지스터, 액티브 매트릭스 기판 및 그 제조방법과 표시장치
JP3844913B2 (ja) アクティブマトリックス型液晶表示装置
CN109671726B (zh) 阵列基板及其制造方法、显示面板、显示装置
US7439090B2 (en) Method for manufacturing a lower substrate of a liquid crystal display device
JP4722118B2 (ja) 液晶表示装置及びその製造方法
WO2014190727A1 (zh) 阵列基板及其制造方法、显示装置
WO2015081652A1 (zh) 阵列基板及其制作方法、显示装置
JP2005346054A (ja) 液晶表示装置及びその製造方法
WO2018120691A1 (zh) 阵列基板及其制造方法、显示装置
US11233106B2 (en) Array substrate, display apparatus, and method of fabricating array substrate
JP2004311931A (ja) 薄膜トランジスタアレイ基板及びその製造方法
US11385732B2 (en) Array substrate, manufacturing method thereof, touch display panel and touch display device
WO2016095639A1 (zh) 阵列基板及其制造方法、显示装置
JP2008139619A (ja) 液晶表示装置及びその製造方法
WO2018090496A1 (zh) 一种阵列基板及其制备方法、液晶显示面板
KR20140013166A (ko) 유기발광소자표시장치 및 그 제조방법
JP3696127B2 (ja) 液晶用マトリクス基板の製造方法
JP5048914B2 (ja) 薄膜トランジスタ表示板の製造方法
WO2019210602A1 (zh) 阵列基板及其制造方法、显示面板
JP2019070768A (ja) アレイ基板およびその製造方法、並びに表示パネル
US9847427B2 (en) Array substrate, method for fabricating the same, and display device
WO2019061751A1 (zh) Tft基板的制作方法及其结构
WO2015096449A1 (zh) 掩膜版组、像素单元及其制作方法、阵列基板以及显示装置
WO2012073942A1 (ja) 半導体装置およびその製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15888944

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15888944

Country of ref document: EP

Kind code of ref document: A1