WO2020258465A1 - 一种阵列基板及其制作方法、显示面板 - Google Patents

一种阵列基板及其制作方法、显示面板 Download PDF

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Publication number
WO2020258465A1
WO2020258465A1 PCT/CN2019/101169 CN2019101169W WO2020258465A1 WO 2020258465 A1 WO2020258465 A1 WO 2020258465A1 CN 2019101169 W CN2019101169 W CN 2019101169W WO 2020258465 A1 WO2020258465 A1 WO 2020258465A1
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Prior art keywords
layer
opening
organic layer
gate insulating
display area
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PCT/CN2019/101169
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English (en)
French (fr)
Inventor
许祖钊
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武汉华星光电半导体显示技术有限公司
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Priority to US16/630,473 priority Critical patent/US11495621B2/en
Publication of WO2020258465A1 publication Critical patent/WO2020258465A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Definitions

  • This application relates to the technical field of display panels, and in particular to an array substrate, a manufacturing method thereof, and a display panel.
  • AMOLED Active-matrix organic light emitting diode
  • the key steps to realize the flexibility of the panel are: before forming the source and drain layers, etching the inorganic film layer with poor stress on the display area and poor flexibility Holes are dug and an organic layer is formed to fill the holes, thereby improving the bending performance of the display area.
  • the organic layer formed in the above steps of achieving panel flexibility will increase the film level difference, which in turn leads to the problem of thinner source and drain layers or even disconnection in the subsequent process of the source and drain layers.
  • the present application provides an array substrate, a manufacturing method thereof, and a display panel, so as to avoid the problem of thinner source and drain layers or even disconnection due to excessive film level difference.
  • an embodiment of the present application provides an array substrate, the array substrate includes: a base, the base includes a display area; an inorganic film layer on the base, the inorganic film layer is provided with a first opening and a second opening Opening, the first opening and the second opening are located in the display area; the first organic layer located on the inorganic film layer, the first organic layer fills the first opening, and the thickness of the first organic layer is not greater than the depth of the first opening, An organic layer does not fill the second opening; the source and drain layer located on the first organic layer covers the inner wall of the second opening.
  • the inorganic film group layer includes a buffer layer, a first gate insulating layer, a second gate insulating layer, and an interlayer dielectric layer which are sequentially away from the substrate.
  • the second opening penetrates the first gate insulating layer, the second gate insulating layer and the interlayer. Medium layer.
  • the array substrate further includes a low-temperature polysilicon layer, a first metal layer, and a second metal layer.
  • the low-temperature polysilicon layer is located between the buffer layer and the first gate insulating layer, and the first metal layer is located between the first gate insulating layer and the second gate insulating layer.
  • the second metal layer is located between the second gate insulating layer and the interlayer dielectric layer; the source and drain layers are connected to the low-temperature polysilicon layer through the second opening, and the projection area of the first opening on the substrate is connected to the low-temperature polysilicon layer ,
  • the projection areas of the first metal layer and the second metal layer on the substrate do not overlap.
  • the depth of the first opening is equal to the thickness of the inorganic film group layer.
  • first openings There are multiple first openings, and the multiple first openings are evenly distributed on the display area.
  • the base further includes a non-display area located at the periphery of the display area
  • the array substrate further includes a second organic layer provided in the same layer as the first organic layer, the second organic layer is located in the non-display area, and the thickness of the first organic layer is smaller than that of the first organic layer. 2. The thickness of the inorganic layer.
  • the ratio of the thickness of the first organic layer to the thickness of the second organic layer ranges from 0.3 to 0.7.
  • the inorganic film group layer is further provided with a third opening, the third opening is located in the non-display area, and the second organic layer fills the third opening.
  • the embodiment of the present application also provides a manufacturing method of an array substrate.
  • the manufacturing method of the array substrate includes: providing a base, the base including a display area; forming an inorganic film layer on the base; The first opening and the second opening are made on the upper surface, the first opening and the second opening are located in the display area; the first organic layer is formed on the inorganic film group layer, the first organic layer fills the first opening, and the thickness of the first organic layer is not If the depth is greater than the first opening, the first organic layer does not fill the second opening; a source drain layer is formed on the first organic layer, and the source drain layer covers the inner wall of the second opening.
  • the inorganic film group layer includes a buffer layer, a first gate insulating layer, a second gate insulating layer, and an interlayer dielectric layer that are sequentially away from the substrate.
  • the step of forming an inorganic film group layer on the substrate specifically includes: depositing on the substrate A buffer layer; depositing a first gate insulating layer on the buffer layer; depositing a second gate insulating layer on the first gate insulating layer; depositing an interlayer dielectric layer on the second gate insulating layer.
  • the base further includes a non-display area located at the periphery of the display area
  • the array substrate further includes a second organic layer provided in the same layer as the first organic layer. The second organic layer is located in the non-display area, and the first organic layer is formed on the inorganic film layer.
  • the steps of the organic layer specifically include: providing a mask, the mask including a light-shielding area and a semi-transmissive area; aligning the mask with the inorganic film group layer, and forming a second organic film on the inorganic film group layer corresponding to the light-shielding area
  • the first organic layer is formed on the inorganic film group layer corresponding to the semi-transmissive region, and the thickness of the first organic layer is smaller than the thickness of the second inorganic layer.
  • embodiments of the present application also provide a display panel, the display panel includes an array substrate, the array substrate includes: a base, the base includes a display area; an inorganic film group layer on the base, the inorganic film group layer is provided There are a first opening and a second opening, the first opening and the second opening are located in the display area; the first organic layer on the inorganic film group layer, the first organic layer fills the first opening, and the thickness of the first organic layer is not greater than For the depth of the first opening, the first organic layer does not fill the second opening; the source and drain layer on the first organic layer covers the inner wall of the second opening.
  • the inorganic film group layer includes a buffer layer, a first gate insulating layer, a second gate insulating layer, and an interlayer dielectric layer which are sequentially away from the substrate.
  • the second opening penetrates the first gate insulating layer, the second gate insulating layer and the interlayer. Medium layer.
  • the array substrate further includes a low-temperature polysilicon layer, a first metal layer, and a second metal layer.
  • the low-temperature polysilicon layer is located between the buffer layer and the first gate insulating layer, and the first metal layer is located between the first gate insulating layer and the second gate insulating layer.
  • the second metal layer is located between the second gate insulating layer and the interlayer dielectric layer; the source and drain layers are connected to the low-temperature polysilicon layer through the second opening, and the projection area of the first opening on the substrate is connected to the low-temperature polysilicon layer ,
  • the projection areas of the first metal layer and the second metal layer on the substrate do not overlap.
  • the depth of the first opening is equal to the thickness of the inorganic film group layer.
  • first openings There are multiple first openings, and the multiple first openings are evenly distributed on the display area.
  • the base further includes a non-display area located at the periphery of the display area
  • the array substrate further includes a second organic layer provided in the same layer as the first organic layer, the second organic layer is located in the non-display area, and the thickness of the first organic layer is smaller than that of the first organic layer. 2. The thickness of the inorganic layer.
  • the ratio of the thickness of the first organic layer to the thickness of the second organic layer ranges from 0.3 to 0.7.
  • the inorganic film group layer is further provided with a third opening, the third opening is located in the non-display area, and the second organic layer fills the third opening.
  • the array substrate provided by the present application includes a base, and an inorganic film group layer, a first organic layer, and a source and drain layer sequentially arranged on the base, wherein the base includes a display area ,
  • the inorganic film layer is provided with a first opening and a second opening, the first opening and the second opening are located in the display area, the first organic layer fills the first opening, and the thickness of the first organic layer is not greater than the depth of the first opening
  • the first organic layer does not fill the second opening, and the source and drain layers cover the inner wall of the second opening. In this way, the thickness of the first organic layer is reduced to reduce the film level difference at the second opening, thereby avoiding the If the level difference is too large, the thickness of the source and drain layer is thin and even the wire is broken, thereby improving the product yield.
  • FIG. 1 is a schematic diagram of the structure of an array substrate provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of another structure of an array substrate provided by an embodiment of the present application.
  • FIG. 3 is another schematic diagram of the structure of the array substrate provided by the embodiment of the present application.
  • FIG. 4 is a schematic flowchart of a manufacturing method of an array substrate provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of the structure of S44 in Figure 4.
  • FIG. 6 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • the organic layer formed in the process of realizing the flexibility of the AMOLED panel will cause the film level difference to increase, which will lead to the problem of thinner source and drain layer or even disconnection in the subsequent process of source and drain layer.
  • the technical solution adopted in the present application is to provide an array substrate to avoid the problem of thin source and drain layers or even disconnection due to excessive film level difference.
  • FIG. 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present application.
  • the array substrate 10 includes a base 11, and an inorganic film group layer 12, a first organic layer 13, and a source/drain layer 14 sequentially disposed on the base 11.
  • the substrate 11 includes a display area C1
  • the inorganic film layer 12 is provided with a first opening 121 and a second opening 122
  • the first opening 121 and the second opening 122 are both located in the display area C1
  • the first organic layer 13 fills the first
  • the thickness T1 of the first organic layer 13 is not greater than the depth D1 of the first opening 121
  • the first organic layer 13 does not fill the second opening 122
  • the source and drain layer 14 covers the inner wall of the second opening 122.
  • the flexibility of the array substrate 10 can be achieved while reducing the size of the first organic layer near the second opening 122.
  • the film level difference caused by 13 prevents the source and drain layer 14 covering the inner wall of the second opening 122 from being locally thin and even disconnected.
  • the substrate 11 is a flexible substrate, and its material can be one of organic polymers such as polyimide, polycarbonate, polyethylene terephthalate, and polyethersulfone substrate.
  • the material of the first organic layer 13 may be an organic insulating material such as polyimide resin, epoxy resin, or acrylic resin.
  • the material of the source and drain layer 14 may be metal materials such as aluminum, copper, and silver.
  • the inorganic film layer 12 may include a buffer layer 123, a first gate insulating layer 124, a second gate insulating layer 125, and an interlayer dielectric layer 126 that are sequentially away from the substrate 11, and a second opening 122 It penetrates the first gate insulating layer 124, the second gate insulating layer 125 and the interlayer dielectric layer 126.
  • the material of the buffer layer 123 may be SiNx, SiOx or other suitable materials
  • the material of the first gate insulating layer 124 may be SiOx
  • the material of the second gate insulating layer 125 may be SiNx
  • the material of the interlayer dielectric layer 126 It can be one or both of SiNx and SiOx.
  • the array substrate 10 may further include a low-temperature polysilicon layer 15, a first metal layer 16 and a second metal layer 17 which are sequentially away from the base 11.
  • the low-temperature polysilicon layer 15, the first metal layer 16 and the second metal layer 17 are all located in the display area C1
  • the low-temperature anti-crystalline silicon layer 15 is located between the buffer layer 123 and the first gate insulating layer 124
  • the first metal layer 16 Located between the first gate insulating layer 124 and the second gate insulating layer 125
  • the second metal layer 17 is located between the second gate insulating layer 125 and the interlayer dielectric layer 126.
  • the low-temperature polysilicon layer 15 may be the active layer of the thin film transistor in the array substrate 10, and the source and drain layer 14 is connected to the low-temperature polysilicon layer 15 through the second opening 122, and the first metal layer 16 may be a patterned gate.
  • the second metal layer 17 may include the upper electrode of the storage capacitor in the array substrate 10, and it includes the gate of the thin film transistor in the array substrate 10 and the lower electrode of the storage capacitor. The bottom electrodes in the array together constitute a storage capacitor in the array substrate 10.
  • the projection area of the first opening 121 on the substrate 11 and the projection area of the low-temperature polysilicon layer 15, the first metal layer 16, and the second metal layer 17 on the substrate 11 do not overlap, that is, in the inorganic
  • the structure of the thin film transistor in the array substrate 10 is not damaged when the first opening 121 is formed on the film layer 12.
  • the first opening 121 is formed on the inorganic film layer 12, and the first organic layer is formed on the inorganic film layer 12. 13, and the first organic layer 13 fills the first opening 121, which can reduce the bending stress on the display area C1, thereby improving the bending performance of the display area C1.
  • the number of the first opening 121 may be multiple, so as to more effectively improve the bending performance of the display area C1. Further, the plurality of first openings 121 may be evenly distributed on the display area C1 to ensure the display uniformity of the display panel.
  • the depth D1 of the first opening 121 may be equal to the thickness of the inorganic film layer 12, that is, the first opening 121 may penetrate the buffer layer 123, the first gate insulating layer 124, and the second gate insulating layer 125. In this way, the bending stress on the display area of the array substrate can be reduced more effectively.
  • the substrate 11 may also include a non-display area C2 located at the periphery of the display area C1, and the array substrate 10 may also include a second organic layer 18 provided on the same layer as the first organic layer 13. .
  • the second organic layer 18 is located in the non-display area C1, and the thickness T1 of the first organic layer 13 is smaller than the thickness T2 of the second inorganic layer 18.
  • a third opening 127 may be opened on the inorganic film layer 12.
  • the third opening 127 is located in the non-display area C2 and the second organic layer 18 fills the third opening 127. In this way, the bending performance of the non-display area C2 can be improved.
  • the source/drain layer 14 may be a patterned source/drain layer 14, and the patterned source/drain layer 14 covers the first organic layer 13 and the second organic layer 18.
  • the source-drain layer 14 may include a plurality of wires arranged at intervals, and the wires span the display area C1 and the non-display area C2, one end is connected to the pixel unit (not shown in the figure) located in the display area C1, and the other One end is connected to the driver interface (not shown in the figure) located in the non-display area C2.
  • the third opening 127 may specifically include a first hole 1271 and a second hole 1272 that are stacked and connected on the substrate 11, wherein the first hole 1271 and the second hole 1272 may pass through the two
  • the second etching process is formed to reduce the thickness of the photoresist that needs to be coated in a single etching process, thereby reducing the energy consumption of the exposure machine in a single etching process, and is beneficial to reducing equipment costs.
  • the organic layer located between the source and drain layer 14 and the inorganic film group layer 13 has a uniform thickness.
  • the thickness of the organic layer located on the display area C1 is the same as that of the organic layer located on the non-display area C2.
  • the thickness of the layers is the same, and they can all be 1500 nm.
  • the film level difference is large, and the source-drain layer 14 is located on the inner wall of the second opening 122, especially at the corner of the second opening 122. , The problem of thinner thickness or even disconnection is easy to occur, which causes the array substrate to have no signal output and the display image is uncontrollable.
  • the thickness T2 of the second organic layer 18 may be the same as the thickness of the organic layer in the existing array substrate, but the thickness T1 of the first organic layer 13 is less than the thickness of the organic layer in the existing array substrate, and not greater than The depth D1 of the first opening 121. That is, compared with the prior art, the present application reduces the thickness of the organic layer on the display area C1, thereby reducing the film level difference.
  • the ratio of the thickness T1 of the first organic layer 13 to the thickness T2 of the second organic layer 18 may range from 0.3 to 0.7.
  • the thickness T1 of the first organic layer 13 may be 740 nm
  • the thickness T2 of the second organic layer 18 may be 1500 nm.
  • the thickness T2 of the second organic layer 18 can also be appropriately reduced without affecting the signal output on the non-display area C2.
  • the thickness T2 of the second organic layer 18 can be set to be the same as the thickness T1 of the first organic layer 13, so that the first organic layer 13 and the second organic layer 18 can be formed by a mask patterning process, thereby simplifying the array The manufacturing process of the substrate.
  • the above-mentioned first organic layer 13 has a uniform thickness layer structure as a whole, but due to the height difference of the inorganic film layer 12 at the first opening 121, the first organic layer 13 fills the first opening 121 Later, there will be a certain degree of uneven thickness at the first opening 121. Therefore, in the present application, the thickness T1 of the first organic layer 13 is based on the thickness of the first organic layer 13 far from the first opening 121. In the same way, the thickness T2 of the second organic layer 18 is also based on the thickness of the second organic layer 18 away from the third opening 127.
  • the array substrate in this embodiment reduces the thickness of the organic layer to reduce the film level difference, thereby avoiding the thinner source and drain layer thickness or even disconnection due to the excessive film level difference. Problems, thereby improving product yield.
  • FIG. 4 is a schematic flow chart of the manufacturing method of the array substrate provided by an embodiment of the present application.
  • the specific process of the manufacturing method of the array substrate may be as follows:
  • S41 Provide a substrate, and the substrate includes a display area.
  • the substrate is a flexible substrate, and its material can be one of organic polymers such as polyimide, polycarbonate, polyethylene terephthalate, and polyethersulfone substrate.
  • the inorganic film group layer may include a buffer layer, a first gate insulating layer, a second gate insulating layer, and an interlayer dielectric layer that are sequentially away from the substrate.
  • S12 may include:
  • Substep A Deposit a buffer layer on the substrate.
  • the material of the buffer layer can be SiNx, SiOx or other suitable materials.
  • the sub-step A may specifically include: using a chemical vapor deposition process to sequentially form a silicon nitride layer and a silicon oxide layer on the substrate.
  • Sub-step B deposit a first gate insulating layer on the buffer layer.
  • a first gate insulating layer is formed on the buffer layer by using a chemical vapor deposition process.
  • the material of the first gate insulating layer may be SiOx.
  • Sub-step C depositing a second gate insulating layer on the first gate insulating layer.
  • a chemical vapor deposition process is used to form a second gate insulating layer on the first gate insulating layer.
  • the material of the second gate insulating layer may be SiNx.
  • Sub-step D depositing an interlayer dielectric layer on the second gate insulating layer.
  • a chemical vapor deposition process is used to form an interlayer dielectric layer on the second gate insulating layer.
  • the material of the interlayer dielectric layer can be one or two of SiNx and SiOx.
  • sub-step A and before sub-step B it may further include:
  • Step (1) forming a low-temperature polysilicon layer on the buffer layer, the low-temperature polysilicon layer is located in the display area, and the first gate insulating layer covers the low-temperature polysilicon layer.
  • step (1) may specifically include: forming an amorphous silicon layer on the buffer layer using a chemical vapor deposition process in the display area, and then using an excimer laser annealing process to process the amorphous silicon layer to form a corresponding low temperature Polysilicon layer.
  • sub-step B and before sub-step C it may also include:
  • Step (2) forming a first metal layer on the first gate insulating layer, the first metal layer is located in the display area, and the second gate insulating layer covers the first metal layer.
  • the first metal layer may be a patterned gate layer, including the gate of the thin film transistor in the array substrate and the lower electrode of the storage capacitor.
  • step (2) may specifically include: in the display area, using a physical vapor deposition process to lay a first metal material layer on the first gate insulating layer, and then pattern the first metal material layer through exposure and etching processes, To obtain a patterned gate layer.
  • the material of the first metal layer may be molybdenum.
  • Step (3) forming a second metal layer on the second gate insulating layer, the second metal layer is located in the display area, and the interlayer dielectric layer covers the second metal layer.
  • the second metal layer includes the upper electrode of the storage capacitor in the array substrate, and the upper electrode and the lower electrode in the first metal layer together constitute the storage capacitor in the array substrate.
  • step (3) may specifically include: in the display area, using a physical vapor deposition process to lay a second metal material layer on the second gate insulating layer, and then pattern the second metal material layer through exposure and etching processes, To obtain the second metal layer.
  • the material of the second metal layer may be molybdenum.
  • the predetermined position of the inorganic film layer on the display area is etched to form a first opening and a second opening, wherein the second opening penetrates the first gate insulating layer, the second gate insulating layer and the layer Intermediate layer, the projection area of the first opening on the substrate does not overlap the projection area of the low-temperature polysilicon layer, the first metal layer and the second metal layer on the substrate, that is, the first opening is made on the inorganic film layer It will not damage the structure of the thin film transistor in the array substrate.
  • the material of the first organic layer may be an organic insulating material such as polyimide resin, epoxy resin or acrylic resin.
  • the first opening is formed on the inorganic film layer and the first organic layer is formed on the inorganic film layer. And the first organic layer fills the first opening, which can reduce the bending stress on the display area of the array substrate, thereby improving the bending performance of the display area.
  • the number of the first openings may be multiple to more effectively improve the bending performance of the display area. Further, the above-mentioned multiple first openings may be evenly distributed on the display area to ensure the display uniformity of the display panel.
  • the depth of the first opening may be equal to the thickness of the inorganic film layer, that is, the first opening may penetrate the buffer layer, the first gate insulating layer, the second gate insulating layer, and the interlayer dielectric layer. Therefore, the bending stress on the display area of the array substrate can be reduced more effectively.
  • the base may further include a non-display area located at the periphery of the display area
  • the array substrate may further include a second organic layer provided in the same layer as the first organic layer, and the second organic layer is located in the non-display area.
  • S44 may specifically include:
  • S441 Provide a mask.
  • the mask includes a shading area and a semi-transmitting area.
  • the mask may be a halftone mask.
  • the half-tone mask includes a light-shielding area and a semi-transmissive area, and the half-tone mask uses the partial light-transmitting characteristics of the semi-transmissive area to form a layer structure with two different film thicknesses through exposure.
  • S442 align the mask with the inorganic film group layer, form a second organic layer on the inorganic film group layer corresponding to the light-shielding area, and form a first organic layer on the inorganic film group layer corresponding to the semi-transmissive area.
  • the thickness of one organic layer is smaller than the thickness of the second inorganic layer.
  • the thickness of the second organic layer may be the same as the thickness of the organic layer in the existing array substrate, but the thickness of the first organic layer is smaller than the thickness of the organic layer in the existing array substrate, and not larger than the first opening. depth. That is, compared with the prior art, the present application reduces the thickness of the organic layer on the display area, thereby reducing the film layer gap.
  • the ratio of the thickness of the first organic layer to the thickness of the second organic layer may range from 0.3 to 0.7.
  • the thickness of the first organic layer may be 740 nm
  • the thickness of the second organic layer may be 1500 nm.
  • the above-mentioned first organic layer and the second organic layer may also be separately formed through two mask patterning processes.
  • the source/drain layer may be a patterned source/drain layer, where S45 may include: laying a source/drain material layer on the inner wall of the second opening and the inorganic film layer by a physical vapor deposition process, and then expose , The etching process patterns the source and drain material layer to obtain a patterned source and drain layer.
  • the material of the source/drain layer may be metal materials such as aluminum, copper, silver, etc., and the source/drain layer is connected to the aforementioned low-temperature polysilicon layer through the second opening.
  • the manufacturing method of the array substrate in this embodiment reduces the thickness of the organic layer to reduce the film level difference, thereby avoiding the thinning of the source and drain layer due to the excessive film level difference.
  • the problem of disconnection thereby improving the product yield.
  • FIG. 6 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • the display panel 80 includes the array substrate 81 of any of the above-mentioned embodiments.
  • the array substrate 81 includes a base, and an inorganic film layer, a first organic layer, and a source/drain layer sequentially arranged on the base, wherein the base includes a display area, and the inorganic film layer is provided with a first opening and a second opening, The first opening and the second opening are located in the display area, the first organic layer fills the first opening, and the thickness of the first organic layer is not greater than the depth of the first opening, the first organic layer does not fill the second opening, and the source drain layer covers The inner wall of the second opening.
  • the display panel in this embodiment reduces the thickness of the organic layer to reduce the film level difference, thereby avoiding the thinner source and drain layer thickness or even disconnection due to the excessive film level difference. Problems, thereby improving product yield.

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Abstract

本申请涉及一种阵列基板及其制作方法、显示面板，该阵列基板包括基底、以及在基底上依次设置的无机膜组层、第一有机层和源漏极层，基底包括显示区域，无机膜组层上设有第一开口和第二开口，第一开口和第二开口位于显示区域，第一有机层填充第一开口，且其厚度不大于第一开口的深度，源漏极层覆盖第二开口的内壁。

Description

一种阵列基板及其制作方法、显示面板 技术领域
本申请涉及显示面板技术领域，具体涉及一种阵列基板及其制作方法、显示面板。
 背景技术
有源矩阵有机发光二极体（Active-matrix organic light emitting diode，简称AMOLED）面板因其高对比度、广色域、低功耗、可折叠等特性，逐渐成为新一代显示技术。
目前，在柔性AMOLED面板的阵列基板制程工艺中，实现面板柔性的关键步骤为：在形成源漏极层之前，对显示区域上的应力较差、以及柔韧性不好的无机膜层进行刻蚀挖孔，并形成一层有机层以填充挖孔，进而提高显示区域的弯曲性能。
但是，在上述实现面板柔性的步骤中形成的有机层会导致膜层段差增大，进而导致在后续源漏极层的制程工艺中出现源漏极层厚度较薄甚至断线的问题。
 技术问题
本申请提供了一种阵列基板及其制作方法、显示面板，以避免由于膜层段差过大而出现源漏极层厚度较薄甚至断线的问题。
 技术解决方案
为了解决上述问题，本申请实施例提供了一种阵列基板，该阵列基板包括：基底，基底包括显示区域；位于基底上的无机膜组层，无机膜组层上设有第一开口和第二开口，第一开口和第二开口位于显示区域；位于无机膜组层上的第一有机层，第一有机层填充第一开口，且第一有机层的厚度不大于第一开口的深度，第一有机层不填充第二开口；位于第一有机层上的源漏极层，源漏极层覆盖第二开口的内壁。
其中，无机膜组层包括依次远离基底的缓冲层、第一栅绝缘层、第二栅绝缘层、以及层间介质层，第二开口贯穿第一栅绝缘层、第二栅绝缘层和层间介质层。
其中，阵列基板还包括低温多晶硅层、第一金属层、以及第二金属层，低温多晶硅层位于缓冲层和第一栅绝缘层之间，第一金属层位于第一栅绝缘层和第二栅绝缘层之间，第二金属层位于第二栅绝缘层和层间介质层之间；源漏极层经第二开口与低温多晶硅层连接，第一开口在基底上的投影区域与低温多晶硅层、第一金属层和第二金属层在基底上的投影区域不重叠。
其中，第一开口的深度等于无机膜组层的厚度。
其中，第一开口为多个，多个第一开口在显示区域上均匀分布。
其中，基底还包括位于显示区域周边的非显示区域，阵列基板还包括与第一有机层同层设置的第二有机层，第二有机层位于非显示区域，且第一有机层的厚度小于第二无机层的厚度。
其中，第一有机层的厚度与第二有机层的厚度之比的范围为0.3~0.7。
其中，无机膜组层上还设有第三开口，第三开口位于非显示区域，第二有机层填充第三开口。
为了解决上述问题，本申请实施例还提供了一种阵列基板的制作方法，该阵列基板的制作方法包括：提供基底，基底包括显示区域；在基底上形成无机膜组层；在无机膜组层上制作第一开口和第二开口，第一开口和第二开口位于显示区域；在无机膜组层上形成第一有机层，第一有机层填充第一开口，且第一有机层的厚度不大于第一开口的深度，第一有机层不填充第二开口；在第一有机层上形成源漏极层，源漏极层覆盖第二开口的内壁。
其中，无机膜组层包括依次远离基底的缓冲层、第一栅绝缘层、第二栅绝缘层、以及层间介质层，在基底上形成无机膜组层的步骤，具体包括：在基底上沉积缓冲层；在缓冲层上沉积第一栅绝缘层；在第一栅绝缘层上沉积第二栅绝缘层；在第二栅绝缘层上沉积层间介质层。
其中，基底还包括位于显示区域周边的非显示区域，阵列基板还包括与第一有机层同层设置的第二有机层，第二有机层位于非显示区域，在无机膜组层上形成第一有机层的步骤具体包括：提供掩膜版，掩膜版包括遮光区域和半透光区域；将掩膜版与无机膜组层对准，在遮光区域对应的无机膜组层上形成第二有机层，并在半透光区域对应的无机膜组层上形成第一有机层，第一有机层的厚度小于第二无机层的厚度。
为了解决上述问题，本申请实施例还提供了一种显示面板，该显示面板包括阵列基板，阵列基板包括：基底，基底包括显示区域；位于基底上的无机膜组层，无机膜组层上设有第一开口和第二开口，第一开口和第二开口位于显示区域；位于无机膜组层上的第一有机层，第一有机层填充第一开口，且第一有机层的厚度不大于第一开口的深度，第一有机层不填充第二开口；位于第一有机层上的源漏极层，源漏极层覆盖第二开口的内壁。
其中，无机膜组层包括依次远离基底的缓冲层、第一栅绝缘层、第二栅绝缘层、以及层间介质层，第二开口贯穿第一栅绝缘层、第二栅绝缘层和层间介质层。
其中，阵列基板还包括低温多晶硅层、第一金属层、以及第二金属层，低温多晶硅层位于缓冲层和第一栅绝缘层之间，第一金属层位于第一栅绝缘层和第二栅绝缘层之间，第二金属层位于第二栅绝缘层和层间介质层之间；源漏极层经第二开口与低温多晶硅层连接，第一开口在基底上的投影区域与低温多晶硅层、第一金属层和第二金属层在基底上的投影区域不重叠。
其中，第一开口的深度等于无机膜组层的厚度。
其中，第一开口为多个，多个第一开口在显示区域上均匀分布。
其中，基底还包括位于显示区域周边的非显示区域，阵列基板还包括与第一有机层同层设置的第二有机层，第二有机层位于非显示区域，且第一有机层的厚度小于第二无机层的厚度。
其中，第一有机层的厚度与第二有机层的厚度之比的范围为0.3~0.7。
其中，无机膜组层上还设有第三开口，第三开口位于非显示区域，第二有机层填充第三开口。
 有益效果
本申请的有益效果是：区别于现有技术，本申请提供的阵列基板包括基底、以及在基底上依次设置的无机膜组层、第一有机层和源漏极层，其中，基底包括显示区域，无机膜组层上设有第一开口和第二开口，第一开口和第二开口位于显示区域，第一有机层填充第一开口，且第一有机层的厚度不大于第一开口的深度，第一有机层不填充第二开口，源漏极层覆盖第二开口的内壁，如此，通过减小第一有机层的厚度，以减小第二开口处的膜层段差，进而避免由于膜层段差过大而出现源漏极层厚度较薄甚至断线的问题，从而提高产品良率。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的阵列基板的结构示意图；
图2是本申请实施例提供的阵列基板的另一结构示意图；
图3是本申请实施例提供的阵列基板的另一结构示意图；
图4是本申请实施例提供的阵列基板的制作方法的流程示意图；
图5是图4中S44的结构示意图；
图6是本申请实施例提供的显示面板的结构示意图。
 本发明的实施方式
下面结合附图和实施例，对本申请作进一步地详细描述。特别指出的是，以下实施例仅用于说明本申请，但不对本申请的范围进行限定。同样的，以下实施例仅为本申请的部分实施例而非全部实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其它实施例，都属于本申请保护的范围。
目前，在实现AMOLED面板柔性的制程工艺中形成的有机层，会导致膜层段差增大，进而导致在后续源漏极层的制程工艺中出现源漏极层厚度较薄甚至断线的问题。为了解决上述技术问题，本申请采用的技术方案是提供一种阵列基板，以避免由于膜层段差过大而出现源漏极层厚度较薄甚至断线的问题。
请参阅图1，图1是本申请实施例提供的阵列基板的结构示意图。如图1所示，该阵列基板10包括基底11、以及在基底11上依次设置的无机膜组层12、第一有机层13、以及源漏极层14。其中，基底11包括显示区域C1，无机膜组层12上设有第一开口121和第二开口122，第一开口121和第二开口122均位于显示区域C1，第一有机层13填充第一开口121，且第一有机层13的厚度T1不大于第一开口121的深度D1，第一有机层13不填充第二开口122，源漏极层14覆盖第二开口122的内壁。
在本实施例中，通过设置第一有机层13的厚度T1不大于第一开口121的深度D1，能够在实现阵列基板10柔性的同时，又减小第二开口122附近由于设置第一有机层13而导致的膜层段差，进而避免覆盖于第二开口122内壁上的源漏极层14出现局部厚度较薄甚至断线的问题。
其中，基底11为柔性基底，且其材质可以为聚酰亚胺、聚碳酸酯、聚对苯二甲酸乙二醇酯、聚醚砜基板等有机聚合物中的一种。第一有机层13的材质可以为聚酰亚胺系树脂、环氧系树脂或亚克力系树脂等有机绝缘材料。源漏极层14的材质可以为铝、铜、银等金属材料。
具体地，如图2所示，无机膜组层12可以包括依次远离基底11的缓冲层123、第一栅绝缘层124、第二栅绝缘层125和层间介质层126，且第二开口122贯穿第一栅绝缘层124、第二栅绝缘层125和层间介质层126。
其中，缓冲层123的材质可以为SiNx、SiOx或者其他适合的材料，第一栅绝缘层124的材质可以为SiOx，第二栅绝缘层125的材质可以为SiNx，层间介电层126的材质可以为SiNx和SiOx中的一种或两种。
请继续参阅图2，阵列基板10还可以包括依次远离基底11的低温多晶硅层15、第一金属层16和第二金属层17。其中，低温多晶硅层15、第一金属层16和第二金属层17均位于显示区域C1，且低温对晶硅层15位于缓冲层123和第一栅绝缘层124之间，第一金属层16位于第一栅绝缘层124和第二栅绝缘层125之间，第二金属层17位于第二栅绝缘层125和层间介质层126之间。
具体地，低温多晶硅层15可以为阵列基板10中薄膜晶体管的有源层，且源漏极层14经第二开口122与低温多晶硅层15连接，第一金属层16可以为图案化的栅极层，且其包括阵列基板10中薄膜晶体管的栅极、以及存储电容的下电极，第二金属层17可以包括阵列基板10中存储电容的上电极，且该上电极与上述第一金属层16中的下电极共同构成阵列基板10中的存储电容。
在本实施例中，第一开口121在基底11上的投影区域与上述低温多晶硅层15、第一金属层16和第二金属层17在基底11上的投影区域不重叠，也即，在无机膜组层12上制作第一开口121时并不会损坏阵列基板10中薄膜晶体管的结构。
具体地，由于有机材料比无机材料具有更小的应力和更佳的柔韧性，因此，通过在无机膜组层12上制作第一开口121，并在无机膜组层12上形成第一有机层13，且第一有机层13填充上述第一开口121，能够减小显示区域C1上的弯折应力，进而提高显示区域C1的弯折性能。
其中，第一开口121的数量可以为多个，以更加有效地提高显示区域C1的弯折性能。进一步地，上述多个第一开口121可以在显示区域C1上均匀分布，以保证显示面板的显示均一性。
在一些实施例中，第一开口121的深度D1可以等于无机膜组层12的厚度，也即，第一开口121可以贯穿上述缓冲层123、第一栅绝缘层124、第二栅绝缘层125和层间介质层126，如此，能够更加有效地较小阵列基板显示区域上的弯折应力。
在一个具体实施例中，如图3所示，基底11还可以包括位于显示区域C1周边的非显示区域C2，阵列基板10还可以包括与第一有机层13同层设置的第二有机层18。其中，第二有机层18位于非显示区域C1，且第一有机层13的厚度T1小于第二无机层18的厚度T2。
具体地，请继续参阅图3，无机膜组层12上还可以开设有第三开口127，其中，第三开口127位于非显示区域C2，且上述第二有机层18填充该第三开口127。如此，能够提高非显示区域C2的弯折性能。
其中，上述源漏极层14可以为图案化的源漏极层14，且该图案化的源漏极层14覆盖上述第一有机层13和第二有机层18。具体地，源漏极层14可以包括多条间隔设置的导线，且该导线横跨显示区域C1和非显示区域C2，一端与位于显示区域C1的像素单元（图中未示出）连接，另一端与位于非显示区域C2的驱动器接口（图中未示出）连接。
在一些实施例中，如图3所示，第三开口127可以具体包括在基底11上层叠连通的第一孔1271和第二孔1272，其中，第一孔1271和第二孔1272可以经过两次刻蚀工艺形成，以减小单次刻蚀工艺中需要涂布的光刻胶的厚度，进而减小单次刻蚀工艺中曝光机的能量消耗，有利于降低设备成本。
在现有的阵列基板中，位于源漏极层14与无机膜组层13之间的有机层具有均一厚度，例如，位于显示区域C1上的有机层的厚度与位于非显示区域C2上的有机层的厚度相同，可以均为1500纳米。在现有的阵列基板中，由于有机层的厚度较大，导致膜层段差较大，进而导致源漏极层14在第二开口122的内壁上，尤其是在第二开口122的椎角处，易出现厚度较薄甚至断线的问题，从而导致阵列基板无信号输出而出现显示画面不可控的现象。
在本实施例中，第二有机层18的厚度T2可以与现有阵列基板中有机层的厚度相同，但第一有机层13的厚度T1小于现有阵列基板中有机层的厚度，且不大于第一开口121的深度D1。也即，与现有技术相比，本申请减小了显示区域C1上有机层的厚度，进而减小了膜层段差。
具体地，第一有机层13的厚度T1与第二有机层18的厚度T2之比的范围可以为0.3~0.7。例如，第一有机层13的厚度T1可以为740纳米，第二有机层18的厚度T2可以为1500纳米。
在一些实施例中，在不影响非显示区域C2上信号输出的情况下，也可以适当减小第二有机层18的厚度T2。例如，可以将第二有机层18的厚度T2设置为与第一有机层13的厚度T1相同，以便于通过一次掩膜版构图工艺形成第一有机层13和第二有机层18，进而简化阵列基板的制程工艺。
需要说明的是，上述第一有机层13在整体上为厚度均一的层结构，但由于无机膜组层12在第一开口121处存在高度差，导致第一有机层13在填充第一开口121后会在第一开口121处出现一定程度的厚度不均一问题，因此，在本申请中，第一有机层13的厚度T1以远离第一开口121的第一有机层13的厚度为准。同理，上述第二有机层18的厚度T2也以远离第三开口127的第二有机层18的厚度为准。
区别于现有技术，本实施例中的阵列基板，通过减小有机层的厚度，以减小膜层段差，进而避免由于膜层段差过大而出现源漏极层厚度较薄甚至断线的问题，从而提高产品良率。
请参阅图4，图4是本申请实施例提供的阵列基板的制作方法的流程示意图，该阵列基板的制作方法具体流程可以如下：
S41：提供基底，基底包括显示区域。
其中，基底为柔性基底，且其材质可以为聚酰亚胺、聚碳酸酯、聚对苯二甲酸乙二醇酯、聚醚砜基板等有机聚合物中的一种。
S42：在基底上形成无机膜组层。
其中，无机膜组层可以包括依次远离基底的缓冲层、第一栅绝缘层、第二栅绝缘层、以及层间介质层。具体地，S12可以包括：
子步骤A：在基底上沉积缓冲层。
其中，缓冲层的材质可以为SiNx、SiOx或者其他适合的材料。例如，子步骤A可以具体包括：利用化学气相沉积工艺，在基板上依次形成氮化硅层和氧化硅层。
子步骤B：在缓冲层上沉积第一栅绝缘层。
例如，利用化学气相沉积工艺，在缓冲层上形成第一栅绝缘层。其中，第一栅绝缘层的材质可以为SiOx。
子步骤C：在第一栅绝缘层上沉积第二栅绝缘层。
例如，利用化学气相沉积工艺，在第一栅绝缘层上形成第二栅绝缘层。其中，第二栅绝缘层的材质可以为SiNx。
子步骤D：在第二栅绝缘层上沉积层间介质层。
例如，利用化学气相沉积工艺，在第二栅绝缘层上形成层间介电层。其中，层间介电层的材质可以为SiNx和SiOx中的一种或两种。
在一个具体实施例中，在子步骤A之后以及子步骤B之前，还可以包括：
步骤（1）：在缓冲层上形成低温多晶硅层，低温多晶硅层位于显示区域，且第一栅绝缘层覆盖低温多晶硅层。
例如，步骤（1）可以具体包括：在显示区域，利用化学气相沉积工艺在缓冲层上形成非晶硅层，然后采用准分子镭射退火工艺对该非晶硅层进行处理，以形成对应的低温多晶硅层。
在子步骤B之后以及子步骤C之前，还可以包括：
步骤（2）：在第一栅绝缘层上形成第一金属层，第一金属层位于显示区域，且第二栅绝缘层覆盖第一金属层。
其中，第一金属层可以为图案化的栅极层，包括阵列基板中薄膜晶体管的栅极、以及存储电容的下电极。具体地，步骤（2）可以具体包括：在显示区域，利用物理气相沉积工艺在第一栅绝缘层上铺设第一金属材料层，然后通过曝光、蚀刻工艺将该第一金属材料层图形化，以得到图案化的栅极层。其中，第一金属层的材质可以为钼。
在子步骤C之后以及子步骤D之前，还可以包括：
步骤（3）：在第二栅绝缘层上形成第二金属层，第二金属层位于显示区域，且层间介质层覆盖第二金属层。
其中，第二金属层包括阵列基板中存储电容的上电极，该上电极与上述第一金属层中的下电极共同构成阵列基板中的存储电容。具体地，步骤（3）可以具体包括：在显示区域，利用物理气相沉积工艺在第二栅绝缘层上铺设第二金属材料层，然后通过曝光、蚀刻工艺将该第二金属材料层图形化，以得到第二金属层。其中，第二金属层的材质可以为钼。
S43：在无机膜组层上制作第一开口和第二开口，第一开口和第二开口位于显示区域。
例如，对位于显示区域上的无机膜组层的预设位置进行刻蚀，以形成第一开口和第二开口，其中，第二开口贯穿上述第一栅绝缘层、第二栅绝缘层和层间介质层，第一开口在基底上的投影区域与上述低温多晶硅层、第一金属层和第二金属层在基底上的投影区域不重叠，也即，在无机膜组层上制作第一开口时并不会损坏阵列基板中薄膜晶体管的结构。
S44：在无机膜组层上形成第一有机层，第一有机层填充第一开口，且第一有机层的厚度不大于第一开口的深度，第一有机层不填充第二开口。
例如，利用化学气相沉积工艺，在无机膜组层上沉积第一有机层。其中，第一有机层的材质可以为聚酰亚胺系树脂、环氧系树脂或亚克力系树脂等有机绝缘材料。
在本实施例中，由于有机材料比无机材料具有更小的应力和更佳的柔韧性，因此，通过在无机膜组层上制作第一开口，并在无机膜组层上形成第一有机层，且第一有机层填充上述第一开口，能够减小阵列基板显示区域上的弯折应力，进而提高显示区域的弯折性能。
其中，第一开口的数量可以为多个，以更加有效地提高显示区域的弯折性能。进一步地，上述多个第一开口可以在显示区域上均匀分布，以保证显示面板的显示均一性。
在一些实施例中，第一开口的深度可以等于无机膜组层的厚度，也即，第一开口可以贯穿上述缓冲层、第一栅绝缘层、第二栅绝缘层和层间介质层，如此，能够更加有效地较小阵列基板显示区域上的弯折应力。
在一个具体实施例中，基底还可以包括位于显示区域周边的非显示区域，阵列基板还可以包括与第一有机层同层设置的第二有机层，且第二有机层位于非显示区域。其中，如图5所示，S44可以具体包括：
S441：提供掩膜版，掩膜版包括遮光区域和半透光区域。
其中，掩膜版可以为半色调掩膜版。具体地，该半色调掩膜版包括遮光区域和半透光区域，且该半色调掩膜版利用半透光区域的部分透光特性，能够通过曝光形成具有两种不同膜厚的层结构。
S442：将掩膜版与无机膜组层对准，在遮光区域对应的无机膜组层上形成第二有机层，并在半透光区域对应的无机膜组层上形成第一有机层，第一有机层的厚度小于第二无机层的厚度。
在本实施例中，第二有机层的厚度可以与现有阵列基板中有机层的厚度相同，但第一有机层的厚度小于现有阵列基板中有机层的厚度，且不大于上述第一开口的深度。也即，与现有技术相比，本申请减小了显示区域上有机层的厚度，进而减小了膜层段差。
具体地，第一有机层的厚度与第二有机层的厚度之比的范围可以为0.3~0.7。例如，第一有机层的厚度可以为740纳米，第二有机层的厚度可以为1500纳米。
在一些实施例中，上述第一有机层和第二有机层还可以通过两次掩膜版构图工艺分别形成。
S45：在第一有机层上形成源漏极层，源漏极层覆盖第二开口的内壁。
具体地，源漏极层可以为图案化的源漏极层，其中，S45可以包括：利用物理气相沉积工艺在第二开口的内壁和无机膜组层上铺设源漏极材料层，然后通过曝光、蚀刻工艺将该源漏极材料层图形化，以得到图案化的源漏极层。其中，源漏极层的材质可以为铝、铜、银等金属材料，且源漏极层经第二开口与上述低温多晶硅层连接。
区别于现有技术，本实施例中的阵列基板的制作方法，通过减小有机层的厚度，以减小膜层段差，进而避免由于膜层段差过大而出现源漏极层厚度较薄甚至断线的问题，从而提高产品良率。
请参阅图6，图6是本申请实施例提供的显示面板的结构示意图。如图6所示，该显示面板80包括上述任一实施例的阵列基板81。
阵列基板81包括基底、以及在基底上依次设置的无机膜组层、第一有机层和源漏极层，其中，基底包括显示区域，无机膜组层上设有第一开口和第二开口，第一开口和第二开口位于显示区域，第一有机层填充第一开口，且第一有机层的厚度不大于第一开口的深度，第一有机层不填充第二开口，源漏极层覆盖第二开口的内壁口。
区别于现有技术，本实施例中的显示面板，通过减小有机层的厚度，以减小膜层段差，进而避免由于膜层段差过大而出现源漏极层厚度较薄甚至断线的问题，从而提高产品良率。
以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本申请的保护范围之内。

Claims (19)

  1. 一种阵列基板，其包括：
    基底，所述基底包括显示区域；
    位于所述基底上的无机膜组层，所述无机膜组层上设有第一开口和第二开口，所述第一开口和所述第二开口位于所述显示区域；
    位于所述无机膜组层上的第一有机层，所述第一有机层填充所述第一开口，且所述第一有机层的厚度不大于所述第一开口的深度，所述第一有机层不填充所述第二开口；
    位于所述第一有机层上的源漏极层，所述源漏极层覆盖所述第二开口的内壁。
  2. 根据权利要求1所述的阵列基板，其中，所述无机膜组层包括依次远离所述基底的缓冲层、第一栅绝缘层、第二栅绝缘层、以及层间介质层，所述第二开口贯穿所述第一栅绝缘层、第二栅绝缘层和层间介质层。
  3. 根据权利要求2所述的阵列基板，其中，所述阵列基板还包括低温多晶硅层、第一金属层、以及第二金属层，所述低温多晶硅层位于所述缓冲层和所述第一栅绝缘层之间，所述第一金属层位于所述第一栅绝缘层和所述第二栅绝缘层之间，所述第二金属层位于所述第二栅绝缘层和所述层间介质层之间；
    所述源漏极层经所述第二开口与所述低温多晶硅层连接，所述第一开口在所述基底上的投影区域与所述低温多晶硅层、第一金属层和第二金属层在所述基底上的投影区域不重叠。
  4. 根据权利要求2所述的阵列基板，其中，所述第一开口的深度等于所述无机膜组层的厚度。
  5. 根据权利要求1所述的阵列基板，其中，所述第一开口为多个，所述多个第一开口在所述显示区域上均匀分布。
  6. 根据权利要求1所述的阵列基板，其中，所述基底还包括位于所述显示区域周边的非显示区域，所述阵列基板还包括与所述第一有机层同层设置的第二有机层，所述第二有机层位于所述非显示区域，且所述第一有机层的厚度小于所述第二无机层的厚度。
  7. 根据权利要求6所述的阵列基板，其中，所述第一有机层的厚度与所述第二有机层的厚度之比的范围为0.3~0.7。
  8. 根据权利要求6所述的阵列基板，其中，所述无机膜组层上还设有第三开口，所述第三开口位于所述非显示区域，所述第二有机层填充所述第三开口。
  9. 一种阵列基板的制作方法，其包括：
    提供基底，所述基底包括显示区域；
    在所述基底上形成无机膜组层；
    在所述无机膜组层上制作第一开口和第二开口，所述第一开口和所述第二开口位于所述显示区域；
    在所述无机膜组层上形成第一有机层，所述第一有机层填充所述第一开口，且所述第一有机层的厚度不大于所述第一开口的深度，所述第一有机层不填充所述第二开口；
    在所述第一有机层上形成源漏极层，所述源漏极层覆盖所述第二开口的内壁。
  10. 根据权利要求9所述的制作方法，其中，所述无机膜组层包括依次远离所述基底的缓冲层、第一栅绝缘层、第二栅绝缘层、以及层间介质层，所述在所述基底上形成无机膜组层的步骤，具体包括：
    在所述基底上沉积所述缓冲层；
    在所述缓冲层上沉积所述第一栅绝缘层；
    在所述第一栅绝缘层上沉积所述第二栅绝缘层；
    在所述第二栅绝缘层上沉积所述层间介质层。
  11. 根据权利要求9所述的制作方法，其中，所述基底还包括位于所述显示区域周边的非显示区域，所述阵列基板还包括与所述第一有机层同层设置的第二有机层，所述第二有机层位于所述非显示区域，所述在所述无机膜组层上形成第一有机层的步骤具体包括：
    提供掩膜版，所述掩膜版包括遮光区域和半透光区域；
    将所述掩膜版与所述无机膜组层对准，在所述遮光区域对应的所述无机膜组层上形成第二有机层，并在所述半透光区域对应的所述无机膜组层上形成第一有机层，所述第一有机层的厚度小于所述第二无机层的厚度。
  12. 一种显示面板，包括阵列基板，所述阵列基板包括：
    基底，所述基底包括显示区域；
    位于所述基底上的无机膜组层，所述无机膜组层上设有第一开口和第二开口，所述第一开口和所述第二开口位于所述显示区域；
    位于所述无机膜组层上的第一有机层，所述第一有机层填充所述第一开口，且所述第一有机层的厚度不大于所述第一开口的深度，所述第一有机层不填充所述第二开口；
    位于所述第一有机层上的源漏极层，所述源漏极层覆盖所述第二开口的内壁。
  13. 根据权利要求12所述的显示面板，其中，所述无机膜组层包括依次远离所述基底的缓冲层、第一栅绝缘层、第二栅绝缘层、以及层间介质层，所述第二开口贯穿所述第一栅绝缘层、第二栅绝缘层和层间介质层。
  14. 根据权利要求13所述的显示面板，其中，所述阵列基板还包括低温多晶硅层、第一金属层、以及第二金属层，所述低温多晶硅层位于所述缓冲层和所述第一栅绝缘层之间，所述第一金属层位于所述第一栅绝缘层和所述第二栅绝缘层之间，所述第二金属层位于所述第二栅绝缘层和所述层间介质层之间；
    所述源漏极层经所述第二开口与所述低温多晶硅层连接，所述第一开口在所述基底上的投影区域与所述低温多晶硅层、第一金属层和第二金属层在所述基底上的投影区域不重叠。
  15. 根据权利要求13所述的显示面板，其中，所述第一开口的深度等于所述无机膜组层的厚度。
  16. 根据权利要求12所述的显示面板，其中，所述第一开口为多个，所述多个第一开口在所述显示区域上均匀分布。
  17. 根据权利要求12所述的显示面板，其中，所述基底还包括位于所述显示区域周边的非显示区域，所述阵列基板还包括与所述第一有机层同层设置的第二有机层，所述第二有机层位于所述非显示区域，且所述第一有机层的厚度小于所述第二无机层的厚度。
  18. 根据权利要求17所述的显示面板，其中，所述第一有机层的厚度与所述第二有机层的厚度之比的范围为0.3~0.7。
  19. 根据权利要求17所述的显示面板，其中，所述无机膜组层上还设有第三开口，所述第三开口位于所述非显示区域，所述第二有机层填充所述第三开口。
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