WO2021227187A1 - 晶体管结构、 goa 电路及显示面板 - Google Patents

晶体管结构、 goa 电路及显示面板 Download PDF

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Publication number
WO2021227187A1
WO2021227187A1 PCT/CN2020/096241 CN2020096241W WO2021227187A1 WO 2021227187 A1 WO2021227187 A1 WO 2021227187A1 CN 2020096241 W CN2020096241 W CN 2020096241W WO 2021227187 A1 WO2021227187 A1 WO 2021227187A1
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Prior art keywords
drain
substrate
source
layer
transistor structure
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PCT/CN2020/096241
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English (en)
French (fr)
Inventor
奚苏萍
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深圳市华星光电半导体显示技术有限公司
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Priority to US16/981,308 priority Critical patent/US20210359090A1/en
Publication of WO2021227187A1 publication Critical patent/WO2021227187A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78636—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with supplementary region or layer for improving the flatness of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • This application relates to the field of display technology, in particular to a transistor structure, a GOA circuit and a display panel.
  • the pixel value of the current display screen is getting higher and higher, and the border of the display screen is getting narrower and narrower.
  • the area of the light area becomes smaller, which affects the aperture ratio of the pixel unit.
  • the size of the transistor will also affect the frame size of the display. If the size of the transistor is larger, the frame will become wider. Therefore, the size of the transistor will limit the aperture ratio of the pixel unit and the size of the frame when the gate drive circuit is integrated and fabricated on the array substrate.
  • the size of the transistor located in the display area is large, it will affect the aperture ratio of the pixel unit; at the same time, if the size of the transistor located in the GOA circuit is large, it will affect the frame size of the display screen. Therefore, how to reduce the size of the transistor in the display screen is an urgent problem to be solved.
  • the embodiments of the present application provide a transistor structure, a GOA circuit, and a display panel, which can effectively reduce the size of the transistor structure.
  • the present application provides a transistor structure, including: a substrate, and a source and drain layer and a passivation layer sequentially arranged on the substrate; wherein,
  • the source-drain layer includes a source electrode and a drain electrode, the source electrode is arranged around the drain electrode, and the source electrode has a ring shape; the passivation layer has a via hole, and the drain electrode is located in the The projection on the passivation layer covers the via.
  • the via hole is correspondingly located in the middle region of the drain.
  • the transistor structure further includes a gate layer, the gate layer is disposed on the substrate, and the gate layer includes a gate; the gate has a ring shape .
  • the projection of the gate on the substrate is arranged around the projection of the drain on the substrate.
  • the transistor structure is a top gate structure or a bottom gate structure.
  • the transistor structure further includes an active layer disposed between the substrate and the source drain layer, and the active layer includes a channel
  • the source and the drain are in direct contact with the channel, so that the source and the drain are electrically connected to the channel.
  • the channel is in a ring shape, and the channel is correspondingly arranged around the via.
  • the projection of the source on the substrate and the projection of the drain on the substrate are at least partially overlapped with the projection of the channel on the substrate.
  • the present application also provides a GOA circuit, which includes a transistor structure, and the transistor structure includes a substrate, a source and drain layer and a passivation layer sequentially disposed on the substrate; wherein,
  • the source-drain layer includes a source electrode and a drain electrode, the source electrode is arranged around the drain electrode, and the source electrode has a ring shape; the passivation layer has a via hole, and the drain electrode is located in the The projection on the passivation layer covers the via.
  • the via hole is correspondingly located in the middle area of the drain.
  • the transistor structure further includes a gate layer, the gate layer is disposed on the substrate, and the gate layer includes a gate; the gate has a ring shape.
  • the projection of the gate on the substrate is arranged around the projection of the drain on the substrate.
  • the transistor structure is a top gate structure or a bottom gate structure.
  • the transistor structure further includes an active layer, the active layer is disposed between the substrate and the source drain layer, and the active layer includes a channel; Both the source and the drain are in direct contact with the channel, so that both the source and the drain are electrically connected to the channel.
  • the channel is in the shape of a ring, and the channel is correspondingly arranged around the via.
  • the projection of the source electrode on the substrate and the projection of the drain electrode on the substrate both at least partially overlap with the projection of the channel on the substrate.
  • the present application also provides a display panel, which includes a transistor structure, and the transistor structure includes a substrate, and a source and drain layer and a passivation layer sequentially disposed on the substrate; wherein,
  • the source-drain layer includes a source electrode and a drain electrode, the source electrode is arranged around the drain electrode, and the source electrode has a ring shape; the passivation layer has a via hole, and the drain electrode is located in the The projection on the passivation layer covers the via.
  • the via hole is correspondingly located in the middle area of the drain.
  • the transistor structure further includes a gate layer, the gate layer is disposed on the substrate, and the gate layer includes a gate; the gate has a ring shape.
  • the transistor structure further includes an active layer, the active layer is disposed between the substrate and the source and drain layers, and the active layer includes a channel; Both the source and the drain are in direct contact with the channel, so that both the source and the drain are electrically connected to the channel.
  • the present application provides a transistor structure, a GOA circuit, and a display panel.
  • the transistor structure includes a substrate, a source and drain layer and a passivation layer sequentially disposed on the substrate; the passivation layer has a via hole; Wherein, by setting the source in a ring shape surrounding the drain, the projection of the drain on the passivation layer covers the via, so that the via can directly correspond to the drain surrounded by the source, thereby reducing the transistor structure size of.
  • FIG. 1 is a first schematic plan view of a transistor structure provided by an embodiment of the present application
  • FIG. 2 is a first structural schematic diagram of a transistor structure provided by an embodiment of the present application.
  • FIG. 3 is a second schematic diagram of the transistor structure provided by an embodiment of the present application.
  • FIG. 4 is a third structural diagram of the transistor structure provided by an embodiment of the present application.
  • FIG. 5 is a fourth schematic diagram of the transistor structure provided by an embodiment of the present application.
  • FIG. 6 is a fifth structural schematic diagram of a transistor structure provided by an embodiment of the present application.
  • FIG. 7 is a sixth structural schematic diagram of the transistor structure provided by an embodiment of the present application.
  • FIG. 8 is a second schematic plan view of the transistor structure provided by an embodiment of the present application.
  • FIG. 9 is a seventh structural diagram of the transistor structure provided by an embodiment of the present application.
  • first and second are only used for description purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as “first” and “second” may explicitly or implicitly include one or more of the features, and therefore cannot be understood as a limitation of the present application.
  • the transistor described in the embodiments of the present application may be a thin film transistor or a field effect transistor or other devices with the same characteristics, and the transistor may be a P-type transistor or an N-type transistor, wherein the P-type transistor is turned on when the gate is low. It is turned off when the gate is at a high level, and the N-type transistor is turned on when the gate is at a high level, and it is turned off when the gate is at a low level.
  • FIG. 1 is a first schematic plan view of a transistor structure provided by an embodiment of the present application
  • FIG. 2 is a first schematic view of a transistor structure provided by an embodiment of the present application.
  • the transistor structure includes a substrate 10, a source and drain layer 14 and a passivation layer 15 which are sequentially disposed on the substrate 10.
  • the source-drain layer 14 includes a source electrode 141 and a drain electrode 142.
  • the source electrode 141 is arranged around the drain electrode 142.
  • the source electrode 141 has a ring shape.
  • the passivation layer 15 has a via hole 150. The projection of the drain 142 on the passivation layer 15 covers the via 150.
  • the ring shape in the embodiments of the present application can be a regular circular ring or a square ring, or other irregular ring shapes; the drain 142 can be a regular pattern such as a circle, a square, or an ellipse, or It can be other irregular patterns; this application does not specifically limit this.
  • the substrate 10 may be a glass substrate, a quartz substrate, a resin substrate, a PI flexible substrate (Polyimide Film) or other types of substrates;
  • the material of the passivation layer 15 may be silicon oxide, silicon nitride or silicon oxide
  • the material of the source and drain layer 14 can be a metal with excellent conductivity, generally molybdenum, copper, aluminum or composite metal; this application does not limit this.
  • the source electrode 141 is arranged in a ring shape surrounding the drain electrode 142, and the projection of the drain electrode 142 on the passivation layer covers the via hole 150, so that the via hole 150 can directly correspond to the source electrode 141.
  • the surrounding drain 142 is provided, thereby reducing the size of the transistor structure.
  • the via hole 150 is correspondingly located in the middle area of the drain electrode 142.
  • the drain electrode 142 has a regular pattern, such as a regular octagon as shown in FIG. 1, the projection of the center symmetry point of the drain electrode 142 on the passivation layer 15 coincides with the center of the via hole 150;
  • the via hole 150 is arranged corresponding to the middle area of the drain electrode 142, and the middle area specifically refers to the area where the drain electrode 142 can match the size of the via hole 150; this solution While ensuring that the drain 142 can be electrically connected to the corresponding electrode line (not shown in the figure) through the via 150 to fully exert its effect, the area of the drain can be reduced as much as possible, thereby reducing the size of the transistor structure .
  • the transistor structure further includes a gate layer 11.
  • the gate layer 11 is provided on the substrate 10.
  • the gate layer 11 includes a gate 110.
  • the gate 110 has a ring shape.
  • a gate insulating layer 12 is provided on the side of the gate layer 11 away from the substrate 10.
  • the material of the gate insulating layer 12 can be an inorganic material, such as silicon oxide, silicon nitride, or a combination of silicon oxide and silicon nitride, etc., or an organic material; the material of the gate layer 11 can be a metal with excellent conductivity, generally It is molybdenum, copper, aluminum or composite metal; this application does not limit this.
  • the projection of the gate 110 on the substrate 10 is arranged around the projection of the drain 142 on the substrate 10. This solution enables the projection of the gate 110 on the passivation layer 15 to be staggered from the via 150, so as to avoid the process error or stress caused by the etching when the passivation layer 15 is etched to form the via 150. Pole 110 caused damage.
  • the projection of the gate 110 on the substrate 10 is arranged around the projection of the source 141 on the substrate 10. This solution makes the projection of the gate 110 on the substrate 10 and the projection of the source 141 on the substrate and the projection of the drain 142 on the substrate 10 do not overlap, avoiding the generation of parasitic capacitance and improving the stability of the transistor structure.
  • the gate 110 may have a circular shape, a square shape, or other patterns.
  • the projection of the gate 110 on the substrate 10 may cover at least the projection of the source 141 on the substrate 10 and the projection of the drain 142 on the substrate 10.
  • the transistor structure further includes an active layer 13.
  • the active layer 13 is provided between the substrate 10 and the source/drain layer 14.
  • the active layer 13 includes a trench 130.
  • the source 141 and the drain 142 are in direct contact with the channel 130, so that the source 141 and the drain 142 are electrically connected to the channel 130.
  • the material of the active layer 13 includes amorphous silicon, low-temperature polysilicon, and metal oxide semiconductor.
  • the metal oxide semiconductor may be indium gallium zinc oxide, indium tin zinc oxide, indium tin oxide, indium zinc oxide, or the like.
  • the channel 130 may be circular, square, or ring-shaped, and the application does not limit this under the premise that the source 141 and the drain 142 are in contact with the channel 130 respectively.
  • the source and drain layer 14 is disposed on the surface of the active layer 13 away from the substrate 10, so that the source electrode 141 and the drain electrode 142 are directly in contact with the channel 130, eliminating the need for the channel 130 in the prior art.
  • the steps of depositing an insulating layer on the channel 130 and etching the through holes on the insulating layer simplifies the manufacturing process and improves the production efficiency.
  • the transistor structure since the transistor structure is arranged in a closed loop type, the size of the transistor structure can be reduced when the channel 130 meets the same channel width and length specifications.
  • the channel 130 has a circular, square, regular octagonal or other polygonal pattern.
  • the projection of the channel 130 on the substrate 10 completely covers the projection of the source 141 on the substrate 10 and the projection of the drain 142 on the substrate 10, so that the source 141 and the drain 142 can interact with the channel 130. Full contact connection.
  • the channel 130 has a ring shape, and the channel 130 is correspondingly disposed around the via 150.
  • the projection of the channel 130 on the substrate 10 completely covers the projection of the source 141 on the substrate 10, and the projection of the channel 130 on the substrate 10 and the projection of the drain 142 on the substrate 10 partially overlap.
  • This solution enables the projection of the channel 130 on the passivation layer 15 to be staggered from the via hole 150, which avoids damage to the channel 130 due to process errors when the passivation layer 15 is etched to form the via hole 152.
  • the projection of the source electrode 141 on the substrate 10 and the projection of the drain electrode 142 on the substrate 10 are at least partially overlapped with the projection of the channel 130 on the substrate 10.
  • the channel 130 has a first side surface 131 and a second side surface 132 opposite to each other.
  • the source electrode 141 is in contact and connection with the first side surface 131
  • the drain electrode 142 is in contact and connection with the second side surface 132. This arrangement places the channel 130 on the same layer as the source electrode 141 and the drain electrode 142, which reduces the film thickness of the transistor structure.
  • the projection of the gate 110 on the substrate 10 coincides with the projection of the channel 130 on the substrate 10.
  • the second schematic plan view of the transistor structure is shown in FIG. 8. This solution further reduces the size of the transistor structure.
  • the projection of the gate 110 on the substrate 10, the projection of the source 141 on the substrate, and the drain 142 The projections on the substrate 10 are not overlapped, which avoids the generation of parasitic capacitance and improves the stability of the transistor structure.
  • the transistor structure may be a top gate structure or a bottom gate structure.
  • the transistor structure is a bottom gate structure.
  • the gate layer 11 is disposed on the substrate 10, and the gate layer 11 includes a gate 110; the gate insulating layer 12 is stacked on the side of the gate layer 11 away from the substrate 10; the active layer 13 is disposed on the gate insulating layer 12 A side away from the substrate 10; the active layer 13 includes a trench 130.
  • the source-drain layer 14 is disposed on the side of the active layer 13 away from the substrate 10; the source-drain layer 14 includes a source 141 and a drain 142; the passivation layer 15 is disposed on the source 141, the drain 142 and the channel 130 , And a via 150 is provided on the passivation layer 15, and the via 150 penetrates the passivation layer 15 to expose a side surface of the drain electrode 142 away from the substrate 20.
  • the source electrode 141 is arranged around the drain electrode 142, and the source electrode 141 has a ring shape.
  • the projection of the drain 142 on the passivation layer 15 covers the via 150.
  • the transistor structure is a top gate structure.
  • the active layer 21 is disposed on the substrate 20; the active layer 21 includes a channel 210.
  • the source-drain layer 22 is arranged on the side of the active layer 21 away from the substrate 20; the source-drain layer includes a source electrode 221 and a drain electrode 222; the gate insulating layer 23 is arranged on the active layer 21, the source-drain layer 22 and the substrate 10
  • the gate layer 24 is disposed on the side of the gate insulating layer 23 away from the substrate 20; the gate layer 24 includes a gate 240; the passivation layer 25 is disposed on the gate layer 24 and the gate insulating layer 23, and the passivation layer
  • a via hole 250 is provided on the passivation layer 25 and extends to the gate insulating layer 23 to expose the side surface of the drain electrode 222 away from the substrate 20; the via hole 250 corresponds to the drain electrode 222.
  • the source electrode 221 is arranged around the drain electrode 222, and the source electrode 221 has a ring shape.
  • the projection of the drain 222 on the passivation layer 25 covers the via 250.
  • the present application provides a GOA circuit, which includes the transistor structure described in any one of the above embodiments.
  • the embodiment of the present application provides a GOA circuit.
  • the GOA circuit is provided with a closed-loop transistor structure, the source is arranged in a ring shape surrounding the drain, and the projection of the drain on the passivation layer covers the via hole and will be in contact with the drain
  • the via hole directly corresponds to the drain surrounded by the source, thereby reducing the size of the transistor structure and effectively saving the wiring space of the GOA circuit.
  • the present application also provides a display panel including the transistor structure described in any one of the above embodiments.
  • the embodiment of the present application provides a display panel.
  • a closed-loop transistor structure is provided, and the source is arranged in a ring shape surrounding the drain, and the projection of the drain on the passivation layer covers the via hole, so that the The via hole in contact with the drain is provided directly corresponding to the drain surrounded by the source, which can effectively reduce the size of the transistor structure, thereby increasing the pixel aperture ratio.
  • the GOA circuit design is adopted in the display panel, the frame size of the display panel can be effectively reduced.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
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  • Thin Film Transistor (AREA)
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Abstract

一种晶体管结构、GOA电路以及显示面板，晶体管结构包括：基板（10,20），以及依次设置在基板（10,20）上的源漏极层（14,22）、钝化层（15,25）；其中，源漏极层（14,22）包括源极（141,221）以及漏极（142,222），源极（141,221）围绕漏极（142,222）设置，且源极（141,221）呈环形状；钝化层（15,25）具有一过孔（150,250），漏极（142,222）在钝化层（15,25）上的投影覆盖过孔（150,250）。

Description

晶体管结构、GOA电路及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种晶体管结构、GOA电路及显示面板。
 背景技术
随着显示技术的发展，目前显示屏的像素值越来越高，且显示屏的边框越来越窄，其中，在显示屏中，晶体管的尺寸较大会造成遮光区域面积变大，进而相应透光区域面积变少，从而影响到像素单元的开口率。而当采用阵列基板栅极驱动技术(Gate Driveron Array，简称GOA)时，晶体管的尺寸也会影响到显示屏的边框大小，如果晶体管的尺寸较大，边框会随之变宽。因此，晶体管的大小会限制像素单元的开口率以及将栅极驱动电路集成制作在阵列基板上时边框的大小。
 技术问题
在显示屏中，如果位于显示区域的晶体管的尺寸较大，会影响到像素单元的开口率；同时，若位于GOA电路中的晶体管的尺寸较大，会影响到显示屏的边框大小。因此，如何减小显示屏中的晶体管的大小是亟需解决的问题。
 技术解决方案
本申请实施例提供一种晶体管结构、GOA电路及显示面板，能够有效减小晶体管结构的尺寸。
本申请提供了一种晶体管结构，包括：基板，以及依次设置在所述基板上的源漏极层和钝化层；其中，
所述源漏极层包括源极以及漏极，所述源极围绕所述漏极设置，且所述源极呈环形状；所述钝化层具有一过孔，所述漏极在所述钝化层上的投影覆盖所述过孔。
在本申请所提供的晶体管结构中，所述过孔对应位于所述漏极的中间区域。
在本申请所提供的晶体管结构中，所述晶体管结构还包括一栅极层，所述栅极层设置在所述基板上，所述栅极层包括一栅极；所述栅极呈环形状。
在本申请所提供的晶体管结构中，所述栅极在所述基板上的投影环绕所述漏极在所述基板上的投影设置。
在本申请所提供的晶体管结构中，所述晶体管结构为顶栅结构或者底栅结构。
在本申请所提供的晶体管结构中，所述晶体管结构还包括一有源层，所述有源层设置在所述基板与所述源漏极层之间，所述有源层包括一沟道；所述源极、所述漏极均与所述沟道直接接触，以使得所述源极、所述漏极均与所述沟道电性连接。
在本申请所提供的晶体管结构中，所述沟道呈环形状，且所述沟道对应围绕所述过孔设置。
在本申请所提供的晶体管结构中，所述源极在所述基板上的投影、所述漏极在所述基板上的投影均与所述沟道在所述基板上的投影至少部分重合。
相应的，本申请还提供一种GOA电路，其包括晶体管结构，所述晶体管结构包括：基板，以及依次设置在所述基板上的源漏极层和钝化层；其中，
所述源漏极层包括源极以及漏极，所述源极围绕所述漏极设置，且所述源极呈环形状；所述钝化层具有一过孔，所述漏极在所述钝化层上的投影覆盖所述过孔。
在本申请提供的GOA电路中，所述过孔对应位于所述漏极的中间区域。
在本申请提供的GOA电路中，所述晶体管结构还包括一栅极层，所述栅极层设置在所述基板上，所述栅极层包括一栅极；所述栅极呈环形状。
在本申请提供的GOA电路中，所述栅极在所述基板上的投影环绕所述漏极在所述基板上的投影设置。
在本申请提供的GOA电路中，所述晶体管结构为顶栅结构或者底栅结构。
在本申请提供的GOA电路中，所述晶体管结构还包括一有源层，所述有源层设置在所述基板与所述源漏极层之间，所述有源层包括一沟道；所述源极、所述漏极均与所述沟道直接接触，以使得所述源极、所述漏极均与所述沟道电性连接。
在本申请提供的GOA电路中，所述沟道呈环形状，且所述沟道对应围绕所述过孔设置。
在本申请提供的GOA电路中，所述源极在所述基板上的投影、所述漏极在所述基板上的投影均与所述沟道在所述基板上的投影至少部分重合。
相应的，本申请还提供一种显示面板，其包括晶体管结构，所述晶体管结构包括：基板，以及依次设置在所述基板上的源漏极层和钝化层；其中，
所述源漏极层包括源极以及漏极，所述源极围绕所述漏极设置，且所述源极呈环形状；所述钝化层具有一过孔，所述漏极在所述钝化层上的投影覆盖所述过孔。
在本申请提供的显示面板中，所述过孔对应位于所述漏极的中间区域。
在本申请提供的显示面板中，所述晶体管结构还包括一栅极层，所述栅极层设置在所述基板上，所述栅极层包括一栅极；所述栅极呈环形状。
在本申请提供的显示面板中，所述晶体管结构还包括一有源层，所述有源层设置在所述基板与所述源漏极层之间，所述有源层包括一沟道；所述源极、所述漏极均与所述沟道直接接触，以使得所述源极、所述漏极均与所述沟道电性连接。
 有益效果
本申请提供一种晶体管结构、GOA电路以及显示面板，所述晶体管结构包括：基板，以及依次设置在所述基板上的源漏极层、钝化层；所述钝化层具有一过孔；其中，通过将源极设置成环绕漏极的环形状，漏极在钝化层上的投影覆盖过孔，从而可将过孔直接对应被源极环绕的漏极设置，从而减小了晶体管结构的尺寸。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的晶体管结构的第一平面示意图；
图2是本申请实施例提供的晶体管结构的第一结构示意图；
图3是本申请实施例提供的晶体管结构的第二结构示意图；
图4是本申请实施例提供的晶体管结构的第三结构示意图；
图5是本申请实施例提供的晶体管结构的第四结构示意图；
图6是本申请实施例提供的晶体管结构的第五结构示意图；
图7是本申请实施例提供的晶体管结构的第六结构示意图；
图8是本申请实施例提供的晶体管结构的第二平面示意图；
图9是本申请实施例提供的晶体管结构的第七结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“第一”和“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”和“第二”等的特征可以明示或者隐含地包括一个或者更多个所述特征，因此不能理解为对本申请的限制。
本申请实施例中描述的晶体管可以为薄膜晶体管或场效应管或其他特性相同的器件，且该晶体管可以是P型晶体管或N型晶体管，其中，P型晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型晶体管为在栅极为高电平时导通，在栅极为低电平时截止。
请参阅图1和图2，图1是本申请实施例提供的晶体管结构的第一平面示意图，图2是本申请实施例提供的晶体管结构的第一结构示意图。如图1和图2所示，该晶体管结构包括：基板10，以及依次设置在基板10上的源漏极层14、钝化层15。其中，源漏极层14包括源极141以及漏极142。源极141围绕漏极142设置。且源极141呈环形状。钝化层15具有一过孔150。漏极142在钝化层15上的投影覆盖过孔150。
需要说明的是，本申请实施例中的环形状可以是规则的圆环或方形环，也可以是不规则的其它环形状；漏极142可以是圆形、方形或椭圆形等规则图案，也可以是不规则的其它图案；本申请对此均不作具体限定。
其中，基板10可以为玻璃基板、石英基板、树脂基板、PI柔性基板（聚酰亚胺薄膜，Polyimide Film）或其他类型基板；钝化层15的材料可以是氧化硅、氮化硅或氧化硅和氮化硅的叠层结构等；源漏层14的材料可以是导电性优的金属，一般为钼、铜、铝或复合金属；本申请对此均不作限定。
本申请实施例提供的晶体管结构，通过源极141设置成环绕漏极142的环形状，漏极142在钝化层上的投影覆盖过孔150，从而可将过孔150直接对应被源极141环绕的漏极142设置，从而减小了晶体管结构的尺寸。
进一步的，过孔150对应位于漏极142的中间区域。在一些实施例中，当漏极142为规则的图案，如图1所示的正八边形时，漏极142的中心对称点在钝化层15上的投影与过孔150的圆心重合；在另一些实施例中，当漏极142为不规则图形时，过孔150对应漏极142的中间区域设置，该中间区域特指漏极142能够与过孔150的尺寸相匹配的区域；该方案在保证漏极142能够通过过孔150与相应电极线（图中未标识）电性连接，以充分发挥其作用的同时，能够尽可能的减小漏极的面积，进而减小晶体管结构的尺寸。
在本申请实施例中，请继续参阅图2，晶体管结构还包括一栅极层11。栅极层11设置在基板10上。栅极层11包括一栅极110。栅极110呈环形状。
其中，栅极层11远离基板10的一侧设置有栅绝缘层12。栅绝缘层12的材料可以是无机材料，例如氧化硅、氮化硅或氧化硅和氮化硅的结合等，也可以为有机材料；栅极层11的材料可以是导电性优的金属，一般为钼、铜、铝或复合金属；本申请对此均不作限定。
在一些实施例中，栅极110在基板10上的投影环绕漏极142在基板10上的投影设置。该方案使得栅极110在钝化层15上的投影与过孔150错开设置，避免在对钝化层15进行刻蚀以形成过孔150时，因存在工艺误差或刻蚀产生的应力对栅极110造成破坏。
进一步的，请参阅图3，栅极110在基板10上的投影环绕源极141在基板10上的投影设置。该方案使得栅极110在基板10上的投影与源极141在基板上的投影以及漏极142在基板10上的投影均不重合，避免了寄生电容的产生，提高了晶体管结构的稳定性。
需要说明的是，在一些实施例中，请参阅图4，栅极110可以呈圆形、方形或其它图案。具体的，栅极110在基板10上的投影可以至少覆盖源极141在基板10上的投影以及漏极142在基板10上的投影。
请继续参阅图2，晶体管结构还包括一有源层13。有源层13设置在基板10与源漏极层14之间。有源层13包括一沟道130。其中，源极141、漏极142均与沟道130直接接触，以使得源极141、漏极142均与沟道130电性连接。
其中，有源层13的材料包括非晶硅、低温多晶硅以及金属氧化物半导体。需要说明的是，该金属氧化物半导体可以是氧化铟镓锌、氧化铟锡锌、氧化铟锡或氧化铟锌等。沟道130可以是圆形、方形或者环形，在保证源极141以及漏极142分别与沟道130接触连接的前提下，本申请对此不做限定。
本申请实施例通过将源漏极层14设置于有源层13远离基板10的一侧表面，使得源极141以及漏极142直接与沟道130接触连接，省去了现有技术中在沟道130上沉积绝缘层并在绝缘层刻蚀通孔的步骤，简化了制成工艺，提高了生产效率。同时，由于晶体管结构设置成闭环型，在沟道130满足相同的沟道宽度和长度规格下，可减小晶体管结构的尺寸。
具体的，在一些实施例中，沟道130呈圆形、方形、正八边形或其他多边形图案。请继续参阅图2，沟道130在基板10上的投影完全覆盖源极141在基板10上的投影以及漏极142在基板10上的投影，使得源极141以及漏极142能够与沟道130充分接触连接。
在一些实施例中，沟道130呈环形状，且沟道130对应围绕过孔150设置。请参阅图5，沟道130在基板10上的投影完全覆盖源极141在基板10上的投影，沟道130在基板10上的投影与漏极142在基板10上的投影部分重合。该方案使得沟道130在钝化层15上的投影与过孔150错开设置，避免在对钝化层15进行刻蚀以形成过孔152时，因存在工艺误差对沟道130造成破坏。
进一步的，源极141在基板10上的投影、漏极142在基板10上的投影均与沟道130在基板10上的投影至少部分重合。
具体的，请参阅图6，沟道130具有相对的第一侧面131与第二侧面132。源极141与第一侧面131接触连接，漏极142与第二侧面132接触连接。该设置将沟道130与源极141以及漏极142同层设置，降低了晶体管结构的膜层厚度。
进一步的，请参阅图7，栅极110在基板10上的投影与沟道130在基板10上的投影重合。此时，晶体管结构的第二平面示意图如图8所示，该方案进一步减小了晶体管结构的尺寸，同时栅极110在基板10上的投影与源极141在基板上的投影以及漏极142在基板10上的投影均不重合，避免了寄生电容的产生，提高了晶体管结构的稳定性。
在本申请实施例中，晶体管结构可以是顶栅结构或者底栅结构。在一些实施例中，请继续参阅图2，晶体管结构为底栅结构。其中，栅极层11设置于基板10上，栅极层11包括一栅极110；栅绝缘层12层叠设置于栅极层11远离基板10的一侧；有源层13设置于栅绝缘层12远离基板10的一侧；有源层13包括一沟道130。源漏极层14设置于有源层13远离基板10的一侧；源漏极层14包括源极141和漏极142；钝化层15设置于源极141、漏极142以及沟道130上，且钝化层15上设有一过孔150，该过孔150贯穿钝化层15，以暴露出漏极142远离基板20的一侧表面。
其中，源极141围绕漏极142设置，且源极141呈环形状。漏极142在钝化层15上的投影覆盖过孔150。
在一些实施例中，请参阅图9，晶体管结构为顶栅结构。其中，有源层21设置于基板20上；有源层21包括一沟道210。源漏极层22设置于有源层21远离基板20的一侧；源漏极层包括源极221和漏极222；栅绝缘层23设置于有源层21、源漏极层22以及基板10上；栅极层24设置于栅绝缘层23远离基板20的一侧；栅极层24包括一栅极240；钝化层25设置于栅极层24以及栅绝缘层23上，且钝化层25上设有一过孔250，该过孔250贯穿钝化层25，并延伸至栅绝缘层23以暴露出漏极222远离基板20的一侧表面；过孔250与漏极222对应。
其中，源极221围绕漏极222设置，且源极221呈环形状。漏极222在钝化层25上的投影覆盖过孔250。
需要说明的是，上述对顶栅结构或者底栅结构的晶体管结构的具体结构说明仅为更好的理解本申请的技术方案，但不能理解为对本申请的限制。
相应的，本申请提供一种GOA电路，该GOA电路包括以上任意一实施例所述的晶体管结构。
本申请实施例提供一种GOA电路，该GOA电路通过设置闭环型晶体管结构，将源极设置成环绕漏极的环形状，漏极在钝化层上的投影覆盖过孔，将与漏极接触的过孔直接对应被源极环绕的漏极设置，从而减小了晶体管结构的尺寸，有效地节省GOA电路的布线空间。
相应的，本申请还提供一种显示面板，该显示面板包括以上任意一项实施例所述的晶体管结构。
本申请实施例提供一种显示面板，在显示面板中，通过设置闭环型晶体管结构，将源极设置成环绕漏极的环形状，漏极在钝化层上的投影覆盖过孔，从而可将与漏极接触的过孔直接对应被源极环绕的漏极设置，能够有效减小晶体管结构的尺寸，从而提高像素开口率。若显示面板中采用GOA电路设计，则能够有效降低显示面板的边框大小。
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种晶体管结构，其包括：基板，以及依次设置在所述基板上的源漏极层和钝化层；其中，
    所述源漏极层包括源极以及漏极，所述源极围绕所述漏极设置，且所述源极呈环形状；所述钝化层具有一过孔，所述漏极在所述钝化层上的投影覆盖所述过孔。
  2. 根据权利要求1所述的晶体管结构，其中，所述过孔对应位于所述漏极的中间区域。
  3. 根据权利要求1所述的晶体管结构，其中，所述晶体管结构还包括一栅极层，所述栅极层设置在所述基板上，所述栅极层包括一栅极；所述栅极呈环形状。
  4. 根据权利要求3所述的晶体管结构，其中，所述栅极在所述基板上的投影环绕所述漏极在所述基板上的投影设置。
  5. 根据权利要求4所述的晶体管结构，其中，所述晶体管结构为顶栅结构或者底栅结构。
  6. 根据权利要求1所述的晶体管结构，其中，所述晶体管结构还包括一有源层，所述有源层设置在所述基板与所述源漏极层之间，所述有源层包括一沟道；所述源极、所述漏极均与所述沟道直接接触，以使得所述源极、所述漏极均与所述沟道电性连接。
  7. 根据权利要求6所述的晶体管结构，其中，所述沟道呈环形状，且所述沟道对应围绕所述过孔设置。
  8. 根据权利要求6所述的晶体管结构，其中，所述源极在所述基板上的投影、所述漏极在所述基板上的投影均与所述沟道在所述基板上的投影至少部分重合。
  9. 一种GOA电路，其包括晶体管结构，所述晶体管结构包括：基板，以及依次设置在所述基板上的源漏极层和钝化层；其中，
    所述源漏极层包括源极以及漏极，所述源极围绕所述漏极设置，且所述源极呈环形状；所述钝化层具有一过孔，所述漏极在所述钝化层上的投影覆盖所述过孔。
  10. 根据权利要求9所述的GOA电路，其中，所述过孔对应位于所述漏极的中间区域。
  11. 根据权利要求9所述的GOA电路，其中，所述晶体管结构还包括一栅极层，所述栅极层设置在所述基板上，所述栅极层包括一栅极；所述栅极呈环形状。
  12. 根据权利要求11所述的GOA电路，其中，所述栅极在所述基板上的投影环绕所述漏极在所述基板上的投影设置。
  13. 根据权利要求12所述的GOA电路，其中，所述晶体管结构为顶栅结构或者底栅结构。
  14. 根据权利要求9所述的GOA电路，其中，所述晶体管结构还包括一有源层，所述有源层设置在所述基板与所述源漏极层之间，所述有源层包括一沟道；所述源极、所述漏极均与所述沟道直接接触，以使得所述源极、所述漏极均与所述沟道电性连接。
  15. 根据权利要求14所述的GOA电路，其中，所述沟道呈环形状，且所述沟道对应围绕所述过孔设置。
  16. 根据权利要求14所述的GOA电路，其中，所述源极在所述基板上的投影、所述漏极在所述基板上的投影均与所述沟道在所述基板上的投影至少部分重合。
  17. 一种显示面板，其包括晶体管结构，所述晶体管结构包括：基板，以及依次设置在所述基板上的源漏极层和钝化层；其中，
    所述源漏极层包括源极以及漏极，所述源极围绕所述漏极设置，且所述源极呈环形状；所述钝化层具有一过孔，所述漏极在所述钝化层上的投影覆盖所述过孔。
  18. 根据权利要求17所述的显示面板，其中，所述过孔对应位于所述漏极的中间区域。
  19. 根据权利要求17所述的显示面板，其中，所述晶体管结构还包括一栅极层，所述栅极层设置在所述基板上，所述栅极层包括一栅极；所述栅极呈环形状。
  20. 根据权利要求17所述的显示面板，其中，所述晶体管结构还包括一有源层，所述有源层设置在所述基板与所述源漏极层之间，所述有源层包括一沟道；所述源极、所述漏极均与所述沟道直接接触，以使得所述源极、所述漏极均与所述沟道电性连接。
PCT/CN2020/096241 2020-05-13 2020-06-16 晶体管结构、 goa 电路及显示面板 WO2021227187A1 (zh)

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