WO2023004668A1 - 阵列基板及其制备方法、显示面板 - Google Patents

阵列基板及其制备方法、显示面板 Download PDF

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Publication number
WO2023004668A1
WO2023004668A1 PCT/CN2021/109159 CN2021109159W WO2023004668A1 WO 2023004668 A1 WO2023004668 A1 WO 2023004668A1 CN 2021109159 W CN2021109159 W CN 2021109159W WO 2023004668 A1 WO2023004668 A1 WO 2023004668A1
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Prior art keywords
shielding portion
layer
drain
source
light
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PCT/CN2021/109159
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English (en)
French (fr)
Inventor
罗传宝
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深圳市华星光电半导体显示技术有限公司
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Priority to US17/600,250 priority Critical patent/US20230024248A1/en
Publication of WO2023004668A1 publication Critical patent/WO2023004668A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield

Definitions

  • the invention relates to the field of display technology, in particular to an array substrate, a preparation method thereof, and a display panel.
  • Mini/Micro LED display technology has entered a stage of accelerated development in the past two years, and can be used in small and medium-sized display applications. Compared with OLED screens, Mini/Micro LED displays can show better performance in terms of cost, contrast, high brightness, and thin and light appearance.
  • TFT Thin Film Transistor (thin film transistor) backplane technology
  • TFT Thin Film Transistor (thin film transistor) backplane technology
  • the array substrate in the prior art usually sets the light shielding part 1 under the active layer 2 to block the light from the outside to the active layer 2 , and between the active layer 2 and the gate 3 Separated by the gate insulating layer 4, and usually by chemical vapor deposition (Chemical Vapor Deposition, CVD) process deposits an interlayer insulating layer 5 on the active layer 2 and the gate 3, prepares a source/drain 6 on the interlayer insulating layer 5, and the source/drain The pole 6 is electrically connected to the active layer 2 through the via hole on the interlayer insulating layer 5 .
  • CVD chemical vapor deposition
  • the preparation process of the existing array substrate needs to use multiple masks, such as the patterning process of the light-shielding part, the patterning process of the active layer, the patterning process of the gate insulating layer, the patterning process of the gate, and the patterning process of the interlayer insulating layer.
  • multiple masks such as the patterning process of the light-shielding part, the patterning process of the active layer, the patterning process of the gate insulating layer, the patterning process of the gate, and the patterning process of the interlayer insulating layer.
  • At least six photomask processes, such as source/drain patterning process make the array substrate process complex and costly.
  • the invention provides an array substrate, a preparation method thereof, and a display panel, which can solve the technical problem of high cost due to the complicated manufacturing process of the TFT backplane in the prior art.
  • An embodiment of the present invention provides an array substrate, including:
  • a light-shielding portion disposed on the substrate
  • an active layer correspondingly disposed on the source, the drain, and the light-shielding portion, the active layer includes a channel region;
  • the light-shielding portion corresponds to the channel region, the source, the drain, and the light-shielding portion are arranged in the same layer, and the source and the drain are made of the same material as the light-shielding portion.
  • the active layer further includes non-channel regions located on both sides of the channel region, and the source and the drain are respectively connected to the non-channel regions. touch.
  • the array substrate further includes a top gate, the top gate is located on the active layer, and the top gate corresponds to the channel region of the active layer set up.
  • the light shielding portion is spaced apart from the source and the drain, and the light shielding portion is disposed opposite to the top gate; or, the light shielding portion connected to at least one of the source and the drain.
  • the light shielding portion includes a first portion connected to the source, and a second portion connected to the drain, the first portion and the The second part is spaced apart.
  • the orthographic projection of the light shielding portion on the substrate covers the orthographic projection of the part corresponding to the channel region of the active layer on the substrate.
  • the top gate is electrically connected to the light shielding portion.
  • the array substrate further includes:
  • a buffer layer disposed between the light shielding portion and the active layer
  • a gate insulating layer corresponding to the channel region, disposed between the active layer and the top gate;
  • a first passivation layer disposed on the top gate
  • the top gate is electrically connected to the light-shielding portion through a conductive layer spaced apart from the active layer, and the conductive layer includes a first lead and a second lead; the first lead is the same as the light-shielding portion
  • the layers are arranged and electrically connected; the second lead is located on the first passivation layer, and one end of the second lead is electrically connected to the top gate through the first via hole penetrating the first passivation layer , and the other end is electrically connected to the first lead through a second via hole penetrating through the first passivation layer and the buffer layer.
  • the top gate and/or the light shielding portion, the source, the drain, and the active layer form a thin film transistor
  • the array substrate includes a driver A thin film transistor and a switching thin film transistor, wherein both the driving thin film transistor and the switching thin film transistor have a top gate structure; or, both the driving thin film transistor and the switching thin film transistor have a bottom gate structure; or, the driving thin film transistor has a bottom gate structure; Both the TFT and the switching TFT have a double-gate structure; or, the driving TFT has a double-gate structure, and the switching TFT has a top-gate or bottom-gate structure.
  • An embodiment of the present invention also provides a display panel, which includes an array substrate and LED diodes, and the array substrate includes:
  • a light-shielding portion disposed on the substrate
  • an active layer correspondingly disposed on the source, the drain, and the light-shielding portion, the active layer includes a channel region;
  • the light-shielding portion corresponds to the channel region, the source, the drain, and the light-shielding portion are arranged in the same layer, and the source and the drain are made of the same material as the light-shielding portion.
  • the active layer further includes non-channel regions located on both sides of the channel region, and the source and the drain are respectively connected to the non-channel regions. touch.
  • the array substrate further includes a top gate, the top gate is located on the active layer, and the top gate corresponds to the channel region of the active layer set up.
  • the light shielding portion is spaced apart from the source and the drain, and the light shielding portion is disposed opposite to the top gate; or, the light shielding portion connected to at least one of the source and the drain.
  • the light shielding portion includes a first portion connected to the source, and a second portion connected to the drain, the first portion and the The second part is spaced apart.
  • the orthographic projection of the light shielding portion on the substrate covers the orthographic projection of the part corresponding to the channel region of the active layer on the substrate.
  • the top gate and the light shielding portion are electrically connected through via holes.
  • the array substrate further includes:
  • a buffer layer disposed between the light shielding portion and the active layer
  • a gate insulating layer corresponding to the channel region, disposed between the active layer and the top gate;
  • a first passivation layer disposed on the top gate
  • the top gate is electrically connected to the light-shielding portion through a conductive layer spaced apart from the active layer, and the conductive layer includes a first lead and a second lead; the first lead is the same as the light-shielding portion
  • the layers are arranged and electrically connected; the second lead is located on the first passivation layer, and one end of the second lead is electrically connected to the top gate through the first via hole penetrating the first passivation layer , and the other end is electrically connected to the first lead through a second via hole penetrating through the first passivation layer and the buffer layer.
  • the top gate and/or the light shielding portion, the source, the drain, and the active layer form a thin film transistor
  • the array substrate includes a driver A thin film transistor and a switching thin film transistor, wherein both the driving thin film transistor and the switching thin film transistor have a top gate structure; or, both the driving thin film transistor and the switching thin film transistor have a bottom gate structure; or, the driving thin film transistor has a bottom gate structure; Both the TFT and the switching TFT have a double-gate structure; or, the driving TFT has a double-gate structure, and the switching TFT has a top-gate or bottom-gate structure.
  • An embodiment of the present invention also provides a method for preparing an array substrate, and the method includes the following steps:
  • Step S11 forming a first metal layer on the substrate, and patterning the first metal layer to form a light shielding portion, a source and a drain;
  • Step S12 forming a buffer layer on the first metal layer, patterning the buffer layer to form a source-drain contact hole penetrating through the buffer layer and corresponding to the source and the drain;
  • Step S13 forming an active layer on the buffer layer, and forming a channel region of the active layer and non-channel regions located on both sides of the channel region;
  • the non-channel region of the active layer is connected to the source and the drain through the source-drain contact hole, and the light shielding portion corresponds to the channel region.
  • the preparation method further includes the following steps:
  • Step S14 forming a laminated gate insulating layer and a top gate on the active layer, the gate insulating layer and the top gate corresponding to the channel region of the active layer.
  • the beneficial effects of the present invention are: the array substrate and its preparation method, and the display panel provided by the present invention, by arranging the source electrode, the drain electrode, and the light-shielding part on the same layer, and using the same material for the source electrode, the drain electrode and the light-shielding part, thereby In the preparation process of the array substrate, the source electrode, the drain electrode and the light-shielding part can be formed simultaneously in the same manufacturing process. process and cost savings.
  • FIG. 1 is a schematic structural view of an array substrate provided by the prior art
  • FIG. 2-4 are schematic structural views of an array substrate with a top-gate structure provided by Embodiment 1 of the present invention.
  • FIG. 5 is a schematic structural diagram of an array substrate with a bottom gate structure provided by Embodiment 2 of the present invention.
  • FIG. 6 is a schematic structural diagram of an array substrate with a double gate structure provided by Embodiment 3 of the present invention.
  • FIG. 7 is a cross-sectional view of the conductive layer of the array substrate provided by Embodiment 3 of the present invention along the winding direction;
  • FIG. 8 is a schematic structural diagram of a display panel provided by Embodiment 5 of the present invention.
  • 9 to 17 are schematic diagrams of the manufacturing process of the display panel provided by Embodiment 5 of the present invention.
  • orientation words such as “up” and “down” usually refer to up and down in the actual use or working state of the device, specifically the direction of the drawing in the drawings ; while “inside” and “outside” refer to the outline of the device.
  • the array substrate of the present invention includes: Substrate 101; source 102, disposed on the substrate 101; drain 103, disposed on the substrate 101; light shielding portion 104, disposed on the substrate 101; active layer 106, correspondingly disposed On the source 102 , the drain 103 and the light shielding portion 104 , the active layer 106 includes a channel region 1061 ; the light shielding portion 104 is disposed corresponding to the channel region 1061 .
  • the source electrode 102 , the drain electrode 103 and the light shielding portion 104 are arranged in the same layer, and the material of the source electrode 102 and the drain electrode 103 is the same as that of the light shielding portion 104 .
  • the “same layer arrangement” mentioned here may mean that the source 102, the drain 103, and the light shielding portion 104 are arranged on the same layer at intervals, or that the light shielding portion 104 and the source 102 and the drain 103 are arranged in the same layer. The connected ones are set on the same layer.
  • the present invention forms the source electrode 102, the drain electrode 103, and the light-shielding portion 104 simultaneously through the same photomask process by using the same material. Compared with the traditional array substrate, a photomask process for separately preparing the source and drain electrodes can be saved, thereby enabling Save process and cost.
  • the active layer 106 includes a channel region 1061 and non-channel regions 1062 located on both sides of the channel region 1061, the source 102 and the drain 103 are respectively in phase with the non-channel regions 1062 touch. Since the source electrode 102 and the drain electrode 103 of the present invention are arranged on the same layer as the light-shielding portion 104, and the bottom of the active layer 106 is in contact with the top of the source electrode 102 and the drain electrode 103, therefore, the cost of preparing the interlayer insulating layer is further saved. craft. In FIG.
  • the interlayer insulating layer 5 is generally prepared by a CVD process, and the process temperature will adversely affect the active layer 2 and the gate 3, especially when the active layer 2 is an oxide semiconductor material, the high temperature of the CVD process will Affects the crystallization properties of oxide semiconductors.
  • the present invention does not require an interlayer insulating layer, so it is beneficial to improve the temperature stability of the device.
  • the array substrate of the present invention may be an array substrate with a bottom gate structure, may also be an array substrate with a top gate structure, may also be an array substrate with a double gate structure (that is, includes a bottom gate and a top gate), or may be one of the above three Any mix of structures.
  • the array substrate includes: a substrate 101, which may be a glass substrate or a flexible substrate; a source 102, a drain 103, and a light shielding portion 104 are arranged on the same layer on the substrate 101 the buffer layer 105 is arranged on the source electrode 102, the drain electrode 103 and the light shielding portion 104; the active layer 106 is arranged on the buffer layer 105, the active layer includes a channel region 1061 and is located in the channel The non-channel regions 1062 on both sides of the region 1061, the source 102 and the drain 103 are respectively in contact with the non-channel regions 1062 of the active layer 106 through the via holes on the buffer layer 105; Pole insulating layer 107, corresponding to the channel region 1061 is disposed on the active layer 106; top gate 108, corresponding to the channel region 1061 is disposed on the gate insulating layer 107; first passiva
  • the light shielding portion 104 is located under the active layer 106 and is used for shielding the light from the outside from the substrate 101 to the channel region 1061 of the active layer 106 . Further, the orthographic projection of the light shielding portion 104 on the substrate 101 covers the orthographic projection of the portion of the active layer 106 corresponding to the channel region 1061 on the substrate 101 . As shown in FIG. 2, the light shielding portion 104 is spaced from the source electrode 102 and the drain electrode 103, and the light shielding portion 104 is located between the source electrode 102 and the drain electrode 103. Due to the three materials Same, therefore the light shielding part 104 , the source 102 and the drain 103 jointly shield the light from the outside from the substrate 101 to the active layer 106 .
  • the light shielding portion 104 and the source electrode 102 are connected to each other, that is, the light shielding portion 104 and the source electrode 102 share the same film layer.
  • the source electrode 102 can connect to the groove A part extending from one side of the track region 1061 is used as the light shielding portion 104 , so that the source electrode 102 and the light shielding portion 104 can be shared.
  • the size and shape of the light shielding portion 104 can be set according to actual conditions, so as to shield the active layer 106 as much as possible.
  • the light-shielding portion 104 may be connected to the drain 103 in a manner similar to that of the above-mentioned light-shielding portion 104 being connected to the source 102 , and details will not be repeated here.
  • the light shielding part (1041, 1042) includes a first part 1041 connected to the source 102, and a second part 1042 connected to the drain 103.
  • the first part 1041 spaced apart from the second portion 1042 . That is to say, a part of the source 102 extending toward the channel region 1061 is used as the first part 1041 of the light shielding portion, and a part of the drain 103 extending toward the channel region 1061 is used as the light shielding portion.
  • Part 1042 of the second part can be shared with the source 102 and the drain 103 . At this time, the light shielding portion ( 1041 , 1042 ), the source electrode 102 and the drain electrode 103 jointly shield the light emitted from the substrate 101 to the active layer 106 .
  • the top gate 108, the source 102, the drain 103 and the active layer 106 form a thin film transistor
  • the thin film transistor can be a driving thin film transistor or a switching thin film transistor
  • the array substrate of this embodiment can be It includes a driving thin film transistor and a switching thin film transistor, wherein both the driving thin film transistor and the switching thin film transistor have a top gate structure.
  • this embodiment can save the photomask process for separately preparing the source and drain electrodes, and save the process for separately preparing the interlayer insulating layer, thereby saving process and cost.
  • the array substrate includes: a substrate 101; a source 102, a drain 103, and a light shielding portion 104 are arranged on the same layer on the substrate 101, and the light shielding portion 104 is located at the source 102 and the drain Between 103, the materials of the light shielding portion 104, the source electrode 102 and the drain electrode 103 are the same, all of which are conductive light shielding materials; the buffer layer 105 is arranged on the source electrode 102, the drain electrode 103 and the light shielding portion 104 on the active layer 106, disposed on the buffer layer 105, the active layer includes a channel region 1061 and non-channel regions 1062 located on both sides of the channel region 1061, the source 102 and the drain The electrodes 103 are respectively in contact with the non-channel region 1062 of the active layer 106 through the via holes on the buffer layer 105, the light shielding portion 104 is facing the channel region 10
  • the light shielding portion 104 is spaced apart from the source 102 and the drain 103, and the orthographic projection of the light shielding portion 104 on the substrate 101 covers the channel region 1061 of the active layer 106 The orthographic projection of the corresponding part on the substrate 101 .
  • the light shielding portion 104 can be used as the bottom gate of the TFT, that is, the light shielding portion 104 can be shared with the bottom gate. Since the material of the light-shielding part 104, the source 102, and the drain 103 is the same, the light-shielding part (bottom gate) 104, the source 102, and the drain 103 can jointly block the external radiation from the substrate 101 to the drain. source layer 106 of light.
  • the light shielding part (bottom gate) 104, the source 102, the drain 103 and the active layer 106 form a thin film transistor
  • the thin film transistor is a switching thin film transistor or a driving thin film transistor.
  • the array substrate may include a driving thin film transistor and a switching thin film transistor, wherein both the driving thin film transistor and the switching thin film transistor have a bottom gate structure.
  • the process can be simplified and the cost can be saved.
  • this embodiment is described by taking an array substrate with a double gate structure as an example.
  • the difference between this embodiment and the above-mentioned embodiment two is:
  • the array substrate of this embodiment further includes a gate insulating layer 107, which is disposed on the active layer 106 corresponding to the channel region 1061; and a top gate 108, which is disposed on the gate insulating layer corresponding to the channel region 1061 107 on.
  • the first passivation layer 109 is disposed on the active layer 106 and the top gate 108 .
  • the top gate 108 is electrically connected to the light shielding portion 104 through a via hole.
  • the top gate 108 is electrically connected to the light shielding portion 104 through a conductive layer, and the conductive layer includes a first lead 111 and a second lead 112 .
  • the first lead 111 is arranged on the same layer as the light shielding portion 104 and electrically connected, the second lead 112 is located on the first passivation layer 109, and one end of the second lead 112 passes through the first passivation layer.
  • the first via hole of a passivation layer 109 is electrically connected to the top gate 108, and the other end of the second lead 112 is connected to the second via hole penetrating through the first passivation layer 109 and the buffer layer 105.
  • the first lead 111 is electrically connected.
  • the first lead 111 may be made of the same material as the light shielding portion 104 , the source 102 and the drain 103 , and formed simultaneously in the same manufacturing process.
  • the light shielding portion 104 and the first lead 111 may be integrally formed.
  • the light-shielding part 104, the source 102, the drain 103, the active layer 106 and the top gate 108 form a double-gate thin film transistor
  • the double-gate thin film transistor is a switching thin film transistor or a driving thin film transistor.
  • Transistors, the array substrate in this embodiment may include a driving thin film transistor and a switching thin film transistor, wherein both the driving thin film transistor and the switching thin film transistor have a double-gate structure.
  • the thin film transistor since the thin film transistor has a double gate structure, compared with the single gate structure thin film transistors in the first and second embodiments, the current driving capability of the thin film transistor in this embodiment is significantly improved. On the one hand, this is because the effective channel width of the double-gate thin film transistor is larger, and on the other hand, because the carriers in the double-gate thin film transistor are less scattered at the interface, the mobility of the carriers is larger.
  • the array substrate of this embodiment includes a driving thin film transistor and a switching thin film transistor. or bottom gate structure.
  • the thin-film transistor with the double-gate structure can refer to the description in the third embodiment above
  • the thin-film transistor with the top-gate structure can refer to the description in the first embodiment above
  • the thin-film transistor with the bottom-gate structure can refer to the above-mentioned embodiment The description in Example 2 will not be repeated here.
  • the active layer 106 of the driving thin film transistor and/or the active layer 106 of the switching thin film transistor are made of indium gallium zinc oxide, indium gallium zinc tin oxide, and indium gallium tin oxide. A sort of.
  • the driving thin film transistor is a metal oxide thin film transistor
  • the switching thin film transistor is a low temperature polysilicon thin film transistor
  • the current required by the LED chip is relatively high, and the total current of the panel is generally 3A ⁇ 8A.
  • the voltage on the metal wiring is relatively high, resulting in the voltage of the metal wiring on the panel Power consumption increases.
  • the VDD/VSS metal wiring in order to meet the high current required by the LED chip, usually adopts a double-layer metal wiring design.
  • double-layer metal wiring increases the number of photomasks on the array substrate, and on the other hand, the risk of short circuit caused by the increase in the number of metal wiring layers also increases.
  • the driving thin film transistor adopts a double-gate structure, which can provide a large current for the LED chip. Therefore, the VDD/VSS metal wiring of this embodiment can be designed as a single-layer metal wiring, thereby further reducing the light intensity. The number of covers to avoid the risk of short circuit.
  • the present invention also provides a display panel, which includes the above-mentioned array substrate and LED diodes, wherein the LED diodes are Mini LEDs or Micro LEDs.
  • the array substrate includes a driving thin film transistor with a double gate structure and a switching thin film transistor with a top gate structure.
  • the display panel includes: a substrate 101; a source 102, a drain 103, and a light-shielding portion 104 are arranged on the same layer on the substrate 101, and the light-shielding portion 104 is located on the driving film.
  • the buffer layer 105 is arranged on the source 102, the drain 103 and the light shielding portion 104; the active layer 106 is arranged on the buffer layer 105 at intervals,
  • the active layer 106 includes a channel region 1061 and non-channel regions 1062 located on both sides of the channel region 1061, the source electrode 102 and the drain electrode 103 communicate with the buffer layer 105 through the via hole respectively.
  • the non-channel region 1062 of the active layer 106 is in contact with each other; the gate insulating layer 107 is arranged on the active layer 106 corresponding to the channel region 1061; the top gate 108 is arranged on the corresponding channel region 1061 On the gate insulating layer 107 ; a first passivation layer 109 is disposed on the active layer 106 and the top gate 108 .
  • the top gate 108 of the driving thin film transistor T1 is electrically connected to the light shielding portion 104 through a via hole.
  • the top gate 108 is electrically connected to the light shielding portion 104 through a conductive layer, and the conductive layer includes a first lead 111 and a second lead 112 .
  • the first lead 111 is arranged on the same layer as the light shielding portion 104 and electrically connected, the second lead 112 is located on the first passivation layer 109, and one end of the second lead 112 passes through the first passivation layer.
  • the first via hole of a passivation layer 109 is electrically connected to the top gate 108, and the other end of the second lead 112 is connected to the second via hole penetrating through the first passivation layer 109 and the buffer layer 105.
  • the first lead 111 is electrically connected.
  • the light shielding part 104 of the driving thin film transistor T1 can be used as a bottom gate at the same time, controlling the passage of electrons on the lower surface of the active layer 106, and the top gate 108 controls the passage of electrons on the upper surface of the active layer 106.
  • the light shielding portion 104 and the top gate 108 jointly control the on and off of the driving thin film transistor T1 through a bridge connection.
  • the display panel further includes: an electrode layer 113, which is disposed on the first passivation layer 109 corresponding to the pixel opening area, and the electrode layer 113 passes through the third via hole penetrating through the first passivation layer 109 and The non-channel region 1062 of the active layer 106 of the driving thin film transistor T1 is in contact with; the pad 114 is arranged on the electrode layer 113 corresponding to the electrode layer 113; the second passivation layer 115 is arranged on the electrode layer 113.
  • the black matrix 116 is disposed above the second passivation layer 115; wherein, the black matrix 116 and the second passivation layer 115 expose the pad in the pixel opening area 114 and the electrode layer 113; the LED diode 117 is located in the pixel opening area and bound to the electrode layer 113 through the pad 114.
  • the LED diodes 117 include red LED diodes, green LED diodes and blue LED diodes.
  • the design of the black matrix 116 can reduce the influence of the thin film transistor on the scattered light of the LED diode.
  • the materials of the light shielding portion 104 , the source electrode 102 and the drain electrode 103 are the same, and are all conductive light shielding materials.
  • the design of the light-shielding portion corresponding to the driving thin film transistor T1 is the same/similar to that of the light-shielding portion in the second embodiment above, that is, the light-shielding portion 104 can be connected to the source 102, the drain The poles 103 are arranged at intervals, and the light shielding part 104, the source electrode 102 and the drain electrode 103 can jointly block the light emitted from the substrate 101 to the active layer 106; or, the light shielding part 104 is connected with the source electrode 102 and the At least one of the drain electrodes 103 is connected, that is, at least one of the source electrode 102 and the drain electrode 103 is used as a light shielding portion.
  • the design of the light shielding portion 104 corresponding to the switching thin film transistor T2 is the same/similar to the design of the light shielding portion 104 in the first embodiment above, that is, the light shielding portion 104 is connected to the source 102 and the The drains 103 are arranged at intervals, and the light shielding part 104, the source 102 and the drain 103 jointly shield the light emitted from the substrate 101 to the active layer 106; or, the light shielding part 104 is connected with the source 102 and the drain At least one of the electrodes 103 is connected, and at least one of the source electrode 102 and the drain electrode 103 is used as a light shielding portion.
  • the design of the light shielding portion 104 corresponding to the switching thin film transistor T2 is the same/similar to the design of the light shielding portion 104 in the first embodiment above, that is, the light shielding portion 104 is connected to the source 102 and the The drains 103 are arranged at intervals, and the light shielding part 104, the source 102
  • the source electrode 102, the drain electrode 103 and the light-shielding portion 104 are of the same layer and material, and are formed simultaneously in the same manufacturing process, compared with the traditional array substrate, it is possible to save separate preparation of the source and drain electrodes and the bottom gate.
  • the number of 2 masks can save process and cost.
  • this embodiment does not require an interlayer insulating layer in a CVD process, so the stability of light and temperature of the device is greatly improved.
  • the driving thin film transistor of this embodiment adopts a double-gate structure, which can provide a large current for the LED diode. Therefore, the VDD/VSS metal wiring of the display panel of this embodiment can be designed as a single-layer metal wiring, thereby reducing the The number of photomasks avoids the risk of short circuit.
  • the present invention also provides a method for manufacturing a display panel, the method for manufacturing a display panel includes a method for manufacturing an array substrate, wherein the method for manufacturing an array substrate includes the following steps:
  • Step S11 forming a first metal layer on the substrate 101 , and patterning the first metal layer to form the light shielding portion 104 , the source 102 and the drain 103 .
  • the material of the first metal layer is a light-shielding conductive material.
  • Step S12 forming a buffer layer 105 on the first metal layer, patterning the buffer layer 105 to form a source-drain contact penetrating through the buffer layer 105 and corresponding to the source 102 and the drain 103 Hole 118.
  • Step S13 forming an active layer 106 on the buffer layer 105 , and forming a channel region 1061 of the active layer 106 and non-channel regions 1062 located on both sides of the channel region 1061 .
  • the non-channel region 1062 of the active layer 106 is connected to the source electrode 102 and the drain electrode 103 through the source-drain contact hole 118 , and the light shielding portion 104 corresponds to the channel region 1061 .
  • the light-shielding portion 104 can prevent external light from projecting from the back of the substrate 101 to the channel region 1061 of the active layer 106, and the light-shielding portion 104 can also be used as a bottom gate, that is, the light-shielding portion 104
  • the portion 104, the source 102, the drain 103 and the active layer 106 form a thin film transistor with a bottom gate structure.
  • the light-shielding portion (bottom gate) 104 is formed simultaneously with the source 102 and the drain 103 , which solves the technical problem of complex process and high cost when the existing light-shielding layer and source and drain are formed by different processes.
  • the preparation method further includes the following steps:
  • Step S14 forming a laminated gate insulating layer 107 and top gate 108 on the active layer 106 , the gate insulating layer 107 and the top gate 108 corresponding to the channel region 1061 located in the active layer 106 .
  • the light-shielding portion 104 can prevent external light from projecting from the back of the substrate 101 to the channel region 1061 of the active layer 106, wherein the source 102, the drain 103, the active The source layer 106 and the top gate 108 form a thin film transistor with a top gate structure.
  • the preparation method of the array substrate includes the following steps:
  • step S1 a first metal layer is formed on the substrate 101 , and the first metal layer is patterned to form a light shielding portion 104 , a source 102 , a drain 103 , and a first lead 111 .
  • the substrate 101 may be a glass substrate, but not limited thereto.
  • the first metal layer can be a laminate such as Mo, or Mo/Cu, or MoTi/Cu, and its thickness is 5000 angstroms-8000 angstroms.
  • the first metal layer can be prepared by physical vapor sputtering deposition.
  • the first metal layer is etched by using H 2 O 2 based chemical solution as an etchant.
  • step S2 as shown in FIG. 10 , a buffer layer 105 is formed on the first metal layer, and the buffer layer 105 is patterned to form a source-drain contact hole 118 penetrating through the buffer layer 105 .
  • the material of the buffer layer 105 can be SiOx or SiNx/SiOx laminated layer, adopt chemical vapor deposition, and perform high-temperature annealing treatment for 2-3 hours at a temperature of 300°C-400°C, and then pattern the source-drain contact holes.
  • step S3 as shown in FIG. 11 , an active layer 106 is formed on the buffer layer 105 .
  • the material of the active layer 106 is one of indium gallium zinc oxide, indium gallium zinc tin oxide and indium gallium tin oxide.
  • Step S4 as shown in FIG. 12 , a stacked gate insulating layer 107 and a top gate 108 are formed on the active layer 106, and the gate insulating layer 107 and the top gate 108 are set corresponding to the channel region 1061 of the active layer 106 .
  • a gate insulating layer and a second metal layer are continuously deposited on the active layer 106, the second metal layer is patterned to form a top gate 108, and the top gate self-alignment process is used to complete the gate insulating layer 107. patterning, and then use plasma to treat the active layer 106 to form the channel region 1061 and the non-channel region 1062 of the thin film transistor respectively, and the non-channel region 1062 is respectively connected to the source electrode through the source-drain contact hole 118 102 is electrically connected to the drain 103.
  • the material of the gate insulating layer 107 may be SiOx, or a stack of SiOx and SiNx, or a stack of SiOx, SiNx and Al 2 O 3 , etc., and its thickness is 2000-5000 angstroms.
  • the material of the top gate 108 can be Mo, or Mo/Cu stack, or MoTi/Cu stack, and its thickness is 5000-8000 Angstroms.
  • the light shielding portion 104 not only has a light shielding effect, but also serves as a bottom gate.
  • the light shielding portion 104 , the source 102 , the drain 103 , the active layer 106 and the top gate 108 form a thin film transistor with a double gate structure.
  • the preparation method of the display panel also includes the following steps:
  • Step S5 as shown in FIG. 13 , forming a first passivation layer 109 on the top gate 108 and patterning the first passivation layer 109 to form a first via hole corresponding to the top gate 108 119 , the second via hole 120 corresponding to the first lead 111 and the third via hole 121 corresponding to the pixel opening area.
  • the material of the first passivation layer 109 can be SiOx or SiOx/SiNx stack.
  • Step S6 as shown in FIG. 14 , an electrode layer 113 is formed on the first passivation layer 109, the electrode layer 113 corresponds to the pixel opening area and passes through the third via hole and the non-channel of the active layer 106 District 1062 contacts.
  • step S7 as shown in FIG. 15 , a pad 114 is formed on the electrode layer 113, and a second lead 112 is formed on the first passivation layer 109 at the same time, wherein one end of the second lead 112 passes through the The first via hole is electrically connected to the top gate 108 , and the other end of the second lead 112 is electrically connected to the first lead 111 through the second via hole.
  • the pad 114 and the second lead 112 are formed simultaneously in the same process using the same material, and the same material may be electrodes such as Cu or Cu/Mo.
  • step S8 as shown in FIG. 16 , a stacked second passivation layer 115 and a black matrix 116 are formed on the first passivation layer 109, wherein the black matrix 116 and the second passivation layer 115 are in the pixel opening The region exposes the pad 114 and the electrode layer 113 .
  • the patterned black matrix 116 is used as a photomask to complete the patterning of the second passivation layer 115 .
  • Step S9 binds the LED diode 117 to the pad 114 .
  • the source 102, the drain 103, the bottom gate and the light-shielding portion 104 are of the same layer and material, and are formed simultaneously in the same manufacturing process, compared with the traditional array substrate, it is possible to save separate preparation of the source and drain. and the number of 2 masks for the bottom gate, which can save process and cost.
  • this embodiment does not require an interlayer insulating layer in a CVD process, so the stability of light and temperature of the device is greatly improved.
  • the driving thin film transistor of this embodiment adopts a double-gate structure, which can provide a large current for the LED diode. Therefore, the VDD/VSS metal wiring of the display panel of this embodiment can be designed as a single-layer metal wiring, thereby reducing the The number of photomasks avoids the risk of short circuit.

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Abstract

一种阵列基板和显示面板，阵列基板包括：衬底（101）；源极（102）和漏极（103），设置于衬底（101）上；遮光部（104），设置于衬底（101）上；有源层（106），对应设置于源极（102）、漏极（103）以及遮光部（104）上，有源层（106）包括沟道区（1061），遮光部（104）对应该沟道区（1061）设置，通过将源极（102）、漏极（103）以及遮光部（104）同层设置，并且使源极（102）、漏极（103）以及遮光部（104）采用相同的材料在同一制程中同时形成，从而节省工艺、节约成本。

Description

阵列基板及其制备方法、显示面板 技术领域
本发明涉及显示技术领域，具体涉及一种阵列基板及其制备方法、显示面板。
 背景技术
Mini/Micro LED显示技术在近两年进入加速发展阶段，可以使用在中小型显示器应用领域。相较于OLED屏幕，Mini/Micro LED显示可以在成本、对比度、高亮度和轻薄外形上表现出更佳性能。在Mini/Micro LED显示技术中，TFT（Thin Film Transistor，薄膜晶体管）背板技术作为关键技术，但其制程工艺复杂，成本较高，不利于Mini/Micro LED显示面板的量产。
请参阅图1，现有技术中的阵列基板通常将遮光部1设置于有源层2的下方，以遮挡外界射向有源层2的光线，所述有源层2和栅极3之间通过栅极绝缘层4隔开，并且通常采用化学气相沉积（Chemical Vapor Deposition, CVD）工艺在所述有源层2和所述栅极3上沉积层间绝缘层5，在所述层间绝缘层5上制备源极/漏极6，所述源极/漏极6通过所述层间绝缘层5上的过孔与所述有源层2电连接。其中，现有阵列基板的制备过程需要使用多道光罩，例如遮光部的构图工艺、有源层的构图工艺、栅极绝缘层的构图工艺、栅极的构图工艺、层间绝缘层的构图工艺以及源极/漏极的构图工艺等至少六道光罩制程，使得阵列基板的制程工艺复杂、成本较高。
 技术问题
本发明提供一种阵列基板及其制备方法、显示面板，能够解决现有技术中由于TFT背板制程工艺复杂而导致成本较高的技术问题。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明实施例提供一种阵列基板，包括：
衬底；
源极，设置于所述衬底上；
漏极，设置于所述衬底上；
遮光部，设置于所述衬底上；
有源层，对应设置于所述源极、所述漏极以及所述遮光部上，所述有源层包括沟道区；
其中，所述遮光部对应所述沟道区，所述源极、所述漏极以及所述遮光部同层设置，且所述源极和所述漏极与所述遮光部的材料相同。
可选的，在本发明的一些实施例中，所述有源层还包括位于沟道区两侧的非沟道区，所述源极和所述漏极分别与所述非沟道区相接触。
可选的，在本发明的一些实施例中，所述阵列基板还包括顶栅，所述顶栅位于所述有源层之上，且所述顶栅对应所述有源层的沟道区设置。
可选的，在本发明的一些实施例中，所述遮光部与所述源极和所述漏极间隔设置，且所述遮光部与所述顶栅正对设置；或者，所述遮光部与所述源极和所述漏极中的至少一者相连接。
可选的，在本发明的一些实施例中，所述遮光部包括与所述源极连接设置的第一部分，以及包括与所述漏极连接设置的第二部分，所述第一部分和所述第二部分相间隔。
可选的，在本发明的一些实施例中，所述遮光部在所述衬底上的正投影覆盖所述有源层的沟道区对应的部分在所述衬底上的正投影。
可选的，在本发明的一些实施例中，所述顶栅和所述遮光部电连接。
可选的，在本发明的一些实施例中，所述阵列基板还包括：
缓冲层，设置于所述遮光部与所述有源层之间；
栅极绝缘层，对应所述沟道区设置于所述有源层与所述顶栅之间；
第一钝化层，设置于所述顶栅之上；
其中，所述顶栅与所述遮光部通过与所述有源层相间隔的导电层电连接，所述导电层包括第一引线和第二引线；所述第一引线与所述遮光部同层设置并且电连接；所述第二引线位于所述第一钝化层之上，所述第二引线的一端通过贯穿所述第一钝化层的第一过孔与所述顶栅电连接，另一端通过贯穿所述第一钝化层和所述缓冲层的第二过孔与所述第一引线电连接。
可选的，在本发明的一些实施例中，所述顶栅和/或所述遮光部、所述源极、所述漏极以及所述有源层组成薄膜晶体管，所述阵列基板包括驱动薄膜晶体管和开关薄膜晶体管，其中，所述驱动薄膜晶体管和所述开关薄膜晶体管均为顶栅结构；或者，所述驱动薄膜晶体管和所述开关薄膜晶体管均为底栅结构；或者，所述驱动薄膜晶体管和所述开关薄膜晶体管均为双栅结构；或者，所述驱动薄膜晶体管为双栅结构，所述开关薄膜晶体管为顶栅或底栅结构。
本发明实施例还提供一种显示面板，其包括阵列基板和LED二极管，所述阵列基板包括：
衬底；
源极，设置于所述衬底上；
漏极，设置于所述衬底上；
遮光部，设置于所述衬底上；
有源层，对应设置于所述源极、所述漏极以及所述遮光部上，所述有源层包括沟道区；
其中，所述遮光部对应所述沟道区，所述源极、所述漏极以及所述遮光部同层设置，且所述源极和所述漏极与所述遮光部的材料相同。
可选的，在本发明的一些实施例中，所述有源层还包括位于沟道区两侧的非沟道区，所述源极和所述漏极分别与所述非沟道区相接触。
可选的，在本发明的一些实施例中，所述阵列基板还包括顶栅，所述顶栅位于所述有源层之上，且所述顶栅对应所述有源层的沟道区设置。
可选的，在本发明的一些实施例中，所述遮光部与所述源极和所述漏极间隔设置，且所述遮光部与所述顶栅正对设置；或者，所述遮光部与所述源极和所述漏极中的至少一者相连接。
可选的，在本发明的一些实施例中，所述遮光部包括与所述源极连接设置的第一部分，以及包括与所述漏极连接设置的第二部分，所述第一部分和所述第二部分相间隔。
可选的，在本发明的一些实施例中，所述遮光部在所述衬底上的正投影覆盖所述有源层的沟道区对应的部分在所述衬底上的正投影。
可选的，在本发明的一些实施例中，所述顶栅和所述遮光部通过过孔电连接。
可选的，在本发明的一些实施例中，所述阵列基板还包括：
缓冲层，设置于所述遮光部与所述有源层之间；
栅极绝缘层，对应所述沟道区设置于所述有源层与所述顶栅之间；
第一钝化层，设置于所述顶栅之上；
其中，所述顶栅与所述遮光部通过与所述有源层相间隔的导电层电连接，所述导电层包括第一引线和第二引线；所述第一引线与所述遮光部同层设置并且电连接；所述第二引线位于所述第一钝化层之上，所述第二引线的一端通过贯穿所述第一钝化层的第一过孔与所述顶栅电连接，另一端通过贯穿所述第一钝化层和所述缓冲层的第二过孔与所述第一引线电连接。
可选的，在本发明的一些实施例中，所述顶栅和/或所述遮光部、所述源极、所述漏极以及所述有源层组成薄膜晶体管，所述阵列基板包括驱动薄膜晶体管和开关薄膜晶体管，其中，所述驱动薄膜晶体管和所述开关薄膜晶体管均为顶栅结构；或者，所述驱动薄膜晶体管和所述开关薄膜晶体管均为底栅结构；或者，所述驱动薄膜晶体管和所述开关薄膜晶体管均为双栅结构；或者，所述驱动薄膜晶体管为双栅结构，所述开关薄膜晶体管为顶栅或底栅结构。
本发明实施例还提供一种阵列基板的制备方法，所述制备方法包括以下步骤：
步骤S11，在衬底上形成第一金属层，对所述第一金属层图案化以形成遮光部、源极和漏极；
步骤S12，在所述第一金属层上形成缓冲层，对所述缓冲层图案化以形成贯穿所述缓冲层并且对应所述源极和所述漏极的源漏极接触孔；
步骤S13，在所述缓冲层上形成有源层，以及形成所述有源层的沟道区和位于所述沟道区两侧的非沟道区；
其中，所述有源层的非沟道区通过所述源漏极接触孔与所述源极和所述漏极连接，所述遮光部对应所述沟道区。
可选的，在本发明的一些实施例中，所述制备方法还包括以下步骤：
步骤S14，在所述有源层上形成层叠的栅极绝缘层和顶栅，所述栅极绝缘层和所述顶栅对应位于有源层的沟道区。
 有益效果
本发明的有益效果为：本发明提供的阵列基板及其制备方法、显示面板，通过将源极、漏极以及遮光部同层设置，并且源极和漏极与遮光部采用相同的材料，从而在阵列基板的制备过程中，可以使源极、漏极以及遮光部能够在同一制程中同时形成，相较于传统结构中采用两道光罩工艺分别形成遮光部和源漏极，本发明可以节省工艺、节约成本。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术提供的阵列基板的结构示意图；
图2-图4是本发明实施例一提供的顶栅结构的阵列基板的结构示意图；
图5是本发明实施例二提供的底栅结构的阵列基板的结构示意图；
图6是本发明实施例三提供的双栅结构的阵列基板的结构示意图；
图7是本发明实施例三提供的阵列基板的导电层沿绕线方向的剖面图；
图8是本发明实施例五提供的显示面板的结构示意图；
图9-图17为本发明实施例五提供的显示面板的制备流程示意图。
 本发明的实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。此外，应当理解的是，此处所描述的具体实施方式仅用于说明和解释本发明，并不用于限制本发明。在本发明中，在未作相反说明的情况下，使用的方位词如“上”和“下”通常是指装置实际使用或工作状态下的上和下，具体为附图中的图面方向；而“内”和“外”则是针对装置的轮廓而言的。
为了解决现有技术中阵列基板的制程工艺复杂、成本较高的技术问题，本发明实施例提供一种阵列基板和显示面板，请参照图2-图17所示，本发明的阵列基板包括：衬底101；源极102，设置于所述衬底101上；漏极103，设置于所述衬底101上；遮光部104，设置于所述衬底101上；有源层106，对应设置于所述源极102、所述漏极103以及所述遮光部104上，所述有源层106包括沟道区1061；所述遮光部104对应所述沟道区1061设置。其中，所述源极102、所述漏极103以及所述遮光部104同层设置，且所述源极102和所述漏极103与所述遮光部104的材料相同。
可以理解的是，这里所说的“同层设置”可以是源极102、漏极103以及遮光部104相互间隔的设置于同一层，也可以是遮光部104与源极102和漏极103中的一者相连接的设置于同一层。
本发明通过采用相同的材料，经过同一光罩制程同时形成了源极102、漏极103以及遮光部104，相较于传统的阵列基板可以节省一道单独制备源漏极的光罩制程，从而能够节省工艺、节约成本。
进一步地，所述有源层106包括沟道区1061以及位于沟道区1061两侧的非沟道区1062，所述源极102和所述漏极103分别与所述非沟道区1062相接触。由于本发明的源极102和漏极103与遮光部104同层设置，且有源层106的底部与源极102和漏极103的顶部相接触，因此，进一步节省了制备层间绝缘层的工艺。在图1中，层间绝缘层5一般采用CVD工艺制备，制程温度会对有源层2和栅极3造成不良影响，尤其当有源层2为氧化物半导体材料时，CVD制程的高温会影响氧化物半导体的结晶性能。而本发明无需层间绝缘层，因此有利于提升器件的温度稳定性。
其中，本发明的阵列基板可以是底栅结构的阵列基板，也可以是顶栅结构的阵列基板，也可以是双栅结构的阵列基板（即包括底栅和顶栅），还可以是以上三种结构的任意混合。
具体请参考以下实施例。需说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。
实施例一
请参阅图2-图4，本实施例以顶栅结构的阵列基板为例进行说明。所述阵列基板包括：衬底101，所述衬底101可以是玻璃衬底，也可以是柔性衬底；源极102、漏极103以及遮光部104同层的设置于所述衬底101上；缓冲层105，设置于所述源极102、漏极103以及遮光部104上；有源层106，设置于所述缓冲层105上，所述有源层包括沟道区1061以及位于沟道区1061两侧的非沟道区1062，所述源极102和所述漏极103分别通过所述缓冲层105上的过孔与所述有源层106的非沟道区1062相接触；栅极绝缘层107，对应所述沟道区1061设置于所述有源层106上；顶栅108，对应所述沟道区1061设置于所述栅极绝缘层107上；第一钝化层109，设置于所述有源层106以及所述顶栅108上。
其中，所述遮光部104位于所述有源层106之下，用于遮挡外界从衬底101射向有源层106的沟道区1061的光线。进一步的，所述遮光部104在所述衬底101上的正投影覆盖所述有源层106的沟道区1061对应的部分在所述衬底101上的正投影。如图2所示，所述遮光部104与所述源极102和所述漏极103间隔设置，所述遮光部104位于所述源极102和所述漏极103之间，由于三者材料相同，因此遮光部104、源极102和漏极103共同遮挡外界从衬底101射向有源层106的光线。
如图3所示，所述遮光部104与所述源极102相互连接设置，即所述遮光部104与所述源极102共用同一膜层，换言之，所述源极102可以向所述沟道区1061一侧延伸出一部分用作所述遮光部104，使得所述源极102和所述遮光部104可以共用。其中，所述遮光部104的大小和形状可根据实际情况而设定，尽可能多的遮挡所述有源层106。
当然，在其他实施例中，遮光部104可以与漏极103相互连接设置，其连接方式与上述遮光部104与源极102连接设置的方式相似，此处不再赘述。
如图4所示，所述遮光部（1041、1042）包括与所述源极102连接设置的第一部分1041，以及包括与所述漏极103连接设置的第二部分1042，所述第一部分1041和所述第二部分1042相间隔。也就是说，所述源极102向沟道区1061一侧延伸出一部分用作所述遮光部的第一部分1041，所述漏极103向沟道区1061一侧延伸出一部分用作所述遮光部的第二部分1042。换言之，所述遮光部（1041、1042）可以与所述源极102以及所述漏极103共用。此时，遮光部（1041、1042）、源极102和漏极103共同遮挡外界从衬底101射向有源层106的光线。
其中，所述顶栅108、所述源极102、所述漏极103以及所述有源层106组成薄膜晶体管，该薄膜晶体管可以为驱动薄膜晶体管或开关薄膜晶体管，本实施例的阵列基板可以包括驱动薄膜晶体管和开关薄膜晶体管，其中，所述驱动薄膜晶体管和所述开关薄膜晶体管均为顶栅结构。
本实施例相较于传统的阵列基板可以节省单独制备源漏极的光罩制程，以及节省单独制备层间绝缘层的制程，从而能够节省工艺、节约成本。
实施例二
请参阅图5，本实施例以底栅结构的阵列基板为例进行说明。所述阵列基板包括：衬底101；源极102、漏极103以及遮光部104同层的设置于所述衬底101上，且所述遮光部104位于所述源极102和所述漏极103之间，所述遮光部104、所述源极102和所述漏极103的材料相同，均为导电遮光材料；缓冲层105，设置于所述源极102、漏极103以及遮光部104上；有源层106，设置于所述缓冲层105上，所述有源层包括沟道区1061以及位于沟道区1061两侧的非沟道区1062，所述源极102和所述漏极103分别通过所述缓冲层105上的过孔与所述有源层106的非沟道区1062相接触，所述遮光部104正对所述沟道区1061；第一钝化层109，设置于所述有源层106上。
其中，所述遮光部104与所述源极102以及所述漏极103均间隔设置，所述遮光部104在所述衬底101上的正投影覆盖所述有源层106的沟道区1061对应的部分在所述衬底101上的正投影。所述遮光部104可用作薄膜晶体管的底栅，即所述遮光部104可以与底栅共用。由于所述遮光部104、所述源极102、所述漏极103三者材料相同，因此遮光部（底栅）104、源极102、漏极103可以共同遮挡外界从衬底101射向有源层106的光线。
其中，所述遮光部（底栅）104、所述源极102、所述漏极103以及所述有源层106组成薄膜晶体管，该薄膜晶体管是开关薄膜晶体管或驱动薄膜晶体管，本实施例的阵列基板可以包括驱动薄膜晶体管和开关薄膜晶体管，其中，所述驱动薄膜晶体管和所述开关薄膜晶体管均为底栅结构。
在本实施例中，由于所述遮光部（底栅）104、所述源极102以及所述漏极103由相同的材料同时形成，因此可以简化工艺、节约成本。
实施例三
请参阅图6和图7，本实施例以双栅结构的阵列基板为例进行说明。本实施例与上述实施例二的区别在于：
本实施例的阵列基板还包括栅极绝缘层107，对应所述沟道区1061设置于所述有源层106上；顶栅108，对应所述沟道区1061设置于所述栅极绝缘层107上。本实施例的第一钝化层109设置于所述有源层106以及所述顶栅108上。其中，所述顶栅108和所述遮光部104通过过孔电连接。具体如图7所示，所述顶栅108与所述遮光部104通过导电层电连接，所述导电层包括第一引线111和第二引线112。所述第一引线111与所述遮光部104同层设置并且电连接，所述第二引线112位于所述第一钝化层109之上，所述第二引线112的一端通过贯穿所述第一钝化层109的第一过孔与所述顶栅108电连接，所述第二引线112的另一端通过贯穿所述第一钝化层109和所述缓冲层105的第二过孔与所述第一引线111电连接。
可选的，所述第一引线111可以与所述遮光部104、源极102和漏极103采用相同的材料，并且在同一制程工艺中同时形成。
可选的，所述遮光部104与所述第一引线111可以一体成型。
其中，所述遮光部104、所述源极102、所述漏极103、所述有源层106以及所述顶栅108组成双栅薄膜晶体管，该双栅薄膜晶体管为开关薄膜晶体管或驱动薄膜晶体管，本实施例的阵列基板可以包括驱动薄膜晶体管和开关薄膜晶体管，其中，所述驱动薄膜晶体管和所述开关薄膜晶体管均为双栅结构。
其中，本实施例的阵列基板的其他结构与上述实施例二的阵列基板的结构相同/相似，此处不再赘述。
在本实施例中，由于薄膜晶体管为双栅结构，相比于实施例一和二的单栅结构的薄膜晶体管，本实施例的薄膜晶体管的电流驱动能力得到了显著提高。这一方面是因为双栅薄膜晶体管的有效沟道宽度较大，另一方面由于双栅薄膜晶体管中载流子受到的界面散射较小，导致载流子的迁移率较大。
实施例四
请参阅图2-图6，本实施例的阵列基板包括驱动薄膜晶体管和开关薄膜晶体管，所述驱动薄膜晶体管为双栅结构，用以提供较大的驱动电流；所述开关薄膜晶体管为顶栅或底栅结构。其中，所述双栅结构的薄膜晶体管可参照上述实施例三中的描述，所述顶栅结构的薄膜晶体管可参照上述实施例一中的描述，所述底栅结构的薄膜晶体管可参照上述实施例二中的描述，此处不再一一赘述。可选的，所述驱动薄膜晶体管的有源层106和/或所述开关薄膜晶体管的有源层106的材料为铟镓锌氧化物、铟镓锌锡氧化物和铟镓锡氧化物中的一种。
可选的，所述驱动薄膜晶体管为金属氧化物薄膜晶体管，所述开关薄膜晶体管为低温多晶硅薄膜晶体管。
在现有技术的Mini/MicroLED显示技术中，LED芯片所需电流较高，面板总电流一般为3A~8A，相应的，金属走线上电压也相对较高，导致面板的金属走线的电压功耗增大。并且，现有技术为满足LED芯片所需的大电流，VDD/VSS金属走线通常采用双层金属走线设计。双层金属走线一方面增加了阵列基板的光罩数量，另一方面，金属走线层数的增加所带来的短路风险也随之变高。
在本实施例中，一方面有源层使用上述金属氧化物材料可以使其具备较高的迁移率，从而能够降低金属走线的电压功耗。另一方面，所述驱动薄膜晶体管采用双栅结构，能够为LED芯片提供大电流，因此，本实施例的VDD/VSS金属走线采用单层金属走线设计即可，从而可以进一步减小光罩数量，避免带来短路风险。
实施例五
本发明还提供一种显示面板，该显示面板包括如上所述的阵列基板和LED二极管，其中，所述LED二极管为Mini LED或Micro LED。此处仅以阵列基板包括双栅结构的驱动薄膜晶体管和顶栅结构的开关薄膜晶体管为例进行说明。
具体请参阅图8，所述显示面板包括：衬底101；源极102、漏极103以及遮光部104同层的设置于所述衬底101上，且所述遮光部104位于所述驱动薄膜晶体管T1的源极102和漏极103之间；缓冲层105，设置于所述源极102、漏极103以及遮光部104上；有源层106，间隔的设置于所述缓冲层105上，所述有源层106包括沟道区1061以及位于沟道区1061两侧的非沟道区1062，所述源极102和所述漏极103分别通过所述缓冲层105上的过孔与所述有源层106的非沟道区1062相接触；栅极绝缘层107，对应所述沟道区1061设置于所述有源层106上；顶栅108，对应所述沟道区1061设置于所述栅极绝缘层107上；第一钝化层109，设置于所述有源层106和所述顶栅108上。
其中，所述驱动薄膜晶体管T1的所述顶栅108和所述遮光部104通过过孔电连接。具体可结合图7所示，所述顶栅108与所述遮光部104通过导电层电连接，所述导电层包括第一引线111和第二引线112。所述第一引线111与所述遮光部104同层设置并且电连接，所述第二引线112位于所述第一钝化层109之上，所述第二引线112的一端通过贯穿所述第一钝化层109的第一过孔与所述顶栅108电连接，所述第二引线112的另一端通过贯穿所述第一钝化层109和所述缓冲层105的第二过孔与所述第一引线111电连接。所述驱动薄膜晶体管T1的所述遮光部104可同时用作底栅，控制着有源层106下表面电子的通道，所述顶栅108控制着有源层106上表面电子的通道，所述遮光部104与所述顶栅108通过桥接共同控制着所述驱动薄膜晶体管T1的打开和关闭。
所述显示面板还包括：电极层113，对应像素开口区域设置于所述第一钝化层109之上，且所述电极层113通过贯穿所述第一钝化层109的第三过孔与所述驱动薄膜晶体管T1的有源层106的非沟道区1062接触；焊盘114，对应所述电极层113设置于所述电极层113之上；第二钝化层115，设置于所述第二引线112之上；黑色矩阵116，设置于所述第二钝化层115之上；其中，所述黑色矩阵116和所述第二钝化层115在像素开口区域暴露出所述焊盘114和所述电极层113；LED二极管117，位于所述像素开口区域，且通过所述焊盘114绑定于所述电极层113上。
其中，所述LED二极管117包括红光LED二极管、绿光LED二极管和蓝光LED二极管。
其中，所述黑色矩阵116的设计可降低薄膜晶体管对LED二极管散射光的影响。
在本实施例中，所述遮光部104、所述源极102和所述漏极103的材料相同，均为导电遮光材料。
在本实施例中，驱动薄膜晶体管T1所对应的遮光部的设计与上述实施例二中的遮光部的设计相同/相似，即，所述遮光部104可以与所述源极102、所述漏极103均间隔设置，遮光部104、源极102以及漏极103可以共同遮挡外界从衬底101射向有源层106的光线；或者，所述遮光部104与所述源极102和所述漏极103中的至少一者连接设置，即所述源极102、所述漏极103中的至少一者被用作遮光部。具体请参照上述实施例二以及附图6，此处不再赘述。
在本实施例中，开关薄膜晶体管T2所对应的遮光部104的设计与上述实施例一中的遮光部104的设计相同/相似，即，所述遮光部104与所述源极102和所述漏极103间隔设置，遮光部104、源极102和漏极103共同遮挡外界从衬底101射向有源层106的光线；或者，所述遮光部104与所述源极102和所述漏极103中的至少一者连接设置，所述源极102和所述漏极103中的至少一者被用作遮光部。具体请参照上述实施例一以及附图2-4，此处不再赘述。
在本实施例中，由于源极102、漏极103与遮光部104同层同材料，并且在同一制程工艺中同时形成，因此相较于传统的阵列基板可以节省单独制备源漏极和底栅的2道光罩数量，从而可以节省工艺、节约成本。同时，本实施例无需CVD制程的层间绝缘层，因此，器件的光照和温度的稳定性大大提升。此外，本实施例的驱动薄膜晶体管采用双栅结构，能够为LED二极管提供大电流，因此，本实施例显示面板的VDD/VSS金属走线采用单层金属走线设计即可，从而可以减小光罩数量，避免带来短路风险。
请参阅图9-图17，本发明还提供了一种显示面板的制备方法，所述显示面板的制备方法包括阵列基板的制备方法，其中，所述阵列基板的制备方法包括以下步骤：
步骤S11，在衬底101上形成第一金属层，对所述第一金属层图案化以形成遮光部104、源极102和漏极103。
其中，所述第一金属层的材料为遮光导电材料。
步骤S12，在所述第一金属层上形成缓冲层105，对所述缓冲层105图案化以形成贯穿所述缓冲层105并且对应所述源极102和所述漏极103的源漏极接触孔118。
步骤S13，在所述缓冲层105上形成有源层106，以及形成所述有源层106的沟道区1061和位于所述沟道区1061两侧的非沟道区1062。
其中，所述有源层106的非沟道区1062通过所述源漏极接触孔118与所述源极102和所述漏极103连接，所述遮光部104对应所述沟道区1061。
在本实施例中，所述遮光部104可以避免外部光线从衬底101的背部射向有源层106的沟道区1061，同时所述遮光部104也可以用作底栅，即所述遮光部104、所述源极102、所述漏极103以及所述有源层106形成底栅结构的薄膜晶体管。其中，遮光部（底栅）104与源极102和漏极103同时形成，解决了现有遮光层与源漏极分别采用不同工艺形成时导致工艺复杂、成本较高的技术问题。
当然，所述遮光部104也可以只用作遮光，在一种实施例中，所述制备方法还包括以下步骤：
步骤S14，在所述有源层106上形成层叠的栅极绝缘层107和顶栅108，所述栅极绝缘层107和所述顶栅108对应位于有源层106的沟道区1061。
在本实施例中，所述遮光部104可以避免外部光线从衬底101的背部射向有源层106的沟道区1061，其中，所述源极102、所述漏极103、所述有源层106以及所述顶栅108形成顶栅结构的薄膜晶体管。
在一种实施例中，所述阵列基板的制备方法包括以下步骤：
步骤S1，如图9所示，在衬底101上形成第一金属层，并对所述第一金属层图案化形成遮光部104、源极102和漏极103以及第一引线111。
其中，所述衬底101可以为玻璃基板，但不以此为限。所述第一金属层可为诸如Mo，或Mo/Cu，或MoTi/Cu等叠层，其厚度为5000埃-8000埃，第一金属层的制备方式可以采用物理气相溅射沉积方式，可采用H 2O 2系药液作为蚀刻剂对第一金属层进行蚀刻。
步骤S2，如图10所示，在所述第一金属层上形成缓冲层105，并对所述缓冲层105图案化，形成贯穿所述缓冲层105的源漏极接触孔118。
其中，缓冲层105的材质可为SiOx或SiNx/SiOx叠层，采用化学气相沉积，并进行高温退火处理2-3h，温度为300℃-400℃，之后图形化形成源漏极接触孔。
步骤S3，如图11所示，在所述缓冲层105上形成有源层106。
其中，有源层106的材料为铟镓锌氧化物、铟镓锌锡氧化物和铟镓锡氧化物中的一种。
步骤S4，如图12所示，在所述有源层106上形成层叠的栅极绝缘层107和顶栅108，栅极绝缘层107和顶栅108对应有源层106的沟道区1061设置。
具体地，在所述有源层106上连续沉积栅极绝缘层和第二金属层，对第二金属层图形化形成顶栅108，并采用顶栅自对准工艺完成栅极绝缘层107的图形化，随后采用等离子体处理有源层106分别形成薄膜晶体管的沟道区1061和非沟道区1062，所述非沟道区1062通过所述源漏极接触孔118分别与所述源极102和所述漏极103电连接。
其中，所述栅极绝缘层107的材质可为SiOx，或SiOx与SiNx叠层，或SiOx、SiNx与Al 2O 3叠层等，其厚度为2000埃-5000埃。所述顶栅108的材质可以为Mo，或Mo/Cu叠层，或MoTi/Cu等叠层，其厚度为5000埃-8000埃。
在本实施例中，所述遮光部104不仅具有遮光作用，而且还可以充当底栅。所述遮光部104、所述源极102、所述漏极103、所述有源层106以及所述顶栅108形成双栅结构的薄膜晶体管。
进一步的，所述显示面板的制备方法还包括以下步骤：
步骤S5，如图13所示，在所述顶栅108上形成第一钝化层109，并对所述第一钝化层109进行图案化，形成对应所述顶栅108的第一过孔119、对应所述第一引线111的第二过孔120以及对应像素开口区域的第三过孔121。
其中，第一钝化层109的材质可为SiOx或SiOx/SiNx叠层。
步骤S6，如图14所示，在所述第一钝化层109上形成电极层113，所述电极层113对应像素开口区域并通过所述第三过孔与有源层106的非沟道区1062接触。
步骤S7，如图15所示，在所述电极层113上形成焊盘114，同时在所述第一钝化层109上形成第二引线112，其中，所述第二引线112的一端通过所述第一过孔与所述顶栅108电连接，所述第二引线112的另一端通过所述第二过孔与所述第一引线111电连接。
其中，所述焊盘114与所述第二引线112采用同种材料在同一制程中同时形成，该同种材料可以为Cu或Cu/Mo等电极。
步骤S8，如图16所示，在第一钝化层109上形成层叠的第二钝化层115和黑色矩阵116，其中，所述黑色矩阵116和所述第二钝化层115在像素开口区域暴露出所述焊盘114和所述电极层113。
其中，在第二钝化层115和黑色矩阵116图案化的过程中，以图案化的所述黑色矩阵116作为光罩完成第二钝化层115的图案化。
步骤S9，如图17所示，将LED二极管117与所述焊盘114绑定。
在本实施例中，由于源极102、漏极103和底栅与遮光部104同层同材料，并且在同一制程工艺中同时形成，因此相较于传统的阵列基板可以节省单独制备源漏极和底栅的2道光罩数量，从而可以节省工艺、节约成本。同时，本实施例无需CVD制程的层间绝缘层，因此，器件的光照和温度的稳定性大大提升。此外，本实施例的驱动薄膜晶体管采用双栅结构，能够为LED二极管提供大电流，因此，本实施例显示面板的VDD/VSS金属走线采用单层金属走线设计即可，从而可以减小光罩数量，避免带来短路风险。
以上对本发明进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想；同时，对于本领域的技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (20)

  1. 一种阵列基板，其中，所述阵列基板包括：
    衬底；
    源极，设置于所述衬底上；
    漏极，设置于所述衬底上；
    遮光部，设置于所述衬底上；
    有源层，对应设置于所述源极、所述漏极以及所述遮光部上，所述有源层包括沟道区；
    其中，所述遮光部对应所述沟道区，所述源极、所述漏极以及所述遮光部同层设置，且所述源极和所述漏极与所述遮光部的材料相同。
  2. 根据权利要求1所述的阵列基板，其中，所述有源层还包括位于沟道区两侧的非沟道区，所述源极和所述漏极分别与所述非沟道区相接触。
  3. 根据权利要求2所述的阵列基板，其中，所述阵列基板还包括顶栅，所述顶栅位于所述有源层之上，且所述顶栅对应所述有源层的沟道区设置。
  4. 根据权利要求3所述的阵列基板，其中，所述遮光部与所述源极和所述漏极间隔设置，且所述遮光部与所述顶栅正对设置；或者，所述遮光部与所述源极和所述漏极中的至少一者相连接。
  5. 根据权利要求4所述的阵列基板，其中，所述遮光部包括与所述源极连接设置的第一部分，以及包括与所述漏极连接设置的第二部分，所述第一部分和所述第二部分相间隔。
  6. 根据权利要求4所述的阵列基板，其中，所述遮光部在所述衬底上的正投影覆盖所述有源层的沟道区对应的部分在所述衬底上的正投影。
  7. 根据权利要求4所述的阵列基板，其中，所述顶栅和所述遮光部通过过孔电连接。
  8. 根据权利要求7所述的阵列基板，其中，所述阵列基板还包括：
    缓冲层，设置于所述遮光部与所述有源层之间；
    栅极绝缘层，对应所述沟道区设置于所述有源层与所述顶栅之间；
    第一钝化层，设置于所述顶栅之上；
    其中，所述顶栅与所述遮光部通过与所述有源层相间隔的导电层电连接，所述导电层包括第一引线和第二引线；所述第一引线与所述遮光部同层设置并且电连接；所述第二引线位于所述第一钝化层之上，所述第二引线的一端通过贯穿所述第一钝化层的第一过孔与所述顶栅电连接，另一端通过贯穿所述第一钝化层和所述缓冲层的第二过孔与所述第一引线电连接。
  9. 根据权利要求4所述的阵列基板，其中，所述顶栅和/或所述遮光部、所述源极、所述漏极以及所述有源层组成薄膜晶体管，所述阵列基板包括驱动薄膜晶体管和开关薄膜晶体管，其中，所述驱动薄膜晶体管和所述开关薄膜晶体管均为顶栅结构；或者，所述驱动薄膜晶体管和所述开关薄膜晶体管均为底栅结构；或者，所述驱动薄膜晶体管和所述开关薄膜晶体管均为双栅结构；或者，所述驱动薄膜晶体管为双栅结构，所述开关薄膜晶体管为顶栅或底栅结构。
  10. 一种显示面板，其包括阵列基板和LED二极管，其中，所述阵列基板包括：
    衬底；
    源极，设置于所述衬底上；
    漏极，设置于所述衬底上；
    遮光部，设置于所述衬底上；
    有源层，对应设置于所述源极、所述漏极以及所述遮光部上，所述有源层包括沟道区；
    其中，所述遮光部对应所述沟道区，所述源极、所述漏极以及所述遮光部同层设置，且所述源极和所述漏极与所述遮光部的材料相同。
  11. 根据权利要求10所述的显示面板，其中，所述有源层还包括位于沟道区两侧的非沟道区，所述源极和所述漏极分别与所述非沟道区相接触。
  12. 根据权利要求11所述的显示面板，其中，所述阵列基板还包括顶栅，所述顶栅位于所述有源层之上，且所述顶栅对应所述有源层的沟道区设置。
  13. 根据权利要求12所述的显示面板，其中，所述遮光部与所述源极和所述漏极间隔设置，且所述遮光部与所述顶栅正对设置；或者，所述遮光部与所述源极和所述漏极中的至少一者相连接。
  14. 根据权利要求13所述的显示面板，其中，所述遮光部包括与所述源极连接设置的第一部分，以及包括与所述漏极连接设置的第二部分，所述第一部分和所述第二部分相间隔。
  15. 根据权利要求13所述的显示面板，其中，所述遮光部在所述衬底上的正投影覆盖所述有源层的沟道区对应的部分在所述衬底上的正投影。
  16. 根据权利要求13所述的显示面板，其中，所述顶栅和所述遮光部通过过孔电连接。
  17. 根据权利要求16所述的显示面板，其中，所述阵列基板还包括：
    缓冲层，设置于所述遮光部与所述有源层之间；
    栅极绝缘层，对应所述沟道区设置于所述有源层与所述顶栅之间；
    第一钝化层，设置于所述顶栅之上；
    其中，所述顶栅与所述遮光部通过与所述有源层相间隔的导电层电连接，所述导电层包括第一引线和第二引线；所述第一引线与所述遮光部同层设置并且电连接；所述第二引线位于所述第一钝化层之上，所述第二引线的一端通过贯穿所述第一钝化层的第一过孔与所述顶栅电连接，另一端通过贯穿所述第一钝化层和所述缓冲层的第二过孔与所述第一引线电连接。
  18. 根据权利要求13所述的显示面板，其中，所述顶栅和/或所述遮光部、所述源极、所述漏极以及所述有源层组成薄膜晶体管，所述阵列基板包括驱动薄膜晶体管和开关薄膜晶体管，其中，所述驱动薄膜晶体管和所述开关薄膜晶体管均为顶栅结构；或者，所述驱动薄膜晶体管和所述开关薄膜晶体管均为底栅结构；或者，所述驱动薄膜晶体管和所述开关薄膜晶体管均为双栅结构；或者，所述驱动薄膜晶体管为双栅结构，所述开关薄膜晶体管为顶栅或底栅结构。
  19. 一种阵列基板的制备方法，其中，所述制备方法包括以下步骤：
    步骤S11，在衬底上形成第一金属层，对所述第一金属层图案化以形成遮光部、源极和漏极；
    步骤S12，在所述第一金属层上形成缓冲层，对所述缓冲层图案化以形成贯穿所述缓冲层并且对应所述源极和所述漏极的源漏极接触孔；
    步骤S13，在所述缓冲层上形成有源层，以及形成所述有源层的沟道区和位于所述沟道区两侧的非沟道区；
    其中，所述有源层的非沟道区通过所述源漏极接触孔与所述源极和所述漏极连接，所述遮光部对应所述沟道区。
  20. 根据权利要求19所述的阵列基板的制备方法，其中，所述制备方法还包括以下步骤：
    步骤S14，在所述有源层上形成层叠的栅极绝缘层和顶栅，所述栅极绝缘层和所述顶栅对应位于有源层的沟道区。
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