WO2016165189A1 - Tft布局结构 - Google Patents

Tft布局结构 Download PDF

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Publication number
WO2016165189A1
WO2016165189A1 PCT/CN2015/079537 CN2015079537W WO2016165189A1 WO 2016165189 A1 WO2016165189 A1 WO 2016165189A1 CN 2015079537 W CN2015079537 W CN 2015079537W WO 2016165189 A1 WO2016165189 A1 WO 2016165189A1
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layer
active layer
source
drain
disposed
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PCT/CN2015/079537
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English (en)
French (fr)
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韩佰祥
石龙强
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深圳市华星光电技术有限公司
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Priority to US14/770,089 priority Critical patent/US9768203B2/en
Publication of WO2016165189A1 publication Critical patent/WO2016165189A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/22—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIBVI compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a TFT layout structure.
  • the flat panel display device has many advantages such as thin body, power saving, no radiation, and has been widely used.
  • the conventional flat panel display device mainly includes a liquid crystal display (LCD) and an organic light emitting display (OLED).
  • TFTs Thin Film Transistors
  • the TFT may be formed on a glass substrate or a plastic substrate, and is generally used as a switching member and a driving member on a flat panel display device such as an LCD or an OLED.
  • a GOA Gate Drive On Array
  • a gate driver Gate Drive IC
  • Array thin film transistor array
  • AMOLED active matrix OLED
  • a pixel compensation circuit composed of a plurality of TFTs is required to compensate a threshold voltage of a driving thin film transistor so that display luminance of the AMOLED is uniform.
  • the existing GOA circuit and the AMOLED pixel compensation circuit usually involve a control signal line for controlling two TFTs.
  • the gates of the first and second thin film transistors T10 and T20 are electrically connected to each other.
  • a control signal line G that is, the first and second thin film transistors T10, T20 are controlled by the control signal line G;
  • FIG. 2 is a TFT layout structure diagram of the circuit shown in FIG. 1, the first thin film transistor T10
  • the source S10 and the drain D10 are both formed on the patterned active layer SC.
  • the source S20 and the drain D20 of the second thin film transistor T20 are also formed on the patterned active layer SC, and are connected to The same gate layer Gate of a control signal line simultaneously controls the first and second thin film transistors T10, T20.
  • the source S10, the drain D10 of the first thin film transistor T10, and the source S20 and the drain D20 of the second thin film transistor T20 The first and second thin film transistors T10 and T20 can be arranged in parallel along the patterning arrangement direction of the active layer SC, and occupy a large layout space. It is not conducive to the development of narrow borders and high-resolution display panels.
  • An object of the present invention is to provide a TFT layout structure suitable for a GOA circuit and an AMOLED pixel compensation circuit, which can reduce the space of the circuit layout while ensuring the function of the circuit, increase the aperture ratio of the display panel, and satisfy the narrow border of the display panel. And high resolution requirements.
  • the present invention provides a TFT layout structure including a first thin film transistor and a second thin film transistor controlled by the same control signal line;
  • the first thin film transistor includes a bottom gate layer, a first active layer, a first source, and a first drain
  • the second thin film transistor includes a second active layer, a second source, and a second drain Pole and top gate layer;
  • the first active layer and the second active layer are located in different layers, and are stacked in space, the first source and the first drain contact the first active layer, the second source a pole, and a second drain contacting the second active layer;
  • the bottom gate layer is located under the first active layer, and the top gate layer is located above the second active layer, and the bottom gate layer and the top gate layer are electrically connected to the control signal line.
  • the opening and closing of the first thin film transistor and the second thin film transistor are separately controlled.
  • the first active layer and the second active layer spatially intersect each other.
  • the TFT layout structure further includes a substrate, a first insulating layer, a passivation layer, and a second insulating layer; the first source and the first drain are located at the second source and the second drain The same layer or different layers.
  • the bottom gate layer is disposed on the substrate, the first insulating layer is disposed on the bottom gate layer, and the substrate, and the first active layer is disposed on the first insulating layer, the blunt
  • the first source and the first drain are disposed on the passivation layer and are respectively contacted by the passivation layer via holes.
  • Two ends of the first active layer, the second active layer is disposed on the passivation layer, and the second source and the second drain are disposed on the passivation layer and respectively cover the The two ends of the second active layer are disposed on the first source, the first drain, the second active layer, the second source, the second drain, and the passivation layer
  • the top gate layer is disposed on the second insulating layer.
  • the bottom gate layer is disposed on the substrate, the first insulating layer is disposed on the bottom gate layer, and the substrate, and the first active layer is disposed on the first insulating layer, the first a source and a first drain are disposed on the first insulating layer and respectively cover both ends of the first active layer, the passivation layer Provided on the first active layer, the first source, the first drain, and the first insulating layer, the second active layer is disposed on the passivation layer, the second source, And a second drain is disposed on the passivation layer and respectively covering both ends of the second active layer, and the second insulating layer is disposed on the second active layer, the second source, and the second On the drain and the passivation layer, the top gate layer is disposed on the second insulating layer.
  • the material of the bottom gate layer, the first source, the first drain, the second source, the second drain, and the top gate layer is one or more of molybdenum, titanium, aluminum, and copper. Stack combination.
  • the material of the first active layer and the second active layer is one of an amorphous silicon-based semiconductor, a polycrystalline silicon-based semiconductor, and a zinc oxide-based semiconductor.
  • the material of the first insulating layer and the second insulating layer is silicon nitride, or silicon oxide, or a combination of the two.
  • the first active layer and the second active layer are both n-type semiconductors or both are p-type semiconductors.
  • One of the first active layer and the second active layer is a p-type semiconductor and the other is an n-type semiconductor.
  • the present invention also provides a TFT layout structure including a first thin film transistor and a second thin film transistor controlled by the same control signal line;
  • the first thin film transistor includes a bottom gate layer, a first active layer, a first source, and a first drain
  • the second thin film transistor includes a second active layer, a second source, and a second drain Pole and top gate layer;
  • the first active layer and the second active layer are located in different layers, and are stacked in space, the first source and the first drain contact the first active layer, the second source a pole, and a second drain contacting the second active layer;
  • the bottom gate layer is located under the first active layer, and the top gate layer is located above the second active layer, and the bottom gate layer and the top gate layer are electrically connected to the control signal line. Controlling opening and closing of the first thin film transistor and the second thin film transistor, respectively;
  • first active layer and the second active layer cross each other spatially;
  • the substrate further includes a substrate, a first insulating layer, a passivation layer, and a second insulating layer; the first source and the first drain are in the same layer or different layers as the second source and the second drain Layer
  • the bottom gate layer is disposed on the substrate, the first insulating layer is disposed on the bottom gate layer, and the substrate, and the first active layer is disposed on the first insulating layer.
  • the passivation layer is disposed on the first active layer and the first insulating layer, and the first source and the first drain are disposed on the passivation layer and are respectively contacted through the via layer through the passivation layer
  • Two ends of the first active layer, the second active layer is disposed on the passivation layer, and the second source and the second drain are disposed on the passivation layer and respectively covered
  • the two ends of the second active layer are disposed on the first source, the first drain, the second active layer, the second source, the second drain, and the passivation On the layer, the top gate layer is provided On the second insulating layer;
  • the material of the bottom gate layer, the first source, the first drain, the second source, the second drain, and the top gate layer is one or more of molybdenum, titanium, aluminum, and copper.
  • the material of the first active layer and the second active layer is one of an amorphous silicon-based semiconductor, a polycrystalline silicon-based semiconductor, and a zinc oxide-based semiconductor;
  • the material of the first insulating layer and the second insulating layer is silicon nitride, or silicon oxide, or a combination of the two.
  • the present invention provides a TFT layout structure in which a first active layer and a second active layer are respectively disposed on a first thin film transistor and a second thin film transistor controlled by the same control signal line, and a bottom gate layer and a top gate layer, and the first active layer and the second active layer are disposed on different layers, so that the two are spatially stacked so that two are controlled by the same control signal line
  • the TFTs are stacked in space, which can reduce the space of the circuit layout while ensuring the function of the circuit, improve the flexibility of the circuit layout, increase the aperture ratio of the display panel, meet the requirements of the narrow border of the display panel, and high resolution, and are suitable for GOA circuit, and AMOLED pixel compensation circuit.
  • 1 is a circuit diagram of a conventional TFT layout
  • FIG. 2 is a structural layout view of a TFT of the circuit shown in FIG. 1;
  • FIG. 3 is a top plan view of a TFT layout structure of the present invention.
  • Figure 4 is an embodiment corresponding to the cross-sectional view at A-A of Figure 3;
  • Figure 5 is another embodiment corresponding to the cross-sectional view taken at A-A in Figure 3;
  • Figure 6 is a cross-sectional view corresponding to B-B in Figure 3;
  • Fig. 7 is a circuit diagram corresponding to the layout structure of the TFT shown in Fig. 3.
  • the present invention provides a TFT layout structure including a first thin film transistor T1 and a second thin film transistor T2 controlled by the same control signal line.
  • the first thin film transistor T1 includes a bottom gate layer Bottom Gate, a first active layer SC1, a first source S1, and a first drain D1; and the second thin film transistor T2 includes a second active layer SC2.
  • the second source S2, the second drain D2, and the top gate layer Top Gate are included in the first thin film transistor T1 and the second thin film transistor T2 in the second thin film transistor T2.
  • the first active layer SC1 and the second active layer SC2 are located in different layers, and are stacked in space.
  • the first source S1 and the first drain D1 are in contact with the first active layer SC1.
  • the second source S2 and the second drain D2 are in contact with the second active layer SC2;
  • the bottom gate layer Bottom Gate is located under the first active layer SC1, and
  • the top gate layer Top Gate is located at the second Above the active layer SC2, the two TFTs of the first thin film transistor T1 and the second thin film transistor T2 are spatially stacked.
  • the bottom gate layer Bottom Gate and the top gate layer Top Gate are electrically connected to the control signal line to respectively control opening and closing of the first thin film transistor T1 and the second thin film transistor T2.
  • the TFT layout structure of the present invention realizes spatially stacking of the first thin film transistor T1 and the second thin film transistor T2, which are controlled by two of the same control signal lines compared to the prior art.
  • the TFTs are arranged in parallel along the patterning arrangement direction of the active layer SC, which can greatly reduce the space of the circuit layout, thereby increasing the aperture ratio of the display panel, satisfying the requirements of the narrow border of the display panel and high resolution.
  • the structure of the double active layer and the double gate layer such as the first active layer SC1, the second active layer SC2 and the bottom gate layer Bottom Gate, and the top gate layer Top Gate can also improve the flexibility of the circuit layout. degree.
  • the first active layer SC1 and the second active layer SC2 are spatially intersected to further reduce the space of the circuit layout, and are convenient for distinguishing the first source S1 and the first An extraction point of the drain D1 on the first active layer SC1, and an extraction point of the second source S2 and the second drain D2 on the second active layer SC2.
  • the TFT layout structure of the present invention further includes a substrate 1, a first insulating layer 3, a passivation layer 5, and a second insulating layer 7. As shown in FIG. 4 and FIG. 6 , the first source S1 and the first drain D1 and the second source S2 and the second drain D2 may be located in the same layer.
  • the bottom gate layer Bottom Gate is disposed on the substrate 1; the first insulating layer 3 is disposed on the bottom gate layer Bottom Gate, and the substrate 1; the first active layer SC1 is disposed on the first An insulating layer 3 is disposed on the first active layer SC1 and the first insulating layer 3; the first source S1 and the first drain D1 are disposed on the blunt layer And contacting the two ends of the first active layer SC1 through the passivation layer via 51; the second active layer SC2 is disposed on the passivation layer 5; the second source S2 and a second drain D2 are disposed on the passivation layer 5 and cover two of the second active layer SC2, respectively.
  • the second source S2 and the second drain D2 are electrically connected to the second active layer SC2, respectively; the second insulating layer 7 is disposed on the first source S1 and the first drain The top D1, the second active layer SC2, the second source S2, the second drain D2, and the passivation layer 5; the top gate layer Top Gate is disposed on the second insulating layer 7.
  • the first source S1, the first drain D1, the second source S2, and the second drain D2 are both located on the passivation layer 5.
  • first source S1 and the first drain D1 and the second source S2 and the second drain D2 may also be located in different layers, as shown in FIG. 5 and FIG. a gate layer Bottom Gate is disposed on the substrate 1; the first insulating layer 3 is disposed on the bottom gate layer Bottom Gate, and the substrate 1; the first active layer SC1 is disposed on the first insulating layer The first source S1 and the first drain D1 are disposed on the first insulating layer 3 and cover the two ends of the first active layer SC1, respectively, such that the first source S1 And the first drain D1 is electrically connected to the first active layer SC1; the passivation layer 5 is disposed on the first active layer SC1, the first source S1, the first drain D1, and The second active layer SC2 is disposed on the passivation layer 5; the second source S2 and the second drain D2 are disposed on the passivation layer 5 and respectively Covering both ends of the second active layer SC2 such that the second source S2 and the second drain D2 are in electrical contact with the second
  • the substrate 1 is a glass substrate or a plastic substrate.
  • the material of the bottom gate layer Bottom Gate, the first source S1, the first drain D1, the second source S2, the second drain D2, and the top gate layer Top Gate is molybdenum, titanium, aluminum, copper A stack combination of one or more of them.
  • the material of the first active layer SC1 and the second active layer SC2 is one of an amorphous silicon-based semiconductor, a polycrystalline silicon-based semiconductor, and a zinc oxide-based semiconductor.
  • the first active layer SC1 and the second active layer SC2 may both be n-type semiconductors or both p-type semiconductors.
  • the bottom gate layer Bottom Gate and the top gate layer Top Gate are controlled by the control signal line, so that the first thin film transistor T1 and the second thin film transistor T2 are simultaneously turned on or off.
  • one of the first active layer SC1 and the second active layer SC2 is a p-type semiconductor, and the other is an n-type semiconductor.
  • the first thin film transistor T1 and the second thin film transistor T2 have opposite threshold voltages, and the bottom gate layer Bottom Gate and the top gate layer TopGate are controlled by the control signal line when the first thin film transistor T1 is turned on.
  • Second thin film transistor T2 is turned off, and when the first thin film transistor T1 is turned off, the second thin film transistor T2 is turned on.
  • the material of the first insulating layer 3 and the second insulating layer 7 is silicon nitride, or silicon oxide, or a combination of the two.
  • the TFT layout structure is applicable to the GOA circuit and the AMOLED pixel compensation circuit, which can reduce the space of the circuit layout while ensuring the function of the circuit, improve the flexibility of the circuit layout, increase the aperture ratio of the display panel, and satisfy the narrow frame of the display panel, and High resolution requirements.
  • the TFT layout structure of the present invention is that a first active layer, a second active layer, and a bottom gate layer are respectively disposed on the first thin film transistor and the second thin film transistor controlled by the same control signal line. And a top gate layer, and the first active layer and the second active layer are disposed on different layers, so that the two are spatially stacked, so that two TFTs controlled by the same control signal line are spatially
  • the cascading setting can reduce the space of the circuit layout while ensuring the function of the circuit, improve the flexibility of the circuit layout, increase the aperture ratio of the display panel, meet the requirements of the narrow border of the display panel, and high resolution, and is suitable for the GOA circuit, and AMOLED pixel compensation circuit.

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Abstract

一种TFT布局结构，包括受同一控制信号线控制的第一薄膜晶体管(T1)、与第二薄膜晶体管(T2)；第一薄膜晶体管(T1)的第一有源层(SC1)、与第二薄膜晶体管(T2)的第二有源层(SC2)位于不同层别，并在空间上层叠设置，第一薄膜晶体管(T1)的第一源极(S1)、及第一漏极(D1)接触第一有源层(SC1)，第二薄膜晶体管(T2)的第二源极(S2)、及第二漏极(D2)接触第二有源层(SC2)；第一薄膜晶体管(T1)的底栅极层(Bottom Gate)位于第一有源层(SC1)下方，第二薄膜晶体管(T2)的顶栅极层(Top Gate)位于第二有源层(SC2)上方。该TFT布局结构能够缩小电路布局的空间，提升电路布局的灵活度，满足显示面板窄边框、及高分辨率的要求。

Description

TFT布局结构 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT布局结构。
背景技术
平板显示装置具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有的平板显示装置主要包括液晶显示装置(Liquid Crystal Display，LCD)及有机发光二极管显示装置(Organic Light Emitting Display，OLED)。
薄膜晶体管(Thin Film Transistor，TFT)是平板显示装置的重要组成部分。TFT可形成在玻璃基板或塑料基板上，通常作为开关部件和驱动部件用在诸如LCD、OLED等平板显示装置上。对于LCD来说，需要由多个TFT构成的GOA(Gate Drive On Array)电路将栅极驱动器(Gate Drive IC)整合在薄膜晶体管阵列(Array)基板上，以实现逐行扫描对液晶面板进行驱动。对于有源矩阵型OLED(Active Matrix OLED，AMOLED)来说，需要由多个TFT构成的像素补偿电路来对驱动薄膜晶体管的阈值电压进行补偿，以使得AMOLED的显示亮度均匀。
随着全球显示面板竞争日趋激烈，各大显示器生产厂商对窄边框、高分辨率的追求也是越来越高，尤其是在移动显示装置领域，目前搭载的显示面板边框已做到2mm以下、像素密度(Pixels Per Inch，PPI)已高达500以上。对于显示面板的设计来说，更窄的边框意味着更窄的GOA布局空间，更高的PPI意味着更小的子像素面积，在制程能力不变的情况下，电路有效布局的面积就越小，尤其是对于AMOLED显示面板，通常一个子像素里包含有2～7个TFT，这就对电路布局提出了更高的要求。
现有的GOA电路、及AMOLED像素补偿电路通常会涉及到一条控制信号线控制两颗TFT的情况，如图1所示，第一、第二薄膜晶体管T10、T20的栅极均电性连接于一控制信号线G，即所述第一、第二薄膜晶体管T10、T20均受该控制信号线G的控制；图2为图1所示电路的TFT布局结构图，所述第一薄膜晶体管T10的源极S10、漏极D10均形成于图案化的有源层SC上，所述第二薄膜晶体管T20的源极S20、漏极D20同样均形成于图案化的有源层SC上，连接于一控制信号线的同一栅极层Gate同时对第一、第二薄膜晶体管T10、T20进行控制。由于所述第一薄膜晶体管T10的源极S10、漏极D10及第二薄膜晶体管T20的源极S20、漏极D20 均形成于同一层图案化的有源层SC上，所述第一、第二薄膜晶体管T10、T20只能沿有源层SC的图案化排布方向进行平行间隔布局，占用的布局空间较大，不利于窄边框、及高分辨率显示面板的开发。
发明内容
本发明的目的在于提供一种TFT布局结构，适用于GOA电路、及AMOLED像素补偿电路，能够在保证电路功能的情况下缩小电路布局的空间，增加显示面板的开口率，满足显示面板窄边框、及高分辨率的要求。
为实现上述目的，本发明提供一种TFT布局结构，包括受同一控制信号线控制的第一薄膜晶体管、与第二薄膜晶体管；
所述第一薄膜晶体管包括底栅极层、第一有源层、第一源极、及第一漏极，所述第二薄膜晶体管包括第二有源层、第二源极、第二漏极、及顶栅极层；
所述第一有源层、与第二有源层位于不同层别，并在空间上层叠设置，所述第一源极、及第一漏极接触第一有源层，所述第二源极、及第二漏极接触第二有源层；
所述底栅极层位于第一有源层下方，所述顶栅极层位于第二有源层上方，所述底栅极层、与顶栅极层均电性连接所述控制信号线以分别控制第一薄膜晶体管、与第二薄膜晶体管的打开与关闭。
所述第一有源层、与第二有源层在空间上相互交叉。
所述TFT布局结构还包括基板、第一绝缘层、钝化层、及第二绝缘层；所述第一源极、及第一漏极与所述第二源极、及第二漏极位于同一层别或不同层别。
所述底栅极层设于所述基板上，所述第一绝缘层设于所述底栅极层、及基板上，所述第一有源层设于第一绝缘层上，所述钝化层设于所述第一有源层、及第一绝缘层上，所述第一源极、及第一漏极设于所述钝化层上并分别通过钝化层过孔接触所述第一有源层的两端，所述第二有源层设于所述钝化层上，所述第二源极、及第二漏极设于所述钝化层上并分别覆盖所述第二有源层的两端，所述第二绝缘层设于所述第一源极、第一漏极、第二有源层、第二源极、第二漏极、及钝化层上，所述顶栅极层设于第二绝缘层上。
所述底栅极层设于所述基板上，所述第一绝缘层设于所述底栅极层、及基板上，所述第一有源层设于第一绝缘层上，所述第一源极、及第一漏极设于所述第一绝缘层上并分别覆盖所述第一有源层的两端，所述钝化层 设于所述第一有源层、第一源极、第一漏极、及第一绝缘层上，所述第二有源层设于所述钝化层上，所述第二源极、及第二漏极设于所述钝化层上并分别覆盖所述第二有源层的两端，所述第二绝缘层设于所述第二有源层、第二源极、第二漏极、及钝化层上，所述顶栅极层设于第二绝缘层上。
所述底栅极层、第一源极、第一漏极、第二源极、第二漏极、及顶栅极层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
所述第一有源层、及第二有源层的材料为非晶硅基半导体、多晶硅基半导体、氧化锌基半导体中的一种。
所述第一绝缘层、及第二绝缘层的材料为氮化硅、或氧化硅、或二者的组合。
所述第一有源层、与第二有源层均为n型半导体或均为p型半导体。
所述第一有源层、与第二有源层的其中之一为p型半导体，另一个为n型半导体。
本发明还提供一种TFT布局结构，包括受同一控制信号线控制的第一薄膜晶体管、与第二薄膜晶体管；
所述第一薄膜晶体管包括底栅极层、第一有源层、第一源极、及第一漏极，所述第二薄膜晶体管包括第二有源层、第二源极、第二漏极、及顶栅极层；
所述第一有源层、与第二有源层位于不同层别，并在空间上层叠设置，所述第一源极、及第一漏极接触第一有源层，所述第二源极、及第二漏极接触第二有源层；
所述底栅极层位于第一有源层下方，所述顶栅极层位于第二有源层上方，所述底栅极层、与顶栅极层均电性连接所述控制信号线以分别控制第一薄膜晶体管、与第二薄膜晶体管的打开与关闭；
其中，所述第一有源层、与第二有源层在空间上相互交叉；
还包括基板、第一绝缘层、钝化层、及第二绝缘层；所述第一源极、及第一漏极与所述第二源极、及第二漏极位于同一层别或不同层别；
其中，所述底栅极层设于所述基板上，所述第一绝缘层设于所述底栅极层、及基板上，所述第一有源层设于第一绝缘层上，所述钝化层设于所述第一有源层、及第一绝缘层上，所述第一源极、及第一漏极设于所述钝化层上并分别通过钝化层过孔接触所述第一有源层的两端，所述第二有源层设于所述钝化层上，所述第二源极、及第二漏极设于所述钝化层上并分别覆盖所述第二有源层的两端，所述第二绝缘层设于所述第一源极、第一漏极、第二有源层、第二源极、第二漏极、及钝化层上，所述顶栅极层设 于第二绝缘层上；
其中，所述底栅极层、第一源极、第一漏极、第二源极、第二漏极、及顶栅极层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；
其中，所述第一有源层、及第二有源层的材料为非晶硅基半导体、多晶硅基半导体、氧化锌基半导体中的一种；
其中，所述第一绝缘层、及第二绝缘层的材料为氮化硅、或氧化硅、或二者的组合。
本发明的有益效果：本发明提供的一种TFT布局结构，为受同一控制信号线控制的第一薄膜晶体管、与第二薄膜晶体管分别设置第一有源层、与第二有源层、及底栅极层、与顶栅极层，并将第一有源层、与第二有源层设于不同层别，使二者在空间上层叠设置，使得受同一控制信号线控制的两颗TFT在空间上层叠设置，能够在保证电路功能的情况下缩小电路布局的空间，提升电路布局的灵活度，增加显示面板的开口率，满足显示面板窄边框、及高分辨率的要求，适用于GOA电路、及AMOLED像素补偿电路。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为一种现有的TFT布局电路图；
图2为图1所示电路的TFT布局结构图；
图3为本发明的TFT布局结构的俯视图；
图4为对应于图3中A-A处剖面图的一种实施方式；
图5为对应于图3中A-A处剖面图的另一种实施方式；
图6为对应于图3中B-B处的剖面图；
图7为对应于图3所示TFT布局结构的电路图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请同时参阅图3、图4、及图6，本发明提供一种TFT布局结构，包括受同一控制信号线控制的第一薄膜晶体管T1、与第二薄膜晶体管T2。
所述第一薄膜晶体管T1包括底栅极层Bottom Gate、第一有源层SC1、第一源极S1、及第一漏极D1；所述第二薄膜晶体管T2包括第二有源层SC2、第二源极S2、第二漏极D2、及顶栅极层Top Gate。
所述第一有源层SC1、与第二有源层SC2位于不同层别，并在空间上层叠设置，所述第一源极S1、及第一漏极D1接触第一有源层SC1，所述第二源极S2、及第二漏极D2接触第二有源层SC2；所述底栅极层Bottom Gate位于第一有源层SC1下方，所述顶栅极层Top Gate位于第二有源层SC2上方，使得所述第一薄膜晶体管T1、与第二薄膜晶体管T2这两颗TFT在空间上层叠设置。
所述底栅极层Bottom Gate、与顶栅极层Top Gate均电性连接所述控制信号线以分别控制第一薄膜晶体管T1、与第二薄膜晶体管T2的打开与关闭。
如图7所示，本发明的TFT布局结构实现了所述第一薄膜晶体管T1、与第二薄膜晶体管T2在空间上层叠设置，相比于现有技术将受控于同一控制信号线的两颗TFT沿有源层SC的图案化排布方向进行平行间隔布局，能够大幅度缩小电路布局的空间，从而增加显示面板的开口率，满足显示面板窄边框、及高分辨率的要求，同时，设置第一有源层SC1、与第二有源层SC2及底栅极层Bottom Gate、与顶栅极层Top Gate这样的双有源层、双栅极层的结构还能够提升电路布局的灵活度。
进一步地，如图3所示，所述第一有源层SC1、与第二有源层SC2在空间上相互交叉，以进一步缩小电路布局的空间，并便于区分第一源极S1、与第一漏极D1在第一有源层SC1上的引出点、及第二源极S2、与第二漏极D2在第二有源层SC2上的引出点。
具体地，本发明的TFT布局结构还包括基板1、第一绝缘层3、钝化层5、及第二绝缘层7。如图4、图6所示，所述第一源极S1、及第一漏极D1与所述第二源极S2、及第二漏极D2可位于同一层别。所述底栅极层Bottom Gate设于所述基板1上；所述第一绝缘层3设于所述底栅极层Bottom Gate、及基板1上；所述第一有源层SC1设于第一绝缘层3上；所述钝化层5设于所述第一有源层SC1、及第一绝缘层3上；所述第一源极S1、及第一漏极D1设于所述钝化层5上并分别通过钝化层过孔51接触所述第一有源层SC1的两端；所述第二有源层SC2设于所述钝化层5上；所述第二源极S2、及第二漏极D2设于所述钝化层5上并分别覆盖所述第二有源层SC2的两 端，使得所述第二源极S2、及第二漏极D2分别与第二有源层SC2形成电性接触；所述第二绝缘层7设于所述第一源极S1、第一漏极D1、第二有源层SC2、第二源极S2、第二漏极D2、及钝化层5上；所述顶栅极层Top Gate设于第二绝缘层7上。在此种实施方式中，所述第一源极S1、及第一漏极D1与所述第二源极S2、及第二漏极D2均位于钝化层5上。
当然，所述第一源极S1、及第一漏极D1与所述第二源极S2、及第二漏极D2也可位于不同层别，如图5、图6所示，所述底栅极层Bottom Gate设于所述基板1上；所述第一绝缘层3设于所述底栅极层Bottom Gate、及基板1上；所述第一有源层SC1设于第一绝缘层3上；所述第一源极S1、及第一漏极D1设于所述第一绝缘层3上并分别覆盖所述第一有源层SC1的两端，使得所述第一源极S1、及第一漏极D1分别与第一有源层SC1形成电性接触；所述钝化层5设于所述第一有源层SC1、第一源极S1、第一漏极D1、及第一绝缘层3上；所述第二有源层SC2设于所述钝化层5上；所述第二源极S2、及第二漏极D2设于所述钝化层5上并分别覆盖所述第二有源层SC2的两端，使得所述第二源极S2、及第二漏极D2分别与第二有源层SC2形成电性接触；所述第二绝缘层7设于所述第二有源层SC2、第二源极S2、第二漏极D2、及钝化层5上；所述顶栅极层Top Gate设于第二绝缘层7上。在此种实施方式中，所述第一源极S1、及第一漏极D1位于所述第一绝缘层3上，而所述第二源极S2、及第二漏极D2位于钝化层5上。
可选地，所述基板1为玻璃基板或塑料基板。
所述底栅极层Bottom Gate、第一源极S1、第一漏极D1、第二源极S2、第二漏极D2、及顶栅极层Top Gate的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
所述第一有源层SC1、及第二有源层SC2的材料为非晶硅基半导体、多晶硅基半导体、氧化锌基半导体中的一种。
所述第一有源层SC1、与第二有源层SC2可均为n型半导体或均为p型半导体。此种情况下，所述底栅极层Bottom Gate与顶栅极层Top Gate受控制信号线控制，使第一薄膜晶体管T1与第二薄膜晶体管T2同时打开或关闭。
或者，所述第一有源层SC1、与第二有源层SC2的其中之一为p型半导体，另一个为n型半导体。此种情况下，第一薄膜晶体管T1与第二薄膜晶体管T2具有相反的阈值电压，所述底栅极层Bottom Gate与顶栅极层TopGate受控制信号线控制，当第一薄膜晶体管T1打开时，第二薄膜晶体管 T2关闭，而当第一薄膜晶体管T1关闭时，第二薄膜晶体管T2打开。
所述第一绝缘层3、及第二绝缘层7的材料为氮化硅、或氧化硅、或二者的组合。
上述TFT布局结构适用于GOA电路、及AMOLED像素补偿电路，能够在保证电路功能的情况下缩小电路布局的空间，提升电路布局的灵活度，增加显示面板的开口率，满足显示面板窄边框、及高分辨率的要求。
综上所述，本发明的TFT布局结构，为受同一控制信号线控制的第一薄膜晶体管、与第二薄膜晶体管分别设置第一有源层、与第二有源层、及底栅极层、与顶栅极层，并将第一有源层、与第二有源层设于不同层别，使二者在空间上层叠设置，使得受同一控制信号线控制的两颗TFT在空间上层叠设置，能够在保证电路功能的情况下缩小电路布局的空间，提升电路布局的灵活度，增加显示面板的开口率，满足显示面板窄边框、及高分辨率的要求，适用于GOA电路、及AMOLED像素补偿电路。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (13)

  1. 一种TFT布局结构，包括受同一控制信号线控制的第一薄膜晶体管、与第二薄膜晶体管；
    所述第一薄膜晶体管包括底栅极层、第一有源层、第一源极、及第一漏极，所述第二薄膜晶体管包括第二有源层、第二源极、第二漏极、及顶栅极层；
    所述第一有源层、与第二有源层位于不同层别，并在空间上层叠设置，所述第一源极、及第一漏极接触第一有源层，所述第二源极、及第二漏极接触第二有源层；
    所述底栅极层位于第一有源层下方，所述顶栅极层位于第二有源层上方，所述底栅极层、与顶栅极层均电性连接所述控制信号线以分别控制第一薄膜晶体管、与第二薄膜晶体管的打开与关闭。
  2. 如权利要求1所述的TFT布局结构，其中，所述第一有源层、与第二有源层在空间上相互交叉。
  3. 如权利要求2所述的TFT布局结构，还包括基板、第一绝缘层、钝化层、及第二绝缘层；所述第一源极、及第一漏极与所述第二源极、及第二漏极位于同一层别或不同层别。
  4. 如权利要求3所述的TFT布局结构，其中，所述底栅极层设于所述基板上，所述第一绝缘层设于所述底栅极层、及基板上，所述第一有源层设于第一绝缘层上，所述钝化层设于所述第一有源层、及第一绝缘层上，所述第一源极、及第一漏极设于所述钝化层上并分别通过钝化层过孔接触所述第一有源层的两端，所述第二有源层设于所述钝化层上，所述第二源极、及第二漏极设于所述钝化层上并分别覆盖所述第二有源层的两端，所述第二绝缘层设于所述第一源极、第一漏极、第二有源层、第二源极、第二漏极、及钝化层上，所述顶栅极层设于第二绝缘层上。
  5. 如权利要求3所述的TFT布局结构，其中，所述底栅极层设于所述基板上，所述第一绝缘层设于所述底栅极层、及基板上，所述第一有源层设于第一绝缘层上，所述第一源极、及第一漏极设于所述第一绝缘层上并分别覆盖所述第一有源层的两端，所述钝化层设于所述第一有源层、第一源极、第一漏极、及第一绝缘层上，所述第二有源层设于所述钝化层上，所述第二源极、及第二漏极设于所述钝化层上并分别覆盖所述第二有源层的两端，所述第二绝缘层设于所述第二有源层、第二源极、第二漏极、及 钝化层上，所述顶栅极层设于第二绝缘层上。
  6. 如权利要求3所述的TFT布局结构，其中，所述底栅极层、第一源极、第一漏极、第二源极、第二漏极、及顶栅极层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
  7. 如权利要求3所述的TFT布局结构，其中，所述第一有源层、及第二有源层的材料为非晶硅基半导体、多晶硅基半导体、氧化锌基半导体中的一种。
  8. 如权利要求3所述的TFT布局结构，其中，所述第一绝缘层、及第二绝缘层的材料为氮化硅、或氧化硅、或二者的组合。
  9. 如权利要求7所述的TFT布局结构，其中，所述第一有源层、与第二有源层均为n型半导体或均为p型半导体。
  10. 如权利要求7所述的TFT布局结构，其中，所述第一有源层、与第二有源层的其中之一为p型半导体，另一个为n型半导体。
  11. 一种TFT布局结构，包括受同一控制信号线控制的第一薄膜晶体管、与第二薄膜晶体管；
    所述第一薄膜晶体管包括底栅极层、第一有源层、第一源极、及第一漏极，所述第二薄膜晶体管包括第二有源层、第二源极、第二漏极、及顶栅极层；
    所述第一有源层、与第二有源层位于不同层别，并在空间上层叠设置，所述第一源极、及第一漏极接触第一有源层，所述第二源极、及第二漏极接触第二有源层；
    所述底栅极层位于第一有源层下方，所述顶栅极层位于第二有源层上方，所述底栅极层、与顶栅极层均电性连接所述控制信号线以分别控制第一薄膜晶体管、与第二薄膜晶体管的打开与关闭；
    其中，所述第一有源层、与第二有源层在空间上相互交叉；
    还包括基板、第一绝缘层、钝化层、及第二绝缘层；所述第一源极、及第一漏极与所述第二源极、及第二漏极位于同一层别或不同层别；
    其中，所述底栅极层设于所述基板上，所述第一绝缘层设于所述底栅极层、及基板上，所述第一有源层设于第一绝缘层上，所述钝化层设于所述第一有源层、及第一绝缘层上，所述第一源极、及第一漏极设于所述钝化层上并分别通过钝化层过孔接触所述第一有源层的两端，所述第二有源层设于所述钝化层上，所述第二源极、及第二漏极设于所述钝化层上并分别覆盖所述第二有源层的两端，所述第二绝缘层设于所述第一源极、第一漏极、第二有源层、第二源极、第二漏极、及钝化层上，所述顶栅极层设 于第二绝缘层上；
    其中，所述底栅极层、第一源极、第一漏极、第二源极、第二漏极、及顶栅极层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；
    其中，所述第一有源层、及第二有源层的材料为非晶硅基半导体、多晶硅基半导体、氧化锌基半导体中的一种；
    其中，所述第一绝缘层、及第二绝缘层的材料为氮化硅、或氧化硅、或二者的组合。
  12. 如权利要求11所述的TFT布局结构，其中，所述第一有源层、与第二有源层均为n型半导体或均为p型半导体。
  13. 如权利要求11所述的TFT布局结构，其中，所述第一有源层、与第二有源层的其中之一为p型半导体，另一个为n型半导体。
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