WO2021159566A1 - 显示面板及其制作方法 - Google Patents

显示面板及其制作方法 Download PDF

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Publication number
WO2021159566A1
WO2021159566A1 PCT/CN2020/077394 CN2020077394W WO2021159566A1 WO 2021159566 A1 WO2021159566 A1 WO 2021159566A1 CN 2020077394 W CN2020077394 W CN 2020077394W WO 2021159566 A1 WO2021159566 A1 WO 2021159566A1
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WIPO (PCT)
Prior art keywords
conductive block
pattern
display panel
block
light
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PCT/CN2020/077394
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English (en)
French (fr)
Inventor
周星宇
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US16/646,156 priority Critical patent/US11856813B2/en
Publication of WO2021159566A1 publication Critical patent/WO2021159566A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/86—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K50/865—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. light-blocking layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/8791—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K59/8792—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. black layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/10—Transparent electrodes, e.g. using graphene
    • H10K2102/101—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO]
    • H10K2102/102—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO] comprising tin oxides, e.g. fluorine-doped SnO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/10—Transparent electrodes, e.g. using graphene
    • H10K2102/101—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO]
    • H10K2102/103—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO] comprising indium oxides, e.g. ITO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance

Definitions

  • This application relates to the field of display technology, in particular to a display panel and a manufacturing method thereof.
  • the transmittance of the display panel plays an extremely important role in its overall display performance.
  • the structure of the display panel usually includes thin film transistors (Thin Film Transistor, TFT) and capacitors.
  • TFT Thin Film Transistor
  • metal layers and ion-doped semiconductor layers are usually used to form the two poles of the capacitor.
  • the metal layer does not transmit light, the light transmission area of the display panel is reduced and the display The transparency of the panel is not high.
  • the present application provides a display panel that uses conductive partial active layer patterns and transparent conductive blocks arranged on a substrate as the two poles of the capacitor. Since the transparent conductive blocks and the semiconductor materials forming the active layer patterns are both transparent materials, , Can increase the light-transmitting area of the display panel and improve the transparency of the display panel.
  • the embodiments of the present application provide a display panel and a manufacturing method thereof, so as to solve the technical problem of the display panel having less light-transmitting area and low transparency.
  • This application provides a display panel, including:
  • a buffer layer provided on the substrate, the light-shielding metal block and the transparent conductive block;
  • An active layer pattern disposed on the buffer layer includes a first conductive block, the first conductive block is disposed opposite to the transparent conductive block, and the first conductive block is a semiconductor material Conduction formation, the transparent conductive block and the first conductive block constitute two poles of a capacitor.
  • the material of the transparent conductive block is indium tin oxide, aluminum zinc oxide or indium zinc oxide.
  • the semiconductor material is a transparent metal oxide semiconductor such as indium gallium zinc oxide, indium tin zinc oxide, or indium gallium zinc tin oxide.
  • the active layer pattern further includes a second conductive block, a third conductive block, and a conductive channel connecting the second conductive block and the third conductive block, and the conductive channel
  • the channel is a semiconductor material, and the second conductive block and the third conductive block are both formed by conducting the semiconductor material.
  • the conductive channel is arranged directly above the light-shielding metal block.
  • the display panel further includes:
  • An interlayer dielectric layer disposed on the buffer layer, the active layer pattern, the insulating layer pattern, and the gate pattern, the interlayer dielectric layer having a first via hole and a second via hole;
  • the interlayer dielectric layer further has a third via hole, and the third via hole penetrates the interlayer dielectric layer and extends to the light-shielding metal block;
  • the source pattern is connected to the light-shielding metal block through the third via hole.
  • the thickness of the active layer pattern is 100 angstroms to 1000 angstroms.
  • the thickness of the transparent conductive block is 200 angstroms to 2000 angstroms.
  • the application also provides a display panel, which includes:
  • a buffer layer provided on the substrate, the light-shielding metal block and the transparent conductive block;
  • An active layer pattern disposed on the buffer layer includes a first conductive block, the first conductive block is disposed opposite to the transparent conductive block, and the first conductive block is a semiconductor material Conduction formation, the transparent conductive block and the first conductive block constitute two poles of a capacitor;
  • the material of the transparent conductive block is indium tin oxide, aluminum zinc oxide or indium zinc oxide
  • the semiconductor material is a transparent metal oxide semiconductor such as indium gallium zinc oxide, indium tin zinc oxide or indium gallium zinc tin oxide.
  • the active layer pattern further includes a second conductive block, a third conductive block, and a conductive channel connecting the second conductive block and the third conductive block, and the conductive channel
  • the channel is a semiconductor material, and the second conductive block and the third conductive block are both formed by conducting the semiconductor material.
  • the conductive channel is arranged directly above the light-shielding metal block.
  • the display panel further includes:
  • An interlayer dielectric layer disposed on the buffer layer, the active layer pattern, the insulating layer pattern, and the gate pattern, the interlayer dielectric layer having a first via hole and a second via hole;
  • the interlayer dielectric layer further has a third via hole, and the third via hole penetrates the interlayer dielectric layer and extends to the light-shielding metal block;
  • the source pattern is connected to the light-shielding metal block through the third via hole.
  • the thickness of the active layer pattern is 100 angstroms to 1000 angstroms.
  • the thickness of the transparent conductive block is 200 angstroms to 2000 angstroms.
  • this application also provides a manufacturing method of a display panel, including:
  • An active layer pattern is formed on the buffer layer, the active layer pattern includes a first conductive block, the first conductive block is disposed opposite to the transparent conductive block, and the first conductive block is a semiconductor material conductor The transparent conductive block and the first conductive block constitute two poles of a capacitor.
  • the present application provides a display panel and a manufacturing method thereof.
  • the display panel uses a conductive partial active layer pattern and a transparent conductive block provided on a substrate as the two poles of the capacitor.
  • the transparent conductive block and the semiconductor forming the active layer pattern The materials are all transparent materials, which effectively increase the light-transmitting area of the display panel, thereby increasing the transparency of the display panel.
  • FIG. 1 is a schematic diagram of a first structure of a display panel provided by the present application.
  • FIG. 2 is a schematic diagram of a second structure of the display panel provided by the present application.
  • FIG. 3 is a schematic diagram of a third structure of the display panel provided by the present application.
  • FIG. 4 is a schematic flow chart of the manufacturing method of the display panel provided by the present application.
  • patterning refers to the step of forming a specific pattern structure, which can be a photolithography process, which includes forming a material layer, coating photoresist, exposing, One or more of the steps of development, etching, photoresist stripping, etc., are processes understood by those skilled in the art, and will not be repeated here.
  • the display panel 100 includes: a substrate 11; a light-shielding metal block 12 and a transparent conductive block 13 arranged on the substrate 11; a buffer layer 14 arranged on the substrate 11, a light-shielding metal block 12, and a transparent conductive block 13; and a buffer layer 14
  • the active layer pattern 15 on the upper surface, the active layer pattern 15 includes a first conductive block 151, the first conductive block 151 is arranged opposite to the transparent conductive block 13, the first conductive block 151 is formed by conducting semiconductor material, and the transparent conductive block 13 And the first conductive block 151 constitute the two poles of the capacitor 20.
  • the substrate 10 may be a glass substrate, a quartz substrate, a resin substrate, a PI flexible substrate (polyimide film, Polyimide Film) or other types of substrates, which will not be repeated here.
  • the material of the light-shielding metal block 12 is a metal with excellent conductivity and good light-shielding properties, generally molybdenum, copper, aluminum, titanium or composite metal, which is not limited in this application.
  • the thickness of the light-shielding metal block 12 is 500 angstroms to 10000 angstroms.
  • the material of the transparent conductive block 13 is indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO) or other suitable transparent conductive materials, and may also be a combination of the foregoing materials.
  • the thickness of the transparent conductive block 13 is 200 angstroms to 2000 angstroms.
  • the semiconductor material forming the active layer pattern 15 may be a transparent metal oxide semiconductor such as indium gallium zinc oxide (IGZO), indium tin zinc oxide (IZTO), or indium gallium zinc tin oxide (IGZTO).
  • IGZO indium gallium zinc oxide
  • IZTO indium tin zinc oxide
  • IGZTO indium gallium zinc tin oxide
  • the thickness of the active layer pattern 15 is 100 angstroms to 1000 angstroms.
  • the buffer layer 14 may be formed of a single layer or multiple layers of silicon dioxide, silicon nitride, or silicon oxynitride. In the direction perpendicular to the substrate 11, the thickness of the buffer layer 14 is 1000 angstroms to 5000 angstroms.
  • the materials and thicknesses of the above film layers can be set according to the actual structural requirements of the display panel 100, which is not specifically limited in this application.
  • the first conductive block 151 and the transparent conductive block 13 are used as the two poles of the capacitor 20 in the embodiment of the present application.
  • the distance between the two electrodes is also significantly reduced. It can be understood that the smaller the distance between the two electrodes of the capacitor 20, the greater the storage capacitance per unit area, and the better the performance of the capacitor 20.
  • the thickness of the buffer layer 14 and the thickness of the transparent conductive block 13 can be set to be similar, and the distance between the first conductive block 151 and the transparent conductive block 13 can also be effectively reduced.
  • the embodiment of the present application can control the distance between the two electrodes of the capacitor 20 by controlling the thickness of the transparent conductive block 13 and the buffer layer 14, thereby increasing the capacitor 20. Performance.
  • the embodiment of the present application provides a display panel 100.
  • the display panel 100 uses a transparent conductive block 13 provided on a substrate 11 and a conductive first conductive block 151 included in the active layer pattern 15 as the two poles of the capacitor 20.
  • the transparent conductive block 13 and the semiconductor material forming the first conductive block 151 are both transparent materials. Therefore, the embodiment of the present application can effectively increase the light-transmitting area of the display panel 100 and improve its transparency.
  • the active layer pattern 15 further includes a second conductive block 152, a third conductive block 154, and a conductive channel 153 connecting the second conductive block 152 and the third conductive block 154.
  • the conductive channel 153 is a semiconductor material.
  • the second conductive block 152 and the third conductive block 154 are both formed by conducting semiconductor materials.
  • the conductive channel 153 is arranged directly above the light-shielding metal block 12. It can be understood that the conductive channel 153 will increase the photo-generated carriers after being irradiated by the light from the side of the substrate 11, causing the thin film transistors to generate threshold voltage drift, leakage current increase and other undesirable phenomena.
  • the light-shielding metal block 12 can block the light incident from the direction of the substrate 11 away from the light-shielding metal block 12, thereby reducing the interference of external light on the conductive channel 153, improving the stability of the pixel driving circuit in the display panel 100, thereby improving the display panel 100 working performance.
  • the display panel 100 further includes: an insulating layer pattern 16 and a gate pattern 17 stacked on the active layer pattern 15;
  • the interlayer dielectric layer 18 on the layer pattern 16 and the gate pattern 17, the interlayer dielectric layer 18 has a first via 18a and a second via 18b; a source pattern 191 and a drain provided on the interlayer dielectric layer 18 In the pattern 192, the source pattern 191 is connected to the second conductive block 152 through the first via 18a, and the drain pattern 192 is connected to the third conductive block 154 through the second via 18b.
  • the material of the insulating layer pattern 16 may be silicon oxide, silicon nitride, or a combination of silicon oxide and silicon nitride, or the like.
  • the insulating layer pattern 16 may have a single-layer structure or a multilayer structure. In the direction perpendicular to the substrate 11, the thickness of the insulating layer pattern 16 is 1000 angstroms to 3000 angstroms.
  • the gate pattern 17 may be a single-layer metal structure or a multilayer metal laminate structure with good conductivity, and the metal may be molybdenum, copper, aluminum, titanium, or a composite metal. In the direction perpendicular to the substrate 11, the thickness of the gate pattern 17 is 2000 angstroms to 8000 angstroms.
  • the material of the interlayer dielectric layer 18 may be silicon oxide, silicon nitride, or a combination of silicon oxide and silicon nitride, or the like.
  • the interlayer dielectric layer 18 may be a single-layer structure or a multilayer structure. In the direction perpendicular to the substrate 11, the thickness of the interlayer dielectric layer 18 is 2000 angstroms to 10000 angstroms.
  • the source pattern 191 and the drain pattern 192 may be a single-layer metal structure or a multilayer metal laminate structure with good conductivity, and the metal may be molybdenum, copper, aluminum, titanium, or a composite metal. In the direction perpendicular to the substrate 11, the thickness of the gate pattern 17 is 2000 angstroms to 8000 angstroms.
  • the display panel 100 in the embodiment of the present application further includes: a passivation layer 21 and a flattening layer 22 stacked on the interlayer dielectric layer 18, the source pattern 191, and the drain pattern 192.
  • the flattening layer 22 has a fourth layer.
  • the via hole 22a, the fourth via hole 22a penetrate the flat layer 22 and extend to the passivation layer 21, and at the same time expose the side of the source pattern 191 away from the substrate 11; the pixel electrode pattern 23 disposed on the flat layer 22, the pixel electrode The pattern 23 is connected to the source pattern 191 through the fourth via 22a; the pixel defining layer 24 is disposed on the flat layer 22 and the pixel electrode pattern 23, the pixel defining layer 24 has a fifth via 24a, and the fifth via 24a is exposed
  • the side of the pixel electrode pattern 23 away from the substrate 11; the light-emitting layer 25 disposed in the fifth via 24 a and the side of the light-emitting layer 25 close to the substrate 11 are connected to the pixel electrode pattern 23.
  • the cathode layer 26 disposed on the pixel defining layer 24 and the light emitting layer 25 is connected to the cathode layer 26 on the side of the light emitting layer 25 away from the substrate 11.
  • the material of the passivation layer 21 may be silicon oxide, silicon nitride, or a combination of silicon oxide and silicon nitride, or the like.
  • the passivation layer 21 may be a single-layer structure or a multi-layer structure. In the direction perpendicular to the substrate 11, the thickness of the passivation layer 21 is 1000 angstroms to 5000 angstroms.
  • the material of the pixel electrode pattern 23 may be metals such as indium tin oxide, silver, and indium zinc oxide.
  • the light-emitting layer 25 includes a light-emitting material capable of emitting red light, green light, or blue light.
  • the materials and thicknesses of the above functional film layers can be set according to the actual structural requirements of the display panel 100, which is not limited in this application.
  • the source pattern 191 and the drain pattern 192 are symmetrically arranged, so the source pattern 191 and the drain pattern 192 are interchangeable.
  • the pixel electrode pattern 23 may be connected to the source pattern 191 or the drain pattern 192.
  • the structure of the display panel 100 shown in FIG. 3 cannot be understood as a limitation of the present application.
  • the interlayer dielectric layer 18 in the display panel 100 further has a third via 18c.
  • the third via 18c penetrates the interlayer dielectric layer 18 and extends to the buffer layer 14, and at the same time exposes the side of the light-shielding metal block 12 away from the substrate 11.
  • the source pattern 191 is connected to the light-shielding metal block 12 through the third via 18c.
  • both the light-shielding metal block 12 and the source pattern 191 are formed of a metal with good conductivity, this arrangement enables the light-shielding metal block 12 to have a light-shielding effect and can also serve as a part of the source pattern 191 to enhance the source pattern 191 The conductivity of the display panel 100, thereby improving the working performance of the thin film transistor in the display panel 100.
  • the present application also provides a manufacturing method of the display panel 100, which specifically includes the following steps:
  • a substrate 11 is provided, and the substrate 11 is cleaned and pre-baked to remove foreign particles such as oil and grease on the surface of the substrate 11.
  • a first metal layer is deposited on the substrate 11, and the first metal layer is patterned to form a light-shielding metal block 12. Then, a transparent conductive layer is deposited on the part of the substrate 11 that is not covered by the light-shielding metal block 12, and the transparent conductive layer is patterned to form the transparent conductive block 13.
  • a buffer layer is deposited on the substrate 11, the light-shielding metal block 12 and the transparent conductive block 13.
  • the buffer layer 14 can be formed by an evaporation process, a chemical vapor deposition process, a coating process, a sol-gel process or other processes.
  • An active layer pattern is formed on the buffer layer, the active layer pattern includes a first conductive block, the first conductive block is disposed opposite to the transparent conductive block, and the first conductive block is a semiconductor
  • the material is formed as a conductor, and the transparent conductive block and the first conductive block constitute two poles of a capacitor.
  • a semiconductor layer is deposited on the buffer layer 14.
  • the semiconductor layer may be a transparent metal oxide such as indium gallium zinc oxide, indium tin zinc oxide, or indium gallium zinc tin oxide.
  • Image processing is performed on the semiconductor layer to form an active layer pattern 15.
  • the active layer pattern 15 includes a first conductive block 151, a second conductive block 152, a third conductive block 154, and a conductive channel 153 connecting the second conductive block 152 and the third conductive block 154.
  • the active layer pattern 15 is subjected to a conductive treatment to make the first conductive block 151, the second conductive block 152, and the third conductive block 154 conductive, and reduce the first conductive block 151, the second conductive block 152, and the first conductive block 151, the second conductive block 152, and the third conductive block 154.
  • the resistance of the three conductive blocks 154 further improves its conductivity.
  • the conductive first conductive block 151 serves as one pole of the capacitor 20, which effectively improves the performance of the capacitor 20.
  • the conductive channel 153 is not conductive, maintaining the semiconductor characteristics.
  • first conductive block 151, the second conductive block 152, and the third conductive block 154 can be ion-doped by ion implantation to realize their conductorization.
  • the implanted ions may be P-type dopants or N-type dopants, which are not limited in this application.
  • the embodiment of the present application provides a method for manufacturing the display panel 100.
  • the active layer pattern 15 is conductively processed to form a conductive first conductive block.
  • the block 151 serves as the other pole of the capacitor 20. Since the transparent conductive block 13 and the semiconductor material forming the first conductive block 151 are both transparent materials, the embodiment of the present application can effectively increase the light-transmitting area of the display panel 100 and improve its transparency.
  • the manufacturing method of the display panel 100 further includes but is not limited to the following steps:
  • an insulating layer is deposited on the buffer layer 14 and the active layer pattern 15, a second metal layer is deposited on the insulating layer, and the second metal layer is patterned to form the gate pattern 17. After that, using the gate pattern 17 as a mask, the insulating layer is etched using a self-aligned process to form the insulating layer pattern 16.
  • the process of conducting the conductive treatment on the active layer pattern 15 in step 104 can be omitted.
  • the gate pattern 17 and the insulating layer pattern 16 are formed, the gate pattern 17 and the insulating layer
  • the layer pattern 16 is a mask, and the portion of the active layer pattern 15 that is not covered by the insulating layer pattern 16 and the gate pattern 17 is conductiveized by a plasma injection process to form a conductive first conductive block 151 and a second conductive block 151.
  • the block 152 and the third conductive block 154 and the conductive channel 153 that is not conductive.
  • the interlayer dielectric layer 18 is deposited on the buffer layer 14, the active layer pattern 15, the insulating layer pattern 16, and the gate pattern 17, and the interlayer dielectric layer 18 is processed by the yellow photolithography process to form the first Via 18a and second via 18b.
  • the first via 18 a is provided corresponding to the second conductive block 152 and exposes a side of the second conductive block 152 away from the substrate 11.
  • the second via 18 b is provided corresponding to the third conductive block 154 and exposes a side of the third conductive block 154 away from the substrate 11.
  • a source pattern and a drain pattern are formed on the interlayer dielectric layer, the source pattern is connected to the second conductive block through the first via hole, and the drain pattern passes through the second conductive block.
  • the via hole is connected to the third conductive block.
  • a third metal layer is deposited on the interlayer dielectric layer 18, and the third metal layer is patterned to form the source pattern 191 and the drain pattern 192.
  • the source pattern 191 is connected to the second conductive block 152 through the first via 18a
  • the drain pattern 192 is connected to the third conductive block 154 through the second via 18b. Since the second conductive block 152 and the third conductive block 154 are already conductive, the resistance value at the contact point between the source pattern 191 and the second conductive block 152, and the drain pattern 192 and the third conductive block 154 is effectively reduced, thereby increasing The connectivity between the source pattern 191, the drain pattern 192, and the conductive channel 153 is improved.
  • the interlayer dielectric layer 18 may be processed by a yellow photolithography process to form the first via 18a, the second via 18b, and the third via. 18c.
  • the third via 18c penetrates the interlayer dielectric layer 18 and extends to the buffer layer 14, and at the same time exposes the side of the light-shielding metal block 12 away from the substrate 11.
  • the source pattern 191 is connected to the light-shielding metal block 12 through the third via 18c.
  • the light-shielding metal block 12 not only has a light-shielding effect, but also serves as a part of the source pattern 191 to enhance the conductivity of the source pattern 191.
  • a passivation layer 21 and a flat layer 22 are sequentially deposited on the interlayer dielectric layer 18, the source pattern 191 and the drain pattern 192, and the flat layer 22 is processed by a yellow light process to form the fourth via 22a.
  • the fourth via hole 22 a penetrates the planar layer 22 and extends to the passivation layer 21, and at the same time exposes a side of the source pattern 191 away from the substrate 11.
  • the passivation layer 21 and the flat layer 22 can be formed by an evaporation process, a chemical vapor deposition process, a coating process, a sol-gel process or other processes.
  • a pixel electrode layer is deposited on the flat layer 21, and the pixel electrode layer is patterned to form a pixel electrode pattern 23, which is connected to the source pattern 191 through the fourth via 22a.
  • the pixel definition layer 24 is deposited on the flat layer 21 and the pixel electrode pattern 223, and the pixel definition layer 24 is etched to form a fifth via 24a. Wherein, the fifth via hole 24a exposes a side of the pixel electrode pattern 23 away from the substrate 11.
  • the light-emitting layer 25 may be formed in the fifth via hole 24a through an inkjet printing process. Then, a cathode layer 26 is deposited on the light-emitting layer 25 and the pixel definition layer 24. The side of the light emitting layer 25 close to the substrate 11 is connected to the pixel electrode pattern 23, and the side of the light emitting layer 25 away from the substrate 11 is connected to the cathode layer.
  • the embodiment of the present application provides a method for manufacturing the display panel 100.
  • the active layer pattern 15 is conductively processed to form a conductive first conductive block.
  • the block 151 serves as the other pole of the capacitor 20. Since the transparent conductive block 13 and the semiconductor material forming the first conductive block 151 are both transparent materials, the embodiment of the present application can effectively increase the light-transmitting area of the display panel 100 and improve its transparency.

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Abstract

本申请公开了一种显示面板及其制作方法，该显示面板包括：基板；设置在基板上的遮光金属块和透明导电块；设置在基板、遮光金属块和透明导电块上的缓冲层；设置在缓冲层上的有源层图案，其包括一第一导电块，第一导电块与透明导电块相对设置，第一导电块为半导体材料导体化形成，透明导电块和第一导电块构成电容的两极。

Description

显示面板及其制作方法 技术领域
本申请涉及显示技术领域，具体涉及一种显示面板及其制作方法。
 背景技术
显示面板的透过率对其整体显示性能起着极为重要的作用，透过率越高，显示面板的可显示亮度越高、透明度越好。显示面板的结构中通常包括薄膜晶体管(Thin Film Transistor，TFT)和电容，在现有技术中，通常采用金属层和离子掺杂的半导体层形成电容的两极，但是由于金属层不透光，进而减少了显示面板的透光区域，使显示面板的透明度不高。
 技术问题
本申请提供一种显示面板，利用导体化的部分有源层图案和设置在基板上的透明导电块作为电容的两极，由于透明导电块和形成有源层图案的半导体材料均为透明材料，因此，可以增加显示面板的透光区域，提高显示面板的透明度。
 技术解决方案
本申请实施例提供一种显示面板及其制作方法，以解决显示面板的透光区域较少，透明度不高的技术问题。
本申请提供一种显示面板，包括：
基板；
设置在所述基板上的遮光金属块和透明导电块；
设置在所述基板、所述遮光金属块和所述透明导电块上的缓冲层；
设置在所述缓冲层上的有源层图案，所述有源层图案包括一第一导电块，所述第一导电块与所述透明导电块相对设置，所述第一导电块为半导体材料导体化形成，所述透明导电块和所述第一导电块构成电容的两极。
在本申请提供的显示面板中，所述透明导电块的材料是氧化铟锡、氧化铝锌或氧化铟锌。
在本申请提供的显示面板中，所述半导体材料是氧化铟镓锌、氧化铟锡锌或氧化铟镓锌锡等透明金属氧化物半导体。
在本申请提供的显示面板中，所述有源层图案还包括第二导电块、第三导电块以及连接所述第二导电块和所述第三导电块的导电沟道，所述导电沟道为半导体材料，所述第二导电块和所述第三导电块均为半导体材料导体化形成。
在本申请提供的显示面板中，所述导电沟道设置在所述遮光金属块正上方。
在本申请提供的显示面板中，所述显示面板还包括：
层叠设置在所述有源层图案上的绝缘层图案和栅极图案；
设置在所述缓冲层、所述有源层图案、所述绝缘层图案和所述栅极图案上的层间介质层，所述层间介质层具有第一过孔和第二过孔；
设置在所述层间介质层上的源极图案和漏极图案，所述源极图案通过所述第一过孔和所述第二导电块连接，所述漏极图案通过所述第二过孔和所述第三导电块连接。
在本申请提供的显示面板中，所述层间介质层还具有第三过孔，所述第三过孔贯穿所述层间介质层并延伸至所述遮光金属块；
其中，所述源极图案通过所述第三过孔与所述遮光金属块连接。
在本申请提供的显示面板中，所述有源层图案的厚度为100埃-1000埃。
在本申请提供的显示面板中，所述透明导电块的厚度为200埃-2000埃。
本申请还提供一种显示面板，其包括：
基板；
设置在所述基板上的遮光金属块和透明导电块；
设置在所述基板、所述遮光金属块和所述透明导电块上的缓冲层；
设置在所述缓冲层上的有源层图案，所述有源层图案包括一第一导电块，所述第一导电块与所述透明导电块相对设置，所述第一导电块为半导体材料导体化形成，所述透明导电块和所述第一导电块构成电容的两极；其中，
所述透明导电块的材料是氧化铟锡、氧化铝锌或氧化铟锌，所述半导体材料是氧化铟镓锌、氧化铟锡锌或氧化铟镓锌锡等透明金属氧化物半导体。
在本申请提供的显示面板中，所述有源层图案还包括第二导电块、第三导电块以及连接所述第二导电块和所述第三导电块的导电沟道，所述导电沟道为半导体材料，所述第二导电块和所述第三导电块均为半导体材料导体化形成。
在本申请提供的显示面板中，所述导电沟道设置在所述遮光金属块正上方。
在本申请提供的显示面板中，所述显示面板还包括：
层叠设置在所述有源层图案上的绝缘层图案和栅极图案；
设置在所述缓冲层、所述有源层图案、所述绝缘层图案和所述栅极图案上的层间介质层，所述层间介质层具有第一过孔和第二过孔；
设置在所述层间介质层上的源极图案和漏极图案，所述源极图案通过所述第一过孔和所述第二导电块连接，所述漏极图案通过所述第二过孔和所述第三导电块连接。
在本申请提供的显示面板中，所述层间介质层还具有第三过孔，所述第三过孔贯穿所述层间介质层并延伸至所述遮光金属块；
其中，所述源极图案通过所述第三过孔与所述遮光金属块连接。
在本申请提供的显示面板中，所述有源层图案的厚度为100埃-1000埃。
在本申请提供的显示面板中，所述透明导电块的厚度为200埃-2000埃。
相应的，本申请还提供一种显示面板的制作方法，包括：
提供一基板；
在所述基板上形成遮光金属块和透明导电块；
在所述基板、所述遮光金属块和所述透明导电块上形成缓冲层；
在所述缓冲层上形成有源层图案，所述有源层图案包括一第一导电块，所述第一导电块与所述透明导电块相对设置，所述第一导电块为半导体材料导体化形成，所述透明导电块和所述第一导电块构成电容的两极。
 有益效果
本申请提供一种显示面板及其制作方法，该显示面板利用导体化的部分有源层图案和设置在基板上的透明导电块作为电容的两极，由于透明导电块和形成有源层图案的半导体材料均为透明材料，有效增加了显示面板的透光区域，进而提高了显示面板的透明度。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请提供的显示面板的第一结构示意图；
图2是本申请提供的显示面板的第二结构示意图；
图3是本申请提供的显示面板的第三结构示意图；
图4是本申请提供的显示面板的制作方法的流程示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“厚度”、“上”、“下”、“垂直”、“一侧”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。术语“第一”和“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”和“第二”等的特征可以明示或者隐含地包括一个或者更多个所述特征，因此不能理解为对本申请的限制。
在本申请的描述中，需要说明的是，“图案化”是指形成具有特定的图形结构的步骤，其可为光刻工艺，光刻工艺包括形成材料层、涂布光刻胶、曝光、显影、刻蚀、光刻胶剥离等步骤中的一步或多步，此为本技术领域的技术人员所理解的工艺制程，在此不再赘述。
请参阅图1，本申请提供一种显示面板100。该显示面板100包括：基板11；设置在基板11上的遮光金属块12和透明导电块13；设置在基板11、遮光金属块12和透明导电块13上的缓冲层14；设置在缓冲层14上的有源层图案15，有源层图案15包括一第一导电块151，第一导电块151与透明导电块13相对设置，第一导电块151为半导体材料导体化形成，透明导电块13和第一导电块151构成电容20的两极。
具体的，基板10可以为玻璃基板、石英基板、树脂基板、PI柔性基板（聚酰亚胺薄膜，Polyimide Film）或其他类型基板，在此不一一赘述。
遮光金属块12的材料为导电性优、遮光性好的金属，一般为钼、铜、铝、钛或复合金属，本申请对此不作限定。在垂直于基板11的方向上，遮光金属块12的厚度为500埃-10000埃。透明导电块13的材料是氧化铟锡（ITO）、氧化铟锌（IZO）、氧化铝锌(AZO)或其它适合的透明导电材料，也可为上述材料的组合。在垂直于基板11的方向上，透明导电块13的厚度为200埃-2000埃。形成有源层图案15的半导体材料可以是氧化铟镓锌（IGZO）、氧化铟锡锌（IZTO）或氧化铟镓锌锡（IGZTO）等透明金属氧化物半导体。在垂直于基板11的方向上，有源层图案15的厚度为100埃-1000埃。缓冲层14可以由单层或多层的二氧化硅、氮化硅或氮氧化硅等形成。在垂直于基板11的方向上，缓冲层14的厚度为1000埃-5000埃。
需要说明的是，以上各膜层的材料及其厚度可根据显示面板100的实际结构要求进行设置，本申请对此不做具体限定。
此外，相对于现有技术中利用金属层和第一导电块151作为电容20的两极，本申请实施例中利用第一导电块151和透明导电块13作为电容20的两极，电容20的两极之间的距离也明显减小，可以理解的是，电容20的两个电极之间的距离越小，单位面积储存电容值越大，电容20的性能越好。进一步的，可以设置缓冲层14的厚度和透光导电块13的厚度相近，也能够有效减少第一导电块151和透明导电块13之间的距离。即，本申请实施例在满足实际生产中显示面板100的结构要求的前提下，可以通过控制透明导电块13和缓冲层14的厚度控制电容20的两个电极之间的距离，进而提高电容20的工作性能。
本申请实施例提供了一种显示面板100，该显示面板100利用设置于基板11上的透明导电块13和有源层图案15包括的导体化的第一导电块151作为电容20的两极，由于透明导电块13和形成第一导电块151的半导体材料均为透明材料，因此本申请实施例能够有效增加显示面板100的透光区域，提高其透明度。
可以理解的是，在本申请实施例中，有源层图案15还包括第二导电块152、第三导电块154以及连接第二导电块152和第三导电块154的导电沟道153。其中，导电沟道153为半导体材料。第二导电块152和第三导电块154均为半导体材料导体化形成。
其中，导电沟道153设置在遮光金属块12正上方。可以理解的是，导电沟道153在受到来自基板11一侧的光照射后会使得光生载流子增加，造成薄膜晶体管产生阈值电压漂移、漏电流增加等不良现象。遮光金属块12可以遮挡从基板11远离遮光金属块12的方向射入的光线，进而减弱外部光线对导电沟道153产生的干扰，提升显示面板100中像素驱动电路的稳定性，从而提高显示面板100的工作性能。
在本实施例中，请参阅图2，显示面板100还包括：层叠设置在有源层图案15上的绝缘层图案16和栅极图案17；设置在缓冲层14、有源层图案15、绝缘层图案16和栅极图案17上的层间介质层18，层间介质层18具有第一过孔18a和第二过孔18b；设置在层间介质层18上的源极图案191和漏极图案192，源极图案191通过第一过孔18a和第二导电块152连接，漏极图案192通过第二过孔18b和第三导电块154连接。
其中，绝缘层图案16的材料可以是氧化硅、氮化硅或氧化硅和氮化硅的结合等。绝缘层图案16可以是单层结构，也可以是多层结构。在垂直于基板11的方向上，绝缘层图案16的厚度为1000埃-3000埃。栅极图案17可以是导电性良好的单层金属结构或多层金属叠层结构，该金属可以是钼、铜、铝、钛或复合金属。在垂直于基板11的方向上，栅极图案17的厚度为2000埃-8000埃。层间介质层18的材料可以是氧化硅、氮化硅或氧化硅和氮化硅的结合等。层间介质层18可以是单层结构，也可以是多层结构。在垂直于基板11的方向上，层间介质层18的厚度为2000埃-10000埃。源极图案191和漏极图案192可以是导电性良好的单层金属结构或多层金属叠层结构，该金属可以是钼、铜、铝、钛或复合金属。在垂直于基板11的方向上，栅极图案17的厚度为2000埃-8000埃。
进一步的，本申请实施例中的显示面板100还包括：层叠设置在层间介质层18、源极图案191和漏极图案192上的钝化层21和平坦层22，平坦层22具有第四过孔22a，第四过孔22a贯穿平坦层22，并延伸至钝化层21，同时暴露出源极图案191远离基板11的一侧；设置在平坦层22上的像素电极图案23，像素电极图案23通过第四过孔22a与源极图案191连接；设置在平坦层22和像素电极图案23上的像素定义层24，像素定义层24具有第五过孔24a，第五过孔24a暴露出像素电极图案23远离基板11的一侧；设置在第五过孔24a内的发光层25，发光层25靠近基板11的一侧与像素电极图案23连接。设置在像素定义层24和发光层25上的阴极层26，发光层25远离基板11的一侧与阴极层26连接。
其中，钝化层21的材料可以是氧化硅、氮化硅或氧化硅和氮化硅的结合等。钝化层21可以是单层结构，也可以是多层结构。在垂直于基板11的方向上，钝化层21的厚度为1000埃-5000埃。像素电极图案23的材料可以是氧化铟锡、银和氧化铟锌等金属。发光层25包括能够发射红光、绿光或蓝光的发光材料。
需要说明的是，以上各功能膜层的材料及厚度均可根据显示面板100的实际结构要求进行设置，本申请对此不作限定。此外，源极图案191和漏极图案192对称设置，所以，源极图案191和漏极图案192是可以互换的。像素电极图案23既可以和源极图案191连接，也可以和漏极图案192连接，图3所示的显示面板100的结构不能理解为对本申请的限制。
请参阅图3，在一些实施例中，显示面板100中的层间介质层18还具有第三过孔18c。第三过孔18c贯穿层间介质层18并延伸至缓冲层14，同时暴露出遮光金属块12远离基板11的一侧。其中，源极图案191通过第三过孔18c与遮光金属块12连接。由于遮光金属块12和源极图案191均使用导电性较好的金属形成，所以该设置使得遮光金属块12在具备遮光作用的同时，还可以作为源极图案191的一部分，增强源极图案191的导电性，进而提高显示面板100中薄膜晶体管的工作性能。
请参阅图2和图4，本申请还提供一种显示面板100的制作方法，具体包括以下步骤：
101、提供一基板。
具体的，提供一基板11，并对基板11进行清洗以及预烘烤，以去除基板11表面的油类、油脂等异物微粒。
102、在所述基板上形成遮光金属块和透明导电块。
首先，在基板11上沉积第一金属层，对第一金属层进行图案化处理，以形成遮光金属块12。然后在基板11未被遮光金属块12覆盖的部分沉积透明导电层，对透明导电层进行图案化处理，以形成透明导电块13。
103、在所述基板、所述遮光金属块和所述透明导电块上形成缓冲层。
在基板11、遮光金属块12和透明导电块13上沉积缓冲层。其中，缓冲层14可采用用蒸镀工艺、化学气相沉积工艺、涂覆工艺、溶胶-凝胶工艺或其他工艺形成。
104、在所述缓冲层上形成有源层图案，所述有源层图案包括一第一导电块，所述第一导电块与所述透明导电块相对设置，所述第一导电块为半导体材料导体化形成，所述透明导电块和所述第一导电块构成电容的两极。
在缓冲层14上沉积一半导体层，该半导体层可以是氧化铟镓锌、氧化铟锡锌或氧化铟镓锌锡等透明金属氧化物。对该半导体层进行图像化处理，以形成有源层图案15。有源层图案15包括第一导电块151、第二导电块152、第三导电块154，以及连接第二导电块152和第三导电块154的导电沟道153。
然后，对有源层图案15进行导体化处理，使第一导电块151、第二导电块152、以及第三导电块154导体化，降低第一导电块151、第二导电块152、以及第三导电块154的阻值，进而提高其导电性。导体化的第一导电块151作为电容20的一极，有效提高了电容20的性能。同时导电沟道153未被导体化，保持半导体特性。
其中，可以采用离子注入的方式对第一导电块151、第二导电块152、以及第三导电块154进行离子掺杂，实现其导体化。注入的离子可以是P型掺杂物或者N型掺杂物，本申请对此不作限定。
本申请实施例提供了一种显示面板100的制作方法，通过在基板11上形成透明导电块13作为电容20的一极，对有源层图案15进行导体化处理，形成导体化的第一导电块151作为电容20的另一极，由于透明导电块13和形成第一导电块151的半导体材料均为透明材料，因此本申请实施例能够有效增加显示面板100的透光区域，提高其透明度。
进一步的，请继续参阅图4，显示面板100的制作方法还包括但不限于以下步骤：
105、在所述有源层图案上形成绝缘层图案和栅极图案。
具体的，在缓冲层14和有源层图案15上沉积绝缘层，在绝缘层上沉积第二金属层，并对第二金属层进行图案化处理，以形成栅极图案17。之后，以栅极图案17为掩膜，采用自对准工艺对绝缘层进行刻蚀，以形成绝缘层图案16。
需要说明的是，在一些实施例中，步骤104中对有源层图案15进行导体化处理的过程可以省略，在形成栅极图案17和绝缘层图案16后，可以以栅极图案17和绝缘层图案16为掩膜，采用等离子注入工艺对有源层图案15未被绝缘层图案16和栅极图案17覆盖的部分进行导体化处理，以形成导体化的第一导电块151、第二导电块152和第三导电块154以及未被导体化的导电沟道153。
106、在所述缓冲层、所述有源层图案、所述绝缘层图案和所述栅极图案上沉积层间介质层，并对所述层间介质层进行图案化处理，以在所述层间介质层上形成第一过孔和第二过孔。
具体的，在缓冲层14、有源层图案15、绝缘层图案16和栅极图案17上沉积层间介质层18，利用黄光刻蚀工艺对层间介质层18进行处理，以形成第一过孔18a和第二过孔18b。第一过孔18a对应第二导电块152设置，并暴露出第二导电块152远离基板11的一侧。第二过孔18b对应第三导电块154设置，并暴露出第三导电块154远离基板11的一侧。
107、在所述层间介质层上形成源极图案和漏极图案，所述源极图案通过所述第一过孔和所述第二导电块连接，所述漏极图案通过所述第二过孔和所述第三导电块连接。
具体的，在层间介质层18上沉积第三金属层，对第三金属层进行图案化处理，以形成源极图案191和漏极图案192。源极图案191通过第一过孔18a和第二导电块152连接，漏极图案192通过第二过孔18b和第三导电块154连接。由于第二导电块152和第三导电块154均已导体化，有效降低了源极图案191与第二导电块152、以及漏极图案192与第三导电块154接触处的阻值，进而提高了源极图案191、漏极图案192与导电沟道153之间的连通性。
需要说明的是，在一些实施例中，在步骤107中，可以利用黄光刻蚀工艺对层间介质层18进行处理，以形成第一过孔18a、第二过孔18b和第三过孔18c。第三过孔18c贯穿层间介质层18并延伸至缓冲层14，同时暴露出遮光金属块12远离基板11的一侧。其中，源极图案191通过第三过孔18c与遮光金属块12连接。遮光金属块12在具备遮光作用的同时，还可以作为源极图案191的一部分，增强源极图案191的导电性。
108、在所述层间介质层、所述源极图案和所述漏极图案上依次沉积钝化层和平坦层，并对所述平坦层进行图案化处理，以形成第四过孔，所述第四过孔对应所述源极图案设置。
具体的，在层间介质层18、源极图案191和漏极图案192上依次沉积钝化层21和平坦层22，利用黄光工艺对平坦层22进行处理，以形成第四过孔22a。第四过孔22a贯穿平坦层22，并延伸至钝化层21，同时暴露出源极图案191远离基板11的一侧。其中，钝化层21和平坦层22均可采用蒸镀工艺、化学气相沉积工艺、涂覆工艺、溶胶-凝胶工艺或其他工艺形成
109、在所述平坦层上沉积像素电极层，并对所述像素电极层进行图案化处理，以形成像素电极图案，所述像素电极图案通过所述第四过孔与所述源极图案连接。
具体的，在平坦层21上沉积像素电极层，并对像素电极层进行图案化处理，以形成像素电极图案23，像素电极图案23通过第四过孔22a与源极图案191连接。
110、在所述平坦层和所述像素电极图案上沉积像素定义层，并对所述像素定义层进行图案化处理，以形成第五过孔。
在平坦层21和像素电极图案223上沉积像素定义层24，并对像素定义层24进行刻蚀，以形成第五过孔24a。其中，第五过孔24a暴露出像素电极图案23远离基板11的一侧。
111、在所述第五过孔沉积发光层，并在所述发光层和所述像素定义层上沉积阴极层。
具体的，可以通过喷墨打印工艺在第五过孔24a内形成发光层25。然后在发光层25和像素定义层24上沉积阴极层26。发光层25靠近基板11的一侧与像素电极图案23连接，发光层25远离基板11的一侧与阴极层连接。
本申请实施例提供了一种显示面板100的制作方法，通过在基板11上形成透明导电块13作为电容20的一极，对有源层图案15进行导体化处理，形成导体化的第一导电块151作为电容20的另一极，由于透明导电块13和形成第一导电块151的半导体材料均为透明材料，因此本申请实施例能够有效增加显示面板100的透光区域，提高其透明度。
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (17)

  1. 一种显示面板，其包括：
    基板；
    设置在所述基板上的遮光金属块和透明导电块；
    设置在所述基板、所述遮光金属块和所述透明导电块上的缓冲层；
    设置在所述缓冲层上的有源层图案，所述有源层图案包括一第一导电块，所述第一导电块与所述透明导电块相对设置，所述第一导电块为半导体材料导体化形成，所述透明导电块和所述第一导电块构成电容的两极。
  2. 根据权利要求1所述的显示面板，其中，所述透明导电块的材料是氧化铟锡、氧化铝锌或氧化铟锌。
  3. 根据权利要求1所述的显示面板，其中，所述半导体材料是氧化铟镓锌、氧化铟锡锌或氧化铟镓锌锡等透明金属氧化物半导体。
  4. 根据权利要求1所述的显示面板，其中，所述有源层图案还包括第二导电块、第三导电块以及连接所述第二导电块和所述第三导电块的导电沟道，所述导电沟道为半导体材料，所述第二导电块和所述第三导电块均为半导体材料导体化形成。
  5. 根据权利要求4所述的显示面板，其中，所述导电沟道设置在所述遮光金属块正上方。
  6. 根据权利要求4所述的显示面板，其中，所述显示面板还包括：
    层叠设置在所述有源层图案上的绝缘层图案和栅极图案；
    设置在所述缓冲层、所述有源层图案、所述绝缘层图案和所述栅极图案上的层间介质层，所述层间介质层具有第一过孔和第二过孔；
    设置在所述层间介质层上的源极图案和漏极图案，所述源极图案通过所述第一过孔和所述第二导电块连接，所述漏极图案通过所述第二过孔和所述第三导电块连接。
  7. 根据权利要求6所述的显示面板，其中，所述层间介质层还具有第三过孔，所述第三过孔贯穿所述层间介质层并延伸至所述遮光金属块；
    其中，所述源极图案通过所述第三过孔与所述遮光金属块连接。
  8. 根据权利要求1所述的显示面板，其中，所述有源层图案的厚度为100埃-1000埃。
  9. 根据权利要求1所述的显示面板，其中，所述透明导电块的厚度为200埃-2000埃。
  10. 一种显示面板，其包括：
    基板；
    设置在所述基板上的遮光金属块和透明导电块；
    设置在所述基板、所述遮光金属块和所述透明导电块上的缓冲层；
    设置在所述缓冲层上的有源层图案，所述有源层图案包括一第一导电块，所述第一导电块与所述透明导电块相对设置，所述第一导电块为半导体材料导体化形成，所述透明导电块和所述第一导电块构成电容的两极；其中，
    所述透明导电块的材料是氧化铟锡、氧化铝锌或氧化铟锌，所述半导体材料是氧化铟镓锌、氧化铟锡锌或氧化铟镓锌锡等透明金属氧化物半导体。
  11. 根据权利要求10所述的显示面板，其中，所述有源层图案还包括第二导电块、第三导电块以及连接所述第二导电块和所述第三导电块的导电沟道，所述导电沟道为半导体材料，所述第二导电块和所述第三导电块均为半导体材料导体化形成。
  12. 根据权利要求11所述的显示面板，其中，所述导电沟道设置在所述遮光金属块正上方。
  13. 根据权利要求11所述的显示面板，其中，所述显示面板还包括：
    层叠设置在所述有源层图案上的绝缘层图案和栅极图案；
    设置在所述缓冲层、所述有源层图案、所述绝缘层图案和所述栅极图案上的层间介质层，所述层间介质层具有第一过孔和第二过孔；
    设置在所述层间介质层上的源极图案和漏极图案，所述源极图案通过所述第一过孔和所述第二导电块连接，所述漏极图案通过所述第二过孔和所述第三导电块连接。
  14. 根据权利要求13所述的显示面板，其中，所述层间介质层还具有第三过孔，所述第三过孔贯穿所述层间介质层并延伸至所述遮光金属块；
    其中，所述源极图案通过所述第三过孔与所述遮光金属块连接。
  15. 根据权利要求10所述的显示面板，其中，所述有源层图案的厚度为100埃-1000埃。
  16. 根据权利要求10所述的显示面板，其中，所述透明导电块的厚度为200埃-2000埃。
  17. 一种显示面板的制作方法，其包括：
    提供一基板；
    在所述基板上形成遮光金属块和透明导电块；
    在所述基板、所述遮光金属块和所述透明导电块上形成缓冲层；
    在所述缓冲层上形成有源层图案，所述有源层图案包括一第一导电块，所述第一导电块与所述透明导电块相对设置，所述第一导电块为半导体材料导体化形成，所述透明导电块和所述第一导电块构成电容的两极。
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