WO2020238384A1 - 阵列基板的制作方法、阵列基板、显示面板及显示装置 - Google Patents

阵列基板的制作方法、阵列基板、显示面板及显示装置 Download PDF

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WO2020238384A1
WO2020238384A1 PCT/CN2020/081886 CN2020081886W WO2020238384A1 WO 2020238384 A1 WO2020238384 A1 WO 2020238384A1 CN 2020081886 W CN2020081886 W CN 2020081886W WO 2020238384 A1 WO2020238384 A1 WO 2020238384A1
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Prior art keywords
layer
array substrate
area
pattern
hole
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PCT/CN2020/081886
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English (en)
French (fr)
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刘军
方金钢
闫梁臣
周斌
黄勇潮
苏同上
刘宁
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Publication of WO2020238384A1 publication Critical patent/WO2020238384A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a manufacturing method of an array substrate, an array substrate, a display panel and a display device.
  • TFT Thin Film Transistor
  • AMOLED Active Matrix Organic Light Emitting Diode
  • the embodiment of the present disclosure provides a manufacturing method of an array substrate, including:
  • the pattern of the thin film transistor, the passivation layer, the pattern of the color resist layer, and the pattern of the planarization layer are sequentially formed on the base substrate; wherein the pattern of the thin film transistor and the pattern of the color resist layer are on the base substrate.
  • the orthographic projections on the above do not overlap each other, and the pattern of the planarization layer has a first through hole above the pattern of the thin film transistor;
  • the photoresist layer is patterned to form a photoresist pattern;
  • the photoresist pattern has a via hole located above the drain in the thin film transistor within the range of the first through hole, and
  • the photoresist pattern has the largest thickness in the area above the pattern of the color resist layer;
  • the photoresist pattern as a shield, dry etching the passivation layer exposed by the via, and the passivation layer forms a second via at a position corresponding to the via;
  • a pattern of an anode is formed on the pattern of the planarization layer, and the anode is electrically connected to the drain through the second through hole.
  • the photoresist pattern includes a completely removed area, a first partially reserved area, and a completely reserved area; the completely removed area is The area where the via is located, the fully reserved area is the area where the pattern of the color resist layer is located, and the first partial reserved area is the area in the first through hole excluding the via;
  • the thickness of the photoresist pattern in the first partial reserved area is less than the thickness of the completely reserved area.
  • the photoresist pattern further includes a second partial reserved area, and the second partial reserved area is in addition to the first A through hole and an area other than the pattern of the color resist layer; the thickness of the photoresist pattern in the second partial reserved area is greater than the thickness of the first partial reserved area and less than the thickness of the completely reserved area.
  • patterning the photoresist layer specifically includes:
  • the photoresist layer is patterned by using a halftone mask or a gray tone mask;
  • the halftone mask includes: a completely light-transmitting area corresponding to the completely removed area, and the first part The first partial light-transmitting area corresponding to the reserved area, the second partial light-transmitting area corresponding to the second partial reserved area, the light-shielding area corresponding to the completely reserved area; the light transmission of the first partial light-transmitting area is The light transmission of the completely light-transmitting area is 50%, and the light transmission of the second partial light-transmitting area is 10%-20% of the light transmission of the completely light-transmitting area.
  • the thickness of the photoresist pattern in the first partial reserved area is 1.5 ⁇ m-1.8 ⁇ m
  • the photolithography The thickness of the photoresist pattern in the completely reserved area is 2.1 ⁇ m
  • the thickness of the photoresist pattern in the second partial reserved area is 1.7 ⁇ m-1.9 ⁇ m.
  • performing dry etching on the passivation layer exposed by the via hole specifically includes:
  • the passivation layer is subjected to dry etching treatment using a combined gas of O 2 and CF 4 with a varying ratio.
  • the combined gas of O 2 and CF 4 with a varying ratio includes: a combined gas with O 2 content greater than CF 4 , and O 2 A combined gas with a content less than CF 4 .
  • the passivation layer is subjected to dry etching treatment by at least two dry etching processes, wherein each dry etching process etching the ratio of O 2 and CF 4 are fixed, two adjacent dry etching of O 2 and CF 4 ratio is varied.
  • the present disclosure in the embodiment of the array substrate manufacturing method provided in the embodiment, before the dry etching in a ratio of O 2 ratio of greater than 2 after a dry etching O.
  • the passivation layer is dry-etched by two dry etching; the first dry-etching
  • the content of O 2 in the etching is 55%-65%, and the content of CF 4 is 35%-45%; the content of O 2 in the second dry etching is 15%-35% and the content of CF 4 is 65% ⁇ 85%.
  • the first dry etching removes half of the thickness of the passivation layer, and the second dry etching The other half of the thickness of the passivation layer is removed by etching.
  • the passivation layer is dry-etched by one dry etching process.
  • the proportion of O 2 gradually decreases.
  • an embodiment of the present disclosure also provides an array substrate, which is manufactured by using any of the above-mentioned manufacturing methods provided in the embodiments of the present disclosure, and the array substrate includes:
  • a thin film transistor located on the base substrate including an active layer, a gate insulating layer, a gate, a source and a drain;
  • a planarization layer located on the color resist layer and having a first through hole covering the thin film transistor
  • the anode is located on the planarization layer and extends to the bottom of the first through hole, and is electrically connected to the drain through the second through hole.
  • the second through hole has at least two slope angles, and is directed toward the second through hole along the base substrate, The degree of the slope angle increases.
  • the thin film transistor is a top-gate thin film transistor.
  • an embodiment of the present disclosure also provides a display panel, including the above-mentioned array substrate provided by the embodiment of the present disclosure.
  • an embodiment of the present disclosure also provides a display device, including the above-mentioned display panel provided by the embodiment of the present disclosure.
  • FIG. 1 is a flowchart of a manufacturing method of an array substrate provided by an embodiment of the disclosure
  • FIG. 2 is a schematic structural diagram of an array substrate provided by an embodiment of the disclosure.
  • 3A to 3E are respectively schematic cross-sectional structural diagrams after performing various steps in the manufacturing method of the array substrate provided by the embodiments of the disclosure.
  • large-size OLEDs have become the mainstream of development due to their high contrast, self-luminescence and becoming a new growth hotspot for TV.
  • TFTs with top-gate structures in large-size OLEDs have higher on-state currents and higher currents than TFTs with bottom-gate structures.
  • the aperture ratio and better TFT stability have attracted attention.
  • large-size OLED adopts WRGB color film technology, that is, BGR is built on the array passivation layer (Array PVX).
  • the current thickness of BGR is relatively thick (generally ⁇ 3.0 ⁇ m ), because the thickness of the BGR is relatively thick, in order to ensure the planarization effect, the corresponding organic planarization layer (Resin) is also thick (generally ⁇ 3.3 ⁇ m).
  • a Resin-free via hole will be formed in the TFT area during the planarization layer process.
  • the subsequent passivation layer via hole mask source drain metal and ITO connection via hole
  • the inherent fluidity will make the photoresist in the Resin through hole thicker than the pixel area, and the photoresist in the pixel area is thinner.
  • the dry etching profile will be affected, the etching rate will slow down, and the passivation layer will be dry Due to the thin photoresist in the pixel area during the method of etching, dry etching damage (DE damage) may occur to the planarization layer of the pixel area, resulting in abnormal evaporation of the subsequent organic light-emitting layer (EL) and reduced organic film transmittance.
  • DE damage dry etching damage
  • embodiments of the present disclosure provide a manufacturing method of an array substrate, an array substrate, a display panel, and a display device.
  • a manufacturing method of an array substrate, an array substrate, a display panel, and a display device In order to make the objectives, technical solutions and advantages of the present disclosure clearer, specific implementations of the array substrate manufacturing method, array substrate, display panel, and display device provided by the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.
  • each layer of the film in the drawings do not reflect the true ratio of the array substrate, and the purpose is only to illustrate the present disclosure.
  • An embodiment of the present disclosure provides a manufacturing method of an array substrate, as shown in FIG. 1, including:
  • the pattern of the thin film transistor, the passivation layer, the pattern of the color resist layer, and the pattern of the planarization layer are sequentially formed on the base substrate; wherein the pattern of the thin film transistor and the pattern of the color resist layer are projected on the base substrate. Do not overlap each other, and the pattern of the planarization layer has a first through hole above the pattern of the thin film transistor;
  • the photoresist pattern has a via hole located above the drain in the thin film transistor within the range of the first through hole, and the photoresist pattern is on the color resist layer
  • the area above the pattern has the largest thickness; for example, the photoresist pattern may include a completely removed area, a first partial reserved area, and a completely reserved area; wherein the completely removed area is the area where the via is located, and the first partial reserved area is the first
  • the area covered by a through hole that is, the area where the first through hole is located except for the via hole, and the completely reserved area is the area where the pattern of the color resist layer is located;
  • the manufacturing method of the above-mentioned array substrate provided by the embodiment of the present disclosure, in the process of patterning the photoresist layer formed above the pattern of the planarization layer, when the via hole of the completely removed area is formed, Make the photoresist pattern have the largest thickness in the area above the pattern of the color resist layer, so that when the passivation layer is subsequently dry etched, it can prevent dry etching damage to the planarization layer above the color resist layer. It is possible that the subsequent evaporation of the organic light-emitting layer is abnormal and the transmittance of the organic film is reduced.
  • the photoresist pattern may include a completely removed area, a first partially reserved area, and a completely reserved area; wherein, the completely removed area is excessive
  • a better dry engraving profile is formed when layering.
  • the photoresist pattern may further include a second Part of the reserved area, the second part of the reserved area is the area other than the pattern of the first through hole and the color resist layer, that is, the second part of the reserved area does not overlap with the orthographic projection of the thin film transistor and the color resist on the base substrate, and
  • the thickness of the photoresist in the second partial reserved area is greater than the thickness of the photoresist in the first partial reserved area and smaller than the thickness of the fully reserved area.
  • patterning the photoresist layer may specifically include:
  • a halftone mask or a gray tone mask is used to pattern the photoresist layer;
  • the halftone mask may include: a completely transparent area corresponding to the completely removed area, and a first part of the transparent area corresponding to the first partial reserved area.
  • the light transmission of the first part of the light transmission area is 50% of the light transmission of the completely light transmission area
  • the light transmission of the two-part light-transmitting area is 10%-20% of the light transmission of the complete light-transmitting area.
  • the thickness of the generally coated photoresist layer in the related art is 1.8 ⁇ m, and the photoresist coated in the present disclosure
  • the thickness of the layer can be 2.1 ⁇ m. Due to the fluidity of the photoresist, the thickness of the photoresist in the first through hole of the planarization layer can be 3 ⁇ m-3.6 ⁇ m, so after the first part of the light-transmitting area is irradiated
  • the thickness of the photoresist pattern in the first part of the reserved area can be 1.5 ⁇ m-1.8 ⁇ m, and the thickness of the photoresist pattern in the completely reserved area is 2.1 ⁇ m.
  • the photoresist pattern The thickness of the reserved area in the second part may be 1.7 ⁇ m-1.9 ⁇ m.
  • the halftone mask or gray tone mask used in the present disclosure makes the photoresist in the first through hole of the planarization layer meet the etching requirements, and the thickness will not be affected by the fluidity of the photoresist. It is thicker, and the corresponding photoresist above the color resist layer is thicker, which can withstand subsequent passivation layer etching, and will not cause dry etching damage to the planarization layer, which improves the reliability of the panel; and the second part is retained The thickness of the photoresist pattern in the region is reduced to 10%-20% of the original photoresist, so that the subsequent remaining photoresist pattern is easily peeled off.
  • the passivation layer when the passivation layer is dry-etched, when the O 2 content is high, the etching rate of the photoresist pattern is faster, but the slope angle of the obtained second through hole is smaller; when CF 4 When the content is high, the passivation layer is etched faster, but the slope angle of the obtained second through hole is larger.
  • generally only one etching is used, and the content of O 2 is greater than the ratio of CF 4 , so that the etching rate of the photoresist pattern is faster, so after the passivation layer is etched, the large amount will be etched away.
  • Part of the photoresist pattern keeps the photoresist pattern above the color resist layer thinner, which is likely to cause dry etching damage to the planarization layer, which affects the subsequent evaporation of the organic functional layer.
  • the dry etching treatment on the passivation layer exposed by the via hole may specifically include:
  • the combined gas of O 2 and CF 4 is used to dry etch the passivation layer, and the ratio of O 2 to CF 4 changes.
  • the ratio of O 2 and CF 4 in the etching process By changing the ratio of O 2 and CF 4 in the etching process, the etching of the photoresist pattern can be reduced, so that the photoresist pattern above the color resist layer remains thick without dry etching damage to the planarization layer , So as not to affect the subsequent evaporation of the organic functional layer.
  • the combined gas of O 2 and CF 4 with a varying ratio may include: a combined gas with an O 2 content greater than CF 4 and a combined gas with an O 2 content less than CF 4 .
  • At least two dry etching may be used to dry the passivation layer, wherein each dry etching the proportion of O 2 in erosion and CF 4 is fixed, two adjacent dry etching of O 2 and CF 4 ratio is varied.
  • At least two dry etching are used to dry the passivation layer, wherein the previous dry etching the proportion of O 2 is greater than the ratio of etching in a dry O 2.
  • the content of O 2 in the first dry etching can be 55%-65%, and the content of CF 4 is 35%. ⁇ 45%; the content of O 2 in the second dry etching can be 15% to 35%, and the content of CF 4 is 65% to 85%.
  • the first dry etching is performed with CF 4 (content 35%-45%) + O 2 (content 55%-65%), and high source power and high bias power are used.
  • Etching about 50% of the passivation layer because the O 2 content is high and the thickness of the photoresist in the first through hole of the planarization layer is not thick, it meets the etching requirements, so that the passivation layer can be etched better
  • the etching rate of the photoresist is faster.
  • only 50% of the thickness of the passivation layer is etched, only about 0.4 ⁇ m ⁇ 0.5 ⁇ m of light is consumed.
  • the resist pattern keeps the photoresist pattern thicker above the color resist layer and will not cause dry etching damage to the planarization layer, thereby not affecting the subsequent evaporation of the organic functional layer.
  • the second dry etching is carried out with CF 4 (content of 65%-85%) + O 2 (content of 15%-35%), and high source power and high bias power are used to etch the remaining
  • the passivation layer with a thickness of 50%, due to the high content of CF 4 will etch the passivation layer faster, and the angle of the dry etching of the passivation layer will be steep (60° ⁇ 70°), but due to the first etching Half of the passivation layer has been etched, so the dry etching angle of the second half of the passivation layer has no effect on the subsequent anode deposition, and because the content of CF 4 is higher, the content of O 2 is less, which can avoid the dry etching process.
  • the further consumption of O 2 prevents the dry etching process from causing dry etching damage to the planarization layer.
  • only one dry etching may be used to dry the passivation layer.
  • the proportion of O 2 gradually decreases.
  • an embodiment of the present disclosure also provides an array substrate, as shown in FIG. 2, which is manufactured by using the above-mentioned manufacturing method provided by the embodiment of the present disclosure.
  • the array substrate includes: a base substrate 1, a thin film transistor 2, a passivation layer 3, a color resist layer 4 and a planarization layer 5 stacked on the base substrate 1 in sequence, and an anode 6.
  • the thin film transistor 2 specifically includes: an active layer 21, a gate insulating layer 22, a gate 23, a source 24 and a drain 25.
  • the planarization layer 5 has a first through hole P1 covering the thin film transistor 2
  • the passivation layer 3 has a drain 21 located in the thin film transistor 2.
  • the anode 6 extends to the bottom of the first through hole P1, and is electrically connected to the drain 21 of the thin film transistor 2 through the second through hole P2 of the passivation layer 3.
  • the thin film transistor 2 may be a top-gate thin film transistor.
  • the array substrate may further include a buffer layer 8 between the thin film transistor 2 and the base substrate 1, a light-shielding metal layer 7 between the buffer layer 8 and the base substrate 1, and the light-shielding metal layer 7 for shielding the active layer 4.
  • an interlayer insulating layer 9 between the source and drain electrodes (24 and 25) and the gate 23.
  • the embodiment takes twice dry etching of the passivation layer as an example, the slope angle has two ⁇ 1 and ⁇ 2), along the base substrate 1 pointing away from the base substrate 1, the degree of the slope angle gradually decreases, and the slope angle is It refers to the angle between the dry-etched slope of the passivation layer 3 and the base substrate 1, that is, the degree of ⁇ 1 is greater than the degree of ⁇ 2.
  • the array substrate may be applied to an organic light emitting diode (OLED) display panel.
  • the array substrate may also include a cathode and an organic functional layer located between the anode and the cathode.
  • a light-shielding metal film can be deposited on the base substrate 1 by chemical vapor deposition.
  • the light-shielding metal film can be a metal such as molybdenum or molybdenum-niobium alloy, and the thickness can be 0.10 ⁇ m ⁇ 0.15 ⁇ m, followed by exposure and development And after wet etching, a light-shielding metal layer 7 is formed. Specifically, the wet etching of the light-shielding metal thin film can be etched with mixed acid.
  • a buffer layer 8 can be deposited on the base substrate 1 on which the light-shielding metal layer 2 is formed by using a chemical vapor deposition method or a magnetron sputtering method.
  • the material of the buffer layer 8 may be silicon oxide, and the thickness may be 0.3 ⁇ m to 0.5 ⁇ m.
  • a metal oxide semiconductor film can be deposited on the buffer layer 8 by a chemical vapor deposition method, and then a patterning process is performed on the metal oxide semiconductor film to form the active layer 21, that is, after the photoresist is coated, a common mask is used.
  • the film plate exposes, develops, and etches the photoresist to form the active layer 21.
  • the material of the active layer 4 may be indium tin oxide (IGZO), and the thickness may be 0.05 ⁇ m to 0.1 ⁇ m.
  • a gate insulating film can be deposited on the base substrate 1 on which the active layer 21 is formed by a chemical vapor deposition method or a magnetron sputtering method.
  • the gate insulating film may be made of silicon oxide with a thickness of 0.1 ⁇ m to 0.2 ⁇ m.
  • a layer of gate metal film can be deposited on the gate insulating film by magnetron sputtering.
  • the gate metal film may be copper metal.
  • the thickness of the gate metal film may be 0.4 ⁇ m to 0.5 ⁇ m.
  • the gate 23 is formed by a patterning process, specifically, a photoresist is coated on the gate metal film, and then the photoresist is exposed by a mask, and the gate 23 is formed after development and etching. This etching process It can be a copper wet etching process, and a hydrogen peroxide solution can be used for wet etching.
  • the gate mask (ie, the photoresist pattern) above the gate 23 is retained to perform a dry etching process on the gate insulating film to form the gate insulating layer 22.
  • a mixed gas of CF 4 with a flow rate of 2000 sccm to 2500 sccm and O 2 with a flow rate of 1000 sccm to 1500 sccm can be used to dry etch the gate insulating film without photoresist protection.
  • the gate mask that is, the photoresist pattern
  • the active layer 21 exposed after the gate insulating layer is dry-etched ⁇ . Since the active layer 21 includes a channel region covered by the gate insulating layer 22 and a source contact region and a drain contact region located on both sides of the channel region, the source contact region and the drain contact region are electrically conductive.
  • the chemical treatment can reduce the contact resistance of the source 24, the drain 25 and the active layer 21 to be formed, and improve the conductivity. Specifically, ammonia gas (NH 3 ) or helium gas (He) can be used for the conduction treatment. After that, the photoresist is wet stripped.
  • a layer of interlayer insulating layer 9 is deposited.
  • the material of the interlayer insulating layer 9 can be silicon oxide, and the thickness can be 0.45 ⁇ m to 0.6 ⁇ m.
  • a layer of photoresist is coated, and then the photoresist is applied by a mask. Exposure is carried out, and after development and etching, contact holes corresponding to the source and drain electrodes to be formed are formed to electrically connect the source and drain electrodes with the active layer 21, and the contact holes are dry-etched and then subjected to wet stripping.
  • the source/drain metal film can be a metal such as copper and aluminum with a thickness of 0.5 ⁇ m to 0.7 ⁇ m.
  • the source electrode 24 and the drain electrode 25 are formed by photolithography and wet etching.
  • a passivation layer 3 is deposited on the base substrate 1 where the source electrode 24 and the drain electrode 25 are formed.
  • the material of the passivation layer 3 can be a silicon oxide-top/silicon nitride/silicon oxide-bottom composite layer, Considering the influence on characteristics, the thickness of the silicon oxide-top can be 0.1 ⁇ m-0.2 ⁇ m, the thickness of the silicon nitride can be 0.03 ⁇ m-0.05 ⁇ m, and the thickness of the silicon oxide-bottom can be 0.1 ⁇ m-0.2 ⁇ m, as shown in FIG. 3A.
  • the color resist layer 4 is formed on the passivation layer 3. Specifically, the Blue, Green, and Red color resist steps can be carried out successively; then a planarization layer 5 is formed on the base substrate 1 on which the color resist layer 4 is formed, and The patterning process forms a first through hole P1 in the corresponding planarization layer 5 above the thin film transistor 2. Specifically, a photoresist is coated on the planarization layer 5, and then the photoresist is exposed by a mask, and the first through hole P1 is formed after development and etching, and then the photoresist is wet stripped. As shown in Figure 3B.
  • a photoresist layer is formed on the planarization layer with the first through hole P1, and then the photoresist layer is exposed, developed and etched using a halftone mask to form a photoresist pattern, as shown in Figure 3C
  • the photoresist pattern includes a completely removed area 01, a first partially reserved area 02, a second partially reserved area 03 and a completely reserved area 04; wherein the completely removed area 01 is within the range of the first through hole P1 and is located Above the drain 25, the first partial reserved area 02 is covered by the first through hole P1, and the completely reserved area 04 covers the area where the color resist layer 4 is located.
  • the photoresist layer is a positive photoresist, and its thickness can be 2.1 ⁇ m. Due to the fluidity of the photoresist, the thickness of the photoresist in the first through hole P1 of the planarization layer 5 is 3 The thickness of the photoresist is variable, so the thickness of the photoresist in the first part of the reserved area 02 is 1.5. The thickness of the photoresist in the reserved area is 2.1. The thickness of the photoresist pattern in the completely reserved area 04 is 2.1. The thickness of the photoresist pattern is 1.7 domains.
  • the photoresist in the first through hole P1 of the planarization layer 5 meets the etching requirements, and the thickness is not thick due to the fluidity of the photoresist, and the color resistance
  • the thickness of the corresponding photoresist above the layer 4 is relatively thick, which can withstand the subsequent etching of the passivation layer 3, will not cause dry etching damage to the planarization layer 5, and improve the reliability of the panel; and the second part of the area 03
  • the thickness of the photoresist pattern is reduced to 10%-20% of the original photoresist, so that it is easy to peel off when the photoresist is subsequently peeled off.
  • the second dry etching is carried out with CF 4 (content of 65%-85%) + O 2 (content of 15%-35%), and high source power and high bias power are used to etch the remaining
  • the passivation layer 3 with a thickness of 50%, due to the higher CF 4 content, will etch the passivation layer 3 faster, and the angle of dry etching on the passivation layer 3 will be steeper (60°-70°).
  • the passivation layer 3 forms a second through hole P2 at a position corresponding to the completely removed area 01, and then strips the photoresist pattern, as shown in FIG. 3D.
  • An anode 6 is formed on the planarization layer 5, and the anode 6 is electrically connected to the drain 25 through the second through hole P2, as shown in FIG. 3E.
  • the array substrate provided by the embodiment of the present disclosure can be manufactured.
  • embodiments of the present disclosure also provide a display panel, including the above-mentioned array substrate provided by the embodiments of the present disclosure.
  • the implementation of the display panel can be referred to the embodiment of the above-mentioned array substrate, and the repetition will not be repeated.
  • an embodiment of the present disclosure also provides a display device, including the above-mentioned display panel provided by the embodiment of the present disclosure.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.
  • a display device reference may be made to the above-mentioned embodiment of the array substrate, and the repetition is not repeated here.
  • the manufacturing method of the array substrate, the display panel, and the display device provided by the embodiments of the present disclosure by patterning the photoresist layer formed on the planarization layer, make a portion of the first through hole above the drain of the thin film transistor There is no photoresist layer, part of the photoresist layer remains in other parts of the first through hole, and the corresponding photoresist layer above the color resist layer is completely retained; in this way, when the passivation layer is subsequently dry etched, the Only part of the photoresist layer remains in the other part of a through hole, which is thinner than the photoresist layer completely reserved in the other part of the first through hole in the related art.
  • the present disclosure is beneficial to form a better passivation layer when dry etching Dry etching Profile;
  • the thickness of the photoresist layer above the color resist layer in the present disclosure is relatively thicker than the thickness of the photoresist layer above the color resist layer in the related art.
  • the present disclosure can prevent The planarization layer above the color resist is damaged by dry etching, so as to avoid the possibility of abnormal evaporation of the subsequent organic light-emitting layer and decrease in the transmittance of the organic film.

Abstract

一种阵列基板的制作方法、阵列基板、显示面板及显示装置，所述制作方法包括：对形成在平坦化层(5)上的光刻胶层进行图案化处理，使薄膜晶体管(2)的漏极(25)上方的部分第一通孔(P1)内没有光刻胶层、第一通孔(P1)的其它部分保留部分光刻胶层、色阻层(4)上方的光刻胶层完全保留；在后续对钝化层(3)进行干刻处理时，由于第一通孔(P1)的其它部分仅保留部分光刻胶层，有利于在干刻钝化层(3)时形成较好的干刻角度；另外，色阻层(4)上方的光刻胶层厚度较厚，在对钝化层(3)进行干刻时，可以防止对色阻层(4)上方的平坦化层(5)产生干刻损伤，避免使得后续有机发光层(EL)蒸镀异常以及有机膜透过率降低的可能。

Description

阵列基板的制作方法、阵列基板、显示面板及显示装置
相关申请的交叉引用
本公开要求在2019年05月30日提交中国专利局、申请号为201910464234.4、申请名称为“阵列基板的制作方法、阵列基板、显示面板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，特别涉及一种阵列基板的制作方法、阵列基板、显示面板及显示装置。
背景技术
薄膜晶体管(Thin Film Transistor，TFT)是液晶显示器和有源矩阵有机发光二极管(Active Matrix Organic Light Emitting Diode，AMOLED)的主要驱动元件。
发明内容
本公开实施例提供了一种阵列基板的制作方法，包括：
在衬底基板上依次形成薄膜晶体管的图形、钝化层、色阻层的图形和平坦化层的图形；其中，所述薄膜晶体管的图形和所述色阻层的图形在所述衬底基板上的正投影互不重叠，所述平坦化层的图形在所述薄膜晶体管的图形的上方具有第一通孔；
在平坦化层的图形上形成光刻胶层；
对所述光刻胶层进行图案化处理，形成光刻胶图案；所述光刻胶图案在所述第一通孔的范围内具有位于所述薄膜晶体管中漏极上方的过孔，所述光刻胶图案在所述色阻层的图形上方的区域具有的厚度最大；
以所述光刻胶图案作为遮挡，对所述过孔露出的所述钝化层进行干法刻 蚀处理，所述钝化层在所述过孔对应的位置形成第二通孔；
剥离所述光刻胶图案；
在所述平坦化层的图形上形成阳极的图形，所述阳极通过所述第二通孔与所述漏极电连接。
可选地，在具体实施时，在本公开实施例提供的上述阵列基板的制作方法中，所述光刻胶图案包括完全去除区域、第一部分保留区域和完全保留区域；所述完全去除区域为所述过孔所在区域，所述完全保留区域为所述色阻层的图形所在区域，所述第一部分保留区域为所述第一通孔中除所述过孔以外的所在区域；
所述光刻胶图案在所述第一部分保留区域的厚度小于所述完全保留区域的厚度。
可选地，在具体实施时，在本公开实施例提供的上述阵列基板的制作方法中，所述光刻胶图案还包括第二部分保留区域，所述第二部分保留区域为除所述第一通孔和所述色阻层的图形以外的区域；所述光刻胶图案在所述第二部分保留区域的厚度大于所述第一部分保留区域的厚度且小于所述完全保留区域的厚度。
可选地，在具体实施时，在本公开实施例提供的上述阵列基板的制作方法中，对所述光刻胶层进行图案化处理，具体包括：
采用半色调掩膜板或灰色调掩模板对所述光刻胶层进行图案化处理；所述半色调掩膜板包括：与所述完全去除区域对应的完全透光区域，与所述第一部分保留区域对应的第一部分透光区域，与所述第二部分保留区域对应的第二部分透光区域，与所述完全保留区域对应的遮光区域；所述第一部分透光区域的透光量为所述完全透光区域的透光量的50％，所述第二部分透光区域的透光量为所述完全透光区域的透光量的10％～20％。
可选地，在具体实施时，在本公开实施例提供的上述阵列基板的制作方法中，所述光刻胶图案在所述第一部分保留区域的厚度为1.5μm-1.8μm，所述光刻胶图案在所述完全保留区域的厚度为2.1μm，所述光刻胶图案在所述第二 部分保留区域的厚度为1.7μm-1.9μm。
可选地，在具体实施时，在本公开实施例提供的上述阵列基板的制作方法中，对所述过孔露出的所述钝化层进行干法刻蚀处理，具体包括：
采用比例变化的O 2和CF 4的组合气体对所述钝化层进行干法刻蚀处理。
可选地，在具体实施时，在本公开实施例提供的上述阵列基板的制作方法中，比例变化的O 2和CF 4的组合气体包括：O 2含量大于CF 4的组合气体，以及O 2含量小于CF 4的组合气体。
可选地，在具体实施时，在本公开实施例提供的上述阵列基板的制作方法中，采用至少两次干法刻蚀对所述钝化层进行干法刻蚀处理，其中每一次干法刻蚀中的O 2和CF 4的比例固定，相邻两次干法刻蚀中的O 2和CF 4的比例是变化的。
可选地，在具体实施时，在本公开实施例提供的上述阵列基板的制作方法中，前一次干法刻蚀中O 2的比例大于后一次干法刻蚀中O 2的比例。
可选地，在具体实施时，在本公开实施例提供的上述阵列基板的制作方法中，采用两次干法刻蚀对所述钝化层进行干法刻蚀处理；第一次干法刻蚀中O 2的含量为55％～65％，CF 4的含量为35％～45％；第二次干法刻蚀中O 2的含量为15％～35％，CF 4的含量为65％～85％。
可选地，在具体实施时，在本公开实施例提供的上述阵列基板的制作方法中，所述第一次干法刻蚀去除所述钝化层厚度的一半，所述第二次干法刻蚀去除所述钝化层厚度的另一半。
可选地，在具体实施时，在本公开实施例提供的上述阵列基板的制作方法中，采用一次干法刻蚀对所述钝化层进行干法刻蚀处理，在处理的过程中，所述O 2的比例逐渐降低。
相应地，本公开实施例还提供了一种阵列基板，采用本公开实施例提供的上述任一项所述的制作方法制得，所述阵列基板包括：
衬底基板；
薄膜晶体管，位于所述衬底基板之上，所述薄膜晶体管包括有源层、栅 极绝缘层、栅极、源极和漏极；
钝化层，位于所述薄膜晶体管之上，所述钝化层具有位于所述薄膜晶体管中漏极上方的第二通孔；
色阻层，位于所述钝化层之上，且所述色阻层和所述薄膜晶体管在所述衬底基板上的正投影互不重叠；
平坦化层，位于所述色阻层之上，且具有覆盖所述薄膜晶体管的第一通孔；
阳极，位于所述平坦化层之上且延伸至所述第一通孔的底部，通过所述第二通孔与所述漏极电连接。
可选地，在具体实施时，在本公开实施例提供的上述阵列基板中，所述第二通孔具有至少两个坡度角，沿所述衬底基板指向所述第二通孔的方向，所述坡度角的度数增大。
可选地，在具体实施时，在本公开实施例提供的上述阵列基板中，所述薄膜晶体管为顶栅型薄膜晶体管。
相应地，本公开实施例还提供了一种显示面板，包括本公开实施例提供的上述阵列基板。
相应地，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述显示面板。
附图说明
图1为本公开实施例提供的阵列基板的制作方法的流程图；
图2为本公开实施例提供的阵列基板的结构示意图；
图3A至图3E分别为本公开实施例提供的阵列基板的制作方法中执行各步骤之后的剖面结构示意图。
具体实施方式
近来大尺寸OLED因其高对比度、自发光和渐成电视新的增长热点而成 为发展主流，其中大尺寸OLED中顶栅结构的TFT相比底栅结构的TFT具有高的开态电流、更高开口率和更好的TFT稳定性而受到关注。目前大尺寸OLED采用WRGB彩膜技术，即将BGR做于阵列钝化层(Array PVX)之上，而由于产品高色域要求以及彩膜材料所限，目前BGR的厚度较厚(一般≥3.0μm)，由于BGR的厚度较厚，为保证平坦化效果，相应的有机平坦化层(Resin)亦厚(一般≥3.3μm)。为保证钝化层过孔，在进行平坦化层工序时会在TFT区域形成一无Resin通孔，在后续钝化层过孔掩膜(源漏极金属与ITO连接过孔)时由于光阻本身流动性会使得Resin通孔内光阻较像素区域厚，像素区光阻薄，在Resin内光阻厚度较厚干刻Profile受影响，刻蚀速率变慢，而在钝化层过孔干法刻蚀的时候由于像素区光阻较薄，可能会对像素区的平坦化层产生干刻损伤(DE Damage)，使得后续有机发光层(EL)蒸镀异常以及有机膜透过率降低。
为了解决以上问题，本公开实施例提供了一种阵列基板的制作方法、阵列基板、显示面板及显示装置。为了使本公开的目的，技术方案和优点更加清楚，下面结合附图，对本公开实施例提供的阵列基板的制作方法、阵列基板、显示面板及显示装置的具体实施方式进行详细地说明。
附图中各层薄膜厚度和形状不反映阵列基板的真实比例，目的只是示意说明本公开内容。
本公开实施例提供的一种阵列基板的制作方法，如图1所示，包括：
S101、在衬底基板上依次形成薄膜晶体管的图形、钝化层、色阻层的图形和平坦化层的图形；其中，薄膜晶体管的图形和色阻层的图形在衬底基板上的正投影互不重叠，平坦化层的图形在薄膜晶体管的图形上方具有第一通孔；
S102、在平坦化层的图形上形成光刻胶层；
S103、对光刻胶层进行图案化处理，形成光刻胶图案；光刻胶图案在第一通孔的范围内具有位于薄膜晶体管中漏极上方的过孔，光刻胶图案在色阻层的图形上方的区域具有的厚度最大；示例性的，光刻胶图案可以包括完全 去除区域、第一部分保留区域和完全保留区域；其中，完全去除区域为过孔所在区域，第一部分保留区域为第一通孔覆盖的区域，即第一通孔中除过孔以外的所在区域，完全保留区域为色阻层的图形所在区域；
S104、以光刻胶图案作为遮挡，对过孔露出的钝化层进行干法刻蚀处理，钝化层在过孔对应的位置形成第二通孔；
S105、剥离光刻胶图案；
S106、在平坦化层的图形上形成阳极的图形，阳极通过第二通孔与漏极电连接。
具体地，在本公开实施例提供的上述阵列基板的制作方法中，在对形成在平坦化层的图形上方的光刻胶层进行图案化处理过程中，在形成完全去除区域的过孔时，使光刻胶图案在色阻层的图形上方的区域具有最大厚度，这样在后续对钝化层进行干法刻蚀处理时，可以防止对色阻层上方的平坦化层产生干刻损伤，避免使得后续有机发光层蒸镀异常以及有机膜透过率降低的可能。
可选地，在具体实施时，在本公开实施例提供的上述阵列基板的制作方法中，光刻胶图案可以包括完全去除区域、第一部分保留区域和完全保留区域；其中，完全去除区域为过孔所在区域，完全保留区域为色阻层的图形所在区域，第一部分保留区域为第一通孔中除过孔以外的所在区域；光刻胶图案在第一部分保留区域的厚度小于完全保留区域的厚度，即第一通孔在除了过孔的其它部分仅保留部分光刻胶图案，相对相关技术中第一通孔的其它部分完全保留的光刻胶层厚度较薄，有利于在干刻钝化层时形成较好的干刻Profile。
可选地，在具体实施时，为了在刻蚀钝化层后容易剥离剩余的光刻胶图案，在本公开实施例提供的上述阵列基板的制作方法中，光刻胶图案还可以包括第二部分保留区域，第二部分保留区域为除第一通孔和色阻层的图形以外的区域，即第二部分保留区域与薄膜晶体管和色阻在衬底基板上的正投影均不重叠，且第二部分保留区域的光刻胶厚度大于第一部分保留区域的光刻 胶厚度且小于完全保留区域的厚度。
可选地，在具体实施时，在本公开实施例提供的上述阵列基板的制作方法中，对光刻胶层进行图案化处理，具体可以包括：
采用半色调掩膜板或灰色调掩模板对光刻胶层进行图案化处理；半色调掩膜板可以包括：与完全去除区域对应的完全透光区域，与第一部分保留区域对应的第一部分透光区域，与第二部分保留区域对应的第二部分透光区域，与完全保留区域对应的遮光区域；第一部分透光区域的透光量为完全透光区域的透光量的50％，第二部分透光区域的透光量为完全透光区域的透光量的10％～20％。
可选地，在具体实施时，在本公开实施例提供的上述阵列基板的制作方法中，相关技术中一般涂覆的光刻胶层的厚度为1.8μm，本公开中涂覆的光刻胶层的厚度可以为2.1μm，由于光刻胶的流动性，会使平坦化层的第一通孔内的光刻胶厚度可以为3μm-3.6μm，因此在经过第一部分透光区域的照射后，光刻胶图案在第一部分保留区域的厚度可以为1.5μm-1.8μm，光刻胶图案在完全保留区域的厚度为2.1μm，在经过第二部分透光区域的照射后，光刻胶图案在第二部分保留区域的厚度可以为1.7μm-1.9μm。
具体地，通过本公开采用的半色调掩膜板或灰色调掩模板使得平坦化层的第一通孔内的光刻胶符合刻蚀要求，且厚度也不会因光刻胶的流动性而较厚，且色阻层上方对应的光刻胶厚度较厚，可耐后续钝化层刻蚀，不会对平坦化层产生干刻损伤，提升了面板的可靠性；并且将第二部分保留区域的光刻胶图案的厚度降低为原光刻胶的10％～20％，这样后续残留的光刻胶图案容易剥离。
具体地，在对钝化层进行干法刻蚀时，当O 2含量高时，对光刻胶图案的刻蚀速率较快，但得到的第二通孔的坡度角较小；当CF 4含量高时，对钝化层刻蚀较快，但得到的第二通孔的坡度角较大。相关技术中一般是仅采用一次刻蚀，且O 2的含量大于CF 4的比例，这样对光刻胶图案的刻蚀速率较快，因此在钝化层刻蚀完成后，会刻蚀掉大部分的光刻胶图案，使色阻层上方的 光刻胶图案保留的较薄，容易对平坦化层产生干刻损伤，影响后续有机功能层的蒸镀。
基于此，在具体实施时，在本公开实施例提供的上述阵列基板的制作方法中，对过孔露出的钝化层进行干法刻蚀处理，具体可以包括：
采用O 2和CF 4的组合气体对钝化层进行干法刻蚀处理，O 2和CF 4的比例是变化的。通过改变刻蚀过程中O 2和CF 4的比例，可以减少对光刻胶图案的刻蚀，使色阻层上方的光刻胶图案保留的较厚，不会对平坦化层产生干刻损伤，从而不影响后续有机功能层的蒸镀。并且，比例变化的O 2和CF 4的组合气体可以包括：O 2含量大于CF 4的组合气体，以及O 2含量小于CF 4的组合气体。
可选地，在具体实施时，在本公开实施例提供的上述阵列基板的制作方法中，可以采用至少两次干法刻蚀对钝化层进行干法刻蚀处理，其中每一次干法刻蚀中的O 2和CF 4的比例固定，相邻两次干法刻蚀中的O 2和CF 4的比例是变化的。
可选地，在具体实施时，在本公开实施例提供的上述阵列基板的制作方法中，采用至少两次干法刻蚀对钝化层进行干法刻蚀处理，其中前一次干法刻蚀中O 2的比例大于后一次干法刻蚀中O 2的比例。具体地，当采用两次干法刻蚀对钝化层进行干法刻蚀处理时，第一次干法刻蚀中O 2的含量可以为55％～65％，CF 4的含量为35％～45％；第二次干法刻蚀中O 2的含量可以为15％～35％，CF 4的含量为65％～85％。
具体地，第一次干法刻蚀采用CF 4(含量为35％～45％)+O 2(含量为55％～65％)进行，且采用高源极功率和高偏置功率进行，刻蚀约50％厚度的钝化层，由于O 2含量较高且平坦化层的第一通孔内的光刻胶厚度不厚，符合刻蚀要求，使钝化层可刻蚀出较好的干刻角度，与此同时，由于O 2含量高，对光刻胶的刻蚀速率较快，但因只刻蚀钝化层厚度的50％，故仅消耗约0.4μm～0.5μm厚度的光刻胶图案，使色阻层上方的光刻胶图案保留的较厚，不会对平坦化层产生干刻损伤，从而不影响后续有机功能层的蒸镀。
第二次干法刻蚀采用CF 4(含量为65％～85％)+O 2(含量为15％～35％)进行，并采用高源极功率和高偏置功率进行，刻蚀剩余的50％厚度的钝化层，由于CF 4含量较高，对钝化层刻蚀较快，对钝化层干刻的角度会较陡(60°～70°)，但因第一次刻蚀时已经刻蚀了一半的钝化层，故而后一半钝化层的干刻角度对后续阳极的沉积无影响，而且由于CF 4含量较高，O 2的含量较少，可避免干刻过程对O 2的进一步消耗使得干刻过程不会对平坦化层造成干刻损伤。
可选地，在具体实施时，在本公开实施例提供的上述阵列基板的制作方法中，还可以仅采用一次干法刻蚀对钝化层进行干法刻蚀处理，在处理的过程中，O 2的比例逐渐降低。
基于同一发明构思，本公开实施例还提供了一种阵列基板，如图2所示，采用本公开实施例提供的上述制作方法制得。具体地，该阵列基板包括：衬底基板1，位于衬底基板1上依次层叠设置的薄膜晶体管2、钝化层3、色阻层4和平坦化层5，以及阳极6。薄膜晶体管2具体包括：有源层21、栅极绝缘层22、栅极23、源极24和漏极25。色阻层4和薄膜晶体管2在衬底基板1上的正投影互不重叠，平坦化层5具有覆盖薄膜晶体管2的第一通孔P1，钝化层3具有位于薄膜晶体管2中漏极21上方的第二通孔P2，阳极6延伸至第一通孔P1的底部，通过钝化层3的第二通孔P2与薄膜晶体管2的漏极21电连接。
可选地，在具体实施时，在本公开实施例提供的上述阵列基板中，如图2所示，薄膜晶体管2可以为顶栅型薄膜晶体管。阵列基板还可以包括位于薄膜晶体管2与衬底基板1之间的缓冲层8，位于缓冲层8与衬底基板1之间的遮光金属层7，遮光金属层7用于遮挡有源层4，以及位于源漏极(24和25)与栅极23之间的层间绝缘层9。
可选地，在具体实施时，在本公开实施例提供的上述阵列基板中，如图2所示，第二通孔P2的截面与衬底基板1之间具有至少两个坡度角(本公开实施例以采用两次干法刻蚀钝化层为例，坡度角具有两个θ1和θ2)，沿衬底基 板1指向远离衬底基板1的方向，坡度角的度数逐渐降低，坡度角是指钝化层3的干刻斜面与衬底基板1之间的夹角，即θ1的度数大于θ2的度数。虽然θ1的角度较大，钝化层3的干刻角度较陡，但因第一次刻蚀时已经刻蚀了一半的钝化层3，故而后一半钝化层3的干刻角度θ1对后续阳极6的沉积无影响。
需要说明的是，本公开实施例提供的阵列基板可以应用于有机电致发光二极管(Organic Light Emitting Diode，OLED)显示面板。该阵列基板还可以包括阴极以及位于阳极和阴极之间的有机功能层。
下面通过具体实施例对本公开实施例提供的阵列基板的制作方法进行详细说明。
(1)可以利用化学气相沉积法在衬底基板1上沉积一层遮光金属薄膜，遮光金属薄膜可以为钼或钼铌合金等金属，厚度可以为0.10μm～0.15μm，紧接着通过曝光、显影和湿法刻蚀后形成遮光金属层7。具体地，湿法刻蚀遮光金属薄膜可采用混酸进行刻蚀。
然后，可以利用化学气相沉积法或者磁控溅射的方法在形成有遮光金属层2的衬底基板1上沉积一层缓冲层8。具体地，该缓冲层8的材料可以为氧化硅，厚度可以为0.3μm～0.5μm。
接着，可以利用化学气相沉积法在缓冲层8上沉积金属氧化物半导体薄膜，然后对金属氧化物半导体薄膜进行一次构图工艺形成有源层21，即在光刻胶涂覆后，用普通的掩膜板对光刻胶进行曝光、显影、刻蚀形成有源层21。具体地，有源层4的材料可以为氧化铟锡(IGZO)，厚度可以为0.05μm～0.1μm。
之后，可以利用化学气相沉积法或者磁控溅射的方法在形成有有源层21的衬底基板1上沉积一层栅极绝缘薄膜。具体地，该栅极绝缘薄膜的材料可以为氧化硅，厚度为0.1μm～0.2μm。
然后，可以利用磁控溅射的方法在栅极绝缘薄膜上沉积一层栅极金属薄膜。具体地，栅极金属薄膜可以为铜金属。具体地，栅极金属薄膜的厚度可以为0.4μm～0.5μm。通过构图工艺形成栅极23，具体地，在栅极金属薄膜上 涂覆光刻胶，然后利用掩膜板对光刻胶进行曝光，并在显影、刻蚀后形成栅极23，此刻蚀工艺可以为铜湿刻工艺，可以采用过氧化氢溶液进行湿刻。
在栅极23湿刻完成后，保留栅极23上方的栅极掩膜(即光刻胶图案)对栅极绝缘薄膜进行干法刻蚀处理，形成栅极绝缘层22。具体地，可采用流量为2000sccm～2500sccm的CF 4和流量为1000sccm～1500sccm的O 2混合气体对无光刻胶保护的栅极绝缘薄膜进行干法刻蚀。
在形成栅极绝缘层22之后，继续保留栅极23上方的栅极掩膜(即光刻胶图案)，对在栅极绝缘层进行干法刻蚀处理后暴露出的有源层21进行导体化处理。由于有源层21包括被栅极绝缘层22覆盖的沟道区以及分别位于沟道区两侧的源极接触区域漏极接触区，因此，通过对源极接触区和漏极接触区进行导体化处理，能够降低即将形成的源极24、漏极25和有源层21的接触电阻，提高导电性。具体地，可以采用氨气(NH 3)或者氦气(He)进行导体化处理。之后，对光刻胶进行湿法剥离。
然后，沉积一层层间绝缘层9，层间绝缘层9的材料可为氧化硅，厚度可以为0.45μm～0.6μm，随后涂覆一层光刻胶，然后利用掩膜板对光刻胶进行曝光，并在显影、刻蚀后形成与即将形成的源极和漏极对应的接触孔，以便电连接源漏极和有源21层，干刻出接触孔后进行湿法剥离。
然后，沉积一层源漏金属薄膜，源漏金属薄膜可为铜和铝等金属，厚度为0.5μm～0.7μm，通过光刻湿刻形成源极24和漏极25。
接着，在形成有源极24和漏极25的衬底基板1上沉积一层钝化层3，钝化层3的材料可为氧化硅-顶部/氮化硅/氧化硅-底部复合层，考虑到对特性影响，氧化硅-顶部厚度可以为0.1μm～0.2μm，氮化硅厚度可以为0.03μm～0.05μm，氧化硅-底部厚度可以为0.1μm～0.2μm，如图3A所示。
(2)在钝化层3上形成色阻层4，具体地，可先后进行Blue、Green以及Red色阻工序；然后在形成有色阻层4的衬底基板1上形成平坦化层5，通过构图工艺在薄膜晶体管2的上方对应的平坦化层5中形成第一通孔P1。具体地，在平坦化层5上涂覆光刻胶，然后利用掩膜板对光刻胶进行曝光，并 在显影、刻蚀后形成第一通孔P1，然后进行光刻胶湿法剥离，如图3B所示。
(3)在具有第一通孔P1的平坦化层上形成光刻胶层，然后利用半色调掩膜板对光刻胶层进行曝光、显影和刻蚀，形成光刻胶图案，如图3C所示；具体地，光刻胶图案包括完全去除区域01、第一部分保留区域02、第二部分保留区域03和完全保留区域04；其中，完全去除区域01在第一通孔P1范围内且位于漏极25上方，第一部分保留区域02被第一通孔P1覆盖，完全保留区域04覆盖色阻层4所在区域。
具体地，光刻胶层为正性光刻胶，其厚度可以为2.1μm，由于光刻胶的流动性，会使平坦化层5的第一通孔P1内的光刻胶厚度为3的光刻胶厚度为动，因此第一部分保留区域02的光刻胶厚度为1.5胶厚度为保留区域会，完全保留区域04的光刻胶图案的厚度为2.1胶图，第二部分保留区域03的光刻胶图案的厚度为1.7胶图案的厚度为域。
通过本公开采用的半色调掩膜板使得平坦化层5的第一通孔P1内的光刻胶符合刻蚀要求，且厚度也不会因光刻胶的流动性而较厚，且色阻层4上方对应的光刻胶厚度较厚，可耐后续钝化层3刻蚀，不会对平坦化层5产生干刻损伤，提升了面板的可靠性；并且将第二部分保留区域03的光刻胶图案的厚度降低为原光刻胶的10％～20％，这样在后续剥离光刻胶时容易剥离。
(4)以光刻胶图案(02、03和04)作为遮挡，对露出的钝化层3进行干法刻蚀处理。具体地，采用两次干法刻蚀对钝化层3进行干法刻蚀处理。第一次干法刻蚀采用CF 4(含量为35％～45％)+O 2(含量为55％～65％)进行，且采用高源极功率和高偏置功率进行，刻蚀约50％厚度的钝化层，由于O 2含量较高且平坦化层4的第一通孔内P1的光刻胶厚度不厚，符合刻蚀要求，使钝化层3可刻蚀出较好的干刻角度。第二次干法刻蚀采用CF 4(含量为65％～85％)+O 2(含量为15％～35％)进行，并采用高源极功率和高偏置功率进行，刻蚀剩余的50％厚度的钝化层3，由于CF 4含量较高，对钝化层3刻蚀较快，对钝化层3干刻的角度会较陡(60°～70°)。通过两次刻蚀后，钝化层3在完全去除区域01对应的位置形成第二通孔P2，随后剥离光刻胶图案， 如图3D所示。
(5)在平坦化层5上形成阳极6，阳极6通过第二通孔P2与漏极25电连接，如图3E所示。
通过上述步骤(1)至步骤(5)后即可制作出本公开实施例提供的阵列基板。
基于同一发明构思，本公开实施例还提供了一种显示面板，包括本公开实施例提供的上述阵列基板。该显示面板的实施可以参见上述阵列基板的实施例，重复之处不再赘述。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述显示面板。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置的实施可以参见上述阵列基板的实施例，重复之处不再赘述。
本公开实施例提供的阵列基板的制作方法、显示面板及显示装置，通过对形成在平坦化层上的光刻胶层进行图案化处理，使薄膜晶体管的漏极上方的部分第一通孔内没有光刻胶层、第一通孔的其它部分保留部分光刻胶层、色阻层上方对应的光刻胶层完全保留；这样在后续对钝化层进行干法刻蚀处理时，由于第一通孔的其它部分仅保留部分光刻胶层，相对相关技术中第一通孔的其它部分完全保留的光刻胶层较薄，本公开有利于在干刻钝化层时形成较好的干刻Profile；另外本公开中色阻层上方的光刻胶层厚度相对相关技术中色阻层上方的光刻胶层厚度较厚，在对钝化层进行干刻时，本公开可以防止对色阻上方的平坦化层产生干刻损伤，避免使得后续有机发光层蒸镀异常以及有机膜透过率降低的可能。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (17)

  1. 一种阵列基板的制作方法，其中，包括：
    在衬底基板上依次形成薄膜晶体管的图形、钝化层、色阻层的图形和平坦化层的图形；其中，所述薄膜晶体管的图形和所述色阻层的图形在所述衬底基板上的正投影互不重叠，所述平坦化层的图形在所述薄膜晶体管的图形上方具有第一通孔；
    在平坦化层的图形上形成光刻胶层；
    对所述光刻胶层进行图案化处理，形成光刻胶图案；所述光刻胶图案在所述第一通孔的范围内具有位于所述薄膜晶体管中漏极上方的过孔，所述光刻胶图案在所述色阻层的图形上方的区域具有的厚度最大；
    以所述光刻胶图案作为遮挡，对所述过孔露出的所述钝化层进行干法刻蚀处理，所述钝化层在所述过孔对应的位置形成第二通孔；
    剥离所述光刻胶图案；
    在所述平坦化层的图形上形成阳极的图形，所述阳极通过所述第二通孔与所述漏极电连接。
  2. 如权利要求1所述的阵列基板的制作方法，其中，所述光刻胶图案包括完全去除区域、第一部分保留区域和完全保留区域；所述完全去除区域为所述过孔所在区域，所述完全保留区域为所述色阻层的图形所在区域，所述第一部分保留区域为所述第一通孔中除所述过孔以外的所在区域；
    所述光刻胶图案在所述第一部分保留区域的厚度小于所述完全保留区域的厚度。
  3. 如权利要求2所述的阵列基板的制作方法，其中，所述光刻胶图案还包括第二部分保留区域，所述第二部分保留区域为除所述第一通孔和所述色阻层的图形以外的区域；所述光刻胶图案在所述第二部分保留区域的厚度大于所述第一部分保留区域的厚度且小于所述完全保留区域的厚度。
  4. 如权利要求3所述的阵列基板的制作方法，其中，对所述光刻胶层进 行图案化处理，具体包括：
    采用半色调掩膜板或灰色调掩模板对所述光刻胶层进行图案化处理；所述半色调掩膜板包括：与所述完全去除区域对应的完全透光区域，与所述第一部分保留区域对应的第一部分透光区域，与所述第二部分保留区域对应的第二部分透光区域，与所述完全保留区域对应的遮光区域；所述第一部分透光区域的透光量为所述完全透光区域的透光量的50％，所述第二部分透光区域的透光量为所述完全透光区域的透光量的10％～20％。
  5. 如权利要求4所述的阵列基板的制作方法，其中，所述光刻胶图案在所述第一部分保留区域的厚度为1.5μm-1.8μm，所述光刻胶图案在所述完全保留区域的厚度为2.1μm，所述光刻胶图案在所述第二部分保留区域的厚度为1.7μm-1.9μm。
  6. 如权利要求1-5任一项所述的阵列基板的制作方法，其中，对所述过孔露出的所述钝化层进行干法刻蚀处理，具体包括：
    采用比例变化的O 2和CF 4的组合气体对所述钝化层进行干法刻蚀处理。
  7. 如权利要求6所述的阵列基板的制作方法，其中，比例变化的O 2和CF 4的组合气体包括：O 2含量大于CF 4的组合气体，以及O 2含量小于CF 4的组合气体。
  8. 如权利要求6所述的阵列基板的制作方法，其中，采用至少两次干法刻蚀对所述钝化层进行干法刻蚀处理，其中每一次干法刻蚀中的O 2和CF 4的比例固定，相邻两次干法刻蚀中的O 2和CF 4的比例是变化的。
  9. 如权利要求8所述的阵列基板的制作方法，其中，前一次干法刻蚀中O 2的比例大于后一次干法刻蚀中O 2的比例。
  10. 如权利要求9所述的阵列基板的制作方法，其中，采用两次干法刻蚀对所述钝化层进行干法刻蚀处理；第一次干法刻蚀中O 2的含量为55％～65％，CF 4的含量为35％～45％；第二次干法刻蚀中O 2的含量为15％～35％，CF 4的含量为65％～85％。
  11. 如权利要求10所述的阵列基板的制作方法，其中，所述第一次干法 刻蚀去除所述钝化层厚度的一半，所述第二次干法刻蚀去除所述钝化层厚度的另一半。
  12. 如权利要求6所述的阵列基板的制作方法，其中，采用一次干法刻蚀对所述钝化层进行干法刻蚀处理，在处理的过程中，所述O 2的比例逐渐降低。
  13. 一种阵列基板，其中，采用如权利要求1-12任一项所述的制作方法制得，所述阵列基板包括：
    衬底基板；
    薄膜晶体管，位于所述衬底基板之上，所述薄膜晶体管包括有源层、栅极绝缘层、栅极、源极和漏极；
    钝化层，位于所述薄膜晶体管之上，所述钝化层具有位于所述薄膜晶体管中漏极上方的第二通孔；
    色阻层，位于所述钝化层之上，且所述色阻层和所述薄膜晶体管在所述衬底基板上的正投影互不重叠；
    平坦化层，位于所述色阻层之上，且具有覆盖所述薄膜晶体管的第一通孔；
    阳极，位于所述平坦化层之上且延伸至所述第一通孔的底部，通过所述第二通孔与所述漏极电连接。
  14. 如权利要求13所述的阵列基板，其中，所述第二通孔具有至少两个坡度角，沿所述衬底基板指向所述第二通孔的方向，所述坡度角的度数增大。
  15. 如权利要求13所述的阵列基板，其中，所述薄膜晶体管为顶栅型薄膜晶体管。
  16. 一种显示面板，其中，包括如权利要13-15任一项所述的阵列基板。
  17. 一种显示装置，其中，包括如权利要16所述的显示面板。
PCT/CN2020/081886 2019-05-30 2020-03-27 阵列基板的制作方法、阵列基板、显示面板及显示装置 WO2020238384A1 (zh)

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