WO2019080252A1 - Oled背板的制作方法 - Google Patents

Oled背板的制作方法

Info

Publication number
WO2019080252A1
WO2019080252A1 PCT/CN2017/113513 CN2017113513W WO2019080252A1 WO 2019080252 A1 WO2019080252 A1 WO 2019080252A1 CN 2017113513 W CN2017113513 W CN 2017113513W WO 2019080252 A1 WO2019080252 A1 WO 2019080252A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
oxide semiconductor
semiconductor layer
ratio
electrode
Prior art date
Application number
PCT/CN2017/113513
Other languages
English (en)
French (fr)
Inventor
刘方梅
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to KR1020207014609A priority Critical patent/KR102299370B1/ko
Priority to US15/742,814 priority patent/US10658446B2/en
Priority to EP17929670.2A priority patent/EP3703112A4/en
Priority to JP2020513706A priority patent/JP2020532877A/ja
Publication of WO2019080252A1 publication Critical patent/WO2019080252A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/16—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering
    • H10K71/166—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering using selective deposition, e.g. using a mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02483—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02491—Conductive materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/38—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions
    • H01L21/383—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions using diffusion into or out of a solid from or into a gaseous phase
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
    • H01L21/441—Deposition of conductive or insulating materials for electrodes
    • H01L21/443—Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/469—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers
    • H01L21/4757—After-treatment
    • H01L21/47573—Etching the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating an OLED backplane.
  • the flat display device has many advantages such as thin body, power saving, no radiation, and has been widely used.
  • the existing flat display devices mainly include a liquid crystal display (LCD) and an organic light emitting display (OLED).
  • the organic light-emitting diode display device has the advantages of self-luminescence, no backlight, high contrast, thin thickness, wide viewing angle, fast response speed, flexible panel, wide temperature range, simple structure and simple process. It is considered to be an emerging application technology for next-generation flat panel displays.
  • An OLED display device generally includes a substrate, an anode disposed on the substrate, an organic light emitting layer disposed on the anode, and a cathode disposed on the organic light emitting layer. Working, the holes from the anode and the electrons from the cathode are emitted to the organic light-emitting layer, and these electrons and holes are combined to generate an excited electron-hole pair, and the excited electron-hole pair is converted from the excited state to the ground state. Achieve light.
  • the OLED display device can be divided into two types: passive matrix OLED (PMOLED) and active matrix OLED (AMOLED), namely direct addressing and thin film transistor (Thin Film Transistor, according to the driving method). TFT) matrix addressing two types.
  • the AMOLED has pixels arranged in an array, which belongs to an active display type, has high luminous efficiency and excellent performance.
  • Thin film transistors commonly used in the prior art include amorphous silicon (a-Si) thin film transistors, low temperature poly-silicon (LTPS) thin film transistors, and oxide semiconductor thin film transistors, oxide semiconductor thin film transistors due to It has high electron mobility, and compared with low-temperature polysilicon thin film transistors, oxide semiconductor thin film transistors have simple process and high compatibility with amorphous silicon thin film transistors, and have been widely used.
  • a-Si amorphous silicon
  • LTPS low temperature poly-silicon
  • oxide semiconductor thin film transistors due to It has high electron mobility, and compared with low-temperature polysilicon thin film transistors, oxide semiconductor thin film transistors have simple process and high compatibility with amorphous silicon thin film transistors, and have been widely used.
  • an oxygen content in an active layer greatly affects device characteristics.
  • an active layer in an oxide semiconductor thin film transistor generally adopts a single film design.
  • the active layer of a single film layer is formed by one deposition. If the oxygen flow rate during deposition is large, the oxygen content of the active layer is too high, the conductivity is deteriorated, and the device mobility is lowered; and if the oxygen flow is deposited, Smaller, the oxygen content in the active layer is too low, and the oxygen vacancies are too much, resulting in an interface between the active layer and the buffer layer and an interface defect at the contact interface between the active layer and the gate insulating layer. The device stability is deteriorated.
  • An object of the present invention is to provide a method for fabricating an OLED backplane, which can improve the conductivity of the active layer of the thin film transistor device, reduce interface defects, and improve the stability of the thin film transistor device.
  • the present invention provides a method for fabricating an OLED backplane, comprising the following steps:
  • Step S1 providing a substrate, and forming a buffer layer on the substrate;
  • Step S2 depositing a first oxide semiconductor layer on the buffer layer, and introducing argon gas and oxygen gas while depositing, the flow ratio of the argon gas and the oxygen gas being a first ratio;
  • Step S3 depositing a second oxide semiconductor layer on the first oxide semiconductor layer, and introducing argon gas and oxygen gas while depositing, the flow ratio of the argon gas and the oxygen gas is a second ratio;
  • Step S4 depositing a third oxide semiconductor layer on the second oxide semiconductor layer, and introducing argon gas and oxygen gas while depositing, the flow ratio of the argon gas and the oxygen gas is a third ratio, thereby obtaining the An active layer of the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer;
  • Step S5 forming a gate insulating layer and a gate on the gate insulating layer on the active layer;
  • Step S6 covering the active layer, the gate, and the gate insulating layer with an interlayer insulating layer;
  • Step S7 forming a source and a drain on the interlayer insulating layer
  • the first ratio and the third ratio are both greater than the second ratio.
  • the first ratio and the third ratio are both 2:1 to 4:1, and the second ratio is 10:1 to 20:1.
  • the first oxide semiconductor layer and the third oxide semiconductor layer have a thickness of 50 to
  • the second oxide semiconductor layer has a thickness of 200 to
  • the materials of the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer are all IGZO, and the buffer layer and the gate insulating layer are made of silicon oxide and silicon nitride. One or a combination of both.
  • the step S1 further includes forming a light shielding layer between the base substrate and the buffer layer, the light shielding layer blocking the active layer.
  • the step S5 specifically includes:
  • the gate insulating film is etched by blocking the gate electrode to form a gate insulating layer.
  • the gate and gate insulating layers cover the center of the active layer in the step S5, and expose both ends of the active layer;
  • the step S5 and the step S6 further includes the step of plasma-treating the active layer such that the resistance of both ends of the active layer is lowered to form an N+ conductor layer.
  • the step S6 further includes: patterning the interlayer insulating layer to form a first via hole and a second via hole exposing both ends of the active layer, and the source and the drain in the step S7 The first via and the second via are respectively in contact with both ends of the active layer.
  • the manufacturing method of the OLED backplane further includes:
  • Step S8 depositing a passivation layer on the interlayer insulating layer, the source, and the drain, and patterning the passivation layer to form a third via hole exposing the drain;
  • Step S9 forming a first electrode on the passivation layer, the first electrode being in contact with the drain through the third via hole;
  • Step S10 forming a pixel defining layer on the first electrode and the passivation layer, and patterning the pixel defining layer to form a pixel defining groove exposing the first electrode;
  • Step S11 forming an organic light emitting layer in the pixel defining groove, and forming a second electrode on the pixel defining layer and the organic light emitting layer.
  • the first electrode is a transparent electrode
  • the second electrode is a reflective electrode
  • the invention also provides a method for manufacturing an OLED backplane, comprising the following steps:
  • Step S1 providing a substrate, and forming a buffer layer on the substrate;
  • Step S2 depositing a first oxide semiconductor layer on the buffer layer, and introducing argon gas and oxygen gas while depositing, the flow ratio of the argon gas and the oxygen gas being a first ratio;
  • Step S3 depositing a second oxide semiconductor layer on the first oxide semiconductor layer, and introducing argon gas and oxygen gas while depositing, the flow ratio of the argon gas and the oxygen gas is a second ratio;
  • Step S4 depositing a third oxide semiconductor layer on the second oxide semiconductor layer, and introducing argon gas and oxygen gas while depositing, the flow ratio of the argon gas and the oxygen gas is a third ratio, thereby obtaining the An active layer of the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer;
  • Step S5 forming a gate insulating layer and a gate on the gate insulating layer on the active layer;
  • Step S6 covering the active layer, the gate, and the gate insulating layer with an interlayer insulating layer;
  • Step S7 forming a source and a drain on the interlayer insulating layer
  • the first ratio and the third ratio are both greater than the second ratio
  • first ratio and the third ratio are both 2:1 to 4:1, and the second ratio is 10:1 to 20:1;
  • first oxide semiconductor layer and the third oxide semiconductor layer have a thickness of 50 to The second oxide semiconductor layer has a thickness of 200 to
  • the materials of the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer are all IGZO, and the buffer layer and the gate insulating layer are made of silicon oxide and silicon nitride. One or a combination of the two;
  • the step S1 further includes: forming a light shielding layer between the base substrate and the buffer layer, the light shielding layer blocking the active layer;
  • the step S5 specifically includes:
  • the gate insulating film is etched by blocking the gate electrode to form a gate insulating layer.
  • the present invention provides a method for fabricating an OLED back sheet, which comprises obtaining a thin film transistor by sequentially depositing a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer.
  • the source layer by causing the flow ratio of argon gas and oxygen gas to be introduced when the first oxide semiconductor layer and the third oxide semiconductor layer are deposited to be larger than the flow ratio of argon gas and oxygen gas introduced when the second oxide semiconductor layer is deposited,
  • the oxygen content of the first oxide semiconductor layer and the third oxide semiconductor layer is made larger than the oxygen content of the second oxide semiconductor layer, thereby improving the conductivity of the active layer of the thin film transistor device, reducing interface defects, and improving the thin film transistor device. stability.
  • FIG. 1 to 2 are schematic views showing a step S1 of a method for fabricating an OLED backplane according to the present invention
  • step S2 is a schematic diagram of step S2 of the method for fabricating an OLED backplane of the present invention
  • step S3 is a schematic diagram of step S3 of the method for fabricating an OLED backplane of the present invention.
  • step S4 is a schematic diagram of step S4 of the method for fabricating an OLED backplane according to the present invention.
  • step S5 is a schematic diagram of step S5 of the method for fabricating an OLED backplane according to the present invention.
  • step S6 is a schematic diagram of step S6 of the method for fabricating an OLED backplane of the present invention.
  • step S7 is a schematic diagram of step S7 of the method for fabricating an OLED backplane of the present invention.
  • step S8 is a schematic diagram of step S8 of the method for fabricating an OLED backplane according to the present invention.
  • step S9 is a schematic diagram of step S9 of the method for fabricating an OLED backplane of the present invention.
  • step S10 is a schematic diagram of step S10 of the method for fabricating an OLED backplane of the present invention.
  • step S11 is a schematic diagram of step S11 of the method for fabricating an OLED backplane according to the present invention.
  • FIG. 13 is a flow chart of a method of fabricating an OLED backplane of the present invention.
  • the present invention provides a method for fabricating an OLED backplane, including the following steps:
  • Step S1 referring to FIG. 1 and FIG. 2, a substrate 1 is provided on which a buffer layer 3 is formed.
  • the step S1 may further include: depositing a light shielding metal film on the base substrate 1 , and patterning the light shielding metal film to obtain an active corresponding to be formed.
  • the area of the layer 4 forms a light-shielding layer 2 covering the light-shielding layer 2 and the base substrate 1 for shielding the subsequently formed active layer 4 to prevent the active layer 4 from being illuminated. This causes a change in device performance.
  • the material of the buffer layer 3 is one or a combination of silicon oxide (SiOx) and silicon nitride (SiNx), and the buffer layer 3 has a thickness of 5000 to
  • Step S2 referring to FIG. 3, a first oxide semiconductor layer 41 is deposited on the buffer layer 3, and argon gas and oxygen gas are introduced while being deposited, and the flow ratio of the argon gas and the oxygen gas is a first ratio.
  • the first oxide semiconductor layer 41 has a thickness of 50 to
  • Step S3 referring to FIG. 4, depositing a second oxide semiconductor layer 42 on the first oxide semiconductor layer 41, and introducing argon gas and oxygen gas while depositing, the flow ratio of the argon gas and the oxygen gas is Two ratios.
  • the second oxide semiconductor layer 41 has a thickness of 200 to
  • Step S4 referring to FIG. 5, depositing a third oxide semiconductor layer 43 on the second oxide semiconductor layer 42, and introducing argon gas and oxygen gas while depositing, the flow ratio of the argon gas and the oxygen gas is At a three ratio, the active layer 4 including the first oxide semiconductor layer 41, the second oxide semiconductor layer 42, and the third oxide semiconductor layer 43 is obtained.
  • the third oxide semiconductor layer 43 has a thickness of 50 to
  • the first ratio and the third ratio are both greater than the second ratio.
  • the first ratio and the third ratio are both 2:1 to 4:1, and the second ratio is 10:1.
  • the first ratio and the third ratio are both 4:1 and the second ratio is 20:1.
  • the materials of the first oxide semiconductor layer 41, the second oxide semiconductor layer 42, and the third oxide semiconductor layer 43 are all IGZO.
  • Step S5 referring to FIG. 6, a gate insulating layer 5 and a gate electrode 6 on the gate insulating layer are formed on the active layer 4.
  • the step S5 specifically includes: depositing a gate insulating film on the active layer 4 and the buffer layer 3, depositing a gate metal film on the gate insulating film; and patterning through a mask process a gate metal film forming a gate electrode 6; etching the gate insulating film with the gate as an occlusion to form a gate insulating layer 5
  • the gate electrode 6 and the gate insulating layer 5 cover the center of the active layer 4 and expose both ends of the active layer 4.
  • the material of the gate insulating layer 5 is one or a combination of silicon oxide and silicon nitride.
  • the material of the gate electrode 6 is a combination of one or more of metals such as molybdenum, aluminum, copper, and titanium.
  • the gate insulating layer 5 has a thickness of 1000 to The thickness of the gate 6 is 2000 to
  • Step S6 referring to FIG. 7, the interlayer insulating layer 7 is covered on the active layer 4, the gate electrode 6, and the gate insulating layer 5.
  • the method further includes the following steps: performing plasma processing on the active layer 4 such that the resistance of both ends of the active layer 4 is lowered to form an N+ conductor layer, and the The center of the active layer 4 is shielded by the gate insulating layer 5 and the gate electrode 6 while still maintaining semiconductor characteristics as a channel region as a thin film transistor device.
  • step S6 further includes: patterning the interlayer insulating layer 7 to form a first via hole 71 and a second via hole 72 exposing both ends of the active layer.
  • the interlayer insulating layer 7 has a thickness of 2000 to
  • Step S7 referring to FIG. 8, a source 81 and a drain 82 are formed on the interlayer insulating layer.
  • the source electrode 81 and the drain electrode 82 are in contact with both ends of the active layer 4 through the first via hole 71 and the second via hole 72, respectively.
  • the step S7 specifically includes: first depositing a source drain metal film, and then patterning the source/drain metal film by a mask process to form the source 81 and the drain 82.
  • the material of the source 81 and the drain 82 is a combination of one or more of metals such as molybdenum, aluminum, copper, and titanium, and the thickness of the source 81 and the drain 82 are both 2000 to
  • Step S8 referring to FIG. 9, a passivation layer 9 is deposited on the interlayer insulating layer 7, the source 81, and the drain 82, and the passivation layer 9 is patterned to form the drain.
  • the material of the passivation layer 9 is a combination of one or more of silicon oxide or silicon nitride, and the passivation layer 9 has a thickness of 1000 to
  • Step S9 referring to FIG. 10, a first electrode 10 is formed on the passivation layer 9, and the first electrode 10 is in contact with the drain 82 through the third via 91.
  • the first electrode 10 is a transparent electrode, preferably made of indium tin oxide (ITO), and the first electrode 10 is an anode of an organic light emitting diode.
  • ITO indium tin oxide
  • Step S10 referring to FIG. 11, a pixel defining layer 11 is formed on the first electrode 10 and the passivation layer 9, and the pixel defining layer 11 is patterned to form a pixel exposing the first electrode 10.
  • a slot 111 is defined.
  • Step S11 referring to FIG. 12, an organic light-emitting layer 12 is formed in the pixel defining groove 111, and a second electrode 13 is formed on the pixel defining layer 11 and the organic light-emitting layer 12.
  • the organic light emitting layer 12 may include a hole transporting functional layer, a light emitting functional layer, and an electron transporting functional layer which are sequentially stacked from bottom to top.
  • the second electrode 13 is a reflective electrode, and the second electrode 13 is a cathode of an organic light emitting diode.
  • both are greater than the second ratio, that is, the amount of oxygen introduced when the second oxide semiconductor layer 42 is deposited is greater than the first oxide.
  • the material semiconductor layer 42 has a high oxygen content and a large number of oxygen vacancies, which can increase the conductivity of the active layer 4 and increase the electron mobility of the thin film transistor device, and the first oxide semiconductor layer 41 and the third oxide.
  • the semiconductor layer 43 has a low oxygen content, which can reduce the contact interface between the active layer 4 and the buffer layer 3 and the contact interface between the active layer 4 and the gate insulating layer 6, thereby improving the stability of the thin film transistor device.
  • the present invention provides a method for fabricating an OLED backplane, which is obtained by sequentially depositing a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer to obtain a thin film transistor.
  • the oxygen content of the first oxide semiconductor layer and the third oxide semiconductor layer is greater than the oxygen content of the second oxide semiconductor layer, thereby improving the conductivity of the active layer of the thin film transistor device, reducing interface defects, and improving the stability of the thin film transistor device. Sex.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Geometry (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明提供一种OLED背板的制作方法。该方法通过依次沉积第一氧化物半导体层、第二氧化物半导体层、及第三氧化物半导体层，得到薄膜晶体管的有源层，通过使得第一氧化物半导体层和第三氧化物半导体层沉积时通入的氩气和氧气的流量比大于第二氧化物半导体层沉积时通入的氩气和氧气的流量比，使得第一氧化物半导体层和第三氧化物半导体层的氧含量大于第二氧化物半导体层的氧含量，从而提升薄膜晶体管器件的有源层的导电性，减少界面缺陷，提升薄膜晶体管器件的稳定性。

Description

OLED背板的制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种OLED背板的制作方法。
背景技术
平面显示器件具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有的平面显示器件主要包括液晶显示器件(Liquid Crystal Display，LCD)及有机发光二极管显示器件(Organic Light Emitting Display，OLED)。
有机发光二极管显示器件由于同时具备自发光，不需背光源、对比度高、厚度薄、视角广、反应速度快、可用于挠曲性面板、使用温度范围广、构造及制程较简单等优异特性，被认为是下一代平面显示器的新兴应用技术。OLED显示装置通常包括：基板、设于基板上的阳极、设于阳极上的有机发光层、以及设于有机发光层上的阴极。工作时向有机发光层发射来自阳极的空穴和来自阴极的电子，将这些电子和空穴组合产生激发性电子-空穴对，并将激发性电子-空穴对从受激态转换为基态实现发光。
OLED显示装置按照驱动方式可以分为无源矩阵型OLED(Passive Matrix OLED，PMOLED)和有源矩阵型OLED(Active Matrix OLED，AMOLED)两大类，即直接寻址和薄膜晶体管(Thin Film Transistor，TFT)矩阵寻址两类。其中，AMOLED具有呈阵列式排布的像素，属于主动显示类型，发光效能高，性能优异。
现有技术中常用的薄膜晶体管包括非晶硅(a-Si)薄膜晶体管、低温多晶硅(Low Temperature Poly-silicon，LTPS)薄膜晶体管以及氧化物半导体(Oxide semiconductor)薄膜晶体管，氧化物半导体薄膜晶体管由于具有较高的电子迁移率，而且相比低温多晶硅薄膜晶体管，氧化物半导体薄膜晶体管制程简单，与非晶硅薄膜晶体管制程相容性较高，而得到了广泛应用。
在氧化物半导体薄膜晶体管中其有源层(即氧化物半导体层)中的氧含量对器件特性影响很大，目前氧化物半导体薄膜晶体管中的有源层一般采用单一膜层的设计，这种单一膜层的有源层通过一次沉积形成，若是在沉积时氧气流量较大，则会使得有源层的含氧量过高，导电性变差，器件迁移率降低；而若是沉积时氧气流量较小，则会使得有源层中的含氧量过低，氧空位过多，导致有源层与缓冲层的接触界面及有源层与栅极绝缘层的接触界面处的界面缺陷增都，器件稳定性变差。
发明内容
本发明的目的在于提供一种OLED背板的制作方法，能够提升薄膜晶体管器件的有源层的导电性，减少界面缺陷，提升薄膜晶体管器件的稳定性。
为实现上述目的，本发明提供了一种OLED背板的制作方法，包括如下步骤：
步骤S1、提供一衬底基板，在所述衬底基板上形成缓冲层；
步骤S2、在所述缓冲层上沉积第一氧化物半导体层，在沉积的同时通入氩气和氧气，所述氩气和氧气的流量比为第一比值；
步骤S3、在所述第一氧化物半导体层上沉积第二氧化物半导体层，在沉积的同时通入氩气和氧气，所述氩气和氧气的流量比为第二比值；
步骤S4、在所述第二氧化物半导体层上沉积第三氧化物半导体层，在沉积的同时通入氩气和氧气，所述氩气和氧气的流量比为第三比值，得到包括所述第一氧化物半导体层、第二氧化物半导体层、及第三氧化物半导体层的有源层；
步骤S5、在所述有源层上形成栅极绝缘层和位于所述栅极绝缘层上的栅极；
步骤S6、在所述有源层、栅极、栅极绝缘层上覆盖层间绝缘层；
步骤S7、在所述层间绝缘层上形成源极、和漏极；
所述第一比值和第三比值均大于所述第二比值。
所述第一比值和第三比值均为2：1至4：1，所述第二比值为10：1至20：1。
所述第一氧化物半导体层及第三氧化物半导体层的厚度为50至
Figure PCTCN2017113513-appb-000001
所述第二氧化物半导体层的厚度为200至
Figure PCTCN2017113513-appb-000002
所述第一氧化物半导体层、第二氧化物半导体层、及第三氧化物半导体层的材料均为IGZO，所述缓冲层和栅极绝缘层的材料均为氧化硅和氮化硅中的一种或二者的组合。
所述步骤S1还包括：在所述衬底基板和缓冲层之间形成遮光层，所述遮光层遮挡所述有源层。
所述步骤S5具体包括：
在所述有源层和缓冲层上沉积栅极绝缘薄膜，在所述栅极绝缘薄膜上沉积栅极金属薄膜；
通过一道光罩制程图案化所述栅极金属薄膜，形成栅极；
以所述栅极为遮挡，蚀刻所述栅极绝缘薄膜，形成栅极绝缘层。
所述步骤S5中所述栅极和栅极绝缘层覆盖所述有源层的中央，并暴露所述有源层的两端；
在所述步骤S5和步骤S6之间还包括如下步骤：对所述有源层进行等离子处理，使得所述有源层的两端的电阻降低，形成N+导体层。
所述步骤S6中还包括：对所述层间绝缘层进行图案化，形成暴露出所述有源层的两端的第一过孔和第二过孔，所述步骤S7中源极和漏极分别通过第一过孔和第二过孔与所述有源层的两端接触。
所述OLED背板的制作方法还包括：
步骤S8、在所述层间绝缘层、源极、和漏极上沉积钝化层，并对所述钝化层进行图案化，形成暴露出所述漏极的第三过孔；
步骤S9、在所述钝化层上形成第一电极，所述第一电极通过所述第三过孔与所述漏极接触；
步骤S10、在所述第一电极和钝化层上形成像素定义层，并对所述像素定义层进行图案化，形成暴露出所述第一电极的像素定义槽；
步骤S11、在所述像素定义槽内形成有机发光层，在所述像素定义层和有机发光层上形成第二电极。
所述第一电极为透明电极，所述第二电极为反射电极。
本发明还提供一种OLED背板的制作方法，包括如下步骤：
步骤S1、提供一衬底基板，在所述衬底基板上形成缓冲层；
步骤S2、在所述缓冲层上沉积第一氧化物半导体层，在沉积的同时通入氩气和氧气，所述氩气和氧气的流量比为第一比值；
步骤S3、在所述第一氧化物半导体层上沉积第二氧化物半导体层，在沉积的同时通入氩气和氧气，所述氩气和氧气的流量比为第二比值；
步骤S4、在所述第二氧化物半导体层上沉积第三氧化物半导体层，在沉积的同时通入氩气和氧气，所述氩气和氧气的流量比为第三比值，得到包括所述第一氧化物半导体层、第二氧化物半导体层、及第三氧化物半导体层的有源层；
步骤S5、在所述有源层上形成栅极绝缘层和位于所述栅极绝缘层上的栅极；
步骤S6、在所述有源层、栅极、及栅极绝缘层上覆盖层间绝缘层；
步骤S7、在所述层间绝缘层上形成源极和漏极；
所述第一比值和第三比值均大于所述第二比值；
其中，所述第一比值和第三比值均为2：1至4：1，所述第二比值为 10：1至20：1；
其中，所述第一氧化物半导体层及第三氧化物半导体层的厚度为50至
Figure PCTCN2017113513-appb-000003
所述第二氧化物半导体层的厚度为200至
Figure PCTCN2017113513-appb-000004
其中，所述第一氧化物半导体层、第二氧化物半导体层、及第三氧化物半导体层的材料均为IGZO，所述缓冲层和栅极绝缘层的材料均为氧化硅和氮化硅中的一种或二者的组合；
其中，所述步骤S1还包括：在所述衬底基板和缓冲层之间形成遮光层，所述遮光层遮挡所述有源层；
其中，所述步骤S5具体包括：
在所述有源层和缓冲层上沉积栅极绝缘薄膜，在所述栅极绝缘薄膜上沉积栅极金属薄膜；
通过一道光罩制程图案化所述栅极金属薄膜，形成栅极；
以所述栅极为遮挡蚀刻所述栅极绝缘薄膜，形成栅极绝缘层。
本发明的有益效果：本发明提供一种OLED背板的制作方法，该方法通过依次沉积第一氧化物半导体层、第二氧化物半导体层、及第三氧化物半导体层，得到薄膜晶体管的有源层，通过使得第一氧化物半导体层和第三氧化物半导体层沉积时通入的氩气和氧气的流量比大于第二氧化物半导体层沉积时通入的氩气和氧气的流量比，使得第一氧化物半导体层和第三氧化物半导体层的氧含量大于第二氧化物半导体层的氧含量，从而提升薄膜晶体管器件的有源层的导电性，减少界面缺陷，提升薄膜晶体管器件的稳定性。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1至图2为本发明的OLED背板的制作方法的步骤S1的示意图；
图3为本发明的OLED背板的制作方法的步骤S2的示意图；
图4为本发明的OLED背板的制作方法的步骤S3的示意图；
图5为本发明的OLED背板的制作方法的步骤S4的示意图；
图6为本发明的OLED背板的制作方法的步骤S5的示意图；
图7为本发明的OLED背板的制作方法的步骤S6的示意图；
图8为本发明的OLED背板的制作方法的步骤S7的示意图；
图9为本发明的OLED背板的制作方法的步骤S8的示意图；
图10为本发明的OLED背板的制作方法的步骤S9的示意图；
图11为本发明的OLED背板的制作方法的步骤S10的示意图；
图12为本发明的OLED背板的制作方法的步骤S11的示意图；
图13为本发明的OLED背板的制作方法的流程图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图13，本发明提供一种OLED背板的制作方法，包括如下步骤：
步骤S1、请参阅图1和图2，提供一衬底基板1，在所述衬底基板1上形成缓冲层3。
在具体实施时，如图1所示，所述步骤S1还可以进一步包括：在所述衬底基板1上沉积遮光金属薄膜，对所述遮光金属薄膜进行图案化，得到对应于待形成有源层4的区域形成遮光层2，所述缓冲层3覆盖所述遮光层2和衬底基板1，所述遮光层2用于遮挡后续形成的有源层4，以防止有源层4因光照而导致器件性能产生变化。
优选地，所述缓冲层3的材料为氧化硅(SiOx)和氮化硅(SiNx)中的一种或二者的组合，所述缓冲层3的厚度为5000至
Figure PCTCN2017113513-appb-000005
步骤S2、请参阅图3，在所述缓冲层3上沉积第一氧化物半导体层41，在沉积的同时通入氩气和氧气，所述氩气和氧气的流量比为第一比值。
具体地，所述第一氧化物半导体层41的厚度为50至
Figure PCTCN2017113513-appb-000006
步骤S3、请参阅图4，在所述第一氧化物半导体层41上沉积第二氧化物半导体层42，在沉积的同时通入氩气和氧气，所述氩气和氧气的流量比为第二比值。
具体地，所述第二氧化物半导体层41的厚度为200至
Figure PCTCN2017113513-appb-000007
步骤S4、请参阅图5，在所述第二氧化物半导体层42上沉积第三氧化物半导体层43，在沉积的同时通入氩气和氧气，所述氩气和氧气的流量比为第三比值，得到包括所述第一氧化物半导体层41、第二氧化物半导体层42、及第三氧化物半导体层43的有源层4。
具体地，所述第三氧化物半导体层43的厚度为50至
Figure PCTCN2017113513-appb-000008
其中，所述第一比值和第三比值均大于所述第二比值，优选地，所述第一比值和第三比值均为2：1至4：1，所述第二比值为10：1至20：1，更优选地，所述第一比值和第三比值均为4：1，所述第二比值为20：1。
优选地，所述第一氧化物半导体层41、第二氧化物半导体层42、及第三氧化物半导体层43的材料均为IGZO。
步骤S5、请参阅图6，在所述有源层4上形成栅极绝缘层5和位于所述栅极绝缘层上的栅极6。
具体地，所述步骤S5具体包括：在所述有源层4和缓冲层3上沉积栅极绝缘薄膜，在所述栅极绝缘薄膜上沉积栅极金属薄膜；通过一道光罩制程图案化所述栅极金属薄膜，形成栅极6；以所述栅极为遮挡，蚀刻所述栅极绝缘薄膜，形成栅极绝缘层5
进一步地，所述步骤S5中所述栅极6和栅极绝缘层5覆盖所述有源层4的中央，并暴露所述有源层4的两端。
优选地，所述栅极绝缘层5的材料为氧化硅和氮化硅中的一种或二者的组合。所述栅极6的材料为钼、铝、铜、及钛等金属中的一种或多种的组合。所述栅极绝缘层5的厚度为1000至
Figure PCTCN2017113513-appb-000009
所述栅极6的厚度为2000至
Figure PCTCN2017113513-appb-000010
步骤S6、请参阅图7，在所述有源层4、栅极6、及栅极绝缘层5上覆盖层间绝缘层7。
具体地，在所述步骤S5和步骤S6之间还包括如下步骤：对所述有源层4进行等离子处理，使得所述有源层4的两端的电阻降低，形成N+导体层，而所述有源层4的中央被所述栅极绝缘层5和栅极6遮挡，仍保持半导体特性，以作为作为薄膜晶体管器件的沟道区。
进一步地，所述步骤S6还包括：对所述层间绝缘层7进行图案化，形成暴露出所述有源层的两端的第一过孔71和第二过孔72。
优选地，所述层间绝缘层7的厚度为2000至
Figure PCTCN2017113513-appb-000011
步骤S7、请参阅图8，在所述层间绝缘层上形成源极81和漏极82。
具体地，所述步骤S7中源极81和漏极82分别通过第一过孔71和第二过孔72与所述有源层4的两端接触。
所述步骤S7具体包括：先沉积一源漏极金属薄膜，随后通过一道光罩制程对所述源漏极金属薄膜进行图案化，形成所述源极81和漏极82。
优选地，所述源极81和漏极82的材料为钼、铝、铜、及钛等金属中的一种或多种的组合，所述源极81和漏极82的厚度均为2000至
Figure PCTCN2017113513-appb-000012
步骤S8、请参阅图9，在所述层间绝缘层7、源极81、和漏极82上沉积钝化层9，并对所述钝化层9进行图案化，形成暴露出所述漏极82的第三过孔91。
优选地，所述钝化层9的材料为氧化硅或氮化硅中的一种或多种的组 合，所述钝化层9的厚度为1000至
Figure PCTCN2017113513-appb-000013
步骤S9、请参阅图10，在所述钝化层9上形成第一电极10，所述第一电极10通过所述第三过孔91与所述漏极82接触。
优选地，所述第一电极10为透明电极，优选材料为氧化铟锡(ITO)，所述第一电极10为有机发光二极管的阳极。
步骤S10、请参阅图11，在所述第一电极10和钝化层9上形成像素定义层11，并对所述像素定义层11进行图案化，形成暴露出所述第一电极10的像素定义槽111。
步骤S11、请参阅图12，在所述像素定义槽111内形成有机发光层12，在所述像素定义层11和有机发光层12上形成第二电极13。
具体地，所述有机发光层12可以包括：自下而上依次层叠的空穴传输功能层、发光功能层、及电子传输功能层。优选地，所述第二电极13为反射电极，所述第二电极13为有机发光二极管的阴极。
需要说明的是，通过设置所述第一比值和第三比值均大于所述第二比值，也即使得所述第二氧化物半导体层42沉积时通入的氧气量大于所述第一氧化物半导体层41及第三氧化物半导体层43时通入的氧气量，从而使得位于所述有源层4的中间的第二氧化物半导体层42的氧含量大于与缓冲层3接触的第一氧化物半导体层41及与栅极绝缘层6接触的第三氧化物半导体层43的氧含量，也即所述有源层4的中间的含量高，上下两侧的含量低，所述第二氧化物半导体层42的氧含量高，氧空位多，可以增大所述有源层4的导电性，提升薄膜晶体管器件的电子迁移率，而所述第一氧化物半导体层41及第三氧化物半导体层43的氧含量低，可以减少有源层4与缓冲层3的接触界面、及有源层4与栅极绝缘层6的接触界面的缺陷，提升薄膜晶体管器件的稳定性。
综上所述，本发明提供一种OLED背板的制作方法，该方法通过依次沉积第一氧化物半导体层、第二氧化物半导体层、及第三氧化物半导体层，得到薄膜晶体管的有源层，通过使得第一氧化物半导体层和第三氧化物半导体层沉积时通入的氩气和氧气的流量比大于第二氧化物半导体层沉积时通入的氩气和氧气的流量比，使得第一氧化物半导体层和第三氧化物半导体层的氧含量大于第二氧化物半导体层的氧含量，从而提升薄膜晶体管器件的有源层的导电性，减少界面缺陷，提升薄膜晶体管器件的稳定性。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (15)

  1. 一种OLED背板的制作方法，包括如下步骤：
    步骤S1、提供一衬底基板，在所述衬底基板上形成缓冲层；
    步骤S2、在所述缓冲层上沉积第一氧化物半导体层，在沉积的同时通入氩气和氧气，所述氩气和氧气的流量比为第一比值；
    步骤S3、在所述第一氧化物半导体层上沉积第二氧化物半导体层，在沉积的同时通入氩气和氧气，所述氩气和氧气的流量比为第二比值；
    步骤S4、在所述第二氧化物半导体层上沉积第三氧化物半导体层，在沉积的同时通入氩气和氧气，所述氩气和氧气的流量比为第三比值，得到包括所述第一氧化物半导体层、第二氧化物半导体层、及第三氧化物半导体层的有源层；
    步骤S5、在所述有源层上形成栅极绝缘层和位于所述栅极绝缘层上的栅极；
    步骤S6、在所述有源层、栅极、及栅极绝缘层上覆盖层间绝缘层；
    步骤S7、在所述层间绝缘层上形成源极和漏极；
    所述第一比值和第三比值均大于所述第二比值。
  2. 如权利要求1所述的OLED背板的制作方法，其中，所述第一比值和第三比值均为2：1至4：1，所述第二比值为10：1至20：1。
  3. 如权利要求1所述的OLED背板的制作方法，其中，所述第一氧化物半导体层及第三氧化物半导体层的厚度为50至
    Figure PCTCN2017113513-appb-100001
    所述第二氧化物半导体层的厚度为200至
    Figure PCTCN2017113513-appb-100002
  4. 如权利要求1所述的OLED背板的制作方法，其中，所述第一氧化物半导体层、第二氧化物半导体层、及第三氧化物半导体层的材料均为IGZO，所述缓冲层和栅极绝缘层的材料均为氧化硅和氮化硅中的一种或二者的组合。
  5. 如权利要求1所述的OLED背板的制作方法，其中，所述步骤S1还包括：在所述衬底基板和缓冲层之间形成遮光层，所述遮光层遮挡所述有源层。
  6. 如权利要求1所述的OLED背板的制作方法，其中，所述步骤S5具体包括：
    在所述有源层和缓冲层上沉积栅极绝缘薄膜，在所述栅极绝缘薄膜上沉积栅极金属薄膜；
    通过一道光罩制程图案化所述栅极金属薄膜，形成栅极；
    以所述栅极为遮挡蚀刻所述栅极绝缘薄膜，形成栅极绝缘层。
  7. 如权利要求1所述的OLED背板的制作方法，其中，所述步骤S5中所述栅极和栅极绝缘层覆盖所述有源层的中央，并暴露所述有源层的两端；
    在所述步骤S5和步骤S6之间还包括如下步骤：对所述有源层进行等离子处理，使得所述有源层的两端的电阻降低，形成N+导体层。
  8. 如权利要求1所述的OLED背板的制作方法，其中，所述步骤S6还包括：对所述层间绝缘层进行图案化，形成分别暴露出所述有源层的两端的第一过孔和第二过孔，所述步骤S7中源极和漏极分别通过第一过孔和第二过孔与所述有源层的两端接触。
  9. 如权利要求1所述的OLED背板的制作方法，还包括：
    步骤S8、在所述层间绝缘层、源极、和漏极上沉积钝化层，并对所述钝化层进行图案化，形成暴露出所述漏极的第三过孔；
    步骤S9、在所述钝化层上形成第一电极，所述第一电极通过所述第三过孔与所述漏极接触；
    步骤S10、在所述第一电极和钝化层上形成像素定义层，并对所述像素定义层进行图案化，形成暴露出所述第一电极的像素定义槽；
    步骤S11、在所述像素定义槽内形成有机发光层，在所述像素定义层和有机发光层上形成第二电极。
  10. 如权利要求9所述的OLED背板的制作方法，其中，所述第一电极为透明电极，所述第二电极为反射电极。
  11. 一种OLED背板的制作方法，包括如下步骤：
    步骤S1、提供一衬底基板，在所述衬底基板上形成缓冲层；
    步骤S2、在所述缓冲层上沉积第一氧化物半导体层，在沉积的同时通入氩气和氧气，所述氩气和氧气的流量比为第一比值；
    步骤S3、在所述第一氧化物半导体层上沉积第二氧化物半导体层，在沉积的同时通入氩气和氧气，所述氩气和氧气的流量比为第二比值；
    步骤S4、在所述第二氧化物半导体层上沉积第三氧化物半导体层，在沉积的同时通入氩气和氧气，所述氩气和氧气的流量比为第三比值，得到包括所述第一氧化物半导体层、第二氧化物半导体层、及第三氧化物半导体层的有源层；
    步骤S5、在所述有源层上形成栅极绝缘层和位于所述栅极绝缘层上的栅极；
    步骤S6、在所述有源层、栅极、及栅极绝缘层上覆盖层间绝缘层；
    步骤S7、在所述层间绝缘层上形成源极和漏极；
    所述第一比值和第三比值均大于所述第二比值；
    其中，所述第一比值和第三比值均为2：1至4：1，所述第二比值为10：1至20：1；
    其中，所述第一氧化物半导体层及第三氧化物半导体层的厚度为50至
    Figure PCTCN2017113513-appb-100003
    所述第二氧化物半导体层的厚度为200至
    Figure PCTCN2017113513-appb-100004
    其中，所述第一氧化物半导体层、第二氧化物半导体层、及第三氧化物半导体层的材料均为IGZO，所述缓冲层和栅极绝缘层的材料均为氧化硅和氮化硅中的一种或二者的组合；
    其中，所述步骤S1还包括：在所述衬底基板和缓冲层之间形成遮光层，所述遮光层遮挡所述有源层；
    其中，所述步骤S5具体包括：
    在所述有源层和缓冲层上沉积栅极绝缘薄膜，在所述栅极绝缘薄膜上沉积栅极金属薄膜；
    通过一道光罩制程图案化所述栅极金属薄膜，形成栅极；
    以所述栅极为遮挡蚀刻所述栅极绝缘薄膜，形成栅极绝缘层。
  12. 如权利要求11所述的OLED背板的制作方法，其中，所述步骤S5中所述栅极和栅极绝缘层覆盖所述有源层的中央，并暴露所述有源层的两端；
    在所述步骤S5和步骤S6之间还包括如下步骤：对所述有源层进行等离子处理，使得所述有源层的两端的电阻降低，形成N+导体层。
  13. 如权利要求11所述的OLED背板的制作方法，其中，所述步骤S6还包括：对所述层间绝缘层进行图案化，形成分别暴露出所述有源层的两端的第一过孔和第二过孔，所述步骤S7中源极和漏极分别通过第一过孔和第二过孔与所述有源层的两端接触。
  14. 如权利要求11所述的OLED背板的制作方法，还包括：
    步骤S8、在所述层间绝缘层、源极、和漏极上沉积钝化层，并对所述钝化层进行图案化，形成暴露出所述漏极的第三过孔；
    步骤S9、在所述钝化层上形成第一电极，所述第一电极通过所述第三过孔与所述漏极接触；
    步骤S10、在所述第一电极和钝化层上形成像素定义层，并对所述像素定义层进行图案化，形成暴露出所述第一电极的像素定义槽；
    步骤S11、在所述像素定义槽内形成有机发光层，在所述像素定义层和 有机发光层上形成第二电极。
  15. 如权利要求14所述的OLED背板的制作方法，其中，所述第一电极为透明电极，所述第二电极为反射电极。
PCT/CN2017/113513 2017-10-24 2017-11-29 Oled背板的制作方法 WO2019080252A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020207014609A KR102299370B1 (ko) 2017-10-24 2017-11-29 Oled 백플레인의 제조 방법
US15/742,814 US10658446B2 (en) 2017-10-24 2017-11-29 Method for manufacturing OLED backplane comprising active layer formed of first, second, and third oxide semiconductor layers
EP17929670.2A EP3703112A4 (en) 2017-10-24 2017-11-29 OLED REAR PANEL MANUFACTURING PROCESS
JP2020513706A JP2020532877A (ja) 2017-10-24 2017-11-29 Ｏｌｅｄ背板の製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201711004263.X 2017-10-24
CN201711004263.XA CN107611085B (zh) 2017-10-24 2017-10-24 Oled背板的制作方法

Publications (1)

Publication Number Publication Date
WO2019080252A1 true WO2019080252A1 (zh) 2019-05-02

Family

ID=61079871

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/113513 WO2019080252A1 (zh) 2017-10-24 2017-11-29 Oled背板的制作方法

Country Status (6)

Country Link
US (1) US10658446B2 (zh)
EP (1) EP3703112A4 (zh)
JP (1) JP2020532877A (zh)
KR (1) KR102299370B1 (zh)
CN (1) CN107611085B (zh)
WO (1) WO2019080252A1 (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3874546B1 (en) 2018-11-01 2023-08-02 Boe Technology Group Co., Ltd. Light emitting diode and fabrication method thereof, array substrate and display panel
CN109755260A (zh) * 2018-12-24 2019-05-14 惠科股份有限公司 一种显示面板、显示面板的制造方法和显示装置
CN110190066A (zh) * 2019-05-14 2019-08-30 深圳市华星光电技术有限公司 阵列基板和阵列基板的制备方法
CN110854204B (zh) * 2019-11-26 2023-10-20 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、像素电路及显示面板
CN111180466B (zh) * 2020-01-06 2023-09-05 深圳市华星光电半导体显示技术有限公司 阵列基板及其制备方法、显示面板
CN111430414A (zh) * 2020-03-31 2020-07-17 京东方科技集团股份有限公司 Oled显示面板及制备方法、显示装置
US11721767B2 (en) * 2020-06-29 2023-08-08 Taiwan Semiconductor Manufacturing Company Limited Oxide semiconductor transistor structure in 3-D device and methods of forming the same
CN113113424B (zh) * 2021-03-17 2024-02-02 武汉华星光电半导体显示技术有限公司 显示面板
CN116314017B (zh) * 2023-05-18 2023-10-27 长鑫存储技术有限公司 半导体结构及其制造方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080246392A1 (en) * 2007-03-07 2008-10-09 Sam-Il Kho Donor substrate, method of fabricating the same, and organic light emitting diode display device
CN104022044A (zh) * 2013-03-01 2014-09-03 北京京东方光电科技有限公司 氧化物薄膜晶体管及其制备方法、阵列基板和显示装置
CN106298958A (zh) * 2016-10-13 2017-01-04 中山大学 氧化物薄膜晶体管及制备方法、显示装置及照相装置
CN106876280A (zh) * 2017-04-24 2017-06-20 京东方科技集团股份有限公司 薄膜晶体管及其制备方法
CN107104150A (zh) * 2017-05-02 2017-08-29 深圳市华星光电技术有限公司 金属氧化物tft器件及其制作方法
CN107123671A (zh) * 2017-05-19 2017-09-01 电子科技大学 基于有机绝缘层的梯度掺杂igzo薄膜晶体管及其制备方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5497417B2 (ja) * 2009-12-10 2014-05-21 富士フイルム株式会社 薄膜トランジスタおよびその製造方法、並びにその薄膜トランジスタを備えた装置
US9153699B2 (en) * 2012-06-15 2015-10-06 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor with multiple oxide semiconductor layers
KR102243843B1 (ko) * 2012-08-03 2021-04-22 가부시키가이샤 한도오따이 에네루기 켄큐쇼 산화물 반도체 적층막 및 반도체 장치
US20150008428A1 (en) * 2013-07-08 2015-01-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
KR102045036B1 (ko) * 2013-08-27 2019-11-14 엘지디스플레이 주식회사 고 개구율 유기발광 다이오드 표시장치 및 그 제조 방법
JP2017076788A (ja) * 2015-10-12 2017-04-20 株式会社半導体エネルギー研究所 半導体装置の作製方法
WO2017153882A1 (en) * 2016-03-11 2017-09-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, manufacturing method thereof, and display device including the semiconductor device
KR102662278B1 (ko) * 2016-11-30 2024-05-02 엘지디스플레이 주식회사 유기 발광 표시 장치 및 그 제조 방법

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080246392A1 (en) * 2007-03-07 2008-10-09 Sam-Il Kho Donor substrate, method of fabricating the same, and organic light emitting diode display device
CN104022044A (zh) * 2013-03-01 2014-09-03 北京京东方光电科技有限公司 氧化物薄膜晶体管及其制备方法、阵列基板和显示装置
CN106298958A (zh) * 2016-10-13 2017-01-04 中山大学 氧化物薄膜晶体管及制备方法、显示装置及照相装置
CN106876280A (zh) * 2017-04-24 2017-06-20 京东方科技集团股份有限公司 薄膜晶体管及其制备方法
CN107104150A (zh) * 2017-05-02 2017-08-29 深圳市华星光电技术有限公司 金属氧化物tft器件及其制作方法
CN107123671A (zh) * 2017-05-19 2017-09-01 电子科技大学 基于有机绝缘层的梯度掺杂igzo薄膜晶体管及其制备方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3703112A4 *

Also Published As

Publication number Publication date
EP3703112A1 (en) 2020-09-02
US10658446B2 (en) 2020-05-19
JP2020532877A (ja) 2020-11-12
CN107611085A (zh) 2018-01-19
CN107611085B (zh) 2019-12-24
EP3703112A4 (en) 2021-07-14
US20190386083A1 (en) 2019-12-19
KR102299370B1 (ko) 2021-09-08
KR20200067890A (ko) 2020-06-12

Similar Documents

Publication Publication Date Title
US10497620B2 (en) TFT substrate and manufacturing method thereof and manufacturing method of OLED panel
WO2018227750A1 (zh) 柔性tft基板的制作方法
US10403757B2 (en) Top-gate self-aligned metal oxide semiconductor TFT and method of making the same
WO2019080252A1 (zh) Oled背板的制作方法
CN106847743B (zh) Tft基板及其制作方法
US20210183977A1 (en) Display panel and method of fabricating same
US9450101B2 (en) Thin film transistor, array substrate and display apparatus
WO2016176886A1 (zh) 柔性oled及其制作方法
US10249652B2 (en) Manufacturing method of flexible TFT substrate
CN108054192A (zh) 柔性amoled基板及其制作方法
WO2015103837A1 (zh) 薄膜晶体管及其制作方法、阵列基板及有机发光显示面板
JP2013168632A (ja) 薄膜トランジスタ、薄膜トランジスタアレイ基板及びそれらの製造方法
US20150069378A1 (en) Thin film transistor array substrate, method of manufacturing the same, and display apparatus including the same
WO2018049744A1 (zh) Amoled像素驱动电路的制作方法
WO2016176879A1 (zh) Amoled背板的制作方法及其结构
WO2015100808A1 (zh) 一种具有氧化物薄膜电晶体的发光装置及其制造方法
WO2019100464A1 (zh) 背沟道蚀刻型氧化物半导体tft基板的制作方法
US20230088235A1 (en) Display panel and method for manufacturing same
CN110071148A (zh) 有机发光二极管显示装置及其制造方法
KR20110135681A (ko) 산화물 반도체를 이용한 박막트랜지스터 기판의 제조방법
US20170263735A1 (en) Method of Manufacturing Thin Film Transistor (TFT) and TFT
CN107808885B (zh) 背沟道蚀刻型氧化物半导体tft基板及其制作方法
WO2019100492A1 (zh) 背沟道蚀刻型tft基板及其制作方法
US11217698B2 (en) Method of manufacturing a thin film transistor
KR20080102665A (ko) 박막 트랜지스터 및 이를 포함하는 표시장치

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17929670

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2020513706

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 20207014609

Country of ref document: KR

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 2017929670

Country of ref document: EP

Effective date: 20200525