WO2019100492A1 - 背沟道蚀刻型tft基板及其制作方法 - Google Patents

背沟道蚀刻型tft基板及其制作方法 Download PDF

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WO2019100492A1
WO2019100492A1 PCT/CN2017/117327 CN2017117327W WO2019100492A1 WO 2019100492 A1 WO2019100492 A1 WO 2019100492A1 CN 2017117327 W CN2017117327 W CN 2017117327W WO 2019100492 A1 WO2019100492 A1 WO 2019100492A1
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layer
source
drain
gate
material layer
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PCT/CN2017/117327
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English (en)
French (fr)
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姜春生
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深圳市华星光电半导体显示技术有限公司
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Priority to US15/749,105 priority Critical patent/US10355035B2/en
Publication of WO2019100492A1 publication Critical patent/WO2019100492A1/zh

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Definitions

  • the present invention relates to the field of display technologies, and in particular, to a back channel etch type TFT substrate and a method of fabricating the same.
  • Liquid crystal display has many advantages such as thin body, power saving, no radiation, etc., and is widely used, such as mobile phones, personal digital assistants (PDAs), digital cameras, computer screens or laptops. Screen, etc.
  • OLED Organic Light-Emitting Diode
  • OLED Organic Light-Emitting Diode
  • the working temperature has wide adaptability, light volume, fast response, easy to realize color display and large screen display, easy to realize integration with integrated circuit driver, easy to realize flexible display, and the like, and thus has broad application prospects.
  • OLED can be divided into two types: passive matrix OLED (PMOLED) and active matrix OLED (AMOLED), namely direct addressing and thin film transistor matrix addressing.
  • PMOLED passive matrix OLED
  • AMOLED active matrix OLED
  • the AMOLED has pixels arranged in an array, belongs to an active display type, has high luminous efficiency, and is generally used as a high-definition large-sized display device.
  • Thin Film Transistor is the main driving component in current liquid crystal display devices and active matrix OLED display devices, and is directly related to the development direction of high performance flat panel display devices.
  • the thin film transistor has various structures, and the material of the thin film transistor for preparing the corresponding structure is also various, and an amorphous silicon (a-Si) material is a relatively common one.
  • the conventional a-Si has a mobility of only about 1 cm 2 /(Vs) which cannot meet the requirements, and indium gallium zinc oxide (IGZO)
  • IGZO indium gallium zinc oxide
  • the representative metal oxide material has a mobility of more than 10 cm 2 /(Vs) or more, and the preparation of the corresponding thin film transistor is compatible with the existing a-Si semiconductor-driven production line, and has rapidly developed into a display field in recent years. the key of.
  • IGZO TFTs Compared to traditional a-Si TFTs, IGZO TFTs have the following advantages:
  • the resolution of the IGZO TFT display backplane can be more than twice that of the a-Si TFT, and the carrier concentration in the IGZO material is high.
  • the mobility is large, which can reduce the size of the TFT and ensure the resolution is improved;
  • IGZO TFT has a leakage current of less than 1pA; the driving frequency is reduced from the original 30-50Hz to 2-5Hz, and even 1Hz can be achieved through a special process.
  • the alignment of the liquid crystal molecules can be maintained without affecting the quality of the picture, thereby reducing the power consumption of the display backplane; in addition, the high mobility of the IGZO semiconductor material allows a smaller size TFT to provide sufficient The charging capacity and the higher capacitance value, and the aperture ratio of the liquid crystal panel is increased, the effective area of light penetration is increased, and the same brightness can be achieved with less backplane components or low power consumption, thereby reducing energy consumption;
  • IGZO as a semiconductor active layer TFT generally adopts an etch barrier (ESL) structure, and an etch barrier layer is used in the source/drain etching process due to the existence of an etch stop layer (Etch Stop Layer). It can effectively protect IGZO from being affected and ensure that the TFT has excellent semiconductor characteristics.
  • ESL etch barrier
  • Etch Stop Layer etch stop layer
  • the preparation process of the IGZO TFT of the ESL structure is complicated, and it is necessary to go through 6 times of yellow light process, which is disadvantageous for cost reduction. Therefore, the industry generally pursues the development of an IGZO TFT with a less back channel etching (BCE) structure with a yellow light process.
  • the source and drain electrodes are covered with a passivation layer (PV).
  • the passivation layer of the IGZO TFT is usually made of silicon oxide (SiOx), and the source and drain metal is made of copper (Cu). Since the bonding strength between copper and silicon oxide is very poor, During the preparation of the TFT substrate, the passivation layer film on the source and drain metal is lifted up to form a bubble, thereby affecting the yield.
  • the present invention provides a method for fabricating a back channel etched TFT substrate, comprising:
  • a source/drain material layer on the active layer and the gate insulating layer Depositing a source/drain material layer on the active layer and the gate insulating layer, the source/drain material layer a first source/drain material layer disposed on the active layer and the gate insulating layer, a second source/drain material layer disposed on the first source/drain material layer, and a second layer a third source/drain material layer on the source/drain material layer, the material of the first source/drain material layer comprises molybdenum, and the material of the second source/drain material layer comprises copper, the third source drain
  • the material layer is a conductive IGZO film layer;
  • the source drain pattern region includes a source predetermined pattern region and a drain predetermined pattern a region and a source-drain spacer region between the source predetermined pattern region and the drain predetermined pattern region;
  • a passivation layer is formed on the source, the drain, the active layer, and the gate insulating layer.
  • the preparation method of the conductive IGZO film layer is magnetron sputtering.
  • the gate includes a first gate layer disposed on the substrate and a second gate layer disposed on the first gate layer, and the material of the first gate layer includes molybdenum
  • the material of the second gate layer includes copper.
  • the material of the active layer includes indium gallium zinc oxide.
  • the material of the passivation layer includes silicon oxide.
  • the present invention also provides a back channel etched TFT substrate, comprising: a substrate substrate, a gate electrode disposed on the substrate substrate, a gate insulating layer disposed on the substrate substrate and the gate electrode, and a gate insulating layer An active layer on the gate insulating layer, a source and a drain disposed on the active layer and spaced apart from each other, and on the source, the drain, the active layer and the gate insulating layer Passivation layer
  • the source and drain electrodes are patterned by a source/drain material layer, and the source/drain material layer includes a first source/drain material layer disposed on the active layer, and is disposed on the first source and drain a second source/drain material layer on the electrode material layer and a third source/drain material layer disposed on the second source/drain material layer, wherein the material of the first source/drain material layer comprises molybdenum,
  • the material of the second source/drain material layer includes copper, and the third source/drain material layer is a conductive IGZO film layer.
  • the gate includes a first gate layer disposed on the substrate and a second gate layer disposed on the first gate layer, and the material of the first gate layer includes molybdenum
  • the material of the second gate layer includes copper.
  • the material of the active layer includes indium gallium zinc oxide.
  • the material of the passivation layer includes silicon oxide.
  • the present invention also provides a method for fabricating a back channel etched TFT substrate, comprising:
  • the source/drain material layer including a first source/drain material layer disposed on the active layer and the gate insulating layer a second source/drain material layer on the first source/drain material layer and a third source/drain material layer on the second source/drain material layer, the first source/drain material layer
  • the material includes molybdenum, the material of the second source/drain material layer comprises copper, and the third source/drain material layer is a conductive IGZO film layer;
  • the source drain pattern region includes a source predetermined pattern region and a drain predetermined pattern a region and a source-drain spacer region between the source predetermined pattern region and the drain predetermined pattern region;
  • the preparation method of the conductive IGZO film layer is magnetron sputtering.
  • the gate includes a first gate layer disposed on the substrate and a second gate layer disposed on the first gate layer, and the material of the first gate layer includes molybdenum
  • the material of the second gate layer comprises copper
  • the material of the active layer comprises indium gallium zinc oxide
  • the material of the passivation layer comprises silicon oxide.
  • the method for fabricating the back channel etched TFT substrate of the present invention has the surface layer of the source and the drain be set as a conductive IGZO film layer, because the bonding force between the conductive IGZO film layer and the silicon oxide is better. Strong, so the bubbling and lifting phenomenon of the passivation layer can be avoided; in addition, the fluorine-free etching solution is used to etch and remove the spacer between the source and the drain during the fabrication of the source and the drain. Damage is caused to the channel region of the active layer.
  • the back channel etch type TFT substrate of the present invention has a surface layer of a source and a drain as a conductor IGZO film layer, and since a bonding force between the conductor IGZO film layer and the silicon oxide is strong, a passivation layer does not occur. Bubbling and lifting.
  • FIG. 1 is a flow chart showing a method of fabricating a back channel etched TFT substrate of the present invention
  • FIG. 2 is a schematic view showing a step S1 of a method of fabricating a back channel etched TFT substrate of the present invention
  • FIG. 3 is a schematic view showing a step S2 of a method of fabricating a back channel etched TFT substrate of the present invention
  • FIG. 4 is a schematic view showing a step S3 of a method of fabricating a back channel etched TFT substrate of the present invention
  • FIG. 10 are schematic diagrams showing a step S4 of a method of fabricating a back channel etched TFT substrate according to the present invention.
  • FIG. 11 is a schematic view showing a step S5 of a method of fabricating a back channel etched TFT substrate of the present invention and a schematic structural view of a back channel etched TFT substrate of the present invention.
  • the present invention provides a method for fabricating a back channel etched TFT substrate, including the following steps:
  • Step S1 as shown in FIG. 2, a substrate substrate 10 is provided, a metal material is deposited on the substrate substrate 10, and a gate electrode 20 is formed by etching, and a gate insulating layer is formed on the substrate substrate 10 and the gate electrode 20.
  • Layer 30 As shown in FIG. 2, a substrate substrate 10 is provided, a metal material is deposited on the substrate substrate 10, and a gate electrode 20 is formed by etching, and a gate insulating layer is formed on the substrate substrate 10 and the gate electrode 20.
  • Layer 30 as shown in FIG. 2
  • the gate 20 includes a first gate layer 21 disposed on the base substrate 10 and a second gate layer 22 disposed on the first gate layer 21, the first gate
  • the material of the pole layer 21 includes molybdenum
  • the material of the second gate layer 22 includes copper.
  • Step S2 as shown in FIG. 3, an active layer 40 is formed on the gate insulating layer 30.
  • the material of the active layer 40 includes indium gallium zinc oxide (IGZO).
  • IGZO indium gallium zinc oxide
  • the active layer 40 is obtained by a sputtering deposition process and a lithography patterning process.
  • Step S3 as shown in FIG. 4, a source/drain material layer 70 is deposited on the active layer 40 and the gate insulating layer 30, and the source/drain material layer 70 is disposed on the active layer 40 and the gate.
  • the method for preparing the conductive IGZO film layer is magnetron sputtering.
  • the invention reduces the oxygen content in the obtained conductive IGZO film layer by removing oxygen in the reaction chamber during the magnetron sputtering process, thereby realizing the conductor function.
  • Step S4 as shown in FIG. 5 to FIG. 6, a source drain pattern region 71 and a non-pattern region 72 disposed around the source/drain pattern region 71 are defined on the source/drain material layer 70, wherein the The source drain pattern region 71 includes a source predetermined pattern region 711, a drain predetermined pattern region 712, and a source and drain spacer region 713 between the source predetermined pattern region 711 and the drain predetermined pattern region 712;
  • a photoresist layer 80 is formed on the source/drain material layer 70, and the photoresist layer 80 is patterned by using a halftone mask 90 to remove the photoresist layer 80 corresponding to the non-pattern region 72. In part, the thickness of the portion of the photoresist layer 80 corresponding to the source and drain spacers 713 is thinned;
  • the non-pattern region 72 of the source/drain material layer 70 is etched away by using a fluorine-containing etchant; the fluorine-containing etchant can simultaneously treat the third source/drain material layer 43, the second source.
  • the drain material layer 42 and the first source/drain material layer 41 are etched, and the fluorine-containing etchant is applied to the third source/drain material layer 43, the second source/drain material layer 42, and the first source/drain material layer. 41 has a faster etch rate.
  • the fluorine-containing etching liquid is a fluorine-containing acid copper etching liquid, and the specific composition thereof is a prior art, which will not be described here.
  • the remaining photoresist layer 80 is subjected to ashing treatment, and a portion of the photoresist layer 80 corresponding to the source/drain spacer 713 is removed, so that the photoresist layer 80 corresponds to the source.
  • the thickness of the portion of the pole predetermined pattern region 711 and the drain predetermined pattern region 712 is thinned;
  • the source/drain spacer 713 of the source/drain material layer 70 is etched and removed by using a fluorine-free etchant; the fluorine-free etchant can simultaneously treat the third source/drain material layer 43, The two source drain material layer 42 and the first source/drain material layer 41 are etched, and the fluorine-free etchant has a faster etching rate to the second source/drain material layer 42 and the first source/drain material layer 41.
  • the third source/drain material layer 43 has a slower etching rate, that is, the etching rate of the fluorine-free etching solution to the IGZO is smaller than the etching rate of the fluorine-containing etching liquid to the IGZO.
  • the etching rate of the IGZO is slower than that of the fluorine-free etching solution, when the source/drain spacer 713 of the source/drain material layer 70 is etched by using the fluorine-free etching solution, the etching time can be ensured by the IGZO material.
  • the channel region of the active layer 40 is not damaged, improving the stability of the TFT device.
  • the fluorine-free etching solution is a fluorine-free acid copper etching solution, and the specific composition thereof is prior art, which is not described herein.
  • the remaining photoresist layer 80 is peeled off to obtain source 51 and drain 52 which are spaced apart.
  • the inventors of the present application have tried to prepare a third source/drain material layer 43 by using another metal material such as titanium instead of the conductor IGZO to enhance the bonding force between the source 51 and the drain 52 and the silicon oxide, but using a metal.
  • the second source drain material layer 42 prepared by copper tends to form a solution cell between the third source drain material layer 43 prepared from other metal materials, resulting in an electrochemical reaction that occurs during the etching of the source and drain material layer 70.
  • the third source/drain material layer 43 layer prepared from other metal materials is easily etched away, causing the photoresist layer 80 above the third source/drain material layer 43 to be stripped off, thereby causing the source 51 and the drain.
  • the lithography process of 52 failed.
  • the present application uses a conductive IGZO material to prepare a third source/drain material layer 43 to enhance the bonding force between the source 51 and the drain 52 and the silicon oxide, and the third source/drain material layer 43 of the conductive IGZO material.
  • a solution cell is not formed between the second source/drain material layer 42 of the metallic copper material, and no electrochemical reaction occurs, so during the etching of the source/drain material layer 70, the third source/drain material layer 43 is not Will be dissolved, and the photoresist layer 80 above it will not be peeled off.
  • Step S5 as shown in FIG. 11, a passivation layer 60 is formed on the source 51, the drain 52, the active layer 40, and the gate insulating layer 30.
  • the material of the passivation layer 60 includes silicon oxide (SiOx).
  • the passivation layer 60 can be avoided. Bubbling and lifting occurred.
  • the surface layer of the source 51 and the drain 52 is provided as a conductive IGZO film layer, and since the bonding force between the conductive IGZO film layer and the silicon oxide is strong, The bubbling and lifting phenomenon of the passivation layer 60 is avoided; in addition, the spacer region between the source 51 and the drain 52 is etched and removed by using a fluorine-free etching solution during the fabrication of the source 51 and the drain 52, Damage to the channel region of the active layer 40 is caused.
  • the present invention provides a back channel etch type TFT substrate, comprising: a substrate substrate 10, a gate electrode 20 on the base substrate 10, a gate insulating layer 30 provided on the base substrate 10 and the gate electrode 20, and an active layer 40 provided on the gate insulating layer 30. a source 51 and a drain 52 disposed on the active layer 40 and a passivation layer 60 disposed on the source 51, the drain 52, the active layer 40, and the gate insulating layer 30;
  • the source and drain electrodes 51 and the drain electrode 52 are patterned by a source/drain material layer 70.
  • the source and drain material layer 70 includes a first source/drain material layer 41 disposed on the active layer 40. a second source/drain material layer 42 on the first source/drain material layer 41 and a third source/drain material layer 43 disposed on the second source/drain material layer 42, the first source drain
  • the material of the pole material layer 41 includes molybdenum
  • the material of the second source/drain material layer 42 includes copper
  • the third source/drain material layer 43 is a conductorized IGZO film layer.
  • the gate electrode 20 includes a first gate layer 21 disposed on the base substrate and a second gate layer 22 disposed on the first gate layer 21, the first gate
  • the material of layer 21 comprises molybdenum and the material of said second gate layer 22 comprises copper.
  • the material of the active layer 40 includes indium gallium zinc oxide (IGZO).
  • IGZO indium gallium zinc oxide
  • the back channel etch type TFT substrate of the present invention has the surface layer of the source 51 and the drain 52 as a conductor IGZO film layer, and since the bonding force between the conductor IGZO film layer and the silicon oxide is strong, bluntness does not occur. The phenomenon of bubbling and lifting of layer 60.
  • the present invention provides a back channel etch type TFT substrate and a method of fabricating the same.
  • the method for fabricating the back channel etched TFT substrate of the present invention has the surface layer of the source and the drain as a conductive IGZO film layer, and since the bonding force between the conductive IGZO film layer and the silicon oxide is strong, bluntness can be avoided Bubbling and lifting phenomenon occurs in the layer; in addition, the fluorine-free etching solution is used to etch and remove the spacer between the source and the drain during the fabrication of the source and the drain, and the active layer is not removed.
  • the channel area causes damage.
  • the back channel etch type TFT substrate of the present invention has a surface layer of a source and a drain as a conductor IGZO film layer, and since a bonding force between the conductor IGZO film layer and the silicon oxide is strong, a passivation layer does not occur. Bubbling and lifting.

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Abstract

提供一种背沟道蚀刻型TFT基板及其制作方法。该背沟道蚀刻型TFT基板的制作方法将源极(51)与漏极(52)的表层设置为导体化IGZO膜层，由于导体化IGZO膜层与氧化硅之间的结合力较强，因此可以避免钝化层(60)出现鼓泡和翘起现象；另外，在源极(51)与漏极(52)的制作过程中采用无氟蚀刻液对源极(51)与漏极(52)之间的间隔区进行蚀刻去除，不会对有源层(40)的沟道区造成损害。该背沟道蚀刻型TFT基板将源极(51)与漏极(52)的表层设置为导体化IGZO膜层，由于导体化IGZO膜层与氧化硅之间的结合力较强，因此不会出现钝化层(60)鼓泡和翘起的现象。

Description

背沟道蚀刻型TFT基板及其制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种背沟道蚀刻型TFT基板及其制作方法。
背景技术
液晶显示装置(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用，如：移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等。
有机发光二极管(Organic Light-Emitting Diode，OLED)显示器，也称为有机电致发光显示器，是一种新兴的平板显示装置，由于其具有制备工艺简单、成本低、功耗低、发光亮度高、工作温度适应范围广、体积轻薄、响应速度快，而且易于实现彩色显示和大屏幕显示、易于实现和集成电路驱动器相匹配、易于实现柔性显示等优点，因而具有广阔的应用前景。
OLED按照驱动方式可以分为无源矩阵型OLED(Passive Matrix OLED，PMOLED)和有源矩阵型OLED(Active Matrix OLED，AMOLED)两大类，即直接寻址和薄膜晶体管矩阵寻址两类。其中，AMOLED具有呈阵列式排布的像素，属于主动显示类型，发光效能高，通常用作高清晰度的大尺寸显示装置。
薄膜晶体管(Thin Film Transistor，简称TFT)是目前液晶显示装置和有源矩阵型OLED显示装置中的主要驱动元件，直接关系到高性能平板显示装置的发展方向。薄膜晶体管具有多种结构，制备相应结构的薄膜晶体管的材料也具有多种，非晶硅(a-Si)材料是比较常见的一种。
随着液晶显示装置和OLED显示装置向着大尺寸和高分辨率的方向发展，传统的a-Si仅有1cm2/(Vs)左右的迁移率已经无法满足要求，以铟镓锌氧化物(IGZO)为代表的金属氧化物材料具备超过10cm2/(Vs)以上的迁移率，而且相应薄膜晶体管的制备与现有的a-Si为半导体驱动的产线的兼容性好，近年来迅速成为显示领域研发的重点。
相对于传统的a-Si TFT，IGZO TFT具有以下优势：
1、提高显示背板的分辨率，在保证相同透过率的前提下，IGZO TFT显示背板的分辨率可以做到a-Si TFT的2倍以上，IGZO材料中的载流子浓度高，迁移率大，可以缩小TFT的体积，保证分辨率的提升；
2、减少显示器件的能耗，IGZO TFT与a-Si TFT、LTPS TFT相比，漏电流小于1pA；驱动频率由原来的30-50Hz减少到2-5Hz，通过特殊工艺，甚至可以达到1Hz，虽然减少TFT的驱动次数，仍然可以维持液晶分子的配向，不影响画面的质量，从而减少显示背板的耗电量；另外，IGZO半导体材料的高迁移率使得较小尺寸的TFT即可提供足够的充电能力和较高的电容值，而且提高了液晶面板的开口率，光穿透的有效面积变大，可以用较少的背板组件或低功率消耗达到相同的亮度，减少能耗；
3、通过采用间歇式驱动等方式，能够降低液晶显示器驱动电路的噪点对触摸屏检测电路造成的影响，可以实现更高的灵敏度，甚至尖头的圆珠笔笔端也能够响应，而且由于画面无更新时可以切断电源，因此其在节能的效果上表现更为优秀。
目前，IGZO作为半导体有源层的TFT一般采用刻蚀阻挡(ESL)结构，由于有刻蚀阻挡层(Etch Stop Layer)存在，源漏极(Source/Drain)的蚀刻过程中，刻蚀阻挡层可以有效的保护IGZO不受到影响，保证TFT具有优异的半导体特性。但是ESL结构的IGZO TFT的制备过程较为复杂，需要经过6次黄光工艺，不利于降低成本，因此业界普遍追求黄光工艺更少的背沟道蚀刻(BCE)结构的IGZO TFT的开发。
无论是ESL结构的TFT还是BCE结构的TFT，源漏极金属上均覆盖有钝化层(PV)。与a-Si TFT不同，IGZO TFT的钝化层的材质通常为氧化硅(SiOx)，源漏极金属的材质为铜(Cu)，由于铜与氧化硅之间的结合力非常差，因此在TFT基板的制备过程中，源漏极金属上的钝化层薄膜会翘起，形成鼓泡(Bubble)，从而影响良率。
发明内容
本发明的目的在于提供一种背沟道蚀刻型TFT基板的制作方法，能够避免钝化层出现鼓泡和翘起现象，同时不会对有源层的沟道区造成损害。
本发明的目的还在于提供一种背沟道蚀刻型TFT基板，其钝化层不会出现鼓泡和翘起现象，具有优异的电学特性。
为实现上述目的，本发明提供一种背沟道蚀刻型TFT基板的制作方法，包括：
提供衬底基板，在所述衬底基板上沉积金属材料并刻蚀形成栅极，在所述衬底基板及栅极上形成栅极绝缘层；
在所述栅极绝缘层上形成有源层；
在所述有源层与栅极绝缘层上沉积源漏极材料层，所述源漏极材料层 包括设于所述有源层与栅极绝缘层上的第一源漏极材料层、设于所述第一源漏极材料层上的第二源漏极材料层以及设于所述第二源漏极材料层上的第三源漏极材料层，所述第一源漏极材料层的材料包括钼，所述第二源漏极材料层的材料包括铜，所述第三源漏极材料层为导体化IGZO膜层；
在源漏极材料层上定义出源漏极图案区与设于所述源漏极图案区周围的非图案区，其中，所述源漏极图案区包括源极预定图案区、漏极预定图案区及位于源极预定图案区与漏极预定图案区之间的源漏极间隔区；
在所述源漏极材料层上形成光阻层，采用半色调掩膜板对所述光阻层进行图形化处理，去除所述光阻层上对应于非图案区的部分，使所述光阻层上对应于源漏极间隔区的部分的厚度减薄；
采用含氟蚀刻液对所述源漏极材料层的非图案区进行蚀刻去除；
对剩余的光阻层进行灰化处理，去除所述光阻层上对应于源漏极间隔区的部分，使所述光阻层上对应于所述源极预定图案区与漏极预定图案区的部分的厚度减薄；
采用无氟蚀刻液对所述源漏极材料层的源漏极间隔区进行蚀刻去除；
剥离剩余的光阻层，得到间隔设置的源极与漏极；
在所述源极、漏极、有源层及栅极绝缘层上形成钝化层。
所述导体化IGZO膜层的制备方法为磁控溅射，磁控溅射过程中，反应腔体内不添加氧气，得到的导体化IGZO膜层中铟镓锌氧的摩尔比为In：Ga：Zn：O＝1：1：1：X，其中X小于4。
所述栅极包括设于所述衬底基板上的第一栅极层与设于所述第一栅极层上的第二栅极层，所述第一栅极层的材料包括钼，所述第二栅极层的材料包括铜。
所述有源层的材料包括铟镓锌氧化物。
所述钝化层的材料包括氧化硅。
本发明还提供一种背沟道蚀刻型TFT基板，包括：衬底基板、设于所述衬底基板上的栅极、设于所述衬底基板及栅极上的栅极绝缘层、设于所述栅极绝缘层上的有源层、设于所述有源层上且间隔设置的源极与漏极以及设于所述源极、漏极、有源层及栅极绝缘层上的钝化层；
所述源极与漏极由源漏极材料层图案化形成，所述源漏极材料层包括设于所述有源层上的第一源漏极材料层、设于所述第一源漏极材料层上的第二源漏极材料层以及设于所述第二源漏极材料层上的第三源漏极材料层，所述第一源漏极材料层的材料包括钼，所述第二源漏极材料层的材料包括铜，所述第三源漏极材料层为导体化IGZO膜层。
所述导体化IGZO膜层中铟镓锌氧的摩尔比为In：Ga：Zn：O＝1：1：1：X，其中X小于4。
所述栅极包括设于所述衬底基板上的第一栅极层与设于所述第一栅极层上的第二栅极层，所述第一栅极层的材料包括钼，所述第二栅极层的材料包括铜。
所述有源层的材料包括铟镓锌氧化物。
所述钝化层的材料包括氧化硅。
本发明还提供一种背沟道蚀刻型TFT基板的制作方法，包括：
提供衬底基板，在所述衬底基板上沉积金属材料并刻蚀形成栅极，在所述衬底基板及栅极上形成栅极绝缘层；
在所述栅极绝缘层上形成有源层；
在所述有源层与栅极绝缘层上沉积源漏极材料层，所述源漏极材料层包括设于所述有源层与栅极绝缘层上的第一源漏极材料层、设于所述第一源漏极材料层上的第二源漏极材料层以及设于所述第二源漏极材料层上的第三源漏极材料层，所述第一源漏极材料层的材料包括钼，所述第二源漏极材料层的材料包括铜，所述第三源漏极材料层为导体化IGZO膜层；
在源漏极材料层上定义出源漏极图案区与设于所述源漏极图案区周围的非图案区，其中，所述源漏极图案区包括源极预定图案区、漏极预定图案区及位于源极预定图案区与漏极预定图案区之间的源漏极间隔区；
在所述源漏极材料层上形成光阻层，采用半色调掩膜板对所述光阻层进行图形化处理，去除所述光阻层上对应于非图案区的部分，使所述光阻层上对应于源漏极间隔区的部分的厚度减薄；
采用含氟蚀刻液对所述源漏极材料层的非图案区进行蚀刻去除；
对剩余的光阻层进行灰化处理，去除所述光阻层上对应于源漏极间隔区的部分，使所述光阻层上对应于所述源极预定图案区与漏极预定图案区的部分的厚度减薄；
采用无氟蚀刻液对所述源漏极材料层的源漏极间隔区进行蚀刻去除；所述无氟蚀刻液对IGZO的蚀刻速度小于所述含氟蚀刻液对IGZO的蚀刻速度；
剥离剩余的光阻层，得到间隔设置的源极与漏极；
在所述源极、漏极、有源层及栅极绝缘层上形成钝化层；
其中，所述导体化IGZO膜层的制备方法为磁控溅射，磁控溅射过程中，反应腔体内不添加氧气，得到的导体化IGZO膜层中铟镓锌氧的摩尔比为In：Ga：Zn：O＝1：1：1：X，其中X小于4；
其中，所述栅极包括设于所述衬底基板上的第一栅极层与设于所述第一栅极层上的第二栅极层，所述第一栅极层的材料包括钼，所述第二栅极层的材料包括铜；
其中，所述有源层的材料包括铟镓锌氧化物；
其中，所述钝化层的材料包括氧化硅。
本发明的有益效果：本发明的背沟道蚀刻型TFT基板的制作方法将源极与漏极的表层设置为导体化IGZO膜层，由于导体化IGZO膜层与氧化硅之间的结合力较强，因此可以避免钝化层出现鼓泡和翘起现象；另外，在源极与漏极的制作过程中采用无氟蚀刻液对源极与漏极之间的间隔区进行蚀刻去除，不会对有源层的沟道区造成损害。本发明的背沟道蚀刻型TFT基板将源极与漏极的表层设置为导体化IGZO膜层，由于导体化IGZO膜层与氧化硅之间的结合力较强，因此不会出现钝化层鼓泡和翘起的现象。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为本发明的背沟道蚀刻型TFT基板的制作方法的流程图；
图2为本发明的背沟道蚀刻型TFT基板的制作方法的步骤S1的示意图；
图3为本发明的背沟道蚀刻型TFT基板的制作方法的步骤S2的示意图；
图4为本发明的背沟道蚀刻型TFT基板的制作方法的步骤S3的示意图；
图5至图10为本发明的背沟道蚀刻型TFT基板的制作方法的步骤S4的示意图；
图11为本发明的背沟道蚀刻型TFT基板的制作方法的步骤S5的示意图及本发明的背沟道蚀刻型TFT基板的结构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，本发明提供一种背沟道蚀刻型TFT基板的制作方法，包括如下步骤：
步骤S1、如图2所示，提供衬底基板10，在所述衬底基板10上沉积金属材料并刻蚀形成栅极20，在所述衬底基板10及栅极20上形成栅极绝缘层30。
具体的，所述栅极20包括设于所述衬底基板10上的第一栅极层21与设于所述第一栅极层21上的第二栅极层22，所述第一栅极层21的材料包括钼，所述第二栅极层22的材料包括铜。
步骤S2、如图3所示，在所述栅极绝缘层30上形成有源层40。
具体的，所述有源层40的材料包括铟镓锌氧化物(IGZO)。
具体的，所述有源层40通过溅射沉积制程与光刻图案化制程得到。
步骤S3、如图4所示，在所述有源层40与栅极绝缘层30上沉积源漏极材料层70，所述源漏极材料层70包括设于所述有源层40与栅极绝缘层30上的第一源漏极材料层41、设于所述第一源漏极材料层41上的第二源漏极材料层42以及设于所述第二源漏极材料层42上的第三源漏极材料层43，所述第一源漏极材料层41的材料包括钼，所述第二源漏极材料层42的材料包括铜，所述第三源漏极材料层43为导体化IGZO膜层。
具体的，所述导体化IGZO膜层的制备方法为磁控溅射，磁控溅射过程中，反应腔体内不添加氧气，得到的导体化IGZO膜层中铟镓锌氧的摩尔比为In：Ga：Zn：O＝1：1：1：X，其中X小于4。
正常情况下，IGZO的磁控溅射过程中，反应腔体内会通入氧气，保证得到的IGZO膜层中铟镓锌氧的比例为In：Ga：Zn：O＝1：1：1：4，从而保证IGZO膜层具有半导体特性。本发明通过去除磁控溅射过程中反应腔体内的氧气，使制得的导体化IGZO膜层中的氧含量降低，实现导体化功能。
步骤S4、如图5至图6所示，在源漏极材料层70上定义出源漏极图案区71与设于所述源漏极图案区71周围的非图案区72，其中，所述源漏极图案区71包括源极预定图案区711、漏极预定图案区712及位于源极预定图案区711与漏极预定图案区712之间的源漏极间隔区713；
在所述源漏极材料层70上形成光阻层80，采用半色调掩膜板90对所述光阻层80进行图形化处理，去除所述光阻层80上对应于非图案区72的部分，使所述光阻层80上对应于源漏极间隔区713的部分的厚度减薄；
如图7所示，采用含氟蚀刻液对所述源漏极材料层70的非图案区72进行蚀刻去除；所述含氟蚀刻液能够同时对第三源漏极材料层43、第二源漏极材料层42及第一源漏极材料层41进行蚀刻，并且所述含氟蚀刻液对第三源漏极材料层43、第二源漏极材料层42及第一源漏极材料层41均具有较快的蚀刻速度。
具体的，所述含氟蚀刻液为含氟酸性铜蚀刻液，其具体成分为现有技术，此处不做介绍。
如图8所示，对剩余的光阻层80进行灰化处理，去除所述光阻层80上对应于源漏极间隔区713的部分，使所述光阻层80上对应于所述源极预定图案区711与漏极预定图案区712的部分的厚度减薄；
如图9所示，采用无氟蚀刻液对所述源漏极材料层70的源漏极间隔区713进行蚀刻去除；所述无氟蚀刻液能够同时对第三源漏极材料层43、第二源漏极材料层42及第一源漏极材料层41进行蚀刻，并且所述无氟蚀刻液对第二源漏极材料层42与第一源漏极材料层41具有较快的蚀刻速度，对第三源漏极材料层43具有较慢的蚀刻速度，即，所述无氟蚀刻液对IGZO的蚀刻速度小于所述含氟蚀刻液对IGZO的蚀刻速度。
由于无氟蚀刻液对IGZO的蚀刻速度较慢，因此采用无氟蚀刻液对所述源漏极材料层70的源漏极间隔区713进行蚀刻时，通过控制蚀刻时间可以保证由IGZO材料制备的有源层40的沟道区不受到损害，提升TFT器件稳定性。
具体的，所述无氟蚀刻液为无氟酸性铜蚀刻液，其具体成分为现有技术，此处不做介绍。
如图10所示，剥离剩余的光阻层80，得到间隔设置的源极51与漏极52。
本申请发明人试验过采用其它金属材料(如钛)代替导体化IGZO来制备第三源漏极材料层43，以增强源极51和漏极52与氧化硅之间的结合力，但是采用金属铜制备的第二源漏极材料层42往往与由其它金属材料制备的第三源漏极材料层43之间形成溶液电池，导致发生电化学反应，从而在源漏极材料层70的蚀刻过程中，由其它金属材料制备的第三源漏极材料层43层容易被腐蚀溶解掉，导致第三源漏极材料层43上方的光阻层80被剥离掉，进而导致源极51和漏极52的光刻制程失败。而本申请采用导体化IGZO材料来制备第三源漏极材料层43，以增强源极51和漏极52与氧化硅之间的结合力，导体化IGZO材料的第三源漏极材料层43与金属铜材料的第二源漏极材料层42之间不会形成溶液电池，不会发生电化学反应，因此在源漏极材料层70的蚀刻过程中，第三源漏极材料层43不会被溶解，其上方的光阻层80不会被剥离掉。
步骤S5、如图11所示，在所述源极51、漏极52、有源层40及栅极绝缘层30上形成钝化层60。
具体的，所述钝化层60的材料包括氧化硅(SiOx)。
由于所述源极51与漏极52的表层即第三源漏极材料层43的材料为导体化IGZO，而导体化IGZO与氧化硅之间的结合力较强，因此可以避免钝化层60出现鼓泡和翘起现象。
本发明的背沟道蚀刻型TFT基板的制作方法将源极51与漏极52的表层设置为导体化IGZO膜层，由于导体化IGZO膜层与氧化硅之间的结合力较强，因此可以避免钝化层60出现鼓泡和翘起现象；另外，在源极51与漏极52的制作过程中采用无氟蚀刻液对源极51与漏极52之间的间隔区进行蚀刻去除，不会对有源层40的沟道区造成损害。
请参阅图11，同时参阅图2至图10，基于上述背沟道蚀刻型TFT基板的制作方法，本发明提供一种背沟道蚀刻型TFT基板，包括：衬底基板10、设于所述衬底基板10上的栅极20、设于所述衬底基板10及栅极20上的栅极绝缘层30、设于所述栅极绝缘层30上的有源层40、设于所述有源层40上且间隔设置的源极51与漏极52以及设于所述源极51、漏极52、有源层40及栅极绝缘层30上的钝化层60；
所述源极51与漏极52由源漏极材料层70图案化形成，所述源漏极材料层70包括设于所述有源层40上的第一源漏极材料层41、设于所述第一源漏极材料层41上的第二源漏极材料层42以及设于所述第二源漏极材料层42上的第三源漏极材料层43，所述第一源漏极材料层41的材料包括钼，所述第二源漏极材料层42的材料包括铜，所述第三源漏极材料层43为导体化IGZO膜层。
具体的，所述导体化IGZO膜层中铟镓锌氧的摩尔比为In：Ga：Zn：O＝1：1：1：X，其中X小于4。
具体的，所述栅极20包括设于所述衬底基板上的第一栅极层21与设于所述第一栅极层21上的第二栅极层22，所述第一栅极层21的材料包括钼，所述第二栅极层22的材料包括铜。
具体的，所述有源层40的材料包括铟镓锌氧化物(IGZO)。
本发明的背沟道蚀刻型TFT基板将源极51与漏极52的表层设置为导体化IGZO膜层，由于导体化IGZO膜层与氧化硅之间的结合力较强，因此不会出现钝化层60鼓泡和翘起的现象。
综上所述，本发明提供一种背沟道蚀刻型TFT基板及其制作方法。本发明的背沟道蚀刻型TFT基板的制作方法将源极与漏极的表层设置为导体化IGZO膜层，由于导体化IGZO膜层与氧化硅之间的结合力较强，因此可以避免钝化层出现鼓泡和翘起现象；另外，在源极与漏极的制作过程中采用无氟蚀刻液对源极与漏极之间的间隔区进行蚀刻去除，不会对有源层的 沟道区造成损害。本发明的背沟道蚀刻型TFT基板将源极与漏极的表层设置为导体化IGZO膜层，由于导体化IGZO膜层与氧化硅之间的结合力较强，因此不会出现钝化层鼓泡和翘起的现象。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (11)

  1. 一种背沟道蚀刻型TFT基板的制作方法，包括：
    提供衬底基板，在所述衬底基板上沉积金属材料并刻蚀形成栅极，在所述衬底基板及栅极上形成栅极绝缘层；
    在所述栅极绝缘层上形成有源层；
    在所述有源层与栅极绝缘层上沉积源漏极材料层，所述源漏极材料层包括设于所述有源层与栅极绝缘层上的第一源漏极材料层、设于所述第一源漏极材料层上的第二源漏极材料层以及设于所述第二源漏极材料层上的第三源漏极材料层，所述第一源漏极材料层的材料包括钼，所述第二源漏极材料层的材料包括铜，所述第三源漏极材料层为导体化IGZO膜层；
    在源漏极材料层上定义出源漏极图案区与设于所述源漏极图案区周围的非图案区，其中，所述源漏极图案区包括源极预定图案区、漏极预定图案区及位于源极预定图案区与漏极预定图案区之间的源漏极间隔区；
    在所述源漏极材料层上形成光阻层，采用半色调掩膜板对所述光阻层进行图形化处理，去除所述光阻层上对应于非图案区的部分，使所述光阻层上对应于源漏极间隔区的部分的厚度减薄；
    采用含氟蚀刻液对所述源漏极材料层的非图案区进行蚀刻去除；
    对剩余的光阻层进行灰化处理，去除所述光阻层上对应于源漏极间隔区的部分，使所述光阻层上对应于所述源极预定图案区与漏极预定图案区的部分的厚度减薄；
    采用无氟蚀刻液对所述源漏极材料层的源漏极间隔区进行蚀刻去除；所述无氟蚀刻液对IGZO的蚀刻速度小于所述含氟蚀刻液对IGZO的蚀刻速度；
    剥离剩余的光阻层，得到间隔设置的源极与漏极；
    在所述源极、漏极、有源层及栅极绝缘层上形成钝化层。
  2. 如权利要求1所述的背沟道蚀刻型TFT基板的制作方法，其中，所述导体化IGZO膜层的制备方法为磁控溅射，磁控溅射过程中，反应腔体内不添加氧气，得到的导体化IGZO膜层中铟镓锌氧的摩尔比为In：Ga：Zn：O＝1：1：1：X，其中X小于4。
  3. 如权利要求1所述的背沟道蚀刻型TFT基板的制作方法，其中，所述栅极包括设于所述衬底基板上的第一栅极层与设于所述第一栅极层上的第二栅极层，所述第一栅极层的材料包括钼，所述第二栅极层的材料包括 铜。
  4. 如权利要求1所述的背沟道蚀刻型TFT基板的制作方法，其中，所述有源层的材料包括铟镓锌氧化物。
  5. 如权利要求1所述的背沟道蚀刻型TFT基板的制作方法，其中，所述钝化层的材料包括氧化硅。
  6. 一种背沟道蚀刻型TFT基板，包括：衬底基板、设于所述衬底基板上的栅极、设于所述衬底基板及栅极上的栅极绝缘层、设于所述栅极绝缘层上的有源层、设于所述有源层上且间隔设置的源极与漏极以及设于所述源极、漏极、有源层及栅极绝缘层上的钝化层；
    所述源极与漏极由源漏极材料层图案化形成，所述源漏极材料层包括设于所述有源层上的第一源漏极材料层、设于所述第一源漏极材料层上的第二源漏极材料层以及设于所述第二源漏极材料层上的第三源漏极材料层，所述第一源漏极材料层的材料包括钼，所述第二源漏极材料层的材料包括铜，所述第三源漏极材料层为导体化IGZO膜层。
  7. 如权利要求6所述的背沟道蚀刻型TFT基板，其中，所述导体化IGZO膜层中铟镓锌氧的摩尔比为In：Ga：Zn：O＝1：1：1：X，其中X小于4。
  8. 如权利要求6所述的背沟道蚀刻型TFT基板，其中，所述栅极包括设于所述衬底基板上的第一栅极层与设于所述第一栅极层上的第二栅极层，所述第一栅极层的材料包括钼，所述第二栅极层的材料包括铜。
  9. 如权利要求6所述的背沟道蚀刻型TFT基板，其中，所述有源层的材料包括铟镓锌氧化物。
  10. 如权利要求6所述的背沟道蚀刻型TFT基板，其中，所述钝化层的材料包括氧化硅。
  11. 一种背沟道蚀刻型TFT基板的制作方法，包括：
    提供衬底基板，在所述衬底基板上沉积金属材料并刻蚀形成栅极，在所述衬底基板及栅极上形成栅极绝缘层；
    在所述栅极绝缘层上形成有源层；
    在所述有源层与栅极绝缘层上沉积源漏极材料层，所述源漏极材料层包括设于所述有源层与栅极绝缘层上的第一源漏极材料层、设于所述第一源漏极材料层上的第二源漏极材料层以及设于所述第二源漏极材料层上的第三源漏极材料层，所述第一源漏极材料层的材料包括钼，所述第二源漏极材料层的材料包括铜，所述第三源漏极材料层为导体化IGZO膜层；
    在源漏极材料层上定义出源漏极图案区与设于所述源漏极图案区周围的非图案区，其中，所述源漏极图案区包括源极预定图案区、漏极预定图 案区及位于源极预定图案区与漏极预定图案区之间的源漏极间隔区；
    在所述源漏极材料层上形成光阻层，采用半色调掩膜板对所述光阻层进行图形化处理，去除所述光阻层上对应于非图案区的部分，使所述光阻层上对应于源漏极间隔区的部分的厚度减薄；
    采用含氟蚀刻液对所述源漏极材料层的非图案区进行蚀刻去除；
    对剩余的光阻层进行灰化处理，去除所述光阻层上对应于源漏极间隔区的部分，使所述光阻层上对应于所述源极预定图案区与漏极预定图案区的部分的厚度减薄；
    采用无氟蚀刻液对所述源漏极材料层的源漏极间隔区进行蚀刻去除；所述无氟蚀刻液对IGZO的蚀刻速度小于所述含氟蚀刻液对IGZO的蚀刻速度；
    剥离剩余的光阻层，得到间隔设置的源极与漏极；
    在所述源极、漏极、有源层及栅极绝缘层上形成钝化层；
    其中，所述导体化IGZO膜层的制备方法为磁控溅射，磁控溅射过程中，反应腔体内不添加氧气，得到的导体化IGZO膜层中铟镓锌氧的摩尔比为In：Ga：Zn：O＝1：1：1：X，其中X小于4；
    其中，所述栅极包括设于所述衬底基板上的第一栅极层与设于所述第一栅极层上的第二栅极层，所述第一栅极层的材料包括钼，所述第二栅极层的材料包括铜；
    其中，所述有源层的材料包括铟镓锌氧化物；
    其中，所述钝化层的材料包括氧化硅。
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