WO2016026178A1 - 氧化物半导体tft基板的制作方法及其结构 - Google Patents

氧化物半导体tft基板的制作方法及其结构 Download PDF

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WO2016026178A1
WO2016026178A1 PCT/CN2014/086259 CN2014086259W WO2016026178A1 WO 2016026178 A1 WO2016026178 A1 WO 2016026178A1 CN 2014086259 W CN2014086259 W CN 2014086259W WO 2016026178 A1 WO2016026178 A1 WO 2016026178A1
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layer
oxide semiconductor
island
shaped
substrate
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PCT/CN2014/086259
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French (fr)
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王俊
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深圳市华星光电技术有限公司
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Priority to US14/427,633 priority Critical patent/US9614036B2/en
Publication of WO2016026178A1 publication Critical patent/WO2016026178A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating an oxide semiconductor TFT substrate and a structure thereof.
  • the flat panel display device has many advantages such as thin body, power saving, no radiation, and has been widely used.
  • the conventional flat panel display device mainly includes a liquid crystal display (LCD) and an organic light emitting display (OLED).
  • OLED display-based OLED display technology Compared with mature LCD, OLED is an active light-emitting display with self-luminous, high contrast, wide viewing angle (up to 170°), fast response, high luminous efficiency, low operating voltage (3 ⁇ ) 10V), ultra-thin (thickness less than 2mm) and other advantages, with superior color display quality, wider viewing range and greater design flexibility.
  • TFTs Thin Film Transistors
  • LCDs LCDs, OLEDs, and electrophoretic display devices (EPDs).
  • EPDs electrophoretic display devices
  • Oxide semiconductor TFT technology is currently a popular technology. Since the carrier mobility of the oxide semiconductor is 20-30 times that of the amorphous silicon semiconductor, and having a high electron mobility, the charge and discharge rate of the TFT electrode can be greatly improved, the response speed of the pixel can be improved, and the pixel can be realized faster. The refresh rate and the ability to increase the line scan rate of pixels make it possible to produce ultra-high resolution flat panel display devices. Compared with low-temperature polysilicon (LTPS), oxide semiconductors are simple in process and highly compatible with amorphous silicon processes. They can be applied to LCD, OLED, flexible display, etc., and are compatible with high-generation production lines. Large, medium and small size display, with good application development prospects.
  • LTPS low-temperature polysilicon
  • the oxide semiconductor layer is generally in direct contact with the source/drain without any treatment, and an electrical connection is formed therebetween, but the ohmic contact resistance between the two is large, resulting in a large
  • the flat panel display device has a higher driving voltage and higher power consumption.
  • An object of the present invention is to provide a method for fabricating an oxide semiconductor TFT substrate, which is capable of The ohmic contact between the oxide semiconductor layer and the source/drain is improved, the ohmic contact resistance between the two is reduced, and the driving voltage of the flat panel display device is lowered, thereby effectively reducing the power consumption of the flat panel display device.
  • the present invention first provides a method for fabricating an oxide semiconductor TFT substrate, comprising the following steps:
  • Step 1 providing a substrate, depositing and patterning a first metal layer on the substrate to form a gate;
  • Step 2 depositing a gate insulating layer on the gate and the substrate;
  • Step 3 depositing and patterning an oxide semiconductor layer on the gate insulating layer to form an island-shaped oxide semiconductor layer directly above the gate;
  • Step 4 sequentially depositing an etch barrier layer and a photoresist layer on the island-shaped oxide semiconductor layer and the gate insulating layer, and then performing a yellow light process on the photoresist layer to form directly above the island-shaped oxide semiconductor layer An island-shaped photoresist layer, which is further etched to form an island-shaped etch barrier layer on the island-shaped oxide semiconductor layer;
  • the island-shaped etch barrier layer has a width smaller than a width of the oxide semiconductor layer; the island-shaped etch barrier layer covers an intermediate portion of the island-shaped oxide semiconductor layer to expose both sides of the oxide peninsula;
  • Step 5 performing ion implantation treatment on both sides of the island-shaped oxide semiconductor layer
  • Step 6 peeling the island photoresist layer from the island etching barrier layer
  • Step 7 depositing and patterning a second metal layer on the island-shaped etch barrier layer and the gate insulating layer to form a source/drain;
  • the source/drain are in contact with both side portions of the oxide semiconductor layer to form an electrical connection
  • Step 8 Depositing and patterning a protective layer on the source/drain and the etch barrier layer to form a via hole on one side of the island-shaped oxide semiconductor layer;
  • Step 9 depositing and patterning a pixel electrode layer on the protective layer
  • Step 10 The substrate obtained in the step 9 is annealed.
  • the patterning is achieved by a yellow light and etching process.
  • the island-shaped oxide semiconductor layer is an IGZO semiconductor layer.
  • the ion implantation treatment is realized by a hydrogen plasma treatment.
  • the material of the pixel electrode layer is ITO or IZO.
  • the material of the protective layer is SiO 2 or SiON.
  • the substrate is a glass substrate.
  • the present invention also provides an oxide semiconductor TFT substrate structure comprising a substrate, a gate on the substrate, a gate insulating layer on the gate and the substrate, and an island on the gate insulating layer directly above the gate.
  • An oxide peninsula body layer, an island-shaped etch barrier layer on the island-shaped oxide semiconductor layer, a source/drain on the island-shaped etch barrier layer and the gate insulating layer, and the source/drain and etch barrier layer a protective layer on the upper surface, and a pixel electrode layer on the protective layer;
  • the island-shaped oxide peninsula body layer includes an intermediate portion and two side portions, the two sides are subjected to ion implantation treatment; and the island-shaped etching barrier layer a width smaller than a width of the oxide semiconductor layer covering only the intermediate portion; the source/drain being in contact with the both side portions to form an electrical connection;
  • the protective layer having the island-shaped oxide semiconductor a via hole on one side of the layer, the pixel electrode layer filling the via hole in contact with the source
  • the island-shaped oxide semiconductor layer is an IGZO semiconductor layer
  • the material of the pixel electrode layer is ITO or IZO
  • the material of the protective layer is SiO 2 or SiON.
  • the substrate is a glass substrate.
  • the method for fabricating an oxide semiconductor TFT substrate of the present invention improves the conductivity of the both sides by performing ion implantation treatment on both sides of the island-shaped oxide peninsula layer.
  • Contact with the source/drain can improve the ohmic contact between the oxide semiconductor layer and the source/drain, reduce the ohmic contact resistance between the two, and reduce the driving voltage of the flat panel display device, thereby effectively reducing the flat panel display device.
  • FIG. 1 is a flow chart showing a method of fabricating an oxide semiconductor TFT substrate of the present invention
  • FIG. 2 is a schematic view showing the first step of the method for fabricating an oxide semiconductor TFT substrate of the present invention
  • FIG. 3 is a schematic view showing a step 2 of a method for fabricating an oxide semiconductor TFT substrate of the present invention
  • FIG. 4 is a schematic view showing a step 3 of a method for fabricating an oxide semiconductor TFT substrate of the present invention
  • FIG. 5 is a schematic view showing a step 4 of a method for fabricating an oxide semiconductor TFT substrate of the present invention
  • FIG. 6 is a schematic view showing a step 6 of a method for fabricating an oxide semiconductor TFT substrate of the present invention
  • FIG. 7 is a schematic view showing a step 7 of a method for fabricating an oxide semiconductor TFT substrate of the present invention.
  • FIG. 8 is a schematic view showing a step 8 of a method for fabricating an oxide semiconductor TFT substrate of the present invention.
  • Fig. 9 is a view showing the step 9 of the method for fabricating the oxide semiconductor TFT substrate of the present invention and the structure of the oxide semiconductor TFT substrate of the present invention.
  • the method for fabricating the oxide semiconductor TFT substrate includes the following steps:
  • Step 1 a substrate 1 is provided on which a first metal layer is deposited and patterned to form a gate 2.
  • the substrate 1 is a transparent substrate.
  • the substrate 1 is a glass substrate.
  • the yellow metal process is performed by a common mask, and the first metal layer is patterned by an etching process to form a desired gate 2.
  • Step 2 Referring to FIG. 3, a gate insulating layer 3 is deposited on the gate 2 and the substrate 1.
  • the gate insulation 3 completely covers the gate 2 and the substrate 1.
  • Step 3 an oxide semiconductor layer is deposited on the gate insulating layer 3 and patterned by a yellow light and an etching process to form an island-shaped oxide semiconductor layer 4 directly above the gate electrode 2.
  • the island-shaped oxide semiconductor layer 4 is an indium gallium zinc oxide (IGZO) semiconductor layer.
  • IGZO indium gallium zinc oxide
  • Step 4 referring to FIG. 5, an etching barrier layer and a photoresist layer are sequentially deposited on the island-shaped oxide semiconductor layer 4 and the gate insulating layer 3, and then the photoresist layer is subjected to a yellow light process to form the island.
  • the island-shaped photoresist layer 6 directly above the oxide semiconductor layer 4 is etched back to form an island-shaped etch barrier layer 5 on the island-shaped oxide semiconductor layer 4.
  • the width of the island-shaped etch barrier layer 5 is smaller than the width of the oxide semiconductor layer 4; the island-shaped etch barrier layer 5 covers the intermediate portion 41 of the island-shaped oxide semiconductor layer 4 to expose the oxide peninsula Both sides of the body 43.
  • Step 5 Perform ion implantation treatment on both side portions 43 of the island-shaped oxide semiconductor layer 4.
  • the ion implantation process is performed by hydrogen plasma treatment (H2 Plasma).
  • H2 Plasma hydrogen plasma treatment
  • a large amount of H 2 ions are implanted into both side portions 43 of the island-shaped oxide semiconductor layer 4, which reduces the forbidden band width of the both side portions 43 and improves the conductivity thereof, thereby reducing the
  • the ohmic contact resistance between the island-shaped oxide semiconductor layer 4 and the source/drain electrodes 7 formed in the subsequent step 7 is described.
  • the specific material is selected to implant a specific ion to achieve the doping purpose, and the ohmic contact resistance between the island-shaped oxide semiconductor layer 4 and the source/drain 7 formed in the subsequent step 7 is reduced.
  • Step 6 Referring to FIG. 6, the island-shaped photoresist layer 6 is peeled off from the island-shaped etching barrier layer 5.
  • Step 7 referring to FIG. 7, depositing on the island-shaped etch barrier layer 5 and the gate insulating layer 3 and patterning the second metal layer by a yellow light and an etching process to form the source/drain electrodes 7.
  • the source/drain electrodes 7 are in contact with both side portions 43 of the oxide semiconductor layer 4 to form an electrical connection. Since both side portions 43 of the oxide semiconductor layer 4 are subjected to ion implantation treatment, electrical conductivity is enhanced, so ohmic contact between the source/drain electrodes 7 and both side portions 43 of the oxide semiconductor layer 4 is obtained. The resistance is reduced, so that the driving voltage and power consumption of the flat panel display device can be effectively reduced.
  • Step 8 referring to FIG. 8, depositing on the source/drain 7 and the etch barrier layer 5 and patterning the protective layer 8 by a yellow light and an etching process to form a side of the island-shaped oxide semiconductor layer 4 Through hole 81.
  • the material of the protective layer 8 is silicon dioxide (SiO 2 ) or silicon oxynitride (SiON).
  • Step 9 a pixel electrode layer 9 is deposited on the protective layer 8 and patterned by a yellow light and an etching process.
  • the material of the pixel electrode layer 9 is indium tin oxide (ITO) or indium zinc oxide (IZO).
  • the pixel electrode layer 9 fills the via hole 81 and is in contact with the source/drain electrodes 7 to form an electrical connection.
  • Step 10 Annealing the substrate 1 obtained in the step 9 to complete the fabrication of the oxide semiconductor TFT substrate.
  • the present invention further provides an oxide semiconductor TFT substrate structure including a substrate 1, a gate 2 on the substrate 1, and a gate 2 on the basis of the method for fabricating the above-described oxide semiconductor TFT substrate.
  • a source/drain 7 on the island-shaped etch barrier layer 5 and the gate insulating layer 3 a protective layer 8 on the source/drain 7 and the etch barrier layer 5, and a pixel electrode on the protective layer 8.
  • Layer 9
  • the island-shaped oxide peninsula body layer 4 includes an intermediate portion 41 and two side portions 43 that are ion-implanted and whose conductivity is enhanced; the width of the island-shaped etching barrier layer 5 is smaller than the The width of the oxide semiconductor layer 4 covers only the intermediate portion 41; the source/drain electrodes 7 are in contact with the two side portions 43 to form an electrical connection, and the ohmic contact resistance between the two is small, so that the flat plate
  • the display device has a low driving voltage and low power consumption.
  • the protective layer 8 has a via 81 on the side of the island-shaped oxide semiconductor layer 4, and the pixel electrode layer 9 fills the via 81 to be in contact with the source/drain 7 to form an electrical connection.
  • the substrate 1 is a glass substrate; the island-shaped oxide semiconductor layer 4 is an IGZO semiconductor layer, the material of the pixel electrode layer 9 is ITO or IZO, and the material of the protective layer 8 is SiO 2 or SiON. .
  • the method for fabricating the oxide semiconductor TFT substrate of the present invention by performing ion implantation treatment on both side portions of the island-shaped oxide peninsula layer, the conductivity of the both side portions is improved, and the both sides are The source/drain contact can improve the ohmic contact between the oxide semiconductor layer and the source/drain, reduce the ohmic contact resistance between the two, and reduce the driving voltage of the flat panel display device, thereby effectively reducing the work of the flat panel display device.
  • both sides of the oxide semiconductor layer are ion-implanted and contacted with the source/drain, and the ohmic contact resistance between the oxide semiconductor layer and the source/drain is small.
  • the driving voltage of the flat panel display device is low and the power consumption is low.

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Abstract

一种氧化物半导体TFT基板的制作方法及其结构。该制作方法包括如下步骤：1、在基板（1）上形成栅极（2）；2、沉积栅极绝缘层（3）；3、形成岛状氧化物半导体层（4）；4、形成岛状光阻层（6）与岛状蚀刻阻挡层（5），所述岛状蚀刻阻挡层（5）覆盖岛状氧化物半导体层（4）的中间部（41）而暴露出氧化物半导体的两侧部（43）；5、对所述岛状氧化物半导体层（4）的两侧部（43）进行离子注入处理；6、将岛状光阻层（6）剥离；7、形成源/漏极（7），所述源/漏极（7）与所述氧化物半导体层（4）的两侧部（43）接触，形成电性连接；8、沉积并图案化保护层（8）；9、沉积并图案化像素电极层（9）；10、进行退火处理。

Description

氧化物半导体TFT基板的制作方法及其结构 技术领域
本发明涉及显示技术领域，尤其涉及一种氧化物半导体TFT基板的制作方法及其结构。
背景技术
平板显示装置具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有的平板显示装置主要包括液晶显示装置(Liquid Crystal Display，LCD)及有机电致发光显示装置(Organic Light Emitting Display，OLED)。
基于有机发光二极管的OLED显示技术同成熟的LCD相比，OLED是主动发光的显示器，具有自发光、高对比度、宽视角(达170°)、快速响应、高发光效率、低操作电压(3～10V)、超轻薄(厚度小于2mm)等优势，具有更优异的彩色显示画质、更宽广的观看范围和更大的设计灵活性。
薄膜晶体管(Thin Film Transistor，TFT)是平板显示装置的重要组成部分，可形成在玻璃基板或塑料基板上，通常作为开光装置和驱动装置用在诸如LCD、OLED、电泳显示装置(EPD)上。
氧化物半导体TFT技术是当前的热门技术。由于氧化物半导体的载流子迁移率是非晶硅半导体的20-30倍，具有较高的电子迁移率，可以大大提高TFT对像素电极的充放电速率，提高像素的响应速度，实现更快的刷新率，并能够提高像素的行扫描速率，使得制作超高分辨率的平板显示装置成为可能。相比低温多晶硅(LTPS)，氧化物半导体制程简单，与非晶硅制程相容性较高，可以应用于LCD、OLED、柔性显示(Flexible)等领域，且与高世代生产线兼容，可应用于大中小尺寸显示，具有良好的应用发展前景。
现有的氧化物半导体TFT基板结构中，氧化物半导体层一般未经任何处理直接与源/漏极接触，二者之间形成电性连接，但二者之间的欧姆接触电阻较大，导致平板显示装置的驱动电压较高、功耗较高。
节能降耗是当今社会发展的需要，努力开发低功耗的显示装置成为了各个显示装置生产厂家的重要目标。
发明内容
本发明的目的在于提供一种氧化物半导体TFT基板的制作方法，能够 改善氧化物半导体层与源/漏极之间的欧姆接触，减小二者之间的欧姆接触电阻，降低平板显示装置的驱动电压，从而有效降低平板显示装置的功耗。
本发明的目的还在于提供一种氧化物半导体TFT基板结构，其氧化物半导体层与源/漏极之间的欧姆接触电阻较小，使得平板显示装置的驱动电压较低、功耗较低。
为实现上述目的，本发明首先提供一种氧化物半导体TFT基板的制作方法，包括如下步骤：
步骤1、提供一基板，在该基板上沉积并图案化第一金属层，形成栅极；
步骤2、在所述栅极与基板上沉积栅极绝缘层；
步骤3、在所述栅极绝缘层上沉积并图案化氧化物半导体层，形成位于所述栅极正上方的岛状氧化物半导体层；
步骤4、在所述岛状氧化物半导体层与栅极绝缘层上依次沉积蚀刻阻挡层、光阻层，之后对光阻层进行黄光制程，形成位于所述岛状氧化物半导体层正上方的岛状光阻层，再蚀刻所述蚀刻阻挡层，形成位于所述岛状氧化物半导体层上的岛状蚀刻阻挡层；
所述岛状蚀刻阻挡层的宽度小于所述氧化物半导体层的宽度；所述岛状蚀刻阻挡层覆盖岛状氧化物半导体层的中间部而暴露出氧化物半岛体的两侧部；
步骤5、对所述岛状氧化物半导体层的两侧部进行离子注入处理；
步骤6、将所述岛状光阻层从岛状蚀刻阻挡层上剥离；
步骤7、在所述岛状蚀刻阻挡层与栅极绝缘层上沉积并图案化第二金属层，形成源/漏极；
所述源/漏极与所述氧化物半导体层的两侧部接触，形成电性连接；
步骤8、在所述源/漏极与蚀刻阻挡层上沉积并图案化保护层，形成位于所述岛状氧化物半导体层一侧的通孔；
步骤9、在所述保护层上沉积并图案化像素电极层；
所述像素电极层填充所述通孔与所述源/漏极接触，形成电性连接；
步骤10、对步骤9得到的基板进行退火处理。
所述图案化通过黄光与蚀刻制程实现。
所述岛状氧化物半导体层为IGZO半导体层。
所述离子注入处理通过氢气等离子体处理的方式实现。
所述像素电极层的材料为ITO或IZO。
所述保护层的材料为SiO2或SiON。
所述基板为玻璃基板。
本发明还提供一种氧化物半导体TFT基板结构，包括一基板、位于基板上的栅极、位于栅极与基板上的栅极绝缘层、于栅极正上方位于栅极绝缘层上的岛状氧化物半岛体层、位于岛状氧化物半导体层上的岛状蚀刻阻挡层、位于岛状蚀刻阻挡层与栅极绝缘层上的源/漏极，位于所述源/漏极与蚀刻阻挡层上的保护层、及位于保护层上的像素电极层；所述岛状氧化物半岛体层包括中间部与两侧部，所述两侧部经离子注入处理；所述岛状蚀刻阻挡层的宽度小于所述氧化物半导体层的宽度，仅覆盖所述中间部；所述源/漏极与所述两侧部接触，形成电性连接；所述保护层具有位于所述岛状氧化物半导体层一侧的通孔，所述像素电极层填充所述通孔与所述源/漏极接触，形成电性连接。
所述岛状氧化物半导体层为IGZO半导体层，所述像素电极层的材料为ITO或IZO，所述保护层的材料为SiO2或SiON。
所述基板为玻璃基板。
本发明的有益效果：本发明的氧化物半导体TFT基板的制作方法，通过对岛状氧化物半岛体层的两侧部进行离子注入处理，提高了该两侧部的导电能力，该两侧部与源/漏极接触，能够改善氧化物半导体层与源/漏极之间的欧姆接触，减小二者之间的欧姆接触电阻，降低平板显示装置的驱动电压，从而有效降低平板显示装置的功耗；本发明的氧化物半导体TFT基板结构，其氧化物半导体层的两侧部经离子注入处理并与源/漏极接触，氧化物半导体层与源/漏极之间的欧姆接触电阻较小，使得平板显示装置的驱动电压较低、功耗较低。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为本发明氧化物半导体TFT基板的制作方法的流程图；
图2为本发明氧化物半导体TFT基板的制作方法的步骤1的示意图；
图3为本发明氧化物半导体TFT基板的制作方法的步骤2的示意图；
图4为本发明氧化物半导体TFT基板的制作方法的步骤3的示意图；
图5为本发明氧化物半导体TFT基板的制作方法的步骤4的示意图；
图6为本发明氧化物半导体TFT基板的制作方法的步骤6的示意图；
图7为本发明氧化物半导体TFT基板的制作方法的步骤7的示意图；
图8为本发明氧化物半导体TFT基板的制作方法的步骤8的示意图；
图9为本发明氧化物半导体TFT基板的制作方法的步骤9暨本发明氧化物半导体TFT基板结构的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其技术效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，为本发明氧化物半导体TFT基板的制作方法的流程图，该氧化物半导体TFT基板的制作方法包括如下步骤：
步骤1、请参阅图2，提供一基板1，在该基板1上沉积并图案化第一金属层，形成栅极2。
所述基板1为透明基板，优选的，所述基板1为玻璃基板。
在该步骤1中，通过一道普通光罩进行黄光制程、再经蚀刻制程图案化所述第一金属层，形成所需要的栅极2。
步骤2、请参阅图3，在所述栅极2与基板1上沉积栅极绝缘层3。
所述栅极绝缘3完全覆盖所述栅极2与基板1。
步骤3、请参阅图4，在所述栅极绝缘层3上沉积并通过黄光与蚀刻制程图案化氧化物半导体层，形成位于所述栅极2正上方的岛状氧化物半导体层4。
具体的，所述岛状氧化物半导体层4为铟镓锌氧化物(IGZO)半导体层。
步骤4、请参阅图5，在所述岛状氧化物半导体层4与栅极绝缘层3上依次沉积蚀刻阻挡层、光阻层，之后对光阻层进行黄光制程，形成位于所述岛状氧化物半导体层4正上方的岛状光阻层6，再蚀刻所述蚀刻阻挡层，形成位于所述岛状氧化物半导体层4上的岛状蚀刻阻挡层5。
进一步的，所述岛状蚀刻阻挡层5的宽度小于所述氧化物半导体层4的宽度；所述岛状蚀刻阻挡层5覆盖岛状氧化物半导体层4的中间部41而暴露出氧化物半岛体的两侧部43。
步骤5、对所述岛状氧化物半导体层4的两侧部43进行离子注入处理。
具体的，针对IGZO半导体层，所述离子注入处理通过氢气等离子体处理(H2 Plasma)的方式实现。经过氢气等离子体处理，大量H2离子注入到所述岛状氧化物半导体层4的两侧部43，降低了所述两侧部43的禁带宽度，提高了其导电能力，从而能够减小所述岛状氧化物半导体层4与后续步骤7中形成的源/漏极7之间的欧姆接触电阻。
当然，在该步骤5中，针对非IGZO半导体层，可根据氧化物半导体层 的具体材料，选择注入特定的离子，以达到掺杂目的，减小所述岛状氧化物半导体层4与后续步骤7中形成的源/漏极7之间的欧姆接触电阻。
步骤6、请参阅图6，将所述岛状光阻层6从岛状蚀刻阻挡层5上剥离。
步骤7、请参阅图7，在所述岛状蚀刻阻挡层5与栅极绝缘层3上沉积并通过黄光与蚀刻制程图案化第二金属层，形成源/漏极7。
所述源/漏极7与所述氧化物半导体层4的两侧部43接触，形成电性连接。由于所述氧化物半导体层4的两侧部43经过了离子注入处理，导电能力得以增强，所以所述源/漏极7与所述氧化物半导体层4的两侧部43之间的欧姆接触电阻减小，从而能够有效降低平板显示装置的驱动电压与功耗。
步骤8、请参阅图8，在所述源/漏极7与蚀刻阻挡层5上沉积并通过黄光与蚀刻制程图案化保护层8，形成位于所述岛状氧化物半导体层4一侧的通孔81。
具体的，所述保护层8的材料为二氧化硅(SiO2)或氮氧化硅(SiON)。
步骤9、请参阅图9，在所述保护层8上沉积并通过黄光与蚀刻制程图案化像素电极层9。
具体的，所述像素电极层9的材料为氧化铟锡(ITO)或氧化铟锌(IZO)。
所述像素电极层9填充所述通孔81与所述源/漏极7接触，形成电性连接。
步骤10、对步骤9得到的基板1进行退火处理，完成该氧化物半导体TFT基板的制作。
请参阅图9，在上述氧化物半导体TFT基板的制作方法的基础上，本发明还提供一种氧化物半导体TFT基板结构，包括一基板1、位于基板1上的栅极2、位于栅极2与基板1上的栅极绝缘层3、于栅极2正上方位于栅极绝缘层3上的岛状氧化物半岛体层4、位于岛状氧化物半导体层4上的岛状蚀刻阻挡层5、位于岛状蚀刻阻挡层5与栅极绝缘层3上的源/漏极7，位于所述源/漏极7与蚀刻阻挡层5上的保护层8、及位于保护层8上的像素电极层9。
所述岛状氧化物半岛体层4包括中间部41与两侧部43，所述两侧部43经离子注入处理，其导电能力得以增强；所述岛状蚀刻阻挡层5的宽度小于所述氧化物半导体层4的宽度，仅覆盖所述中间部41；所述源/漏极7与所述两侧部43接触，形成电性连接，二者之间的欧姆接触电阻较小，使得平板显示装置的驱动电压较低、功耗较低。
所述保护层8具有位于所述岛状氧化物半导体层4一侧的通孔81，所述像素电极层9填充所述通孔81与所述源/漏极7接触，形成电性连接。
具体的，所述基板1为玻璃基板；所述岛状氧化物半导体层4为IGZO半导体层，所述像素电极层9的材料为ITO或IZO，所述保护层8的材料为SiO2或SiON。
综上所述，本发明的氧化物半导体TFT基板的制作方法，通过对岛状氧化物半岛体层的两侧部进行离子注入处理，提高了该两侧部的导电能力，该两侧部与源/漏极接触，能够改善氧化物半导体层与源/漏极之间的欧姆接触，减小二者之间的欧姆接触电阻，降低平板显示装置的驱动电压，从而有效降低平板显示装置的功耗；本发明的氧化物半导体TFT基板结构，其氧化物半导体层的两侧部经离子注入处理并与源/漏极接触，氧化物半导体层与源/漏极之间的欧姆接触电阻较小，使得平板显示装置的驱动电压较低、功耗较低。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (11)

  1. 一种氧化物半导体TFT基板的制作方法，包括如下步骤：
    步骤1、提供一基板，在该基板上沉积并图案化第一金属层，形成栅极；
    步骤2、在所述栅极与基板上沉积栅极绝缘层；
    步骤3、在所述栅极绝缘层上沉积并图案化氧化物半导体层，形成位于所述栅极正上方的岛状氧化物半导体层；
    步骤4、在所述岛状氧化物半导体层与栅极绝缘层上依次沉积蚀刻阻挡层、光阻层，之后对光阻层进行黄光制程，形成位于所述岛状氧化物半导体层正上方的岛状光阻层，再蚀刻所述蚀刻阻挡层，形成位于所述岛状氧化物半导体层上的岛状蚀刻阻挡层；
    所述岛状蚀刻阻挡层的宽度小于所述氧化物半导体层的宽度；所述岛状蚀刻阻挡层覆盖岛状氧化物半导体层的中间部而暴露出氧化物半岛体的两侧部；
    步骤5、对所述岛状氧化物半导体层的两侧部进行离子注入处理；
    步骤6、将所述岛状光阻层从岛状蚀刻阻挡层上剥离；
    步骤7、在所述岛状蚀刻阻挡层与栅极绝缘层上沉积并图案化第二金属层，形成源/漏极；
    所述源/漏极与所述氧化物半导体层的两侧部接触，形成电性连接；
    步骤8、在所述源/漏极与蚀刻阻挡层上沉积并图案化保护层，形成位于所述岛状氧化物半导体层一侧的通孔；
    步骤9、在所述保护层上沉积并图案化像素电极层；
    所述像素电极层填充所述通孔与所述源/漏极接触，形成电性连接；
    步骤10、对步骤9得到的基板进行退火处理。
  2. 如权利要求1所述的氧化物半导体TFT基板的制作方法，其中，所述图案化通过黄光与蚀刻制程实现。
  3. 如权利要求1所述的氧化物半导体TFT基板的制作方法，其中，所述岛状氧化物半导体层为IGZO半导体层。
  4. 如权利要求3所述的氧化物半导体TFT基板的制作方法，其中，所述离子注入处理通过氢气等离子体处理的方式实现。
  5. 如权利要求1所述的氧化物半导体TFT基板的制作方法，其中，所述像素电极层的材料为ITO或IZO。
  6. 如权利要求1所述的氧化物半导体TFT基板的制作方法，其中，所 述保护层的材料为SiO2或SiON。
  7. 如权利要求1所述的氧化物半导体TFT基板的制作方法，其中，所述基板为玻璃基板。
  8. 一种氧化物半导体TFT基板结构，包括一基板、位于基板上的栅极、位于栅极与基板上的栅极绝缘层、于栅极正上方位于栅极绝缘层上的岛状氧化物半岛体层、位于岛状氧化物半导体层上的岛状蚀刻阻挡层、位于岛状蚀刻阻挡层与栅极绝缘层上的源/漏极，位于所述源/漏极与蚀刻阻挡层上的保护层、及位于保护层上的像素电极层；所述岛状氧化物半岛体层包括中间部与两侧部，所述两侧部经离子注入处理；所述岛状蚀刻阻挡层的宽度小于所述氧化物半导体层的宽度，仅覆盖所述中间部；所述源/漏极与所述两侧部接触，形成电性连接；所述保护层具有位于所述岛状氧化物半导体层一侧的通孔，所述像素电极层填充所述通孔与所述源/漏极接触，形成电性连接。
  9. 如权利要求8所述的氧化物半导体TFT基板结构，其中，所述岛状氧化物半导体层为IGZO半导体层，所述像素电极层的材料为ITO或IZO，所述保护层的材料为SiO2或SiON。
  10. 如权利要求8所述的氧化物半导体TFT基板结构，其中，所述基板为玻璃基板。
  11. 一种氧化物半导体TFT基板结构，包括一基板、位于基板上的栅极、位于栅极与基板上的栅极绝缘层、于栅极正上方位于栅极绝缘层上的岛状氧化物半岛体层、位于岛状氧化物半导体层上的岛状蚀刻阻挡层、位于岛状蚀刻阻挡层与栅极绝缘层上的源/漏极，位于所述源/漏极与蚀刻阻挡层上的保护层、及位于保护层上的像素电极层；所述岛状氧化物半岛体层包括中间部与两侧部，所述两侧部经离子注入处理；所述岛状蚀刻阻挡层的宽度小于所述氧化物半导体层的宽度，仅覆盖所述中间部；所述源/漏极与所述两侧部接触，形成电性连接；所述保护层具有位于所述岛状氧化物半导体层一侧的通孔，所述像素电极层填充所述通孔与所述源/漏极接触，形成电性连接；
    其中，所述岛状氧化物半导体层为IGZO半导体层，所述像素电极层的材料为ITO或IZO，所述保护层的材料为SiO2或SiON；
    其中，所述基板为玻璃基板。
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