WO2016033836A1 - 氧化物半导体tft基板的制作方法及结构 - Google Patents

氧化物半导体tft基板的制作方法及结构 Download PDF

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WO2016033836A1
WO2016033836A1 PCT/CN2014/086880 CN2014086880W WO2016033836A1 WO 2016033836 A1 WO2016033836 A1 WO 2016033836A1 CN 2014086880 W CN2014086880 W CN 2014086880W WO 2016033836 A1 WO2016033836 A1 WO 2016033836A1
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layer
oxide semiconductor
oxide
insulating layer
tft substrate
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PCT/CN2014/086880
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English (en)
French (fr)
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李文辉
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深圳市华星光电技术有限公司
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Priority to JP2017510494A priority Critical patent/JP2017526185A/ja
Priority to US14/426,152 priority patent/US9705008B2/en
Priority to KR1020177003553A priority patent/KR20170028986A/ko
Priority to GB1700579.4A priority patent/GB2542316B/en
Publication of WO2016033836A1 publication Critical patent/WO2016033836A1/zh

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    • H—ELECTRICITY
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating an oxide semiconductor TFT substrate and a structure thereof.
  • the flat panel display device has many advantages such as thin body, power saving, no radiation, and has been widely used.
  • the conventional flat panel display device mainly includes a liquid crystal display (LCD) and an organic light emitting display (OLED).
  • OLED display-based OLED display technology Compared with mature LCD, OLED is an active light-emitting display with self-luminous, high contrast, wide viewing angle (up to 170°), fast response, high luminous efficiency, low operating voltage (3 ⁇ ) 10V), ultra-thin (thickness less than 2mm) and other advantages, with superior color display quality, wider viewing range and greater design flexibility.
  • TFTs Thin Film Transistors
  • LCDs LCDs, OLEDs, and electrophoretic display devices (EPDs).
  • EPDs electrophoretic display devices
  • Oxide semiconductor TFT technology is currently a popular technology.
  • the oxide semiconductor has a high electron mobility (the oxide semiconductor mobility is >10 cm 2 /Vs, the a-Si mobility is only 0.5 to 0.8 cm 2 /Vs), and the oxide semiconductor is compared to LTPS (low temperature polysilicon).
  • the process is simple, and has high compatibility with the a-Si process, and can be applied to LCD (liquid crystal display), organic electroluminescence (OLED), flexible display, etc., and can be applied to large and small size display, and has good application.
  • LCD liquid crystal display
  • OLED organic electroluminescence
  • flexible display etc.
  • the development prospects are hot for current industry research.
  • FIG. 1 shows a conventional BCE (back channel etch) structure TFT, which has a simple structure and few production processes, and has a high yield and is most mature in a-Si TFT production. Therefore, the development of BCE structure oxide semiconductor TFTs with excellent properties is also popular for current research.
  • the substrate 100, the gate electrode 200, the gate insulating layer 300, and the oxide semiconductor layer 600 on the gate insulating layer 300 are required after the oxide semiconductor layer 600 is completed.
  • the metal source/drain electrode 400 is fabricated.
  • the wet etching process of the metal electrode uses a strong acid and a mixture thereof (HNO3/H3PO4/CH3COOH, etc.) to easily cause destruction of the oxide semiconductor at the back channel, which is difficult to produce.
  • the source/drain electrodes 400 are generally thick, and the line width is difficult to control when patterned, and the channel width is liable to be deviated.
  • FIG. 2 shows a conventional ESL (etch barrier) TFT including a substrate 100, a gate 200, a gate insulating layer 300, an IGZO 600 on the gate insulating layer 300, and a metal source.
  • the drain electrode 400 has a protective layer 700 above the IGZO600 channel to protect the IGZO600 from damage, but requires an additional process of the ESL700, and the width of the channel becomes larger, and the size of the TFT increases, so that the design space becomes smaller.
  • FIG. 3 shows a conventional reverse-planar Coplanar structure TFT including a substrate 100, a gate electrode 200, and a gate insulating layer 300.
  • the source-drain electrodes 400 are fabricated first, and then the IGZO600 is fabricated, due to the source-drain electrodes 400. Thickness, IGZO600 is prone to poor edge climbing at the edge of the channel, affecting performance.
  • metal ions at the cross section of the source and drain electrode 400 are easily diffused to IGZO600, contaminating IGZO600.
  • the source/drain electrodes 400 are generally thick, and the line width is difficult to control when patterned, and the channel width is liable to be deviated.
  • An object of the present invention is to provide a method for fabricating an oxide semiconductor TFT substrate, which reduces the process difficulty of the conventional oxide semiconductor TFT substrate, improves substrate performance, improves production yield, and defines an oxide semiconductor TFT by using an oxide conductor.
  • the channel of the substrate allows the channel width to be made smaller, thereby reducing the size of the TFT and making the channel width more accurate.
  • Another object of the present invention is to provide an oxide semiconductor TFT substrate structure in which an oxide conductor is used to define a channel of an oxide semiconductor TFT substrate, so that the channel width can be made small due to oxide conductors and oxidation.
  • the structure of the semiconductor is similar, so it can form a good Good ohmic contact; the oxide conductor does not cause metal ion contamination to the oxide semiconductor layer; since the oxide conductor is transparent, the aperture ratio can be increased.
  • the present invention provides a method of fabricating an oxide semiconductor TFT substrate, comprising the steps of:
  • Step 1 providing a substrate, depositing and patterning an oxide conductor layer on the substrate to obtain an oxide conductor layer having a channel;
  • Step 2 depositing and patterning an oxide semiconductor layer on the oxide conductor layer to obtain an oxide semiconductor layer
  • Step 3 depositing a first insulating layer on the oxide semiconductor layer
  • Step 4 depositing and patterning a first metal layer on the first insulating layer to form a gate
  • Step 5 depositing a second insulating layer on the gate
  • Step 6 the first insulating layer and the second insulating layer are simultaneously patterned to obtain via holes;
  • Step 7 Form a source and a drain on the second insulating layer.
  • the specific operation of the step 7 is: depositing and patterning a second metal layer on the second insulating layer, the second metal layer filling the via hole and electrically connecting with the oxide semiconductor layer to form a drain and a source .
  • step 7 The specific operation of the step 7 is:
  • Step 71 depositing and patterning a second metal layer on the second insulating layer, the second metal layer filling a via hole and electrically connecting with the oxide semiconductor layer to form a drain;
  • Step 72 depositing and patterning a second oxide conductor layer on the second insulating layer, the second oxide conductor layer filling the via hole and electrically connecting with the oxide semiconductor layer to form a source.
  • the substrate is a glass substrate, and the patterning is achieved by a yellow light and an etching process.
  • the oxide conductor layer is ITO or IZO, and the thickness of the oxide conductor layer is smaller than the thickness of the drain.
  • the source is extremely ITO or IZO.
  • the source serves as a pixel electrode at the same time.
  • the oxide semiconductor layer is an IGZO semiconductor layer.
  • the present invention also provides an oxide semiconductor TFT substrate structure comprising a substrate, an oxide conductor layer on the substrate, an oxide semiconductor layer on the oxide conductor layer, and a first insulation sequentially on the substrate and the oxide semiconductor layer a layer and a second insulating layer, a gate electrode between the first insulating layer and the second insulating layer, a drain electrode on the second insulating layer and electrically connected to the oxide semiconductor layer through the via hole, and a second insulating layer a source on the layer and electrically connected to the oxide semiconductor layer through the via.
  • the oxide conductor layer has a channel thereon, the oxide conductor layer has a thickness smaller than a thickness of the drain, and the drain is a metal.
  • the source is a metal or oxide conductor.
  • the method and structure for fabricating an oxide semiconductor TFT substrate provided by the present invention define a channel of an oxide semiconductor TFT substrate by using an oxide conductor layer, since the oxide conductor layer is thin and existing Compared with the technology, the width of the channel can be made smaller, and the channel width can be accurately controlled, thereby reducing the process difficulty of the oxide semiconductor TFT substrate, improving the performance of the oxide semiconductor TFT substrate, and improving the production. rate.
  • the oxide semiconductor TFT substrate structure produced by the present invention since the oxide conductor layer and the oxide semiconductor layer have similar structural compositions, a good ohmic contact can be formed; the oxide conductor layer does not cause metal ion contamination to the oxide semiconductor layer. Since the oxide conductor layer is transparent, the aperture ratio can be increased.
  • FIG. 1 is a schematic cross-sectional view showing a structure of a conventional oxide semiconductor TFT substrate
  • FIG. 2 is a schematic cross-sectional view showing another conventional oxide semiconductor TFT substrate structure
  • FIG. 3 is a schematic cross-sectional view showing another conventional oxide semiconductor TFT substrate structure
  • FIG. 4 is a schematic flow chart of a method for fabricating an oxide semiconductor TFT substrate of the present invention.
  • FIG. 5 is a cross-sectional view showing a first embodiment of an oxide semiconductor TFT substrate structure according to the present invention.
  • Fig. 6 is a cross-sectional view showing a second embodiment of an oxide semiconductor TFT substrate structure of the present invention.
  • the first embodiment of the method for fabricating an oxide semiconductor TFT substrate of the present invention includes the following steps:
  • Step 1 A substrate 1 is provided, and an oxide conductor layer is deposited and patterned on the substrate 1 to obtain an oxide conductor layer 5 having a channel 51.
  • the substrate 1 is a glass substrate.
  • the oxide conductor layer 5 is ITO or IZO.
  • the oxide conductor layer 5 is ITO.
  • Step 2 Depositing and patterning an oxide semiconductor layer on the oxide conductor layer 5 to obtain an oxide semiconductor layer 6.
  • the oxide semiconductor layer 6 is IGZO (Indium Gallium Zinc Oxide).
  • the oxide semiconductor layer 6 fills the channel 51.
  • Step 3 Depositing a first insulating layer 3 on the oxide semiconductor layer 6.
  • Step 4 depositing and patterning a first metal layer on the first insulating layer 3 to form a gate electrode 2.
  • Step 5 Deposit a second insulating layer 31 on the gate 2.
  • the second insulating layer 31 completely covers the first insulating layer 3.
  • Step 6 The first insulating layer 3 and the second insulating layer 31 are simultaneously patterned to obtain via holes 32 and 33.
  • Step 7 Depositing and patterning a second metal layer on the second insulating layer 31.
  • the second metal layer fills the via holes 32 and 33 and is electrically connected to the oxide semiconductor layer 6 to form the drain 4 and the source. 52.
  • the thickness of the oxide conductor layer 5 is smaller than the thickness of the drain 4; the patterning is achieved by a yellow light and an etching process.
  • the semiconductor semiconductor TFT substrate structure includes: a substrate 1, an oxide conductor layer 5 on the substrate 1, an oxide semiconductor layer 6 on the oxide conductor layer 5, and a first layer sequentially on the substrate 1 and the oxide semiconductor layer 6.
  • the drain 4 and the source 52 are electrically connected.
  • the oxide conductor layer 5 has a channel 51 thereon, and the thickness of the oxide conductor layer 5 is smaller than the thickness of the drain electrode 4.
  • the oxide conductor layer 5 is ITO or IZO.
  • the oxide conductor layer 5 is ITO.
  • the substrate 1 is a glass substrate, the drain 4 and the source 52 are both metal, and the oxide semiconductor layer 6 is IGZO.
  • a second embodiment of the method for fabricating an oxide semiconductor TFT substrate of the present invention includes the following steps:
  • Step 1 A substrate 1 is provided, and a first oxide conductor layer is deposited and patterned on the substrate 1 to obtain an oxide conductor layer 5 having a channel 51.
  • the substrate 1 is a glass substrate.
  • the oxide conductor layer 5 is ITO or IZO.
  • the oxide conductor layer 5 is ITO.
  • Step 2 Depositing and patterning an oxide semiconductor layer on the oxide conductor layer 5 to obtain an oxide semiconductor layer 6.
  • the oxide semiconductor layer 6 is IGZO.
  • the oxide semiconductor layer 6 fills the channel 51.
  • Step 3 Depositing a first insulating layer 3 on the oxide semiconductor layer 6.
  • Step 4 depositing and patterning a first metal layer on the first insulating layer 3 to form a gate electrode 2.
  • Step 5 Deposit a second insulating layer 31 on the gate 2.
  • the second insulating layer 31 completely covers the first insulating layer 3.
  • Step 6 The first insulating layer 3 and the second insulating layer 31 are simultaneously patterned to obtain via holes 32 and 33.
  • Step 7 Depositing and patterning a second metal layer on the second insulating layer 31.
  • the second metal layer fills the via 32 and is electrically connected to the oxide semiconductor layer 6 to form the drain 4.
  • Step 8 Depositing and patterning a second oxide conductor layer on the second insulating layer 31.
  • the second oxide conductor layer fills the via 33 and is electrically connected to the oxide semiconductor layer 6 to form a source 52.
  • the thickness of the oxide conductor layer 5 is smaller than the thickness of the drain 4, and the patterning is realized by a yellow light and an etching process.
  • the present invention further provides an oxide semiconductor TFT substrate structure including: a substrate 1, an oxide conductor layer 5 on the substrate 1, and an oxide conductor based on the manufacturing method of the second embodiment.
  • the oxide semiconductor layer 6 on the layer 5, the first insulating layer 3 and the second insulating layer 31 which are sequentially located on the substrate 1 and the oxide semiconductor layer 6, and the gate between the first insulating layer 3 and the second insulating layer 31 a pole 2, a drain 4 on the second insulating layer 31 and electrically connected to the oxide semiconductor layer 6 through the via 32, and a second insulating layer 31 and electrically connected to the oxide semiconductor layer 6 through the via 33 Connected source 52.
  • the oxide conductor layer 5 has a channel 51, the oxide conductor layer 5 and the source 52 are oxide conductors, and the oxide conductor is ITO or IZO.
  • the oxide conductor It is ITO; the thickness of the oxide conductor layer 5 is smaller than the thickness of the drain 4.
  • the substrate 1 is a glass substrate, the drain 4 is a metal, and the oxide semiconductor layer 6 is IGZO.
  • oxide semiconductor layer in the method of fabricating the oxide semiconductor TFT substrate of the present invention may be replaced by another semiconductor such as a-Si (amorphous silicon), a poly-Si (polysilicon) semiconductor, an organic semiconductor or the like.
  • oxide semiconductor TFT substrate structure of the present invention can be applied to LCD, OLED, EPD display, etc., and is suitable for active display applications such as non-flexible or flexible display, and large and medium-sized display devices can also use the oxidation of the present invention.
  • Semiconductor TFT substrate structure is suitable for active display applications such as non-flexible or flexible display, and large and medium-sized display devices can also use the oxidation of the present invention.
  • the method and structure for fabricating an oxide semiconductor TFT substrate define a channel of an oxide semiconductor TFT substrate by using an oxide conductor layer, and the oxide conductor layer is thin, and the prior art In contrast, the width of the channel can be made smaller, and the channel width can be accurately controlled, thereby reducing the process difficulty of the oxide semiconductor TFT substrate, improving the performance of the oxide semiconductor TFT substrate, and improving the production yield. .
  • the oxide semiconductor TFT substrate structure produced by the present invention since the oxide conductor layer and the oxide semiconductor layer have similar structural compositions, a good ohmic contact can be formed; the oxide conductor layer does not cause metal ion contamination to the oxide semiconductor layer. Since the oxide conductor layer is transparent, the aperture ratio can be increased.

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  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

一种氧化物半导体TFT基板的制作方法及结构，通过采用氧化物导体层（5）来定义氧化物半导体TFT基板的沟道（51），由于该氧化物导体层（5）较薄，与现有技术相比，所述沟道（51）的宽度可以制作得较小，并且沟道（51）宽度可以得到准确控制，因此降低了氧化物半导体TFT基板的制程难度，提升了氧化物半导体TFT基板的性能，提高生产良率。在制得的氧化物半导体TFT基板结构中，由于氧化物导体层（5）与氧化物半导体层（6）结构组成类似，因此可形成良好的欧姆接触；氧化物导体层（5）不会给氧化物半导体层（6）造成金属离子污染；由于氧化物导体层（5）是透明的，因此可提高开口率。

Description

氧化物半导体TFT基板的制作方法及结构 技术领域
本发明涉及显示技术领域，尤其涉及一种氧化物半导体TFT基板的制作方法及其结构。
背景技术
平板显示装置具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有的平板显示装置主要包括液晶显示装置(Liquid Crystal Display，LCD)及有机电致发光显示装置(Organic Light Emitting Display，OLED)。
基于有机发光二极管的OLED显示技术同成熟的LCD相比，OLED是主动发光的显示器，具有自发光、高对比度、宽视角(达170°)、快速响应、高发光效率、低操作电压(3～10V)、超轻薄(厚度小于2mm)等优势，具有更优异的彩色显示画质、更宽广的观看范围和更大的设计灵活性。
薄膜晶体管(Thin Film Transistor，TFT)是平板显示装置的重要组成部分，可形成在玻璃基板或塑料基板上，通常作为开光装置和驱动装置用在诸如LCD、OLED、电泳显示装置(EPD)上。
氧化物半导体TFT技术是当前的热门技术。氧化物半导体由于具有较 高的电子迁移率(氧化物半导体迁移率＞10cm2/Vs，a-Si迁移率仅0.5～0.8cm2/Vs)，而且相比LTPS(低温多晶硅)，氧化物半导体制程简单，与a-Si制程相容性较高，可应用于LCD(液晶显示)、有机电致发光(OLED)、柔性显示(Flexible)等等，可应用于大小尺寸显示，具有良好的应用发展前景，为当前业界研究热门。
但氧化物半导体的应用及开发仍面临很多问题。
图1所示为一种现有BCE(背沟道刻蚀)结构TFT，结构简单，生产工序少，在a-Si TFT生产中，良率较高，最为成熟。因此，开发具有优良性能的BCE结构氧化物半导体TFT，也为当前研究热门。传统的BCE结构氧化物半导体TFT中，包括基板100、栅极200、栅极绝缘层300、及位于栅极绝缘层300上的氧化物半导体层600，在氧化物半导体层600制作完成后，需制作金属源漏电极400，金属电极的湿蚀刻制程使用强酸及其混合物(HNO3/H3PO4/CH3COOH等)易造成背沟道处氧化物半导体破坏，生产难度较大。源漏电极400一般较厚，图形化时线宽较难控制，沟道宽度易产生偏差。
如图2所示为一种现有ESL(刻蚀阻挡层)结构TFT，包括基板100、栅极200、栅极绝缘层300、位于栅极绝缘层300上的IGZO600、及金属源 漏电极400，IGZO600沟道上方具有保护层700，保护IGZO600免受破坏，但需额外一道ESL700的制程，且沟道的宽度变大，TFT尺寸增大，使得设计空间变小。
图3所示为一种现有反转共平面(Coplanar)结构TFT，包括基板100、栅极200、栅极绝缘层300，先制作源漏电极400，再制作IGZO600，由于源漏电极400的厚度，IGZO600在沟道边缘爬坡处易发生不良，影响性能，此外，源漏电极400断面处的金属离子容易扩散至IGZO600，污染IGZO600。源漏电极400一般较厚，图形化时线宽较难控制，沟道宽度易产生偏差。
发明内容
本发明的目的在于提供一种氧化物半导体TFT基板的制作方法，降低了现有氧化物半导体TFT基板的制程难度，提升基板性能，提高生产良率，通过采用氧化物导体来定义氧化物半导体TFT基板的沟道，使得沟道宽度可以制作得更小，从而减小TFT的尺寸，且沟道宽度更准确。
本发明的另一目的在于提供一种氧化物半导体TFT基板结构，采用氧化物导体来定义氧化物半导体TFT基板的沟道，使得所述沟道宽度可以制作得较小，由于氧化物导体与氧化物半导体结构组成类似，因此可形成良 好的欧姆接触；氧化物导体不会给氧化物半导体层造成金属离子污染；由于氧化物导体是透明的，因此可提高开口率。
为实现上述目的，本发明提供一种氧化物半导体TFT基板的制作方法，包括如下步骤：
步骤1、提供一基板，在该基板上沉积并图案化氧化物导体层，得到具有沟道的氧化物导体层；
步骤2、在所述氧化物导体层上沉积并图案化氧化物半导体层，得到氧化物半导体层；
步骤3、在所述氧化物半导体层上沉积第一绝缘层；
步骤4、在所述第一绝缘层上沉积并图案化第一金属层，形成栅极；
步骤5、在所述栅极上沉积第二绝缘层；
步骤6、对所述第一绝缘层与第二绝缘层同时进行图案化处理，得到过孔；
步骤7、在所述第二绝缘层上形成源极与漏极。
所述步骤7的具体操作为：在所述第二绝缘层上沉积并图案化第二金属层，该第二金属层填充过孔并与氧化物半导体层电性连接，形成漏极与源极。
所述步骤7的具体操作为：
步骤71、在所述第二绝缘层上沉积并图案化第二金属层，该第二金属层填充过孔并与氧化物半导体层电性连接，形成漏极；
步骤72、在所述第二绝缘层上沉积并图案化第二氧化物导体层，该第二氧化物导体层填充过孔并与氧化物半导体层电性连接，形成源极。
所述基板为玻璃基板，所述图案化通过黄光与蚀刻制程实现。
所述氧化物导体层为ITO或IZO，所述氧化物导体层的厚度小于漏极的厚度。
所述源极为ITO或IZO。
所述源极同时作为像素电极。
所述氧化物半导体层为IGZO半导体层。
本发明还提供一种氧化物半导体TFT基板结构，包括基板、位于基板上的氧化物导体层、位于氧化物导体层上的氧化物半导体层、依次位于基板与氧化物半导体层上的第一绝缘层与第二绝缘层、位于第一绝缘层与第二绝缘层之间的栅极、位于第二绝缘层上且通过过孔与氧化物半导体层电性连接的漏极、及位于第二绝缘层上且通过过孔与氧化物半导体层电性连接的源极。
所述氧化物导体层上具有沟道，所述氧化物导体层的厚度小于所述漏极的厚度，所述漏极为金属。
所述源极为金属或氧化物导体。
本发明的有益效果：本发明提供的氧化物半导体TFT基板的制作方法及结构，通过采用氧化物导体层来定义氧化物半导体TFT基板的沟道，由于该氧化物导体层较薄，与现有技术相比，所述沟道的宽度可以制作得较小，并且沟道宽度可以得到准确控制，因此降低了氧化物半导体TFT基板的制程难度，提升了氧化物半导体TFT基板的性能，提高生产良率。本发明制得的氧化物半导体TFT基板结构中，由于氧化物导体层与氧化物半导体层结构组成类似，因此可形成良好的欧姆接触；氧化物导体层不会给氧化物半导体层造成金属离子污染；由于氧化物导体层是透明的，因此可提高开口率。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明 的技术方案及其他有益效果显而易见。
附图中，
图1为一种现有氧化物半导体TFT基板结构的剖面示意图；
图2为另一种现有氧化物半导体TFT基板结构的剖面示意图；
图3为又一种现有氧化物半导体TFT基板结构的剖面示意图；
图4为本发明氧化物半导体TFT基板制作方法的示意流程图；
图5为本发明氧化物半导体TFT基板结构第一实施例的剖面示意图；
图6为本发明氧化物半导体TFT基板结构第二实施例的剖面示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请同时参阅图4与图5，本发明氧化物半导体TFT基板的制作方法第一实施例，包括如下步骤：
步骤1、提供一基板1，在该基板1上沉积并图案化氧化物导体层，得到具有沟道51的氧化物导体层5。
优选的，所述基板1为玻璃基板。
所述氧化物导体层5为ITO或IZO。优选的，所述氧化物导体层5为 ITO。
步骤2、在所述氧化物导体层5上沉积并图案化氧化物半导体层，得到氧化物半导体层6。
优选的，所述氧化物半导体层6为IGZO(铟镓锌氧化物)。所述氧化物半导体层6填充所述沟道51。
步骤3、在所述氧化物半导体层6上沉积第一绝缘层3。
步骤4、在所述第一绝缘层3上沉积并图案化第一金属层，形成栅极2。
步骤5、在所述栅极2上沉积第二绝缘层31。
所述第二绝缘层31完全覆盖第一绝缘层3。
步骤6、对所述第一绝缘层3与第二绝缘层31同时进行图案化处理，得到过孔32、33。
步骤7、在所述第二绝缘层31上沉积并图案化第二金属层，该第二金属层填充过孔32、33并与氧化物半导体层6电性连接，形成漏极4与源极52。
其中，所述氧化物导体层5的厚度小于漏极4的厚度；所述图案化通过黄光与蚀刻制程实现。
如图5所示，基于上述第一实施例的制作方法，本发明还提供一种氧 化物半导体TFT基板结构，包括：基板1、位于基板1上的氧化物导体层5、位于氧化物导体层5上的氧化物半导体层6、依次位于基板1与氧化物半导体层6上的第一绝缘层3与第二绝缘层31、位于第一绝缘层3与第二绝缘层31之间的栅极2、及位于第二绝缘层31上且通过过孔32、33与氧化物半导体层6电性连接的漏极4与源极52。
其中，所述氧化物导体层5上具有沟道51，所述氧化物导体层5的厚度小于漏极4的厚度。所述氧化物导体层5为ITO或IZO，优选的，所述氧化物导体层5为ITO。
所述基板1为玻璃基板，所述漏极4与源极52均为金属，所述氧化物半导体层6为IGZO。
请参阅图4及图6，本发明氧化物半导体TFT基板的制作方法第二实施例，包括如下步骤：
步骤1、提供一基板1，在该基板1上沉积并图案化第一氧化物导体层，得到具有沟道51的氧化物导体层5。
优选的，所述基板1为玻璃基板。
所述氧化物导体层5为ITO或IZO。优选的，所述氧化物导体层5为ITO。
步骤2、在所述氧化物导体层5上沉积并图案化氧化物半导体层，得到氧化物半导体层6。
优选的，所述氧化物半导体层6为IGZO。所述氧化物半导体层6填充所述沟道51。
步骤3、在所述氧化物半导体层6上沉积第一绝缘层3。
步骤4、在所述第一绝缘层3上沉积并图案化第一金属层，形成栅极2。
步骤5、在所述栅极2上沉积第二绝缘层31。
所述第二绝缘层31完全覆盖第一绝缘层3。
步骤6、对所述第一绝缘层3与第二绝缘层31同时进行图案化处理，得到过孔32、33。
步骤7、在所述第二绝缘层31上沉积并图案化第二金属层，该第二金属层填充过孔32并与氧化物半导体层6电性连接，形成漏极4。
步骤8、在所述第二绝缘层31上沉积并图案化第二氧化物导体层，该第二氧化物导体层填充过孔33并与氧化物半导体层6电性连接，形成源极52。
其中，所述氧化物导体层5的厚度小于漏极4的厚度，所述图案化通过黄光与蚀刻制程实现。
如图6所示，基于上述该第二实施例的制作方法，本发明还提供一种氧化物半导体TFT基板结构，包括：基板1、位于基板1上的氧化物导体层5、位于氧化物导体层5上的氧化物半导体层6、依次位于基板1与氧化物半导体层6上的第一绝缘层3与第二绝缘层31、位于第一绝缘层3与第二绝缘层31之间的栅极2、位于第二绝缘层31上且通过过孔32与氧化物半导体层6电性连接的漏极4、及位于第二绝缘层31上且通过过孔33与氧化物半导体层6电性连接的源极52。
其中，所述氧化物导体层5上具有沟道51，所述氧化物导体层5与源极52均为氧化物导体，所述氧化物导体为ITO或IZO，优选的，所述氧化物导体为ITO；所述氧化物导体层5的厚度小于漏极4的厚度。
所述基板1为玻璃基板，所述漏极4为金属，所述氧化物半导体层6为IGZO。
值得一提的是，本发明氧化物半导体TFT基板制作方法中的氧化物半导体层也可以用其他半导体代替，如a-Si(非晶硅)，poly-Si(多晶硅)半导体，有机半导体等。并且本发明氧化物半导体TFT基板结构可应用于LCD，OLED，EPD显示等等，并适用于非柔性或柔性显示等主动性显示应用领域，同时大中小尺寸显示器件也均可使用本发明的氧化物半导体 TFT基板结构。
综上所述，本发明提供的氧化物半导体TFT基板的制作方法及结构，通过采用氧化物导体层来定义氧化物半导体TFT基板的沟道，由于该氧化物导体层较薄，与现有技术相比，所述沟道的宽度可以制作得较小，并且沟道宽度可以得到准确控制，因此降低了氧化物半导体TFT基板的制程难度，提升了氧化物半导体TFT基板的性能，提高生产良率。本发明制得的氧化物半导体TFT基板结构中，由于氧化物导体层与氧化物半导体层结构组成类似，因此可形成良好的欧姆接触；氧化物导体层不会给氧化物半导体层造成金属离子污染；由于氧化物导体层是透明的，因此可提高开口率。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (11)

  1. 一种氧化物半导体TFT基板的制作方法，包括如下步骤：
    步骤1、提供一基板，在该基板上沉积并图案化氧化物导体层，得到具有沟道的氧化物导体层；
    步骤2、在所述氧化物导体层上沉积并图案化氧化物半导体层，得到氧化物半导体层；
    步骤3、在所述氧化物半导体层上沉积第一绝缘层；
    步骤4、在所述第一绝缘层上沉积并图案化第一金属层，形成栅极；
    步骤5、在所述栅极上沉积第二绝缘层；
    步骤6、对所述第一绝缘层与第二绝缘层同时进行图案化处理，得到过孔；
    步骤7、在所述第二绝缘层上形成源极与漏极。
  2. 如权利要求1所述的氧化物半导体TFT基板的制作方法，其中，所述步骤7的具体操作为：在所述第二绝缘层上沉积并图案化第二金属层，该第二金属层填充过孔并与氧化物半导体层电性连接，形成漏极与源极。
  3. 如权利要求1所述的氧化物半导体TFT基板的制作方法，其中，所述步骤7的具体操作为：
    步骤71、在所述第二绝缘层上沉积并图案化第二金属层，该第二金属层填充过孔并与氧化物半导体层电性连接，形成漏极；
    步骤72、在所述第二绝缘层上沉积并图案化第二氧化物导体层，该第二氧化物导体层填充过孔并与氧化物半导体层电性连接，形成源极。
  4. 如权利要求1所述的氧化物半导体TFT基板的制作方法，其中，所述基板为玻璃基板，所述图案化通过黄光与蚀刻制程实现。
  5. 如权利要求1所述的氧化物半导体TFT基板的制作方法，其中，所述氧化物导体层为ITO或IZO，所述氧化物导体层的厚度小于漏极的厚度。
  6. 如权利要求3所述的氧化物半导体TFT基板的制作方法，其中，所述源极为ITO或IZO。
  7. 如权利要求1所述的氧化物半导体TFT基板的制作方法，其中，所述源极同时作为像素电极；所述氧化物半导体层为IGZO。
  8. 一种氧化物半导体TFT基板结构，包括基板、位于基板上的氧化物导体层、位于氧化物导体层上的氧化物半导体层、依次位于基板与氧化物半导体层上的第一绝缘层与第二绝缘层、位于第一绝缘层与第二绝缘层之间的栅极、位于第二绝缘层上且通过过孔与氧化物半导体层电性连接的漏极、及位于第二绝缘层上且通过过孔与氧化物半导体层电性连接的源极。
  9. 如权利要求8所述的氧化物半导体TFT基板结构，其中，所述氧化物导体层上具有沟道，所述氧化物导体层的厚度小于所述漏极的厚度，所述漏极为金属。
  10. 如权利要求9所述的氧化物半导体TFT基板结构，其中，所述源极为金属或氧化物导体。
  11. 一种氧化物半导体TFT基板结构，包括基板、位于基板上的氧化物导体层、位于氧化物导体层上的氧化物半导体层、依次位于基板与氧化物半导体层上的第一绝缘层与第二绝缘层、位于第一绝缘层与第二绝缘层之间的栅极、位于第二绝缘层上且通过过孔与氧化物半导体层电性连接的漏极、及位于第二绝缘层上且通过过孔与氧化物半导体层电性连接的源极；
    其中，所述氧化物导体层上具有沟道，所述氧化物导体层的厚度小于所述漏极的厚度，所述漏极为金属；
    其中，所述源极为金属或氧化物导体。
PCT/CN2014/086880 2014-09-02 2014-09-19 氧化物半导体tft基板的制作方法及结构 WO2016033836A1 (zh)

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KR1020177003553A KR20170028986A (ko) 2014-09-02 2014-09-19 산화물 반도체 tft 기판의 제작방법 및 구조
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