JP2007073705A - 酸化物半導体チャネル薄膜トランジスタおよびその製造方法 - Google Patents
酸化物半導体チャネル薄膜トランジスタおよびその製造方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
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- 229910007541 Zn O Inorganic materials 0.000 claims abstract description 21
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- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 3
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 3
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- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 6
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
【解決手段】プラスチックフィルム基板1上にITO膜からなるドレイン電極5、ソース電極6を形成し、In−M−Zn−O(MはGa、Al、Feのうち少なくとも1種)を主たる構成元素とする酸化物半導体からなるチャネル層2を形成し、チャネル層2上にゲート絶縁膜3を介してITO膜からなるゲート電極4を形成し、TFTを作製する。そのTFT素子上に金属酸化物膜、シリコン酸化物膜、シリコン窒化物膜、シリコン炭化物膜、有機物膜あるいは有機物膜と金属膜の積層膜により保護膜7を200℃以下の成膜温度で形成する。その保護膜7にコンタクトホール8を形成し、これを介し、TFTの各電極4、5、6と、保護膜7上に形成したTFTの各端子9、10、11とを接続する。
【選択図】図1
Description
まず、本発明の第1の実施の形態による酸化物半導体チャネル薄膜トランジスタを形成しているTFT素子構成について説明する。
次に、本発明の第2の実施の形態を説明する。本実施の形態としては、上記のTFT素子上に形成される保護膜として、シリコン窒化物(SiNx)、あるいはシリコン酸化物(SiOx)、あるいはシリコン炭化物(SiOxNy)のうち少なくとも1種から構成される膜を用いることができる。
本発明の第3の実施の形態としては、上記のTFT素子上に形成される保護膜として、有機物膜を用いることができる。この場合、有機物膜として、ポリイミド膜を用いるのが好ましい形態のひとつであり、シリコーン等のフッ素系有機物樹脂膜を用いるのも好ましい形態のひとつである。
本発明の第4の実施の形態としては、上記のTFT素子上に形成される保護膜として、有機物膜と金属膜の積層膜を用いる。この場合、有機物膜としては、ポリイミド膜を用いるのが好ましい形態のひとつであり、シリコーン等のフッ素系有機物樹脂膜を用いるのも好ましい形態のひとつである。金属膜としては、アルミニウム膜を用いるのが好ましい形態のひとつである。
1)TFT素子の作製
本実施例のTFT素子として、図1に示すトップゲート型MISFET(Metal-Insulator-Semiconductor Field Effect Transistor)素子を作製した。
TFT素子を作製した基板を乾燥空気中150℃で20分間加熱し、吸着水分等を取り除いた。その後速やかにTFT素子基板を電子ビーム蒸着装置に導入し、電子ビーム蒸着により保護膜7として、Al2O3膜を200nm堆積させた。そのときの成膜温度は室温である。堆積させたAl2O3膜のうち、ゲート電極4、ドレイン電極5、ソース電極6上の一部をフォトリソグラフィー法およびアルゴンミリング法により除去し、コンタクトホール8を形成した。
図2に、室温大気下で測定したTFT素子の伝達特性を示す。これによると、上記の保護膜を形成したTFT素子は、ゲート電圧VGSの増加に伴い、ドレイン電流IDSが増加した。オン・オフ電流比は、106以上であった。また、出力特性から電界効果移動度を算出したところ、飽和領域において約7cm2(Vs)−1の電界効果移動度が得られた。さらに素子を真空チャンバー中に設置し、真空中での測定を行ったところ、特性の変化は見られなかった。
1)TFT素子の作製
本実施例のTFT素子として、図1に示すトップゲート型MISFET素子を作製した。
TFT素子を作製した基板を乾燥空気中150℃で20分間加熱し、吸着水分等を取り除いた。その後速やかにTFT素子基板をプラズマCVD装置に導入し、SiH4とNH3を原料ガスに用いたプラズマCVD法により保護膜7として、SiNx膜を200nm堆積させた。そのときの成膜温度は100℃である。
図2に、室温大気下で測定したTFT素子の伝達特性を示す。これによると、上記の保護膜を形成したTFT素子は、ゲート電圧VGSの増加に伴い、ドレイン電流IDSが増加した。オン・オフ電流比は、106以上であった。また、出力特性から電界効果移動度を算出したところ、飽和領域において約7cm2(Vs)−1の電界効果移動度が得られた。さらに素子を真空チャンバー中に設置し、真空中での測定を行ったところ、特性の変化は見られなかった。
1)TFT素子の作製
本実施例のTFT素子として、図1に示すトップゲート型MISFET素子を作製した。
TFT素子を作製した基板を乾燥空気中150℃で20分間加熱し、吸着水分等を取り除いた。その後速やかにTFT素子基板上にシリコーン系樹脂を含む溶液をスピンコート法により塗布した。塗布後、基板を100℃乾燥大気下で乾燥させることで、保護膜7としてシリコーン系樹脂膜を200nm堆積させた。堆積させたシリコーン系樹脂膜のうち、ゲート電極4、ドレイン電極5、ソース電極6上の一部をフォトリソグラフィー法および有機溶媒によるエッチングにより除去し、コンタクトホール8を形成した。
図2に、室温大気下で測定したTFT素子のドレイン電圧+4ボルトでの伝達特性を示す。これによると、上記の保護膜を形成したTFT素子では、ゲート電圧VGSの増加に伴い、ドレイン電流IDSが増加した。オン・オフ電流比は106以上であった。また、出力特性から電界効果移動度を算出したところ、飽和領域において約7cm2(Vs)−1の電界効果移動度が得られた。さらに素子を真空チャンバー中に設置し、真空中での測定を行ったところ、特性の変化は見られなかった。
1)TFT素子の作製
本実施例のTFT素子として、図4に示すトップゲート型MISFET素子を作製した。
TFT素子を作製した基板を乾燥空気中150℃で20分間加熱し、吸着水分等を取り除いた。その後速やかにTFT素子基板上にシリコン系樹脂を含む溶液をスピンコート法により塗布した。塗布後、基板を100℃乾燥大気下で乾燥させることで、シリコーン系樹脂膜を100nm堆積させた。引き続き、基板を電子ビーム蒸着装置に導入し、電子ビーム蒸着によりAl膜を100nm堆積させた。そのときの成膜温度は室温である。
図2に、室温大気下で測定したTFT素子の伝達特性を示す。これによると、上記の保護膜を形成したTFT素子では、ゲート電圧VGSの増加に伴い、ドレイン電流IDSが増加した。オン・オフ電流比は106以上であった。また、出力特性から電界効果移動度を算出したところ、飽和領域において約7cm2(Vs)−1の電界効果移動度が得られた。さらに素子を真空チャンバー中に設置し、真空中での測定を行ったところ、特性の変化は見られなかった。
本実施例では、上記実施例1から4に対し、ゲート絶縁膜として、厚さ100nmのY2O3膜の代わりに厚さ100nmのAl2O3を電子ビーム蒸着法により堆積させたTFTを作製した。その他のTFT素子の構成および製造方法は上記実施例1〜4と同様である。作製されたTFTに対し、保護膜形成後に特性を評価したところ、前述のY2O3ゲート絶縁膜を用いたTFTと同等の性能と安定性が得られた。
本実施例では、上記実施例1から4に対し、ゲート絶縁膜として、厚さ100nmのY2O3膜の代わりに厚さ100nmのHfO2を電子ビーム蒸着法により堆積させたTFTを作製した。その他のTFT素子の構成および製造方法は上記実施例1〜4と同様である。作製されたTFTに対し、保護膜形成後に特性を評価したところ、前述のY2O3ゲート絶縁膜を用いたTFTと同等の性能と安定性が得られた。
本実施例では、上記実施例1から4に対し、ゲート絶縁膜として、厚さ100nmのY2O3膜の代わりに厚さ100nmのZrO2を電子ビーム蒸着法により堆積させたTFTを作製した。その他のTFT素子の構成および製造方法は上記実施例1〜4と同様である。作製されたTFTに対し、保護膜形成後に特性を評価したところ、前述のY2O3ゲート絶縁膜を用いたTFTと同等の性能と安定性が得られた。
本実施例では、上記実施例1から4に対し、ゲート絶縁膜として、厚さ100nmのY2O3膜の代わりに厚さ100nmのTiO2を電子ビーム蒸着法により堆積させたTFTを作製した。その他のTFT素子の構成および製造方法は上記実施例1〜4と同様である。作製されたTFTに対し、保護膜形成後に特性を評価したところ、前述のY2O3ゲート絶縁膜を用いたTFTと同等の性能と安定性が得られた。
2 チャネル層
3 ゲート絶縁膜
4 ゲート電極
5 ドレイン電極
6 ソース電極
7 保護膜
8 コンタクトホール
9 ゲート端子
10 ドレイン端子
11 ソース端子
17 有機物膜
18 貫通孔
27 金属膜
28 コンタクトホール
37 絶縁膜
Claims (10)
- In−M−Zn−O(MはGa、Al、Feのうち少なくとも1種)を主たる構成元素とする酸化物半導体をチャネル層に用いる薄膜トランジスタにおいて、
前記酸化物半導体チャネル層上を保護膜で覆うことを特徴とする酸化物半導体チャネル薄膜トランジスタ。 - 前記保護膜が、少なくとも1種の金属元素を含む金属酸化物膜であることを特徴とする請求項1記載の酸化物半導体チャネル薄膜トランジスタ。
- 前記保護膜が、シリコンの窒化物、酸化物、炭化物のうち少なくとも1種から構成される膜であることを特徴とする請求項1記載の酸化物半導体チャネル薄膜トランジスタ。
- 前記保護膜が、有機物膜であることを特徴とする請求項1記載の酸化物半導体チャネル薄膜トランジスタ。
- 前記保護膜が、有機物膜と金属膜の積層膜であることを特徴とする請求項1記載の酸化物半導体チャネル薄膜トランジスタ。
- 前記薄膜トランジスタのゲート絶縁膜が、酸化イットリウムであることを特徴とする請求項1から5のいずれか1項に記載の酸化物半導体チャネル薄膜トランジスタ。
- 前記薄膜トランジスタのゲート絶縁膜が、酸化イットリウム、酸化アルミニウム、酸化ハフニウム、酸化ジルコニウム、酸化チタンのうち少なくとも1種を含むことを特徴とする請求項1から5のいずれか1項に記載の酸化物半導体チャネル薄膜トランジスタ。
- 前記保護膜は、微小空隙が形成されていることを特徴とする請求項1から7のいずれか1項に記載の酸化物半導体チャネル薄膜トランジスタ。
- In−M−Zn−O(MはGa、Al、Feのうち少なくとも1種)を主たる構成元素とする酸化物半導体をチャネル層に用いる薄膜トランジスタの製造方法であって、
前記酸化物半導体チャネル層上に所定の成膜温度で保護膜を形成し、当該チャネル層上を当該保護膜で覆うことを特徴とする酸化物半導体チャネル薄膜トランジスタの製造方法。 - 前記成膜温度は、200℃以下であることを特徴とする請求項9記載の酸化物半導体チャネル薄膜トランジスタの製造方法。
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