JP5539846B2 - 評価方法、半導体装置の作製方法 - Google Patents
評価方法、半導体装置の作製方法 Download PDFInfo
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- JP5539846B2 JP5539846B2 JP2010246924A JP2010246924A JP5539846B2 JP 5539846 B2 JP5539846 B2 JP 5539846B2 JP 2010246924 A JP2010246924 A JP 2010246924A JP 2010246924 A JP2010246924 A JP 2010246924A JP 5539846 B2 JP5539846 B2 JP 5539846B2
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- Prior art keywords
- oxide semiconductor
- semiconductor layer
- carrier density
- transistor
- dielectric constant
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
Description
図1(A)及び図1(B)にMOSキャパシタの一例を示す。
MOSキャパシタのCV測定の結果(CV特性)の評価について説明する。
水素が少量しか含まれていない場合、実施の形態2の方法では評価が難しい場合がある。
酸化物半導体層の比誘電率εをCV特性から求めることも可能である。
評価結果の活用方法の一例を示す。
(実施の形態6)
評価結果の活用方法の一例を示す。
200 半導体層
300 ゲート絶縁層
400 ゲート電極層
101 ゲート電極層
201 ゲート絶縁層
301 半導体層
401 ソース電極層
501 ドレイン電極層
102 シリコンウェハ
202 酸化物半導体層
302 ゲート電極層
Claims (3)
- 酸化物半導体を含むトランジスタを形成し、
前記トランジスタのソース、ドレイン及びゲートを電気的に接続して、CV特性を取得し、
前記CV特性に基づき、ゲート電圧Vgと(1/C)2との関係をプロットしたグラフを取得し、
前記グラフにおいて弱反転領域での(1/C)2の微分値を求め、前記微分値を下記数式(12)に代入することによりキャリア密度Ndの大きさを求め、
前記キャリア密度Ndが1×1018cm−3以上の場合、前記トランジスタに加熱処理を加えることが好ましいと評価することを特徴とする評価方法。
(但し、数式(12)中、eは電子電荷、ε0は真空の誘電率、εは前記酸化物半導体の比誘電率である。) - 請求項1において、
前記トランジスタは基板の上方に位置し、
前記加熱処理として、150℃以上前記基板の耐熱温度以下の温度の加熱処理を加えることが好ましいと評価することを特徴とする評価方法。 - 酸化物半導体を含むトランジスタを形成し、
前記トランジスタのソース、ドレイン及びゲートを電気的に接続して、CV特性を取得し、
前記CV特性に基づき、ゲート電圧Vgと(1/C)2との関係をプロットしたグラフを取得し、
前記グラフにおいて弱反転領域での(1/C)2の微分値を求め、前記微分値を下記数式(12)に代入することによりキャリア密度Ndの大きさを求め、
前記キャリア密度Ndが1×1018cm−3以上の場合、前記トランジスタに加熱処理を加えることを特徴とする半導体装置の作製方法。
(但し、数式(12)中、eは電子電荷、ε0は真空の誘電率、εは前記酸化物半導体の比誘電率である。)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP2010246924A JP5539846B2 (ja) | 2009-11-06 | 2010-11-03 | 評価方法、半導体装置の作製方法 |
Applications Claiming Priority (3)
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JP2009255230 | 2009-11-06 | ||
JP2009255230 | 2009-11-06 | ||
JP2010246924A JP5539846B2 (ja) | 2009-11-06 | 2010-11-03 | 評価方法、半導体装置の作製方法 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2011119712A JP2011119712A (ja) | 2011-06-16 |
JP2011119712A5 JP2011119712A5 (ja) | 2013-11-28 |
JP5539846B2 true JP5539846B2 (ja) | 2014-07-02 |
Family
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Family Applications (1)
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JP2010246924A Expired - Fee Related JP5539846B2 (ja) | 2009-11-06 | 2010-11-03 | 評価方法、半導体装置の作製方法 |
Country Status (2)
Country | Link |
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US (1) | US8541782B2 (ja) |
JP (1) | JP5539846B2 (ja) |
Families Citing this family (3)
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---|---|---|---|---|
WO2011074590A1 (en) | 2009-12-17 | 2011-06-23 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, measurement apparatus, and measurement method of relative permittivity |
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KR102526654B1 (ko) | 2015-03-03 | 2023-04-26 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 산화물 반도체막, 상기 산화물 반도체막을 포함하는 반도체 장치, 및 상기 반도체 장치를 포함하는 표시 장치 |
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-
2010
- 2010-11-03 JP JP2010246924A patent/JP5539846B2/ja not_active Expired - Fee Related
- 2010-11-05 US US12/940,724 patent/US8541782B2/en active Active
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US8541782B2 (en) | 2013-09-24 |
JP2011119712A (ja) | 2011-06-16 |
US20110111535A1 (en) | 2011-05-12 |
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