WO2010013621A1 - 半導体装置の製造方法および半導体装置 - Google Patents
半導体装置の製造方法および半導体装置 Download PDFInfo
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- WO2010013621A1 WO2010013621A1 PCT/JP2009/063096 JP2009063096W WO2010013621A1 WO 2010013621 A1 WO2010013621 A1 WO 2010013621A1 JP 2009063096 W JP2009063096 W JP 2009063096W WO 2010013621 A1 WO2010013621 A1 WO 2010013621A1
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1229—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with different crystal properties within a device or between different devices
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/466—Lateral bottom-gate IGFETs comprising only a single gate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
- H10K19/10—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising field-effect transistors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/10—Deposition of organic active material
- H10K71/12—Deposition of organic active material using liquid deposition, e.g. spin coating
Definitions
- the present invention relates to a method for manufacturing a semiconductor device having a first transistor and a second transistor formed on the same substrate, and a semiconductor device.
- a semiconductor device using an organic semiconductor material may be manufactured at a lower cost than a silicon semiconductor device, and may have a large area and a mechanically flexible semiconductor device. Therefore, it is likely to be used as a substitute for a silicon semiconductor device depending on the application, and is attracting attention as one of useful semiconductor devices.
- Complementary logic circuits composed of complementary transistors are indispensable for current integrated circuits because they are energy efficient and advantageous for miniaturization.
- this complementary logic circuit In order to manufacture this complementary logic circuit at low cost, it has been studied to form a complementary transistor with a semiconductor device using an organic semiconductor material.
- a complementary transistor in which each channel of an n-type transistor and a p-type transistor is configured by an organic semiconductor film has been proposed (see Patent Document 1).
- an object of the present invention is to provide a semiconductor device manufacturing method and a semiconductor device that can easily manufacture a high-performance complementary transistor.
- a first transistor having a first source electrode, a first drain electrode, a first semiconductor film, and a first gate electrode and formed on a substrate; a second source electrode; A second drain electrode; a second semiconductor film; a second gate electrode electrically connected to the first gate electrode; and a second transistor formed on the substrate.
- a first gate electrode forming step for forming the first gate electrode on the substrate, and a first source / drain for forming the first source electrode and the first drain electrode.
- the second source power A semiconductor comprising: a second source / drain electrode forming step of forming a pole and the second drain electrode; and a second semiconductor film forming step of forming the second semiconductor film using an organic semiconductor material Device manufacturing method.
- the first semiconductor film forming step the first semiconductor film is formed by a sputtering method using the oxide semiconductor material, and in the second semiconductor film forming step, the organic semiconductor material is applied as a coating solution.
- the first semiconductor film forming step the first semiconductor film is formed by a coating method using the oxide semiconductor material as a coating solution, and in the second semiconductor film forming step, the organic semiconductor material is formed.
- the first semiconductor film is formed using zinc tin oxide as the oxide semiconductor material. The manufacturing method of the semiconductor device of description.
- the method further includes a protective film forming step of forming a protective film on a surface of one or both of the first semiconductor film and the second semiconductor film, and the protective film is made of a fluororesin.
- the first transistor includes a first gate electrode, a first source electrode, and a first drain electrode.
- the second transistor includes the first gate electrode A second gate electrode electrically connected to the second source electrode, a second source electrode, a second drain electrode, and the second source electrode and the second drain electrode formed by an organic semiconductor
- a semiconductor device comprising: a second semiconductor film configured.
- the mobility of both the n-type and p-type transistors satisfies the desired value.
- the first and second semiconductor films are formed using different semiconductor materials of an oxide semiconductor and an organic semiconductor, these semiconductors are formed.
- a combination of an oxide semiconductor material and an organic semiconductor material for forming a film can be selected as appropriate, and a high-performance complementary transistor can be manufactured.
- the first transistor and the second transistor are formed using an oxide semiconductor material and an organic semiconductor material that can be formed by a simple process, not a silicon material that requires a complicated process, high performance The complementary transistor can be easily manufactured.
- FIG. 1 is a circuit diagram showing an electrical configuration of a semiconductor device constituted by complementary transistors according to the first embodiment of the present invention.
- FIG. 2 is a plan view of a semiconductor device including complementary transistors according to the first embodiment of the present invention.
- FIG. 3 is a cross-sectional view of the semiconductor device including the complementary transistors according to the first embodiment of the present invention.
- FIG. 4A is a cross-sectional view illustrating the method of manufacturing the semiconductor device shown in FIG.
- FIG. 4B is a cross-sectional view illustrating the method of manufacturing the semiconductor device shown in FIG. 4-3 is a cross-sectional view illustrating a method of manufacturing the semiconductor device shown in FIG.
- FIG. 4-4 is a cross-sectional view illustrating the method of manufacturing the semiconductor device shown in FIG.
- FIG. 4-5 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 4-6 is a cross-sectional view showing a method of manufacturing the semiconductor device shown in FIG. 4-7 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG.
- FIG. 4-8 is a cross-sectional view showing a method of manufacturing the semiconductor device shown in FIG. 4-9 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG.
- FIG. 5 is a cross-sectional view of a semiconductor device composed of complementary transistors according to the second embodiment of the present invention.
- FIG. 6A is a cross-sectional view illustrating a method of manufacturing the semiconductor device shown in FIG. 6-2 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 6-3 is a cross-sectional view illustrating the method of manufacturing the semiconductor device shown in FIG.
- each step in the manufacturing method of each embodiment of the present invention includes a baking (heat treatment) step for improving the film quality of the formed film after forming each film, if necessary. In the following, the description is omitted for the sake of simplicity.
- FIG. 1 is a circuit diagram showing an electrical configuration of a semiconductor device including complementary transistors according to the first embodiment.
- FIG. 2 is a plan view of the semiconductor device configured by the complementary transistors according to the first embodiment.
- the semiconductor device has a p-type transistor Q1 and an n-type transistor Q2.
- the p-type transistor Q1 is a transistor that forms a p-type (for example, the first conductivity type) channel
- the n-type transistor Q2 is an n-type that is different from the p-type (for example, the second conductivity type). )) Is formed.
- each gate (corresponding to the gate electrode 2 in FIG. 2 or FIG. 3) is connected to a contact C2, which is a common wiring on the input side, and each drain (FIG. 2). (Or equivalent to the drain electrode 4d in FIG. 3) is connected to a contact C32 which is a common wiring on the output side.
- a complementary semiconductor device for example, a CMOS transistor
- the source of the p-type transistor Q1 (corresponding to the source electrode 4ps in FIG. 2 or FIG. 3) is connected to a power supply line to which, for example, the power supply voltage Vdd is applied via the contact C31, and the source of the n-type transistor Q2 (see FIG. 2 or equivalent to the source electrode 4ns in FIG. 3) is connected to a ground line having a ground potential Vss, for example, via a contact C33.
- the planar structure of the semiconductor device of the present embodiment has, for example, a common gate electrode 2 formed in a plate shape, a source electrode 4ps of a p-type transistor Q1, and a source of an n-type transistor Q2.
- the electrode 4ns, the drain electrodes 4d of the p-type and n-type transistors Q1 and Q2, the organic semiconductor film 7 functioning as the channel of the p-type transistor, and the oxide semiconductor film 5 functioning as the channel of the n-type transistor are illustrated.
- a part of the common gate electrode 2 functions as a gate for the p-type transistor Q1, and a part functions as a gate for the n-type transistor Q2.
- the source electrode 4ps of the p-type transistor Q1 includes a first wiring portion extending along the gate electrode 2 in one of the short sides of the gate electrode 2 in plan view, and a region of the gate electrode 2 from the first wiring portion. And two electrode portions extending upward.
- the source electrode 4ns of the n-type transistor Q2 includes a second wiring portion extending along the gate electrode 2 on the other side in the short direction of the gate electrode 2 in plan view, and a gate electrode 2 region extending from the second wiring portion. One electrode portion extending upward.
- the drain electrodes 4d of the p-type and n-type transistors Q1, Q2 have a third wiring portion extending along the gate electrode 2 between the gate electrode 2 and the second wiring portion in plan view, and the third wiring portion An electrode portion of the n-type transistor Q2 extending from the wiring portion onto the gate electrode 2 region and facing the electrode portion of the source electrode 4ns of the n-type transistor Q2, and from the third wiring portion to the gate electrode 2 region And the three electrode portions of the p-type transistor Q1 provided between the two electrode portions of the source electrode 4ps of the p-type transistor Q1 and at positions sandwiching the two electrode portions, respectively.
- the contact C31 connected to the source electrode 4ps is connected to the wiring connected to the power supply, and the power supply voltage Vdd is supplied to the source electrode 4ps via the contact C31.
- the contact C32 connected to the drain electrode 4d is connected to a wiring connected to the output mechanism, and the output voltage Vout output from each transistor is output to the output mechanism via the contact C32.
- the contact C33 connected to the source electrode 4ns is connected to a wiring connected to the ground.
- the contact C2 connected to the common gate electrode 2 is connected to a wiring connected to the input mechanism, and the input voltage Vin is supplied to the common gate electrode 2 via the contact C2. That is, the semiconductor device according to the first embodiment has a configuration in which a p-type transistor and an n-type transistor are formed on the same substrate.
- FIG. 3 is a cross-sectional view of the semiconductor device including the complementary transistors according to the first embodiment.
- FIG. 3 schematically shows a layer structure of a continuous cut end surface along A-A ′ in FIG. 2.
- a contact C2 connected to the common gate electrode 2 and a contact C32 connected to the drain electrode 4d are also illustrated.
- a gate for a p-type transistor Q1 and a gate for an n-type transistor Q2 are integrally formed on a substrate 1 such as glass or plastic.
- an oxide semiconductor film 5 that functions as a channel of the n-type transistor is formed at least in a region on the gate insulating film 3 sandwiched between the source electrode 4ns and the drain electrode 4d. Is done.
- This oxide semiconductor film 5 is formed of ZTO which is an oxide semiconductor capable of realizing high electron mobility.
- This ZTO is ZnO—SnO 2 , that is, an oxide of zinc and tin.
- the material forming the oxide semiconductor film 5 is not limited to ZTO, and any semiconductor material that can realize high electron mobility can be used.
- the oxide semiconductor film 5 may be opaque or transparent, and whether the oxide semiconductor film 5 is a transparent film or an opaque film is appropriately selected according to the use of the semiconductor device.
- a semiconductor film formed of an inorganic oxide such as ZTO can be a film that is transparent to visible light depending on the composition or manufacturing conditions, and is oxidized using such a transparent inorganic oxide semiconductor.
- a transparent semiconductor element can be formed.
- the oxide semiconductor film 5 when the oxide semiconductor film 5 is formed by sputtering, the oxide semiconductor film 5 can be formed into a transparent or opaque film by adjusting the oxygen concentration in the atmosphere and the substrate temperature.
- the opaque oxide semiconductor film 5 can also be formed by mixing predetermined impurities into the composition of the sputtering target.
- an organic semiconductor film 7 that functions as a channel of the p-type transistor is formed at least on the region on the gate insulating film 3 sandwiched between the source electrode 4ps and the drain electrode 4d.
- the organic semiconductor film 7 may be formed using any organic semiconductor that can realize a high hole mobility of 1 cm 2 / Vs or more, and includes, for example, a precursor of pentacene or tetrabenzoporphyrin. It is formed of an organic semiconductor or the like.
- the organic semiconductor film 7 may be, for example, transparent or semi-transparent. By forming the organic semiconductor film 7 using a transparent organic semiconductor material, a transparent semiconductor element can be formed.
- An interlayer film 6 made of a photosensitive resin is formed on the oxide semiconductor film 5 in a region other than the region where the organic semiconductor film 7 is formed.
- a protective film 8 using a fluorine resin material having high solvent selectivity with respect to the organic semiconductor film 7 is formed on the organic semiconductor film 7, a protective film 8 using a fluorine resin material having high solvent selectivity with respect to the organic semiconductor film 7 is formed.
- the fluorine-based resin material has a property of being soluble in a fluorine-based solvent in which the constituent material of the organic semiconductor film 7 is insoluble. Further, the fluorine-based resin material hardly reacts with the constituent material of the organic semiconductor film 7. For this reason, the protective film 8 can stably protect the organic semiconductor film 7 without damaging the organic semiconductor film 7.
- the contact 13 in order to connect the drain electrode 4d and the wiring layer 14a connected to the output mechanism, the contact 13 (in FIG. 2) is formed in the interlayer film 6 between the drain electrode 4d and the wiring layer 14a.
- Contact C32 a contact (corresponding to the contact C33 in FIG. 2) for connecting the source electrode 4ns and a wiring layer (not shown) connected to, for example, a ground line is formed between the source electrode 4ns and the wiring layer.
- a contact (corresponding to the contact C31 in FIG. 2) for connecting the source electrode 4ps and a wiring layer (not shown) connected to a power source, for example, is formed between the source electrode 4ps and the wiring layer.
- the semiconductor device 100 in order to connect the common gate electrode 2 and the wiring layer 14b connected to the input mechanism, the same layer as the contact 11, the source electrodes 4ns, 4ps and the drain electrode 4d in the gate insulating film 3 is used.
- the connection layer 4a formed on the first layer and the contact 12 in the interlayer film 6 are provided at a position overlapping the wiring layer 14b in plan view. That is, the contact C2 shown in FIG. 2 includes the contact 11, the connection layer 4a, and the contact 12 in FIG.
- a passivation film 15 is formed to cover the whole from one side in the thickness direction of the substrate 1 in order to protect each transistor and the wiring layers 14a and 14b.
- a semiconductor film made of an oxide semiconductor that can ensure high electron mobility is used for channel formation of an n-type transistor, and a p-type transistor is used. Since a semiconductor film made of an organic semiconductor capable of ensuring high hole mobility is used for forming the channel of the transistor, a complementary logic circuit is secured while ensuring the desired mobility of each of the n-type and p-type transistors. As a result, a semiconductor device with high performance that operates stably can be realized.
- FIGS. 4-1 to 4-9 are cross-sectional views illustrating a method of manufacturing the semiconductor device 100 shown in FIG.
- FIGS. 4-1 to 4-9 show cross sections corresponding to A-A ′ shown in FIG.
- a metal film such as Cr, Mo, AlNb, ITO, or ZTO is formed directly on the substrate 1 by using a sputtering method, a vacuum deposition method, a coating method, or the like to form the common gate electrode 2.
- a photolithography method may include a patterning step such as an etching step as shown in FIG. 4A. .
- Is used to pattern the common gate electrode 2.
- the number of masks may be reduced by forming the common gate electrode 2 using an inkjet printing method, a printing method, or the like.
- substrate 1 should just be a board
- the substrate 1 may be a so-called flexible substrate that exhibits flexibility. Further, the substrate 1 is not necessarily transparent.
- a gate insulating film 3 is formed using a photosensitive resin or the like as a material.
- the gate insulating film 3 is formed of a material having a dielectric constant of 1.5 or more, preferably 3.5 or more, and is desirably formed with a film thickness of 500 nm or less in order to realize a desired switching speed. . Further, it is desirable that the gate insulating film 3 is sufficiently cross-linked to ensure flatness of 1 nm or less.
- the gate insulating film 3 is formed using a method according to a material such as a spin coat method.
- a contact hole is formed on the common gate electrode 2 in the gate insulating film 3 by using a photolithography method or the like.
- a vacuum deposition method in order to bury a conductive material in the contact hole and to form the source electrode 4 ns, 4 ps, the drain electrode 4 d and the connection layer 4 a, first, using a vacuum deposition method, a sputtering method, a coating method, etc., ITO , ZTO, Au, Mo, Cu, Al, Ag, MoO 3 , MoN, TiN, and other conductive or high work function metal films, oxide conductive films, nitride conductive films, and the like are formed over the entire surface.
- the source electrode 4 ns, 4 ps, the drain electrode 4 d, and the connection layer 4 a are patterned using a photolithography method, an etching method, or the like.
- the contact 11, the source electrodes 4ns, 4ps, the drain electrode 4d, and the connection layer 4a can be formed together to simplify the manufacturing process.
- the number of masks can be reduced by forming the source electrodes 4 ns, 4 ps, the drain electrode 4 d, and the connection layer 4 a using an inkjet printing method, a printing method, or the like.
- a step of forming the contact 11 shown in FIG. 4-3 by embedding a conductive material in the contact hole is provided. Also good.
- an oxide semiconductor layer 5a such as ZTO is formed over the entire surface on the source electrode 4ns, 4ps, the drain electrode 4d, the connection layer 4a, and the gate insulating film 3.
- the oxide semiconductor layer 5a is formed by a sputtering method.
- a photoresist is spin-coated, and further exposed and developed to form a photoresist thin film 16 on the oxide semiconductor film 5 formation region.
- the oxide semiconductor layer 5a is etched, so that an n-type transistor is interposed between the source electrode 4ns and the drain electrode 4d of the n-type transistor as shown in FIG. 4-5.
- the oxide semiconductor film 5 functioning as a channel is patterned. Thereafter, as shown in FIG. 4-6, the photoresist thin film 16 is removed.
- a photosensitive resin film is formed on the entire surface, and then exposed and developed to expose at least a part of the opening exposing the p-type transistor region pTr and the connection layer 4a as shown in FIG. 4-7.
- the interlayer film 6 in which the contact hole 12a to be formed and the contact hole 13a for exposing at least a part of the drain electrode 4d are formed is formed.
- the interlayer film 6 is formed with a film thickness of 1 ⁇ m, for example.
- the organic semiconductor film 7 is formed by a coating method using an organic semiconductor material as a coating solution.
- the organic semiconductor material is liquid and includes a material that becomes the organic semiconductor film 7 and a solvent or dispersion medium that dissolves or disperses the material.
- the liquid state includes a solution state, a dispersion state, and a sol form.
- the organic semiconductor film 7 is formed by coating using an organic semiconductor material in a solution state as a coating solution.
- the organic semiconductor film 7 is easily formed in a lyophilic region. Therefore, in order to form the organic semiconductor film 7 only in the p-type transistor region pTr, the interlayer film 6 is subjected to liquid repellent treatment, and as shown in FIG.
- the opening region of the interlayer film 6, that is, the p-type transistor A liquid organic semiconductor material is supplied to the region pTr.
- the organic semiconductor film 7 functioning as a channel of the p-type transistor can be appropriately formed between the source electrode 4ps and the drain electrode 4d of the p-type transistor.
- the organic semiconductor film 7 is formed of a semiconductor material having a precursor of pentacene or tetrabenzoporphyrin.
- the organic semiconductor film 7 is formed using an inkjet printing method, a printing method, or the like.
- the thickness of the organic semiconductor film 7 is, for example, 50 to 70 nm. If the interlayer film 6 is subjected to a liquid repellent treatment and the opening region of the interlayer film 6 is made lyophilic, the organic semiconductor film 7 can be selectively formed using a spin coating method.
- a protective film 8 is formed on the organic semiconductor film 7 by a coating method using an inkjet printing method, a printing method, or the like.
- This protective film 8 is formed of, for example, a fluorine resin having a thickness of 500 nm to 1 ⁇ m.
- the protective film 8 is formed by a coating method using a coating solution containing a fluorine-based solvent and a fluorine-based resin that does not substantially dissolve the organic semiconductor film 7.
- the organic semiconductor film 7 since the organic semiconductor film 7 is not damaged and hardly reacts with the organic semiconductor film 7, the organic semiconductor film 7 can be stably protected.
- the protective film 8 is formed using a coating method such as an inkjet printing method or a printing method instead of a photolithography method, damage to the organic semiconductor film 7 when the protective film 8 is formed can be reduced.
- the contacts 12 and 13 shown in FIG. 3 are formed by embedding a conductive material in the contact holes 12 a and 13 a formed in the interlayer film 6.
- a metal film or the like is formed on the protective film 8 and the contacts 12 and 13 by using a vacuum deposition method, a sputtering method, or a coating method, and then a photolithography method is used.
- the wiring layers 14a and 14b are patterned.
- the semiconductor device 100 shown in FIG. 3 can be obtained.
- the contacts 12 and 13 and the wiring layers 14a and 14b may be collectively formed in the same process as described above. Further, the wiring layers 14a and 14b may be formed using an inkjet printing method, a printing method, or the like.
- the semiconductor layer (corresponding to the oxide semiconductor film 5) that is the channel layer of the n-type transistor is not a silicon material but a semiconductor that can ensure high electron mobility.
- a semiconductor film which can be formed using an oxide semiconductor material capable of forming a film and can secure high hole mobility in a semiconductor layer (corresponding to the organic semiconductor film 7) which is a channel layer of a p-type transistor is formed. It is formed using an organic semiconductor material that can be used. For this reason, in the first embodiment, since it is not necessary to perform the carrier doping process, it is not necessary to perform a high temperature process for activating the channel, and further, an advanced vacuum process is not necessarily required. High-performance complementary transistors that operate stably as complementary logic circuits while ensuring the desired mobility of each of the n-type and p-type transistors with a simple process without using a large device can do.
- the semiconductor device 100 according to the first embodiment does not need to be subjected to a high temperature process for channel activation, it is not necessary to limit the type of the substrate 1 and a substrate 1 made of various materials can be selected. .
- the manufacturing of the semiconductor device is further simplified by forming the channel of the n-type transistor by a coating method using a sol-shaped oxide semiconductor material as a coating solution.
- a channel of an n-type transistor is formed by a so-called sol-gel method in which a sol-shaped oxide semiconductor material is applied to a predetermined position and further gelled.
- FIG. 5 is a cross-sectional view of a semiconductor device configured by complementary transistors according to the second embodiment.
- FIG. 5 also shows contacts connected to the common gate electrode 2 and contacts connected to the source electrodes 4 ns and 4 ps and the drain electrode 4 d, respectively.
- the semiconductor device according to the second embodiment has a planar configuration similar to that of the plan view shown in FIG.
- the channel of the n-type transistor is an oxide formed by using a sol-gel method instead of the oxide semiconductor film 5 shown in FIG.
- the semiconductor film 205 is used.
- the sol-gel method here refers to a dispersion (sol state) in which an oxide semiconductor material in a fine particle state is dispersed into a non-fluid aggregate (gel state) by hydrolysis and polycondensation reaction, and this is heated. Thus, an oxide semiconductor is obtained.
- the oxide semiconductor film 205 may be, for example, transparent or translucent.
- a transparent semiconductor element can be formed by forming the oxide semiconductor film 205 using an oxide semiconductor material in which nanoparticles composed of ZTO are dispersed in a dispersion medium.
- the formed film can be baked to improve the film quality, but the description thereof is omitted in the following description for the sake of brevity.
- a protective film 208 made of the same material is formed on the oxide semiconductor film 205 and the organic semiconductor film 7. Similar to the protective film 8 shown in FIG. 3, the protective film 208 is formed of a fluorine resin material having high solvent selectivity with respect to the organic semiconductor film 7. In addition, since the fluorine-based resin material hardly reacts with the constituent material of the oxide semiconductor film 205, the oxide semiconductor film 205 can be stably protected without damaging the oxide semiconductor film 205. Can do.
- a semiconductor film that can ensure high hole mobility for forming a semiconductor layer (corresponding to the organic semiconductor film 7) that is a channel layer of a p-type transistor Since the organic semiconductor material capable of forming the n-type and p-type transistors is used, the high-complementarity that stably operates as a complementary logic circuit while ensuring the desired mobility of each of the n-type and p-type transistors Type transistor can be realized.
- FIGS. 4A to 4C are cross-sectional views illustrating a method for manufacturing the semiconductor device 200 shown in FIG.
- an oxide semiconductor film 205 is formed in the n-type transistor region nTr by using a sol-gel method.
- This oxide semiconductor film 205 is formed by coating using a printing method.
- the oxide semiconductor film 205 may be formed by forming a film formed using an oxide semiconductor by a coating method such as a spin coating method or an inkjet printing method in addition to a printing method.
- an organic semiconductor film 7 is formed in the p-type transistor region pTr using an organic semiconductor material.
- the organic semiconductor film 7 is formed using a printing method.
- the organic semiconductor film 7 may be formed by forming a film made of an organic semiconductor using a coating method such as a spin coating method or an ink jet printing method.
- a fluorine-based resin material is applied onto the source electrode 4ns, 4ps, the drain electrode 4d, the connection layer 4a, the oxide semiconductor film 205, and the organic semiconductor film 7, and further a photolithography method.
- the protective film 208 in which the contact holes 12a and 13a are formed on the connection layer 4a and the predetermined source electrodes 4ns, 4ps and the drain electrode 4d is formed.
- the contacts 12 and 13 shown in FIG. 5 are formed by embedding a conductive material in the contact holes 12a and 13a, and the wiring layers 14a and 14b are formed. Pattern. Then, by forming the passivation film 15 on the entire surface, the semiconductor device 200 shown in FIG. 5 can be obtained.
- the channel of the n-type transistor is formed using an oxide semiconductor material capable of forming a semiconductor film that can ensure high electron mobility instead of a silicon material, and a high hole is formed.
- an oxide semiconductor material capable of forming a semiconductor film that can ensure high electron mobility instead of a silicon material and a high hole is formed.
- carrier doping treatment, channel activation high-temperature process, and Stable as a complementary logic circuit while ensuring the desired mobility of each of the n-type and p-type transistors with a simple process that does not require an advanced vacuum process and does not require a large device.
- a complementary transistor with high performance can be manufactured.
- the oxide semiconductor film 205 is formed by applying a sol-state oxide semiconductor material to a predetermined position by a printing method or the like, forming a gel state, and performing heat treatment. Therefore, according to the second embodiment, the photolithography process and the etching process for forming the oxide semiconductor film 5 that are necessary in the first embodiment can be omitted. Furthermore, a high-performance complementary transistor can be manufactured by a simple process.
- the organic semiconductor film 7 serving as the channel of the p-type transistor and the oxide semiconductor film 205 serving as the channel of the n-type transistor are formed by a printing method, and then the same material is formed on the entire surface of the substrate 1.
- a protective film 208 is formed.
- a high-performance complementary transistor can be manufactured by a simple process.
- the protective film 208 is formed using a fluorine-based resin material that hardly reacts with the oxide semiconductor film 205 and the organic semiconductor film 7, both the oxide semiconductor film 205 and the organic semiconductor film 7 are formed. Since the protection can be stably performed, the performance of the complementary transistor can be appropriately maintained.
- each film from the common gate electrode 2 to the protective film 208 is formed using a coating method such as an ink jet printing method or a printing method, all layers up to the protective film 208 are simplified. In addition to being able to be formed by a coating process, the number of masks can be reduced.
- a semiconductor layer (oxide semiconductor film 5 or 205) which is a channel layer of an n-type transistor is formed using an oxide semiconductor material, and is a channel layer of a p-type transistor.
- the case where the semiconductor layer (organic semiconductor film 7) is formed using an organic semiconductor material has been described as an example.
- a semiconductor layer that is a channel layer of an n-type transistor is formed using an organic semiconductor material, and a p-type transistor is formed.
- the semiconductor layer which is the channel layer may be formed using an oxide semiconductor material.
- a high-temperature process or an advanced vacuum process is not required, so that a complementary transistor can be manufactured by a simple process.
- the drain electrodes of the p-type transistor Q1 and the n-type transistor Q2 are formed of the same material and in the same process, but the drain electrodes are formed of different materials.
- the gate electrodes of the p-type transistor Q1 and the n-type transistor Q2 may also be made of different materials and formed in different steps. May be.
- the gate for the p-type transistor Q1 and the gate for the n-type transistor Q2 are integrally formed.
- the gate for the p-type transistor Q1 and the gate for the n-type transistor Q2 are provided.
- the gates for the p-type transistor Q1 and the gate for the n-type transistor Q2 may be connected by wiring, and the gate for the p-type transistor Q1 and the gate for the n-type transistor Q2 may be connected to each other. You may make it comprise with a different material.
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Abstract
Description
[1] 第1のソース電極、第1のドレイン電極、第1の半導体膜、および第1のゲート電極を有し、かつ基板上に形成される第1のトランジスタと、第2のソース電極、第2のドレイン電極、第2の半導体膜、および前記第1のゲート電極に電気的に接続される第2のゲート電極を有し、かつ前記基板上に形成される第2のトランジスタとを有する半導体装置の製造方法において、前記基板上に前記第1のゲート電極を形成する第1ゲート電極形成工程と、前記第1のソース電極と前記第1のドレイン電極とを形成する第1ソース/ドレイン電極形成工程と、酸化物半導体材料を用いて前記第1の半導体膜を形成する第1の半導体膜形成工程と、前記基板上に前記第2のゲート電極を形成する第2ゲート電極形成工程と、前記第2のソース電極と前記第2のドレイン電極とを形成する第2ソース/ドレイン電極形成工程と、有機半導体材料を用いて前記第2の半導体膜を形成する第2の半導体膜形成工程と、を含む、半導体装置の製造方法。
[2] 前記第1の半導体膜形成工程では、前記酸化物半導体材料を用いるスパッタ法によって前記第1の半導体膜を形成し、前記第2の半導体膜形成工程では、前記有機半導体材料を塗布液として用いる塗布法によって前記第2の半導体膜を形成する、前記[1]に記載の半導体装置の製造方法。
[3] 前記第1の半導体膜形成工程では、前記酸化物半導体材料を塗布液として用いる塗布法によって前記第1の半導体膜を形成し、前記第2の半導体膜形成工程では、前記有機半導体材料を塗布液として用いる塗布法によって前記第2の半導体膜を形成する、前記[1]に記載の半導体装置の製造方法。
[4] 前記第1のトランジスタは、n型トランジスタであり、前記第2のトランジスタは、p型トランジスタであることを特徴とする前記[1]~[3]のいずれか一つに記載の半導体装置の製造方法。
[5] 前記第1の半導体膜形成工程では、前記酸化物半導体材料として亜鉛スズ酸化物を用いて前記第1の半導体膜を形成する、前記[1]~[4]のいずれか一つに記載の半導体装置の製造方法。
[6] 前記第1の半導体膜及び前記第2の半導体膜のいずれか一方又は双方の表面上に保護膜を形成する保護膜形成工程をさらに含み、前記保護膜は、フッ素系樹脂によって構成される、前記[1]~[5]のいずれか一つに記載の半導体装置の製造方法。
[7] 同一基板上に形成される第1および第2のトランジスタを有する半導体装置において、前記第1のトランジスタは、第1のゲート電極と、第1のソース電極と、第1のドレイン電極と、前記第1のソース電極および前記第1のドレイン電極の間に形成され、酸化物半導体によって構成される第1の半導体膜と、を備え、前記第2のトランジスタは、前記第1のゲート電極に電気的に接続される第2のゲート電極と、第2のソース電極と、第2のドレイン電極と、前記第2のソース電極および前記第2のドレイン電極の間に形成され、有機半導体によって構成される第2の半導体膜と、を備える、半導体装置。
[8] 前記酸化物半導体は、亜鉛スズ酸化物であることを特徴とする前記[7]に記載の半導体装置。
[9] 前記第1の半導体膜及び第2の半導体膜のいずれか一方又は双方の表面上に形成され、フッ素系樹脂によって構成される保護膜をさらに備える、前記[8]に記載の半導体装置。
が提供される。
まず、実施の形態1について説明する。図1は、本実施の形態1にかかる相補型トランジスタによって構成される半導体装置の電気的構成を示す回路図である。また、図2は、本実施の形態1にかかる相補型トランジスタによって構成される半導体装置の平面図である。
つぎに、実施の形態2について説明する。実施の形態2においては、ゾル状の酸化物半導体材料を塗布液として用いる塗布法によってn型トランジスタのチャネルを形成することによって、半導体装置の製造をさらに簡易化している。具体的には、ゾル状の酸化物半導体材料を所定の位置に塗布し、これをさらにゲル化させるいわゆるゾルゲル法によってn型トランジスタのチャネルを形成する。
2 共通ゲート電極
3 ゲート絶縁膜
4a 接続層
4d ドレイン電極
4ns,4ps ソース電極
5,205 酸化物半導体膜
6 層間膜
7 有機半導体膜
8,208 保護膜
11,12,13 コンタクト
14a,14b 配線層
15 パッシベーション膜
16 フォトレジスト薄膜
100,200 半導体装置
Claims (9)
- 第1のソース電極、第1のドレイン電極、第1の半導体膜、および第1のゲート電極を有し、かつ基板上に形成される第1のトランジスタと、
第2のソース電極、第2のドレイン電極、第2の半導体膜、および前記第1のゲート電極に電気的に接続される第2のゲート電極を有し、かつ前記基板上に形成される第2のトランジスタとを有する半導体装置の製造方法において、
前記基板上に前記第1のゲート電極を形成する第1ゲート電極形成工程と、
前記第1のソース電極と前記第1のドレイン電極とを形成する第1ソース/ドレイン電極形成工程と、
酸化物半導体材料を用いて前記第1の半導体膜を形成する第1の半導体膜形成工程と、
前記基板上に前記第2のゲート電極を形成する第2ゲート電極形成工程と、
前記第2のソース電極と前記第2のドレイン電極とを形成する第2ソース/ドレイン電極形成工程と、
有機半導体材料を用いて前記第2の半導体膜を形成する第2の半導体膜形成工程と、
を含む、半導体装置の製造方法。 - 前記第1の半導体膜形成工程では、前記酸化物半導体材料を用いるスパッタ法によって前記第1の半導体膜を形成し、
前記第2の半導体膜形成工程では、前記有機半導体材料を塗布液として用いる塗布法によって前記第2の半導体膜を形成する、請求項1に記載の半導体装置の製造方法。 - 前記第1の半導体膜形成工程では、前記酸化物半導体材料を塗布液として用いる塗布法によって前記第1の半導体膜を形成し、
前記第2の半導体膜形成工程では、前記有機半導体材料を塗布液として用いる塗布法によって前記第2の半導体膜を形成する、請求項1に記載の半導体装置の製造方法。 - 前記第1のトランジスタは、n型トランジスタであり、
前記第2のトランジスタは、p型トランジスタであることを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記第1の半導体膜形成工程では、前記酸化物半導体材料として亜鉛スズ酸化物を用いて前記第1の半導体膜を形成する、請求項1に記載の半導体装置の製造方法。
- 前記第1の半導体膜及び前記第2の半導体膜のいずれか一方又は双方の表面上に保護膜を形成する保護膜形成工程をさらに含み、
前記保護膜は、フッ素系樹脂によって構成される、請求項1に記載の半導体装置の製造方法。 - 同一基板上に形成される第1および第2のトランジスタを有する半導体装置において、
前記第1のトランジスタは、
第1のゲート電極と、
第1のソース電極と、
第1のドレイン電極と、
前記第1のソース電極および前記第1のドレイン電極の間に形成され、酸化物半導体によって構成される第1の半導体膜と、
を備え、
前記第2のトランジスタは、
前記第1のゲート電極に電気的に接続される第2のゲート電極と、
第2のソース電極と、
第2のドレイン電極と、
前記第2のソース電極および前記第2のドレイン電極の間に形成され、有機半導体によって構成される第2の半導体膜と、
を備える、半導体装置。 - 前記酸化物半導体は、亜鉛スズ酸化物であることを特徴とする請求項7に記載の半導体装置。
- 前記第1の半導体膜及び第2の半導体膜のいずれか一方又は双方の表面上に形成され、フッ素系樹脂によって構成される保護膜をさらに備える、請求項8に記載の半導体装置。
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EP09802864A EP2312638A4 (en) | 2008-07-30 | 2009-07-22 | METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT AND SEMICONDUCTOR COMPONENT |
US13/055,808 US20110127528A1 (en) | 2008-07-30 | 2009-07-22 | Method for manufacturing semiconductor device and semiconductor device |
CN2009801291340A CN102105988A (zh) | 2008-07-30 | 2009-07-22 | 半导体装置的制造方法及半导体装置 |
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JP2008-195775 | 2008-07-30 | ||
JP2008195775A JP2010034343A (ja) | 2008-07-30 | 2008-07-30 | 半導体装置の製造方法および半導体装置 |
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WO2010013621A1 true WO2010013621A1 (ja) | 2010-02-04 |
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PCT/JP2009/063096 WO2010013621A1 (ja) | 2008-07-30 | 2009-07-22 | 半導体装置の製造方法および半導体装置 |
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US (1) | US20110127528A1 (ja) |
EP (1) | EP2312638A4 (ja) |
JP (1) | JP2010034343A (ja) |
KR (1) | KR20110038703A (ja) |
CN (1) | CN102105988A (ja) |
TW (1) | TW201013848A (ja) |
WO (1) | WO2010013621A1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2011118741A1 (en) * | 2010-03-26 | 2011-09-29 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
CN105324848A (zh) * | 2013-06-11 | 2016-02-10 | 庆熙大学校产学协力团 | 作为显示装置的像素元件的氧化物半导体晶体管及其制造方法 |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2011118510A1 (en) | 2010-03-26 | 2011-09-29 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US9696642B2 (en) | 2015-12-08 | 2017-07-04 | S-Printing Solution Co., Ltd. | Electrophotographic photoreceptor and electrophotographic imaging apparatus employing the same |
JP2022130245A (ja) * | 2021-02-25 | 2022-09-06 | 国立大学法人 東京大学 | 無機/有機ハイブリッド相補型半導体デバイス及びその製造方法 |
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WO2011118741A1 (en) * | 2010-03-26 | 2011-09-29 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US8461584B2 (en) | 2010-03-26 | 2013-06-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device with metal oxide film |
US9012908B2 (en) | 2010-03-26 | 2015-04-21 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device with metal oxide film |
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CN105324848A (zh) * | 2013-06-11 | 2016-02-10 | 庆熙大学校产学协力团 | 作为显示装置的像素元件的氧化物半导体晶体管及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
CN102105988A (zh) | 2011-06-22 |
KR20110038703A (ko) | 2011-04-14 |
US20110127528A1 (en) | 2011-06-02 |
EP2312638A4 (en) | 2012-08-01 |
EP2312638A1 (en) | 2011-04-20 |
JP2010034343A (ja) | 2010-02-12 |
TW201013848A (en) | 2010-04-01 |
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